Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:20:14.597771 lava-dispatcher, installed at version: 2024.01
2 10:20:14.598604 start: 0 validate
3 10:20:14.599078 Start time: 2024-09-19 10:20:14.599047+00:00 (UTC)
4 10:20:14.599646 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:20:14.600192 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 10:20:14.640221 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:20:14.640743 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 10:20:14.671067 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:20:14.671678 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 10:20:14.704140 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:20:14.704649 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 10:20:14.742652 validate duration: 0.14
14 10:20:14.743524 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:20:14.743852 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:20:14.744188 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:20:14.744784 Not decompressing ramdisk as can be used compressed.
18 10:20:14.745213 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 10:20:14.745485 saving as /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/ramdisk/rootfs.cpio.gz
20 10:20:14.745759 total size: 47897469 (45 MB)
21 10:20:14.782113 progress 0 % (0 MB)
22 10:20:14.812688 progress 5 % (2 MB)
23 10:20:14.843114 progress 10 % (4 MB)
24 10:20:14.873569 progress 15 % (6 MB)
25 10:20:14.903380 progress 20 % (9 MB)
26 10:20:14.934015 progress 25 % (11 MB)
27 10:20:14.964135 progress 30 % (13 MB)
28 10:20:14.994676 progress 35 % (16 MB)
29 10:20:15.024691 progress 40 % (18 MB)
30 10:20:15.054381 progress 45 % (20 MB)
31 10:20:15.084521 progress 50 % (22 MB)
32 10:20:15.114197 progress 55 % (25 MB)
33 10:20:15.144785 progress 60 % (27 MB)
34 10:20:15.174573 progress 65 % (29 MB)
35 10:20:15.204963 progress 70 % (32 MB)
36 10:20:15.234897 progress 75 % (34 MB)
37 10:20:15.264779 progress 80 % (36 MB)
38 10:20:15.295056 progress 85 % (38 MB)
39 10:20:15.325107 progress 90 % (41 MB)
40 10:20:15.355437 progress 95 % (43 MB)
41 10:20:15.385172 progress 100 % (45 MB)
42 10:20:15.385944 45 MB downloaded in 0.64 s (71.35 MB/s)
43 10:20:15.386508 end: 1.1.1 http-download (duration 00:00:01) [common]
45 10:20:15.387415 end: 1.1 download-retry (duration 00:00:01) [common]
46 10:20:15.387724 start: 1.2 download-retry (timeout 00:09:59) [common]
47 10:20:15.388030 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 10:20:15.388536 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/kernel/Image
49 10:20:15.388788 saving as /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/kernel/Image
50 10:20:15.389003 total size: 45724160 (43 MB)
51 10:20:15.389223 No compression specified
52 10:20:15.428956 progress 0 % (0 MB)
53 10:20:15.459237 progress 5 % (2 MB)
54 10:20:15.489031 progress 10 % (4 MB)
55 10:20:15.518673 progress 15 % (6 MB)
56 10:20:15.549208 progress 20 % (8 MB)
57 10:20:15.579165 progress 25 % (10 MB)
58 10:20:15.608484 progress 30 % (13 MB)
59 10:20:15.638619 progress 35 % (15 MB)
60 10:20:15.668154 progress 40 % (17 MB)
61 10:20:15.697640 progress 45 % (19 MB)
62 10:20:15.727218 progress 50 % (21 MB)
63 10:20:15.756582 progress 55 % (24 MB)
64 10:20:15.787032 progress 60 % (26 MB)
65 10:20:15.816309 progress 65 % (28 MB)
66 10:20:15.845011 progress 70 % (30 MB)
67 10:20:15.873988 progress 75 % (32 MB)
68 10:20:15.903182 progress 80 % (34 MB)
69 10:20:15.932540 progress 85 % (37 MB)
70 10:20:15.960923 progress 90 % (39 MB)
71 10:20:15.989756 progress 95 % (41 MB)
72 10:20:16.018766 progress 100 % (43 MB)
73 10:20:16.019398 43 MB downloaded in 0.63 s (69.17 MB/s)
74 10:20:16.019881 end: 1.2.1 http-download (duration 00:00:01) [common]
76 10:20:16.020738 end: 1.2 download-retry (duration 00:00:01) [common]
77 10:20:16.021013 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:20:16.021274 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:20:16.021744 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 10:20:16.021994 saving as /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 10:20:16.022202 total size: 53209 (0 MB)
82 10:20:16.022411 No compression specified
83 10:20:16.063372 progress 61 % (0 MB)
84 10:20:16.064562 progress 100 % (0 MB)
85 10:20:16.065133 0 MB downloaded in 0.04 s (1.18 MB/s)
86 10:20:16.065602 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:20:16.066417 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:20:16.066678 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:20:16.066941 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:20:16.067422 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/modules.tar.xz
92 10:20:16.067668 saving as /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/modules/modules.tar
93 10:20:16.067874 total size: 11604668 (11 MB)
94 10:20:16.068114 Using unxz to decompress xz
95 10:20:16.101904 progress 0 % (0 MB)
96 10:20:16.170201 progress 5 % (0 MB)
97 10:20:16.256179 progress 10 % (1 MB)
98 10:20:16.343424 progress 15 % (1 MB)
99 10:20:16.425399 progress 20 % (2 MB)
100 10:20:16.503394 progress 25 % (2 MB)
101 10:20:16.582298 progress 30 % (3 MB)
102 10:20:16.655360 progress 35 % (3 MB)
103 10:20:16.735393 progress 40 % (4 MB)
104 10:20:16.820055 progress 45 % (5 MB)
105 10:20:16.903347 progress 50 % (5 MB)
106 10:20:16.987797 progress 55 % (6 MB)
107 10:20:17.072402 progress 60 % (6 MB)
108 10:20:17.159043 progress 65 % (7 MB)
109 10:20:17.233780 progress 70 % (7 MB)
110 10:20:17.317476 progress 75 % (8 MB)
111 10:20:17.414050 progress 80 % (8 MB)
112 10:20:17.513409 progress 85 % (9 MB)
113 10:20:17.583895 progress 90 % (9 MB)
114 10:20:17.663354 progress 95 % (10 MB)
115 10:20:17.739532 progress 100 % (11 MB)
116 10:20:17.752255 11 MB downloaded in 1.68 s (6.57 MB/s)
117 10:20:17.753325 end: 1.4.1 http-download (duration 00:00:02) [common]
119 10:20:17.755064 end: 1.4 download-retry (duration 00:00:02) [common]
120 10:20:17.755636 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 10:20:17.756264 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 10:20:17.756827 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:20:17.757378 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 10:20:17.758773 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc
125 10:20:17.760037 makedir: /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin
126 10:20:17.760985 makedir: /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/tests
127 10:20:17.761868 makedir: /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/results
128 10:20:17.762588 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-add-keys
129 10:20:17.763958 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-add-sources
130 10:20:17.765356 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-background-process-start
131 10:20:17.766824 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-background-process-stop
132 10:20:17.768328 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-common-functions
133 10:20:17.769707 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-echo-ipv4
134 10:20:17.771056 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-install-packages
135 10:20:17.772533 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-installed-packages
136 10:20:17.773900 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-os-build
137 10:20:17.775277 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-probe-channel
138 10:20:17.776647 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-probe-ip
139 10:20:17.777718 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-target-ip
140 10:20:17.778752 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-target-mac
141 10:20:17.779835 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-target-storage
142 10:20:17.780977 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-test-case
143 10:20:17.781991 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-test-event
144 10:20:17.782955 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-test-feedback
145 10:20:17.783914 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-test-raise
146 10:20:17.784973 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-test-reference
147 10:20:17.786178 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-test-runner
148 10:20:17.787180 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-test-set
149 10:20:17.788221 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-test-shell
150 10:20:17.789231 Updating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-install-packages (oe)
151 10:20:17.790314 Updating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/bin/lava-installed-packages (oe)
152 10:20:17.791234 Creating /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/environment
153 10:20:17.792039 LAVA metadata
154 10:20:17.792572 - LAVA_JOB_ID=742828
155 10:20:17.793040 - LAVA_DISPATCHER_IP=192.168.6.2
156 10:20:17.793779 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 10:20:17.795748 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 10:20:17.796443 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 10:20:17.796896 skipped lava-vland-overlay
160 10:20:17.797435 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 10:20:17.798001 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 10:20:17.798468 skipped lava-multinode-overlay
163 10:20:17.798995 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 10:20:17.799541 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 10:20:17.800137 Loading test definitions
166 10:20:17.800696 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 10:20:17.801147 Using /lava-742828 at stage 0
168 10:20:17.803288 uuid=742828_1.5.2.4.1 testdef=None
169 10:20:17.803859 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 10:20:17.804411 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 10:20:17.807686 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 10:20:17.808728 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 10:20:17.810957 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 10:20:17.811792 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 10:20:17.813934 runner path: /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/0/tests/0_igt-gpu-panfrost test_uuid 742828_1.5.2.4.1
178 10:20:17.814530 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 10:20:17.815336 Creating lava-test-runner.conf files
181 10:20:17.815543 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/742828/lava-overlay-tgbcd9zc/lava-742828/0 for stage 0
182 10:20:17.815894 - 0_igt-gpu-panfrost
183 10:20:17.816268 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 10:20:17.816548 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 10:20:17.840196 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 10:20:17.840609 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 10:20:17.840869 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 10:20:17.841135 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 10:20:17.841399 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 10:20:24.723216 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 10:20:24.723738 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 10:20:24.724274 extracting modules file /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742828/extract-overlay-ramdisk-f_kkkhoi/ramdisk
193 10:20:26.419667 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 10:20:26.420341 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 10:20:26.420762 [common] Applying overlay /var/lib/lava/dispatcher/tmp/742828/compress-overlay-gcrakinv/overlay-1.5.2.5.tar.gz to ramdisk
196 10:20:26.421085 [common] Applying overlay /var/lib/lava/dispatcher/tmp/742828/compress-overlay-gcrakinv/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/742828/extract-overlay-ramdisk-f_kkkhoi/ramdisk
197 10:20:26.472488 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 10:20:26.473077 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 10:20:26.473433 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 10:20:26.473722 Converting downloaded kernel to a uImage
201 10:20:26.474137 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/kernel/Image /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/kernel/uImage
202 10:20:27.046410 output: Image Name:
203 10:20:27.046827 output: Created: Thu Sep 19 10:20:26 2024
204 10:20:27.047038 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 10:20:27.047243 output: Data Size: 45724160 Bytes = 44652.50 KiB = 43.61 MiB
206 10:20:27.047462 output: Load Address: 01080000
207 10:20:27.047692 output: Entry Point: 01080000
208 10:20:27.047903 output:
209 10:20:27.048283 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 10:20:27.048556 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 10:20:27.048826 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 10:20:27.049078 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 10:20:27.049337 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 10:20:27.049613 Building ramdisk /var/lib/lava/dispatcher/tmp/742828/extract-overlay-ramdisk-f_kkkhoi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/742828/extract-overlay-ramdisk-f_kkkhoi/ramdisk
215 10:20:33.887931 >> 502458 blocks
216 10:20:55.544718 Adding RAMdisk u-boot header.
217 10:20:55.545170 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/742828/extract-overlay-ramdisk-f_kkkhoi/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/742828/extract-overlay-ramdisk-f_kkkhoi/ramdisk.cpio.gz.uboot
218 10:20:56.225119 output: Image Name:
219 10:20:56.225515 output: Created: Thu Sep 19 10:20:55 2024
220 10:20:56.225739 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 10:20:56.225949 output: Data Size: 65723187 Bytes = 64182.80 KiB = 62.68 MiB
222 10:20:56.226152 output: Load Address: 00000000
223 10:20:56.226357 output: Entry Point: 00000000
224 10:20:56.226560 output:
225 10:20:56.227162 rename /var/lib/lava/dispatcher/tmp/742828/extract-overlay-ramdisk-f_kkkhoi/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/ramdisk/ramdisk.cpio.gz.uboot
226 10:20:56.227589 end: 1.5.8 compress-ramdisk (duration 00:00:29) [common]
227 10:20:56.227895 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 10:20:56.228232 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 10:20:56.228490 No LXC device requested
230 10:20:56.228767 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 10:20:56.229039 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 10:20:56.229300 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 10:20:56.229522 Checking files for TFTP limit of 4294967296 bytes.
234 10:20:56.231076 end: 1 tftp-deploy (duration 00:00:41) [common]
235 10:20:56.231416 start: 2 uboot-action (timeout 00:05:00) [common]
236 10:20:56.231704 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 10:20:56.231972 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 10:20:56.232265 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 10:20:56.232557 Using kernel file from prepare-kernel: 742828/tftp-deploy-0bgu_qlb/kernel/uImage
240 10:20:56.232881 substitutions:
241 10:20:56.233101 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 10:20:56.233307 - {DTB_ADDR}: 0x01070000
243 10:20:56.233509 - {DTB}: 742828/tftp-deploy-0bgu_qlb/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 10:20:56.233715 - {INITRD}: 742828/tftp-deploy-0bgu_qlb/ramdisk/ramdisk.cpio.gz.uboot
245 10:20:56.233923 - {KERNEL_ADDR}: 0x01080000
246 10:20:56.234124 - {KERNEL}: 742828/tftp-deploy-0bgu_qlb/kernel/uImage
247 10:20:56.234324 - {LAVA_MAC}: None
248 10:20:56.234551 - {PRESEED_CONFIG}: None
249 10:20:56.234755 - {PRESEED_LOCAL}: None
250 10:20:56.234955 - {RAMDISK_ADDR}: 0x08000000
251 10:20:56.235155 - {RAMDISK}: 742828/tftp-deploy-0bgu_qlb/ramdisk/ramdisk.cpio.gz.uboot
252 10:20:56.235359 - {ROOT_PART}: None
253 10:20:56.235558 - {ROOT}: None
254 10:20:56.235757 - {SERVER_IP}: 192.168.6.2
255 10:20:56.235959 - {TEE_ADDR}: 0x83000000
256 10:20:56.236183 - {TEE}: None
257 10:20:56.236389 Parsed boot commands:
258 10:20:56.236584 - setenv autoload no
259 10:20:56.236782 - setenv initrd_high 0xffffffff
260 10:20:56.236980 - setenv fdt_high 0xffffffff
261 10:20:56.237180 - dhcp
262 10:20:56.237384 - setenv serverip 192.168.6.2
263 10:20:56.237586 - tftpboot 0x01080000 742828/tftp-deploy-0bgu_qlb/kernel/uImage
264 10:20:56.237788 - tftpboot 0x08000000 742828/tftp-deploy-0bgu_qlb/ramdisk/ramdisk.cpio.gz.uboot
265 10:20:56.237988 - tftpboot 0x01070000 742828/tftp-deploy-0bgu_qlb/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 10:20:56.238186 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 10:20:56.238387 - bootm 0x01080000 0x08000000 0x01070000
268 10:20:56.238658 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 10:20:56.239487 start: 2.3 connect-device (timeout 00:05:00) [common]
271 10:20:56.239743 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 10:20:56.252456 Setting prompt string to ['lava-test: # ']
273 10:20:56.254048 end: 2.3 connect-device (duration 00:00:00) [common]
274 10:20:56.254700 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 10:20:56.255301 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 10:20:56.255868 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 10:20:56.257205 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 10:20:56.294025 >> OK - accepted request
279 10:20:56.296451 Returned 0 in 0 seconds
280 10:20:56.397501 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 10:20:56.398441 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 10:20:56.398761 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 10:20:56.399047 Setting prompt string to ['Hit any key to stop autoboot']
285 10:20:56.399304 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 10:20:56.400284 Trying 192.168.56.21...
287 10:20:56.400562 Connected to conserv1.
288 10:20:56.400790 Escape character is '^]'.
289 10:20:56.401002
290 10:20:56.401230 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 10:20:56.401456
292 10:21:04.213223 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 10:21:04.213657 bl2_stage_init 0x01
294 10:21:04.213910 bl2_stage_init 0x81
295 10:21:04.218700 hw id: 0x0000 - pwm id 0x01
296 10:21:04.219126 bl2_stage_init 0xc1
297 10:21:04.224307 bl2_stage_init 0x02
298 10:21:04.224723
299 10:21:04.225087 L0:00000000
300 10:21:04.225431 L1:00000703
301 10:21:04.225687 L2:00008067
302 10:21:04.225909 L3:15000000
303 10:21:04.229929 S1:00000000
304 10:21:04.230320 B2:20282000
305 10:21:04.230682 B1:a0f83180
306 10:21:04.231026
307 10:21:04.231368 TE: 69415
308 10:21:04.231704
309 10:21:04.235483 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 10:21:04.235772
311 10:21:04.241094 Board ID = 1
312 10:21:04.241405 Set cpu clk to 24M
313 10:21:04.241633 Set clk81 to 24M
314 10:21:04.246691 Use GP1_pll as DSU clk.
315 10:21:04.246988 DSU clk: 1200 Mhz
316 10:21:04.247212 CPU clk: 1200 MHz
317 10:21:04.252292 Set clk81 to 166.6M
318 10:21:04.257917 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 10:21:04.258221 board id: 1
320 10:21:04.264169 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 10:21:04.276067 fw parse done
322 10:21:04.281049 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 10:21:04.325897 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 10:21:04.336376 PIEI prepare done
325 10:21:04.336709 fastboot data load
326 10:21:04.336948 fastboot data verify
327 10:21:04.341918 verify result: 266
328 10:21:04.347499 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 10:21:04.347957 LPDDR4 probe
330 10:21:04.348370 ddr clk to 1584MHz
331 10:21:04.354524 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 10:21:04.393359
333 10:21:04.393770 dmc_version 0001
334 10:21:04.399401 Check phy result
335 10:21:04.406220 INFO : End of CA training
336 10:21:04.406662 INFO : End of initialization
337 10:21:04.411742 INFO : Training has run successfully!
338 10:21:04.412066 Check phy result
339 10:21:04.417348 INFO : End of initialization
340 10:21:04.417774 INFO : End of read enable training
341 10:21:04.422996 INFO : End of fine write leveling
342 10:21:04.428576 INFO : End of Write leveling coarse delay
343 10:21:04.428895 INFO : Training has run successfully!
344 10:21:04.429125 Check phy result
345 10:21:04.434140 INFO : End of initialization
346 10:21:04.434444 INFO : End of read dq deskew training
347 10:21:04.439751 INFO : End of MPR read delay center optimization
348 10:21:04.445350 INFO : End of write delay center optimization
349 10:21:04.450999 INFO : End of read delay center optimization
350 10:21:04.451315 INFO : End of max read latency training
351 10:21:04.456548 INFO : Training has run successfully!
352 10:21:04.456981 1D training succeed
353 10:21:04.464800 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 10:21:04.513121 Check phy result
355 10:21:04.513554 INFO : End of initialization
356 10:21:04.540610 INFO : End of 2D read delay Voltage center optimization
357 10:21:04.564860 INFO : End of 2D read delay Voltage center optimization
358 10:21:04.622396 INFO : End of 2D write delay Voltage center optimization
359 10:21:04.676514 INFO : End of 2D write delay Voltage center optimization
360 10:21:04.681899 INFO : Training has run successfully!
361 10:21:04.682226
362 10:21:04.682453 channel==0
363 10:21:04.687518 RxClkDly_Margin_A0==78 ps 8
364 10:21:04.687961 TxDqDly_Margin_A0==98 ps 10
365 10:21:04.693217 RxClkDly_Margin_A1==88 ps 9
366 10:21:04.693685 TxDqDly_Margin_A1==88 ps 9
367 10:21:04.694024 TrainedVREFDQ_A0==74
368 10:21:04.698708 TrainedVREFDQ_A1==74
369 10:21:04.699036 VrefDac_Margin_A0==24
370 10:21:04.699254 DeviceVref_Margin_A0==40
371 10:21:04.704302 VrefDac_Margin_A1==22
372 10:21:04.704753 DeviceVref_Margin_A1==40
373 10:21:04.705083
374 10:21:04.705402
375 10:21:04.705714 channel==1
376 10:21:04.709937 RxClkDly_Margin_A0==78 ps 8
377 10:21:04.710265 TxDqDly_Margin_A0==88 ps 9
378 10:21:04.715572 RxClkDly_Margin_A1==88 ps 9
379 10:21:04.715932 TxDqDly_Margin_A1==88 ps 9
380 10:21:04.721282 TrainedVREFDQ_A0==77
381 10:21:04.721649 TrainedVREFDQ_A1==78
382 10:21:04.721872 VrefDac_Margin_A0==22
383 10:21:04.726751 DeviceVref_Margin_A0==37
384 10:21:04.727232 VrefDac_Margin_A1==22
385 10:21:04.727584 DeviceVref_Margin_A1==36
386 10:21:04.732348
387 10:21:04.732838 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 10:21:04.733092
389 10:21:04.765965 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 10:21:04.766401 2D training succeed
391 10:21:04.771558 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 10:21:04.777323 auto size-- 65535DDR cs0 size: 2048MB
393 10:21:04.777847 DDR cs1 size: 2048MB
394 10:21:04.782765 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 10:21:04.783139 cs0 DataBus test pass
396 10:21:04.788400 cs1 DataBus test pass
397 10:21:04.788910 cs0 AddrBus test pass
398 10:21:04.789260 cs1 AddrBus test pass
399 10:21:04.789507
400 10:21:04.793973 100bdlr_step_size ps== 471
401 10:21:04.794334 result report
402 10:21:04.799587 boot times 0Enable ddr reg access
403 10:21:04.803866 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 10:21:04.817495 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 10:21:05.477905 bl2z: ptr: 05129330, size: 00001e40
406 10:21:05.486357 0.0;M3 CHK:0;cm4_sp_mode 0
407 10:21:05.486848 MVN_1=0x00000000
408 10:21:05.487134 MVN_2=0x00000000
409 10:21:05.497822 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 10:21:05.498308 OPS=0x04
411 10:21:05.498588 ring efuse init
412 10:21:05.503506 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 10:21:05.504223 [0.017355 Inits done]
414 10:21:05.504711 secure task start!
415 10:21:05.511149 high task start!
416 10:21:05.511749 low task start!
417 10:21:05.512138 run into bl31
418 10:21:05.519739 NOTICE: BL31: v1.3(release):4fc40b1
419 10:21:05.527589 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 10:21:05.528099 NOTICE: BL31: G12A normal boot!
421 10:21:05.543208 NOTICE: BL31: BL33 decompress pass
422 10:21:05.548868 ERROR: Error initializing runtime service opteed_fast
423 10:21:06.763924 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 10:21:06.764411 bl2_stage_init 0x01
425 10:21:06.764638 bl2_stage_init 0x81
426 10:21:06.769484 hw id: 0x0000 - pwm id 0x01
427 10:21:06.769864 bl2_stage_init 0xc1
428 10:21:06.774716 bl2_stage_init 0x02
429 10:21:06.775087
430 10:21:06.775344 L0:00000000
431 10:21:06.775588 L1:00000703
432 10:21:06.775830 L2:00008067
433 10:21:06.776111 L3:15000000
434 10:21:06.780282 S1:00000000
435 10:21:06.780657 B2:20282000
436 10:21:06.780910 B1:a0f83180
437 10:21:06.781148
438 10:21:06.781387 TE: 68590
439 10:21:06.781623
440 10:21:06.785900 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 10:21:06.791477
442 10:21:06.791852 Board ID = 1
443 10:21:06.792143 Set cpu clk to 24M
444 10:21:06.792395 Set clk81 to 24M
445 10:21:06.797068 Use GP1_pll as DSU clk.
446 10:21:06.797427 DSU clk: 1200 Mhz
447 10:21:06.797686 CPU clk: 1200 MHz
448 10:21:06.802658 Set clk81 to 166.6M
449 10:21:06.808273 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 10:21:06.808637 board id: 1
451 10:21:06.815817 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 10:21:06.826553 fw parse done
453 10:21:06.832487 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 10:21:06.875159 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 10:21:06.886060 PIEI prepare done
456 10:21:06.886465 fastboot data load
457 10:21:06.886729 fastboot data verify
458 10:21:06.891745 verify result: 266
459 10:21:06.897291 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 10:21:06.897670 LPDDR4 probe
461 10:21:06.897929 ddr clk to 1584MHz
462 10:21:08.264372 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c00 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 10:21:08.264789 bl2_stage_init 0x01
464 10:21:08.265012 bl2_stage_init 0x81
465 10:21:08.269770 hw id: 0x0000 - pwm id 0x01
466 10:21:08.270098 bl2_stage_init 0xc1
467 10:21:08.275397 bl2_stage_init 0x02
468 10:21:08.275836
469 10:21:08.276253 L0:00000000
470 10:21:08.276588 L1:00000703
471 10:21:08.276828 L2:00008067
472 10:21:08.277038 L3:15000000
473 10:21:08.281309 S1:00000000
474 10:21:08.281768 B2:20282000
475 10:21:08.282106 B1:a0f83180
476 10:21:08.282429
477 10:21:08.282757 TE: 70451
478 10:21:08.282997
479 10:21:08.286956 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 10:21:08.287286
481 10:21:08.292546 Board ID = 1
482 10:21:08.292976 Set cpu clk to 24M
483 10:21:08.293317 Set clk81 to 24M
484 10:21:08.298100 Use GP1_pll as DSU clk.
485 10:21:08.298398 DSU clk: 1200 Mhz
486 10:21:08.298621 CPU clk: 1200 MHz
487 10:21:08.303689 Set clk81 to 166.6M
488 10:21:08.309282 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 10:21:08.309579 board id: 1
490 10:21:08.316190 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 10:21:08.327056 fw parse done
492 10:21:08.333052 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 10:21:08.376164 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 10:21:08.387275 PIEI prepare done
495 10:21:08.387617 fastboot data load
496 10:21:08.387835 fastboot data verify
497 10:21:08.392879 verify result: 266
498 10:21:08.398454 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 10:21:08.398799 LPDDR4 probe
500 10:21:08.399015 ddr clk to 1584MHz
501 10:21:08.406442 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 10:21:08.444257
503 10:21:08.444662 dmc_version 0001
504 10:21:08.451277 Check phy result
505 10:21:08.457266 INFO : End of CA training
506 10:21:08.457789 INFO : End of initialization
507 10:21:08.462913 INFO : Training has run successfully!
508 10:21:08.463283 Check phy result
509 10:21:08.468437 INFO : End of initialization
510 10:21:08.468946 INFO : End of read enable training
511 10:21:08.474073 INFO : End of fine write leveling
512 10:21:08.479702 INFO : End of Write leveling coarse delay
513 10:21:08.480113 INFO : Training has run successfully!
514 10:21:08.480362 Check phy result
515 10:21:08.485270 INFO : End of initialization
516 10:21:08.485631 INFO : End of read dq deskew training
517 10:21:08.490859 INFO : End of MPR read delay center optimization
518 10:21:08.496434 INFO : End of write delay center optimization
519 10:21:08.502091 INFO : End of read delay center optimization
520 10:21:08.502434 INFO : End of max read latency training
521 10:21:08.507659 INFO : Training has run successfully!
522 10:21:08.508158 1D training succeed
523 10:21:08.516890 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 10:21:08.565206 Check phy result
525 10:21:08.565640 INFO : End of initialization
526 10:21:08.592528 INFO : End of 2D read delay Voltage center optimization
527 10:21:08.616869 INFO : End of 2D read delay Voltage center optimization
528 10:21:08.673515 INFO : End of 2D write delay Voltage center optimization
529 10:21:08.731816 INFO : End of 2D write delay Voltage center optimization
530 10:21:08.732657 INFO : Training has run successfully!
531 10:21:08.733215
532 10:21:08.733755 channel==0
533 10:21:08.737278 RxClkDly_Margin_A0==78 ps 8
534 10:21:08.737911 TxDqDly_Margin_A0==88 ps 9
535 10:21:08.742842 RxClkDly_Margin_A1==88 ps 9
536 10:21:08.743413 TxDqDly_Margin_A1==88 ps 9
537 10:21:08.748482 TrainedVREFDQ_A0==74
538 10:21:08.749058 TrainedVREFDQ_A1==75
539 10:21:08.749598 VrefDac_Margin_A0==23
540 10:21:08.754126 DeviceVref_Margin_A0==40
541 10:21:08.754473 VrefDac_Margin_A1==22
542 10:21:08.754704 DeviceVref_Margin_A1==39
543 10:21:08.754921
544 10:21:08.759801
545 10:21:08.760140 channel==1
546 10:21:08.760369 RxClkDly_Margin_A0==78 ps 8
547 10:21:08.765308 TxDqDly_Margin_A0==98 ps 10
548 10:21:08.765748 RxClkDly_Margin_A1==78 ps 8
549 10:21:08.766111 TxDqDly_Margin_A1==88 ps 9
550 10:21:08.770862 TrainedVREFDQ_A0==78
551 10:21:08.771297 TrainedVREFDQ_A1==75
552 10:21:08.776536 VrefDac_Margin_A0==22
553 10:21:08.776868 DeviceVref_Margin_A0==36
554 10:21:08.777100 VrefDac_Margin_A1==22
555 10:21:08.782166 DeviceVref_Margin_A1==39
556 10:21:08.782493
557 10:21:08.787829 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 10:21:08.788324
559 10:21:08.815596 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
560 10:21:08.816001 2D training succeed
561 10:21:08.821221 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 10:21:08.826820 auto size-- 65535DDR cs0 size: 2048MB
563 10:21:08.827156 DDR cs1 size: 2048MB
564 10:21:08.832391 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 10:21:08.832855 cs0 DataBus test pass
566 10:21:08.837979 cs1 DataBus test pass
567 10:21:08.838443 cs0 AddrBus test pass
568 10:21:08.843624 cs1 AddrBus test pass
569 10:21:08.843949
570 10:21:08.844212 100bdlr_step_size ps== 464
571 10:21:08.844438 result report
572 10:21:08.849166 boot times 0Enable ddr reg access
573 10:21:08.855486 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 10:21:08.869349 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 10:21:09.528327 bl2z: ptr: 05129330, size: 00001e40
576 10:21:09.537464 0.0;M3 CHK:0;cm4_sp_mode 0
577 10:21:09.537970 MVN_1=0x00000000
578 10:21:09.538239 MVN_2=0x00000000
579 10:21:09.548981 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 10:21:09.549391 OPS=0x04
581 10:21:09.549629 ring efuse init
582 10:21:09.554559 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 10:21:09.555034 [0.017354 Inits done]
584 10:21:09.555374 secure task start!
585 10:21:09.562610 high task start!
586 10:21:09.563134 low task start!
587 10:21:09.563401 run into bl31
588 10:21:09.571206 NOTICE: BL31: v1.3(release):4fc40b1
589 10:21:09.578969 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 10:21:09.579296 NOTICE: BL31: G12A normal boot!
591 10:21:09.594560 NOTICE: BL31: BL33 decompress pass
592 10:21:09.600240 ERROR: Error initializing runtime service opteed_fast
593 10:21:10.814390 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 10:21:10.814778 bl2_stage_init 0x01
595 10:21:10.814994 bl2_stage_init 0x81
596 10:21:10.820061 hw id: 0x0000 - pwm id 0x01
597 10:21:10.820381 bl2_stage_init 0xc1
598 10:21:10.820605 bl2_stage_init 0x02
599 10:21:10.820821
600 10:21:10.825627 L0:00000000
601 10:21:10.825976 L1:00000703
602 10:21:10.826238 L2:00008067
603 10:21:10.826496 L3:15000000
604 10:21:10.826753 S1:00000000
605 10:21:10.831181 B2:20282000
606 10:21:10.831562 B1:a0f83180
607 10:21:10.831793
608 10:21:10.832046 TE: 69696
609 10:21:10.832276
610 10:21:10.836895 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 10:21:10.837281
612 10:21:10.842445 Board ID = 1
613 10:21:10.842849 Set cpu clk to 24M
614 10:21:10.843086 Set clk81 to 24M
615 10:21:10.848100 Use GP1_pll as DSU clk.
616 10:21:10.848499 DSU clk: 1200 Mhz
617 10:21:10.848728 CPU clk: 1200 MHz
618 10:21:10.848946 Set clk81 to 166.6M
619 10:21:10.859212 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 10:21:10.859883 board id: 1
621 10:21:10.865615 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 10:21:10.876298 fw parse done
623 10:21:10.882285 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 10:21:10.925021 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 10:21:10.935864 PIEI prepare done
626 10:21:10.936403 fastboot data load
627 10:21:10.936687 fastboot data verify
628 10:21:10.941432 verify result: 266
629 10:21:10.947069 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 10:21:10.947409 LPDDR4 probe
631 10:21:10.947654 ddr clk to 1584MHz
632 10:21:10.955056 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 10:21:10.992296
634 10:21:10.992722 dmc_version 0001
635 10:21:10.999009 Check phy result
636 10:21:11.004865 INFO : End of CA training
637 10:21:11.005212 INFO : End of initialization
638 10:21:11.010468 INFO : Training has run successfully!
639 10:21:11.010822 Check phy result
640 10:21:11.016082 INFO : End of initialization
641 10:21:11.016423 INFO : End of read enable training
642 10:21:11.021660 INFO : End of fine write leveling
643 10:21:11.027246 INFO : End of Write leveling coarse delay
644 10:21:11.027591 INFO : Training has run successfully!
645 10:21:11.027826 Check phy result
646 10:21:11.032854 INFO : End of initialization
647 10:21:11.033202 INFO : End of read dq deskew training
648 10:21:11.038589 INFO : End of MPR read delay center optimization
649 10:21:11.044072 INFO : End of write delay center optimization
650 10:21:11.049642 INFO : End of read delay center optimization
651 10:21:11.050137 INFO : End of max read latency training
652 10:21:11.055196 INFO : Training has run successfully!
653 10:21:11.055679 1D training succeed
654 10:21:11.064401 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 10:21:11.112128 Check phy result
656 10:21:11.112633 INFO : End of initialization
657 10:21:11.133431 INFO : End of 2D read delay Voltage center optimization
658 10:21:11.152742 INFO : End of 2D read delay Voltage center optimization
659 10:21:11.205478 INFO : End of 2D write delay Voltage center optimization
660 10:21:11.254719 INFO : End of 2D write delay Voltage center optimization
661 10:21:11.260191 INFO : Training has run successfully!
662 10:21:11.260612
663 10:21:11.260986 channel==0
664 10:21:11.265734 RxClkDly_Margin_A0==78 ps 8
665 10:21:11.266173 TxDqDly_Margin_A0==98 ps 10
666 10:21:11.271309 RxClkDly_Margin_A1==78 ps 8
667 10:21:11.271734 TxDqDly_Margin_A1==88 ps 9
668 10:21:11.272268 TrainedVREFDQ_A0==74
669 10:21:11.277046 TrainedVREFDQ_A1==74
670 10:21:11.277964 VrefDac_Margin_A0==23
671 10:21:11.278330 DeviceVref_Margin_A0==40
672 10:21:11.282517 VrefDac_Margin_A1==23
673 10:21:11.282951 DeviceVref_Margin_A1==40
674 10:21:11.283305
675 10:21:11.283628
676 10:21:11.283974 channel==1
677 10:21:11.288133 RxClkDly_Margin_A0==88 ps 9
678 10:21:11.288556 TxDqDly_Margin_A0==98 ps 10
679 10:21:11.293716 RxClkDly_Margin_A1==88 ps 9
680 10:21:11.294135 TxDqDly_Margin_A1==88 ps 9
681 10:21:11.299364 TrainedVREFDQ_A0==78
682 10:21:11.299763 TrainedVREFDQ_A1==75
683 10:21:11.300139 VrefDac_Margin_A0==23
684 10:21:11.304933 DeviceVref_Margin_A0==36
685 10:21:11.305326 VrefDac_Margin_A1==22
686 10:21:11.310545 DeviceVref_Margin_A1==39
687 10:21:11.310970
688 10:21:11.311325 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 10:21:11.311650
690 10:21:11.344120 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
691 10:21:11.344605 2D training succeed
692 10:21:11.349814 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 10:21:11.355349 auto size-- 65535DDR cs0 size: 2048MB
694 10:21:11.355758 DDR cs1 size: 2048MB
695 10:21:11.360954 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 10:21:11.361355 cs0 DataBus test pass
697 10:21:11.366547 cs1 DataBus test pass
698 10:21:11.366970 cs0 AddrBus test pass
699 10:21:11.367326 cs1 AddrBus test pass
700 10:21:11.367644
701 10:21:11.372159 100bdlr_step_size ps== 478
702 10:21:11.372593 result report
703 10:21:11.377713 boot times 0Enable ddr reg access
704 10:21:11.382921 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 10:21:11.396774 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 10:21:12.051458 bl2z: ptr: 05129330, size: 00001e40
707 10:21:12.058075 0.0;M3 CHK:0;cm4_sp_mode 0
708 10:21:12.059343 MVN_1=0x00000000
709 10:21:12.059901 MVN_2=0x00000000
710 10:21:12.069475 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 10:21:12.069923 OPS=0x04
712 10:21:12.070171 ring efuse init
713 10:21:12.075101 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 10:21:12.075510 [0.017310 Inits done]
715 10:21:12.075771 secure task start!
716 10:21:12.082435 high task start!
717 10:21:12.082828 low task start!
718 10:21:12.083044 run into bl31
719 10:21:12.091044 NOTICE: BL31: v1.3(release):4fc40b1
720 10:21:12.099026 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 10:21:12.099396 NOTICE: BL31: G12A normal boot!
722 10:21:12.114289 NOTICE: BL31: BL33 decompress pass
723 10:21:12.119971 ERROR: Error initializing runtime service opteed_fast
724 10:21:12.914013
725 10:21:12.914437
726 10:21:12.919380 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 10:21:12.919663
728 10:21:12.922881 Model: Libre Computer AML-S905D3-CC Solitude
729 10:21:13.069775 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 10:21:13.084313 DRAM: 2 GiB (effective 3.8 GiB)
731 10:21:13.186129 Core: 406 devices, 33 uclasses, devicetree: separate
732 10:21:13.191961 WDT: Not starting watchdog@f0d0
733 10:21:13.217035 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 10:21:13.229298 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 10:21:13.234250 ** Bad device specification mmc 0 **
736 10:21:13.244321 Card did not respond to voltage select! : -110
737 10:21:13.251931 ** Bad device specification mmc 0 **
738 10:21:13.252237 Couldn't find partition mmc 0
739 10:21:13.260298 Card did not respond to voltage select! : -110
740 10:21:13.265789 ** Bad device specification mmc 0 **
741 10:21:13.266049 Couldn't find partition mmc 0
742 10:21:13.270818 Error: could not access storage.
743 10:21:13.568352 Net: eth0: ethernet@ff3f0000
744 10:21:13.568770 starting USB...
745 10:21:13.813164 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 10:21:13.813557 Starting the controller
747 10:21:13.820072 USB XHCI 1.10
748 10:21:15.373837 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 10:21:15.382179 scanning usb for storage devices... 0 Storage Device(s) found
751 10:21:15.433194 Hit any key to stop autoboot: 1
752 10:21:15.433833 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 10:21:15.434188 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 10:21:15.434457 Setting prompt string to ['=>']
755 10:21:15.434717 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 10:21:15.448224 0
757 10:21:15.448874 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 10:21:15.549684 => setenv autoload no
760 10:21:15.550374 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 10:21:15.554742 setenv autoload no
763 10:21:15.655783 => setenv initrd_high 0xffffffff
764 10:21:15.656436 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 10:21:15.660928 setenv initrd_high 0xffffffff
767 10:21:15.761967 => setenv fdt_high 0xffffffff
768 10:21:15.762634 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
769 10:21:15.766937 setenv fdt_high 0xffffffff
771 10:21:15.867960 => dhcp
772 10:21:15.868604 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
773 10:21:15.872734 dhcp
774 10:21:16.478287 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 10:21:16.478887 Speed: 1000, full duplex
776 10:21:16.479293 BOOTP broadcast 1
777 10:21:16.726500 BOOTP broadcast 2
778 10:21:17.227571 BOOTP broadcast 3
779 10:21:18.228414 BOOTP broadcast 4
780 10:21:20.229561 BOOTP broadcast 5
781 10:21:20.242936 DHCP client bound to address 192.168.6.12 (3764 ms)
783 10:21:20.344307 => setenv serverip 192.168.6.2
784 10:21:20.344979 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
785 10:21:20.349505 setenv serverip 192.168.6.2
787 10:21:20.450617 => tftpboot 0x01080000 742828/tftp-deploy-0bgu_qlb/kernel/uImage
788 10:21:20.451341 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
789 10:21:20.458002 tftpboot 0x01080000 742828/tftp-deploy-0bgu_qlb/kernel/uImage
790 10:21:20.458565 Speed: 1000, full duplex
791 10:21:20.458977 Using ethernet@ff3f0000 device
792 10:21:20.463606 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 10:21:20.469032 Filename '742828/tftp-deploy-0bgu_qlb/kernel/uImage'.
794 10:21:20.472861 Load address: 0x1080000
795 10:21:23.951110 Loading: *################################################## 43.6 MiB
796 10:21:23.951536 12.5 MiB/s
797 10:21:23.951750 done
798 10:21:23.955356 Bytes transferred = 45724224 (2b9b240 hex)
800 10:21:24.056509 => tftpboot 0x08000000 742828/tftp-deploy-0bgu_qlb/ramdisk/ramdisk.cpio.gz.uboot
801 10:21:24.057339 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
802 10:21:24.064156 tftpboot 0x08000000 742828/tftp-deploy-0bgu_qlb/ramdisk/ramdisk.cpio.gz.uboot
803 10:21:24.064677 Speed: 1000, full duplex
804 10:21:24.065112 Using ethernet@ff3f0000 device
805 10:21:24.069907 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
806 10:21:24.079304 Filename '742828/tftp-deploy-0bgu_qlb/ramdisk/ramdisk.cpio.gz.uboot'.
807 10:21:24.079870 Load address: 0x8000000
808 10:21:29.400157 Loading: *################################################# UDP wrong checksum 0000000f 000075ed
809 10:21:34.399095 T UDP wrong checksum 0000000f 000075ed
810 10:21:36.000257 UDP wrong checksum 000000ff 000040f5
811 10:21:36.030238 UDP wrong checksum 000000ff 0000c9e7
812 10:21:44.402430 T T UDP wrong checksum 0000000f 000075ed
813 10:22:04.403592 T T T UDP wrong checksum 0000000f 000075ed
814 10:22:24.410496 T T T T
815 10:22:24.411186 Retry count exceeded; starting again
817 10:22:24.412811 end: 2.4.3 bootloader-commands (duration 00:01:09) [common]
820 10:22:24.414959 end: 2.4 uboot-commands (duration 00:01:28) [common]
822 10:22:24.416546 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
824 10:22:24.417670 end: 2 uboot-action (duration 00:01:28) [common]
826 10:22:24.419401 Cleaning after the job
827 10:22:24.420051 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/ramdisk
828 10:22:24.421303 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/kernel
829 10:22:24.452856 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/dtb
830 10:22:24.454290 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742828/tftp-deploy-0bgu_qlb/modules
831 10:22:24.461061 start: 4.1 power-off (timeout 00:00:30) [common]
832 10:22:24.462130 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
833 10:22:24.497251 >> OK - accepted request
834 10:22:24.499378 Returned 0 in 0 seconds
835 10:22:24.601471 end: 4.1 power-off (duration 00:00:00) [common]
837 10:22:24.603377 start: 4.2 read-feedback (timeout 00:10:00) [common]
838 10:22:24.604640 Listened to connection for namespace 'common' for up to 1s
839 10:22:25.605345 Finalising connection for namespace 'common'
840 10:22:25.605859 Disconnecting from shell: Finalise
841 10:22:25.606155 =>
842 10:22:25.706810 end: 4.2 read-feedback (duration 00:00:01) [common]
843 10:22:25.707263 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/742828
844 10:22:26.453712 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/742828
845 10:22:26.454269 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.