Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 9
- Errors: 0
- Boot result: PASS
- Kernel Errors: 5
1 08:42:50.362573 lava-dispatcher, installed at version: 2024.01
2 08:42:50.363403 start: 0 validate
3 08:42:50.363904 Start time: 2024-09-19 08:42:50.363873+00:00 (UTC)
4 08:42:50.364504 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:42:50.365062 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 08:42:50.405231 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:42:50.405795 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:42:50.434282 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:42:50.434899 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:42:50.467258 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:42:50.467801 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:42:50.498291 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:42:50.498809 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 08:42:50.536454 validate duration: 0.17
16 08:42:50.537284 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:42:50.537598 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:42:50.537900 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:42:50.538469 Not decompressing ramdisk as can be used compressed.
20 08:42:50.538907 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 08:42:50.539178 saving as /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/ramdisk/initrd.cpio.gz
22 08:42:50.539438 total size: 5628169 (5 MB)
23 08:42:50.572451 progress 0 % (0 MB)
24 08:42:50.576933 progress 5 % (0 MB)
25 08:42:50.581192 progress 10 % (0 MB)
26 08:42:50.584813 progress 15 % (0 MB)
27 08:42:50.589052 progress 20 % (1 MB)
28 08:42:50.593023 progress 25 % (1 MB)
29 08:42:50.597421 progress 30 % (1 MB)
30 08:42:50.601831 progress 35 % (1 MB)
31 08:42:50.605966 progress 40 % (2 MB)
32 08:42:50.610376 progress 45 % (2 MB)
33 08:42:50.614310 progress 50 % (2 MB)
34 08:42:50.618749 progress 55 % (2 MB)
35 08:42:50.623218 progress 60 % (3 MB)
36 08:42:50.627137 progress 65 % (3 MB)
37 08:42:50.631530 progress 70 % (3 MB)
38 08:42:50.635429 progress 75 % (4 MB)
39 08:42:50.639726 progress 80 % (4 MB)
40 08:42:50.643410 progress 85 % (4 MB)
41 08:42:50.647227 progress 90 % (4 MB)
42 08:42:50.650980 progress 95 % (5 MB)
43 08:42:50.654413 progress 100 % (5 MB)
44 08:42:50.655113 5 MB downloaded in 0.12 s (46.41 MB/s)
45 08:42:50.655700 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:42:50.656711 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:42:50.657022 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:42:50.657295 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:42:50.657769 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/kernel/Image
51 08:42:50.658012 saving as /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/kernel/Image
52 08:42:50.658220 total size: 45724160 (43 MB)
53 08:42:50.658434 No compression specified
54 08:42:50.693830 progress 0 % (0 MB)
55 08:42:50.723012 progress 5 % (2 MB)
56 08:42:50.753347 progress 10 % (4 MB)
57 08:42:50.783073 progress 15 % (6 MB)
58 08:42:50.811689 progress 20 % (8 MB)
59 08:42:50.840762 progress 25 % (10 MB)
60 08:42:50.869356 progress 30 % (13 MB)
61 08:42:50.898660 progress 35 % (15 MB)
62 08:42:50.927380 progress 40 % (17 MB)
63 08:42:50.955574 progress 45 % (19 MB)
64 08:42:50.984421 progress 50 % (21 MB)
65 08:42:51.014764 progress 55 % (24 MB)
66 08:42:51.045481 progress 60 % (26 MB)
67 08:42:51.075579 progress 65 % (28 MB)
68 08:42:51.105145 progress 70 % (30 MB)
69 08:42:51.135152 progress 75 % (32 MB)
70 08:42:51.165199 progress 80 % (34 MB)
71 08:42:51.194718 progress 85 % (37 MB)
72 08:42:51.223903 progress 90 % (39 MB)
73 08:42:51.253859 progress 95 % (41 MB)
74 08:42:51.282140 progress 100 % (43 MB)
75 08:42:51.282792 43 MB downloaded in 0.62 s (69.82 MB/s)
76 08:42:51.283304 end: 1.2.1 http-download (duration 00:00:01) [common]
78 08:42:51.284243 end: 1.2 download-retry (duration 00:00:01) [common]
79 08:42:51.284561 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:42:51.284865 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:42:51.285368 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 08:42:51.285644 saving as /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/dtb/meson-g12b-a311d-libretech-cc.dtb
83 08:42:51.285874 total size: 54703 (0 MB)
84 08:42:51.286107 No compression specified
85 08:42:51.330103 progress 59 % (0 MB)
86 08:42:51.331041 progress 100 % (0 MB)
87 08:42:51.331667 0 MB downloaded in 0.05 s (1.14 MB/s)
88 08:42:51.332214 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:42:51.333057 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:42:51.333326 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:42:51.333605 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:42:51.334070 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 08:42:51.334318 saving as /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/nfsrootfs/full.rootfs.tar
95 08:42:51.334529 total size: 120894716 (115 MB)
96 08:42:51.334742 Using unxz to decompress xz
97 08:42:51.373564 progress 0 % (0 MB)
98 08:42:52.213489 progress 5 % (5 MB)
99 08:42:53.144409 progress 10 % (11 MB)
100 08:42:53.946594 progress 15 % (17 MB)
101 08:42:54.687028 progress 20 % (23 MB)
102 08:42:55.279688 progress 25 % (28 MB)
103 08:42:56.114023 progress 30 % (34 MB)
104 08:42:56.990789 progress 35 % (40 MB)
105 08:42:57.380332 progress 40 % (46 MB)
106 08:42:57.767052 progress 45 % (51 MB)
107 08:42:58.510983 progress 50 % (57 MB)
108 08:42:59.402116 progress 55 % (63 MB)
109 08:43:00.184310 progress 60 % (69 MB)
110 08:43:00.951481 progress 65 % (74 MB)
111 08:43:01.740745 progress 70 % (80 MB)
112 08:43:02.576699 progress 75 % (86 MB)
113 08:43:03.365485 progress 80 % (92 MB)
114 08:43:04.130810 progress 85 % (98 MB)
115 08:43:04.993405 progress 90 % (103 MB)
116 08:43:05.789132 progress 95 % (109 MB)
117 08:43:06.635259 progress 100 % (115 MB)
118 08:43:06.648779 115 MB downloaded in 15.31 s (7.53 MB/s)
119 08:43:06.649374 end: 1.4.1 http-download (duration 00:00:15) [common]
121 08:43:06.650204 end: 1.4 download-retry (duration 00:00:15) [common]
122 08:43:06.650472 start: 1.5 download-retry (timeout 00:09:44) [common]
123 08:43:06.650735 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 08:43:06.651241 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/modules.tar.xz
125 08:43:06.651497 saving as /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/modules/modules.tar
126 08:43:06.651706 total size: 11604668 (11 MB)
127 08:43:06.651919 Using unxz to decompress xz
128 08:43:06.694579 progress 0 % (0 MB)
129 08:43:06.760995 progress 5 % (0 MB)
130 08:43:06.847178 progress 10 % (1 MB)
131 08:43:06.935385 progress 15 % (1 MB)
132 08:43:07.017719 progress 20 % (2 MB)
133 08:43:07.096072 progress 25 % (2 MB)
134 08:43:07.174609 progress 30 % (3 MB)
135 08:43:07.248266 progress 35 % (3 MB)
136 08:43:07.329315 progress 40 % (4 MB)
137 08:43:07.414097 progress 45 % (5 MB)
138 08:43:07.494641 progress 50 % (5 MB)
139 08:43:07.576643 progress 55 % (6 MB)
140 08:43:07.655344 progress 60 % (6 MB)
141 08:43:07.740090 progress 65 % (7 MB)
142 08:43:07.814600 progress 70 % (7 MB)
143 08:43:07.897999 progress 75 % (8 MB)
144 08:43:07.997490 progress 80 % (8 MB)
145 08:43:08.096841 progress 85 % (9 MB)
146 08:43:08.167927 progress 90 % (9 MB)
147 08:43:08.247508 progress 95 % (10 MB)
148 08:43:08.324075 progress 100 % (11 MB)
149 08:43:08.336620 11 MB downloaded in 1.68 s (6.57 MB/s)
150 08:43:08.337272 end: 1.5.1 http-download (duration 00:00:02) [common]
152 08:43:08.338105 end: 1.5 download-retry (duration 00:00:02) [common]
153 08:43:08.338376 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 08:43:08.338643 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 08:43:25.850316 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/742845/extract-nfsrootfs-1xjfryqp
156 08:43:25.850925 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 08:43:25.851213 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 08:43:25.851832 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo
159 08:43:25.852302 makedir: /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin
160 08:43:25.852638 makedir: /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/tests
161 08:43:25.852956 makedir: /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/results
162 08:43:25.853284 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-add-keys
163 08:43:25.853802 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-add-sources
164 08:43:25.854304 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-background-process-start
165 08:43:25.854801 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-background-process-stop
166 08:43:25.855317 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-common-functions
167 08:43:25.855847 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-echo-ipv4
168 08:43:25.856507 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-install-packages
169 08:43:25.857015 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-installed-packages
170 08:43:25.857491 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-os-build
171 08:43:25.857963 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-probe-channel
172 08:43:25.858436 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-probe-ip
173 08:43:25.858904 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-target-ip
174 08:43:25.859367 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-target-mac
175 08:43:25.859838 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-target-storage
176 08:43:25.860357 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-test-case
177 08:43:25.860841 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-test-event
178 08:43:25.861359 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-test-feedback
179 08:43:25.861915 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-test-raise
180 08:43:25.862391 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-test-reference
181 08:43:25.862866 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-test-runner
182 08:43:25.863345 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-test-set
183 08:43:25.863815 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-test-shell
184 08:43:25.864369 Updating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-add-keys (debian)
185 08:43:25.864911 Updating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-add-sources (debian)
186 08:43:25.865422 Updating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-install-packages (debian)
187 08:43:25.865921 Updating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-installed-packages (debian)
188 08:43:25.866406 Updating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/bin/lava-os-build (debian)
189 08:43:25.866834 Creating /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/environment
190 08:43:25.867202 LAVA metadata
191 08:43:25.867460 - LAVA_JOB_ID=742845
192 08:43:25.867673 - LAVA_DISPATCHER_IP=192.168.6.2
193 08:43:25.868058 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 08:43:25.869036 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 08:43:25.869346 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 08:43:25.869555 skipped lava-vland-overlay
197 08:43:25.869794 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 08:43:25.870045 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 08:43:25.870261 skipped lava-multinode-overlay
200 08:43:25.870503 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 08:43:25.870752 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 08:43:25.870998 Loading test definitions
203 08:43:25.871272 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 08:43:25.871489 Using /lava-742845 at stage 0
205 08:43:25.872569 uuid=742845_1.6.2.4.1 testdef=None
206 08:43:25.872870 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 08:43:25.873132 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 08:43:25.874779 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 08:43:25.875567 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 08:43:25.877503 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 08:43:25.878323 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 08:43:25.880167 runner path: /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/0/tests/0_timesync-off test_uuid 742845_1.6.2.4.1
215 08:43:25.880718 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 08:43:25.881525 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 08:43:25.881747 Using /lava-742845 at stage 0
219 08:43:25.882102 Fetching tests from https://github.com/kernelci/test-definitions.git
220 08:43:25.882389 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/0/tests/1_kselftest-alsa'
221 08:43:29.248625 Running '/usr/bin/git checkout kernelci.org
222 08:43:29.486467 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 08:43:29.487942 uuid=742845_1.6.2.4.5 testdef=None
224 08:43:29.488534 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 08:43:29.489976 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 08:43:29.495304 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 08:43:29.496904 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 08:43:29.503945 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 08:43:29.505616 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 08:43:29.512672 runner path: /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/0/tests/1_kselftest-alsa test_uuid 742845_1.6.2.4.5
234 08:43:29.513199 BOARD='meson-g12b-a311d-libretech-cc'
235 08:43:29.513603 BRANCH='next'
236 08:43:29.513995 SKIPFILE='/dev/null'
237 08:43:29.514386 SKIP_INSTALL='True'
238 08:43:29.514775 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 08:43:29.515170 TST_CASENAME=''
240 08:43:29.515560 TST_CMDFILES='alsa'
241 08:43:29.516559 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 08:43:29.518086 Creating lava-test-runner.conf files
244 08:43:29.518486 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/742845/lava-overlay-o0zqkydo/lava-742845/0 for stage 0
245 08:43:29.519127 - 0_timesync-off
246 08:43:29.519576 - 1_kselftest-alsa
247 08:43:29.520225 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 08:43:29.520764 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 08:43:53.049705 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 08:43:53.050170 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 08:43:53.050474 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 08:43:53.050790 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 08:43:53.051090 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 08:43:53.686456 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 08:43:53.686947 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 08:43:53.687222 extracting modules file /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742845/extract-nfsrootfs-1xjfryqp
257 08:43:55.323104 extracting modules file /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742845/extract-overlay-ramdisk-0cmc2ytj/ramdisk
258 08:43:56.801200 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 08:43:56.801709 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 08:43:56.801998 [common] Applying overlay to NFS
261 08:43:56.802252 [common] Applying overlay /var/lib/lava/dispatcher/tmp/742845/compress-overlay-vcrgk8k_/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/742845/extract-nfsrootfs-1xjfryqp
262 08:43:59.607952 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 08:43:59.608514 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 08:43:59.608868 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 08:43:59.609150 Converting downloaded kernel to a uImage
266 08:43:59.609494 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/kernel/Image /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/kernel/uImage
267 08:44:00.304440 output: Image Name:
268 08:44:00.304869 output: Created: Thu Sep 19 08:43:59 2024
269 08:44:00.305135 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 08:44:00.305348 output: Data Size: 45724160 Bytes = 44652.50 KiB = 43.61 MiB
271 08:44:00.305585 output: Load Address: 01080000
272 08:44:00.305788 output: Entry Point: 01080000
273 08:44:00.306017 output:
274 08:44:00.306365 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 08:44:00.306723 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 08:44:00.307044 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 08:44:00.307323 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 08:44:00.307591 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 08:44:00.307973 Building ramdisk /var/lib/lava/dispatcher/tmp/742845/extract-overlay-ramdisk-0cmc2ytj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/742845/extract-overlay-ramdisk-0cmc2ytj/ramdisk
280 08:44:02.896520 >> 166871 blocks
281 08:44:10.787778 Adding RAMdisk u-boot header.
282 08:44:10.788266 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/742845/extract-overlay-ramdisk-0cmc2ytj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/742845/extract-overlay-ramdisk-0cmc2ytj/ramdisk.cpio.gz.uboot
283 08:44:11.034181 output: Image Name:
284 08:44:11.034575 output: Created: Thu Sep 19 08:44:10 2024
285 08:44:11.035041 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 08:44:11.035564 output: Data Size: 23441886 Bytes = 22892.47 KiB = 22.36 MiB
287 08:44:11.036088 output: Load Address: 00000000
288 08:44:11.036551 output: Entry Point: 00000000
289 08:44:11.037001 output:
290 08:44:11.038177 rename /var/lib/lava/dispatcher/tmp/742845/extract-overlay-ramdisk-0cmc2ytj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/ramdisk/ramdisk.cpio.gz.uboot
291 08:44:11.038976 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 08:44:11.039592 end: 1.6 prepare-tftp-overlay (duration 00:01:03) [common]
293 08:44:11.040248 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:39) [common]
294 08:44:11.040781 No LXC device requested
295 08:44:11.041361 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 08:44:11.041943 start: 1.8 deploy-device-env (timeout 00:08:39) [common]
297 08:44:11.042504 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 08:44:11.042964 Checking files for TFTP limit of 4294967296 bytes.
299 08:44:11.046018 end: 1 tftp-deploy (duration 00:01:21) [common]
300 08:44:11.046679 start: 2 uboot-action (timeout 00:05:00) [common]
301 08:44:11.047275 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 08:44:11.047874 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 08:44:11.048501 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 08:44:11.049102 Using kernel file from prepare-kernel: 742845/tftp-deploy-dax833k9/kernel/uImage
305 08:44:11.049810 substitutions:
306 08:44:11.050275 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 08:44:11.050731 - {DTB_ADDR}: 0x01070000
308 08:44:11.051181 - {DTB}: 742845/tftp-deploy-dax833k9/dtb/meson-g12b-a311d-libretech-cc.dtb
309 08:44:11.051634 - {INITRD}: 742845/tftp-deploy-dax833k9/ramdisk/ramdisk.cpio.gz.uboot
310 08:44:11.052118 - {KERNEL_ADDR}: 0x01080000
311 08:44:11.052570 - {KERNEL}: 742845/tftp-deploy-dax833k9/kernel/uImage
312 08:44:11.053016 - {LAVA_MAC}: None
313 08:44:11.053502 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/742845/extract-nfsrootfs-1xjfryqp
314 08:44:11.053954 - {NFS_SERVER_IP}: 192.168.6.2
315 08:44:11.054397 - {PRESEED_CONFIG}: None
316 08:44:11.054835 - {PRESEED_LOCAL}: None
317 08:44:11.055274 - {RAMDISK_ADDR}: 0x08000000
318 08:44:11.055707 - {RAMDISK}: 742845/tftp-deploy-dax833k9/ramdisk/ramdisk.cpio.gz.uboot
319 08:44:11.056182 - {ROOT_PART}: None
320 08:44:11.056623 - {ROOT}: None
321 08:44:11.057058 - {SERVER_IP}: 192.168.6.2
322 08:44:11.057493 - {TEE_ADDR}: 0x83000000
323 08:44:11.057928 - {TEE}: None
324 08:44:11.058361 Parsed boot commands:
325 08:44:11.058782 - setenv autoload no
326 08:44:11.059214 - setenv initrd_high 0xffffffff
327 08:44:11.059646 - setenv fdt_high 0xffffffff
328 08:44:11.060105 - dhcp
329 08:44:11.060547 - setenv serverip 192.168.6.2
330 08:44:11.060997 - tftpboot 0x01080000 742845/tftp-deploy-dax833k9/kernel/uImage
331 08:44:11.061498 - tftpboot 0x08000000 742845/tftp-deploy-dax833k9/ramdisk/ramdisk.cpio.gz.uboot
332 08:44:11.061973 - tftpboot 0x01070000 742845/tftp-deploy-dax833k9/dtb/meson-g12b-a311d-libretech-cc.dtb
333 08:44:11.062421 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/742845/extract-nfsrootfs-1xjfryqp,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 08:44:11.062873 - bootm 0x01080000 0x08000000 0x01070000
335 08:44:11.063451 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 08:44:11.065177 start: 2.3 connect-device (timeout 00:05:00) [common]
338 08:44:11.065657 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 08:44:11.081524 Setting prompt string to ['lava-test: # ']
340 08:44:11.083192 end: 2.3 connect-device (duration 00:00:00) [common]
341 08:44:11.083891 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 08:44:11.084608 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 08:44:11.085266 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 08:44:11.086527 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 08:44:11.121750 >> OK - accepted request
346 08:44:11.124181 Returned 0 in 0 seconds
347 08:44:11.225435 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 08:44:11.227295 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 08:44:11.227952 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 08:44:11.228607 Setting prompt string to ['Hit any key to stop autoboot']
352 08:44:11.229125 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 08:44:11.230845 Trying 192.168.56.21...
354 08:44:11.231372 Connected to conserv1.
355 08:44:11.231848 Escape character is '^]'.
356 08:44:11.232483
357 08:44:11.232969 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 08:44:11.233450
359 08:44:23.423070 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 08:44:23.423743 bl2_stage_init 0x01
361 08:44:23.424273 bl2_stage_init 0x81
362 08:44:23.428598 hw id: 0x0000 - pwm id 0x01
363 08:44:23.429159 bl2_stage_init 0xc1
364 08:44:23.429805 bl2_stage_init 0x02
365 08:44:23.430287
366 08:44:23.434266 L0:00000000
367 08:44:23.435014 L1:20000703
368 08:44:23.435504 L2:00008067
369 08:44:23.435960 L3:14000000
370 08:44:23.439808 B2:00402000
371 08:44:23.440400 B1:e0f83180
372 08:44:23.440868
373 08:44:23.441315 TE: 58124
374 08:44:23.441855
375 08:44:23.445425 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 08:44:23.445964
377 08:44:23.446416 Board ID = 1
378 08:44:23.451010 Set A53 clk to 24M
379 08:44:23.451536 Set A73 clk to 24M
380 08:44:23.452019 Set clk81 to 24M
381 08:44:23.456629 A53 clk: 1200 MHz
382 08:44:23.457175 A73 clk: 1200 MHz
383 08:44:23.457646 CLK81: 166.6M
384 08:44:23.458115 smccc: 00012a92
385 08:44:23.462155 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 08:44:23.467714 board id: 1
387 08:44:23.473747 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 08:44:23.484213 fw parse done
389 08:44:23.490145 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 08:44:23.532813 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 08:44:23.543686 PIEI prepare done
392 08:44:23.544192 fastboot data load
393 08:44:23.544631 fastboot data verify
394 08:44:23.549416 verify result: 266
395 08:44:23.555081 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 08:44:23.555591 LPDDR4 probe
397 08:44:23.556066 ddr clk to 1584MHz
398 08:44:23.562348 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 08:44:23.600311
400 08:44:23.600911 dmc_version 0001
401 08:44:23.606882 Check phy result
402 08:44:23.612848 INFO : End of CA training
403 08:44:23.613354 INFO : End of initialization
404 08:44:23.618354 INFO : Training has run successfully!
405 08:44:23.618851 Check phy result
406 08:44:23.623952 INFO : End of initialization
407 08:44:23.624483 INFO : End of read enable training
408 08:44:23.629571 INFO : End of fine write leveling
409 08:44:23.635130 INFO : End of Write leveling coarse delay
410 08:44:23.635609 INFO : Training has run successfully!
411 08:44:23.636102 Check phy result
412 08:44:23.640731 INFO : End of initialization
413 08:44:23.641215 INFO : End of read dq deskew training
414 08:44:23.646330 INFO : End of MPR read delay center optimization
415 08:44:23.651922 INFO : End of write delay center optimization
416 08:44:23.657578 INFO : End of read delay center optimization
417 08:44:23.658094 INFO : End of max read latency training
418 08:44:23.663122 INFO : Training has run successfully!
419 08:44:23.663604 1D training succeed
420 08:44:23.671350 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 08:44:23.720062 Check phy result
422 08:44:23.720596 INFO : End of initialization
423 08:44:23.741753 INFO : End of 2D read delay Voltage center optimization
424 08:44:23.761861 INFO : End of 2D read delay Voltage center optimization
425 08:44:23.813959 INFO : End of 2D write delay Voltage center optimization
426 08:44:23.863319 INFO : End of 2D write delay Voltage center optimization
427 08:44:23.868837 INFO : Training has run successfully!
428 08:44:23.869323
429 08:44:23.869776 channel==0
430 08:44:23.874402 RxClkDly_Margin_A0==88 ps 9
431 08:44:23.874894 TxDqDly_Margin_A0==98 ps 10
432 08:44:23.877731 RxClkDly_Margin_A1==88 ps 9
433 08:44:23.878202 TxDqDly_Margin_A1==98 ps 10
434 08:44:23.883269 TrainedVREFDQ_A0==74
435 08:44:23.883746 TrainedVREFDQ_A1==75
436 08:44:23.888922 VrefDac_Margin_A0==25
437 08:44:23.889398 DeviceVref_Margin_A0==40
438 08:44:23.889846 VrefDac_Margin_A1==25
439 08:44:23.894502 DeviceVref_Margin_A1==39
440 08:44:23.894982
441 08:44:23.895435
442 08:44:23.895880 channel==1
443 08:44:23.896364 RxClkDly_Margin_A0==98 ps 10
444 08:44:23.900093 TxDqDly_Margin_A0==98 ps 10
445 08:44:23.900581 RxClkDly_Margin_A1==98 ps 10
446 08:44:23.905765 TxDqDly_Margin_A1==88 ps 9
447 08:44:23.906247 TrainedVREFDQ_A0==77
448 08:44:23.906696 TrainedVREFDQ_A1==77
449 08:44:23.911333 VrefDac_Margin_A0==22
450 08:44:23.911807 DeviceVref_Margin_A0==37
451 08:44:23.916888 VrefDac_Margin_A1==22
452 08:44:23.917366 DeviceVref_Margin_A1==37
453 08:44:23.917811
454 08:44:23.922491 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 08:44:23.922983
456 08:44:23.950486 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 08:44:23.956103 2D training succeed
458 08:44:23.961745 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 08:44:23.962228 auto size-- 65535DDR cs0 size: 2048MB
460 08:44:23.967313 DDR cs1 size: 2048MB
461 08:44:23.967786 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 08:44:23.972865 cs0 DataBus test pass
463 08:44:23.973338 cs1 DataBus test pass
464 08:44:23.973784 cs0 AddrBus test pass
465 08:44:23.978550 cs1 AddrBus test pass
466 08:44:23.979069
467 08:44:23.979543 100bdlr_step_size ps== 420
468 08:44:23.980033 result report
469 08:44:23.984121 boot times 0Enable ddr reg access
470 08:44:23.991918 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 08:44:24.005376 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 08:44:24.578985 0.0;M3 CHK:0;cm4_sp_mode 0
473 08:44:24.579416 MVN_1=0x00000000
474 08:44:24.584484 MVN_2=0x00000000
475 08:44:24.590257 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 08:44:24.590666 OPS=0x10
477 08:44:24.590905 ring efuse init
478 08:44:24.591110 chipver efuse init
479 08:44:24.595828 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 08:44:24.601444 [0.018961 Inits done]
481 08:44:24.601882 secure task start!
482 08:44:24.602459 high task start!
483 08:44:24.605098 low task start!
484 08:44:24.605643 run into bl31
485 08:44:24.612782 NOTICE: BL31: v1.3(release):4fc40b1
486 08:44:24.620514 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 08:44:24.621052 NOTICE: BL31: G12A normal boot!
488 08:44:24.645954 NOTICE: BL31: BL33 decompress pass
489 08:44:24.651711 ERROR: Error initializing runtime service opteed_fast
490 08:44:25.884534
491 08:44:25.885209
492 08:44:25.892468 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 08:44:25.893043
494 08:44:25.893527 Model: Libre Computer AML-A311D-CC Alta
495 08:44:26.101448 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 08:44:26.123977 DRAM: 2 GiB (effective 3.8 GiB)
497 08:44:26.267847 Core: 408 devices, 31 uclasses, devicetree: separate
498 08:44:26.273621 WDT: Not starting watchdog@f0d0
499 08:44:26.306007 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 08:44:26.318337 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 08:44:26.323319 ** Bad device specification mmc 0 **
502 08:44:26.333622 Card did not respond to voltage select! : -110
503 08:44:26.341261 ** Bad device specification mmc 0 **
504 08:44:26.341804 Couldn't find partition mmc 0
505 08:44:26.349668 Card did not respond to voltage select! : -110
506 08:44:26.355153 ** Bad device specification mmc 0 **
507 08:44:26.355701 Couldn't find partition mmc 0
508 08:44:26.359293 Error: could not access storage.
509 08:44:27.613335 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 08:44:27.613949 bl2_stage_init 0x01
511 08:44:27.614179 bl2_stage_init 0x81
512 08:44:27.618718 hw id: 0x0000 - pwm id 0x01
513 08:44:27.619255 bl2_stage_init 0xc1
514 08:44:27.619733 bl2_stage_init 0x02
515 08:44:27.620248
516 08:44:27.624324 L0:00000000
517 08:44:27.624841 L1:20000703
518 08:44:27.625324 L2:00008067
519 08:44:27.625787 L3:14000000
520 08:44:27.627146 B2:00402000
521 08:44:27.627433 B1:e0f83180
522 08:44:27.627915
523 08:44:27.628415 TE: 58124
524 08:44:27.628897
525 08:44:27.638383 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 08:44:27.638916
527 08:44:27.639379 Board ID = 1
528 08:44:27.639832 Set A53 clk to 24M
529 08:44:27.640336 Set A73 clk to 24M
530 08:44:27.644092 Set clk81 to 24M
531 08:44:27.644612 A53 clk: 1200 MHz
532 08:44:27.645064 A73 clk: 1200 MHz
533 08:44:27.649501 CLK81: 166.6M
534 08:44:27.649776 smccc: 00012a92
535 08:44:27.655279 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 08:44:27.655815 board id: 1
537 08:44:27.660714 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 08:44:27.674564 fw parse done
539 08:44:27.680460 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 08:44:27.723340 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 08:44:27.734041 PIEI prepare done
542 08:44:27.734621 fastboot data load
543 08:44:27.735093 fastboot data verify
544 08:44:27.739591 verify result: 266
545 08:44:27.745340 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 08:44:27.745963 LPDDR4 probe
547 08:44:27.746421 ddr clk to 1584MHz
548 08:44:27.752350 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 08:44:27.790561
550 08:44:27.791262 dmc_version 0001
551 08:44:27.797199 Check phy result
552 08:44:27.802983 INFO : End of CA training
553 08:44:27.803610 INFO : End of initialization
554 08:44:27.808685 INFO : Training has run successfully!
555 08:44:27.809264 Check phy result
556 08:44:27.814293 INFO : End of initialization
557 08:44:27.814854 INFO : End of read enable training
558 08:44:27.817451 INFO : End of fine write leveling
559 08:44:27.823123 INFO : End of Write leveling coarse delay
560 08:44:27.828709 INFO : Training has run successfully!
561 08:44:27.829265 Check phy result
562 08:44:27.829717 INFO : End of initialization
563 08:44:27.834384 INFO : End of read dq deskew training
564 08:44:27.839899 INFO : End of MPR read delay center optimization
565 08:44:27.840498 INFO : End of write delay center optimization
566 08:44:27.845494 INFO : End of read delay center optimization
567 08:44:27.850963 INFO : End of max read latency training
568 08:44:27.851310 INFO : Training has run successfully!
569 08:44:27.856674 1D training succeed
570 08:44:27.862660 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 08:44:27.910260 Check phy result
572 08:44:27.910940 INFO : End of initialization
573 08:44:27.932779 INFO : End of 2D read delay Voltage center optimization
574 08:44:27.952146 INFO : End of 2D read delay Voltage center optimization
575 08:44:28.003686 INFO : End of 2D write delay Voltage center optimization
576 08:44:28.053619 INFO : End of 2D write delay Voltage center optimization
577 08:44:28.059110 INFO : Training has run successfully!
578 08:44:28.059429
579 08:44:28.059664 channel==0
580 08:44:28.064695 RxClkDly_Margin_A0==88 ps 9
581 08:44:28.065272 TxDqDly_Margin_A0==98 ps 10
582 08:44:28.070411 RxClkDly_Margin_A1==88 ps 9
583 08:44:28.070729 TxDqDly_Margin_A1==88 ps 9
584 08:44:28.070942 TrainedVREFDQ_A0==74
585 08:44:28.075766 TrainedVREFDQ_A1==74
586 08:44:28.076097 VrefDac_Margin_A0==24
587 08:44:28.076503 DeviceVref_Margin_A0==40
588 08:44:28.081539 VrefDac_Margin_A1==24
589 08:44:28.082102 DeviceVref_Margin_A1==40
590 08:44:28.082661
591 08:44:28.083146
592 08:44:28.083611 channel==1
593 08:44:28.086919 RxClkDly_Margin_A0==88 ps 9
594 08:44:28.087434 TxDqDly_Margin_A0==88 ps 9
595 08:44:28.092719 RxClkDly_Margin_A1==98 ps 10
596 08:44:28.093300 TxDqDly_Margin_A1==88 ps 9
597 08:44:28.098400 TrainedVREFDQ_A0==77
598 08:44:28.098706 TrainedVREFDQ_A1==77
599 08:44:28.098911 VrefDac_Margin_A0==23
600 08:44:28.103901 DeviceVref_Margin_A0==37
601 08:44:28.104503 VrefDac_Margin_A1==23
602 08:44:28.109541 DeviceVref_Margin_A1==37
603 08:44:28.110117
604 08:44:28.110570 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 08:44:28.111013
606 08:44:28.143155 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
607 08:44:28.143832 2D training succeed
608 08:44:28.148720 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 08:44:28.154410 auto size-- 65535DDR cs0 size: 2048MB
610 08:44:28.154988 DDR cs1 size: 2048MB
611 08:44:28.159931 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 08:44:28.160546 cs0 DataBus test pass
613 08:44:28.165514 cs1 DataBus test pass
614 08:44:28.166140 cs0 AddrBus test pass
615 08:44:28.166896 cs1 AddrBus test pass
616 08:44:28.167357
617 08:44:28.170992 100bdlr_step_size ps== 420
618 08:44:28.171349 result report
619 08:44:28.176534 boot times 0Enable ddr reg access
620 08:44:28.180926 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 08:44:28.195394 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 08:44:28.769251 0.0;M3 CHK:0;cm4_sp_mode 0
623 08:44:28.769903 MVN_1=0x00000000
624 08:44:28.774643 MVN_2=0x00000000
625 08:44:28.780417 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 08:44:28.780996 OPS=0x10
627 08:44:28.781472 ring efuse init
628 08:44:28.781930 chipver efuse init
629 08:44:28.788554 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 08:44:28.789131 [0.018961 Inits done]
631 08:44:28.796110 secure task start!
632 08:44:28.796425 high task start!
633 08:44:28.796662 low task start!
634 08:44:28.796884 run into bl31
635 08:44:28.802994 NOTICE: BL31: v1.3(release):4fc40b1
636 08:44:28.810478 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 08:44:28.810809 NOTICE: BL31: G12A normal boot!
638 08:44:28.836403 NOTICE: BL31: BL33 decompress pass
639 08:44:28.841936 ERROR: Error initializing runtime service opteed_fast
640 08:44:30.075014
641 08:44:30.075667
642 08:44:30.083432 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 08:44:30.083961
644 08:44:30.084446 Model: Libre Computer AML-A311D-CC Alta
645 08:44:30.291902 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 08:44:30.315205 DRAM: 2 GiB (effective 3.8 GiB)
647 08:44:30.458106 Core: 408 devices, 31 uclasses, devicetree: separate
648 08:44:30.464110 WDT: Not starting watchdog@f0d0
649 08:44:30.496268 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 08:44:30.508747 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 08:44:30.513752 ** Bad device specification mmc 0 **
652 08:44:30.524090 Card did not respond to voltage select! : -110
653 08:44:30.531774 ** Bad device specification mmc 0 **
654 08:44:30.532317 Couldn't find partition mmc 0
655 08:44:30.540173 Card did not respond to voltage select! : -110
656 08:44:30.545635 ** Bad device specification mmc 0 **
657 08:44:30.546137 Couldn't find partition mmc 0
658 08:44:30.550607 Error: could not access storage.
659 08:44:30.892265 Net: eth0: ethernet@ff3f0000
660 08:44:30.892826 starting USB...
661 08:44:31.144828 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 08:44:31.145484 Starting the controller
663 08:44:31.151858 USB XHCI 1.10
664 08:44:32.863507 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 08:44:32.863937 bl2_stage_init 0x01
666 08:44:32.864225 bl2_stage_init 0x81
667 08:44:32.869058 hw id: 0x0000 - pwm id 0x01
668 08:44:32.869352 bl2_stage_init 0xc1
669 08:44:32.869575 bl2_stage_init 0x02
670 08:44:32.869789
671 08:44:32.874635 L0:00000000
672 08:44:32.875037 L1:20000703
673 08:44:32.875375 L2:00008067
674 08:44:32.875697 L3:14000000
675 08:44:32.877441 B2:00402000
676 08:44:32.877828 B1:e0f83180
677 08:44:32.878159
678 08:44:32.878484 TE: 58167
679 08:44:32.878724
680 08:44:32.888613 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 08:44:32.888925
682 08:44:32.889166 Board ID = 1
683 08:44:32.889392 Set A53 clk to 24M
684 08:44:32.889604 Set A73 clk to 24M
685 08:44:32.894276 Set clk81 to 24M
686 08:44:32.894598 A53 clk: 1200 MHz
687 08:44:32.894816 A73 clk: 1200 MHz
688 08:44:32.897703 CLK81: 166.6M
689 08:44:32.897997 smccc: 00012abd
690 08:44:32.903316 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 08:44:32.908980 board id: 1
692 08:44:32.913839 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 08:44:32.924787 fw parse done
694 08:44:32.930748 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 08:44:32.973350 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 08:44:32.984330 PIEI prepare done
697 08:44:32.984831 fastboot data load
698 08:44:32.985087 fastboot data verify
699 08:44:32.990049 verify result: 266
700 08:44:32.995506 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 08:44:32.995823 LPDDR4 probe
702 08:44:32.996078 ddr clk to 1584MHz
703 08:44:33.003479 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 08:44:33.040759
705 08:44:33.041138 dmc_version 0001
706 08:44:33.047412 Check phy result
707 08:44:33.053276 INFO : End of CA training
708 08:44:33.053594 INFO : End of initialization
709 08:44:33.058859 INFO : Training has run successfully!
710 08:44:33.059286 Check phy result
711 08:44:33.064440 INFO : End of initialization
712 08:44:33.064739 INFO : End of read enable training
713 08:44:33.070092 INFO : End of fine write leveling
714 08:44:33.075782 INFO : End of Write leveling coarse delay
715 08:44:33.076243 INFO : Training has run successfully!
716 08:44:33.076491 Check phy result
717 08:44:33.081266 INFO : End of initialization
718 08:44:33.081581 INFO : End of read dq deskew training
719 08:44:33.086886 INFO : End of MPR read delay center optimization
720 08:44:33.092405 INFO : End of write delay center optimization
721 08:44:33.097992 INFO : End of read delay center optimization
722 08:44:33.098511 INFO : End of max read latency training
723 08:44:33.103583 INFO : Training has run successfully!
724 08:44:33.104160 1D training succeed
725 08:44:33.112765 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 08:44:33.160429 Check phy result
727 08:44:33.161043 INFO : End of initialization
728 08:44:33.182154 INFO : End of 2D read delay Voltage center optimization
729 08:44:33.200550 INFO : End of 2D read delay Voltage center optimization
730 08:44:33.252664 INFO : End of 2D write delay Voltage center optimization
731 08:44:33.303041 INFO : End of 2D write delay Voltage center optimization
732 08:44:33.308471 INFO : Training has run successfully!
733 08:44:33.308846
734 08:44:33.309089 channel==0
735 08:44:33.314052 RxClkDly_Margin_A0==88 ps 9
736 08:44:33.314396 TxDqDly_Margin_A0==98 ps 10
737 08:44:33.319686 RxClkDly_Margin_A1==88 ps 9
738 08:44:33.320182 TxDqDly_Margin_A1==98 ps 10
739 08:44:33.320594 TrainedVREFDQ_A0==74
740 08:44:33.325352 TrainedVREFDQ_A1==74
741 08:44:33.325743 VrefDac_Margin_A0==25
742 08:44:33.326016 DeviceVref_Margin_A0==40
743 08:44:33.332267 VrefDac_Margin_A1==25
744 08:44:33.332854 DeviceVref_Margin_A1==40
745 08:44:33.333258
746 08:44:33.333633
747 08:44:33.336568 channel==1
748 08:44:33.337128 RxClkDly_Margin_A0==98 ps 10
749 08:44:33.337418 TxDqDly_Margin_A0==88 ps 9
750 08:44:33.342180 RxClkDly_Margin_A1==88 ps 9
751 08:44:33.342714 TxDqDly_Margin_A1==88 ps 9
752 08:44:33.347805 TrainedVREFDQ_A0==75
753 08:44:33.348224 TrainedVREFDQ_A1==77
754 08:44:33.348446 VrefDac_Margin_A0==23
755 08:44:33.353297 DeviceVref_Margin_A0==39
756 08:44:33.353690 VrefDac_Margin_A1==24
757 08:44:33.359099 DeviceVref_Margin_A1==37
758 08:44:33.359669
759 08:44:33.360106 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 08:44:33.360389
761 08:44:33.392503 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 08:44:33.392948 2D training succeed
763 08:44:33.398152 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 08:44:33.403682 auto size-- 65535DDR cs0 size: 2048MB
765 08:44:33.404212 DDR cs1 size: 2048MB
766 08:44:33.409269 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 08:44:33.409594 cs0 DataBus test pass
768 08:44:33.414979 cs1 DataBus test pass
769 08:44:33.415420 cs0 AddrBus test pass
770 08:44:33.415783 cs1 AddrBus test pass
771 08:44:33.416160
772 08:44:33.420482 100bdlr_step_size ps== 420
773 08:44:33.420814 result report
774 08:44:33.426069 boot times 0Enable ddr reg access
775 08:44:33.430360 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 08:44:33.444791 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 08:44:34.018541 0.0;M3 CHK:0;cm4_sp_mode 0
778 08:44:34.019148 MVN_1=0x00000000
779 08:44:34.024108 MVN_2=0x00000000
780 08:44:34.029868 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 08:44:34.030444 OPS=0x10
782 08:44:34.030848 ring efuse init
783 08:44:34.031239 chipver efuse init
784 08:44:34.035396 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 08:44:34.041035 [0.018961 Inits done]
786 08:44:34.041495 secure task start!
787 08:44:34.041891 high task start!
788 08:44:34.045576 low task start!
789 08:44:34.046048 run into bl31
790 08:44:34.052265 NOTICE: BL31: v1.3(release):4fc40b1
791 08:44:34.060158 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 08:44:34.060662 NOTICE: BL31: G12A normal boot!
793 08:44:34.085454 NOTICE: BL31: BL33 decompress pass
794 08:44:34.091143 ERROR: Error initializing runtime service opteed_fast
795 08:44:35.323975
796 08:44:35.324715
797 08:44:35.332393 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 08:44:35.332857
799 08:44:35.333274 Model: Libre Computer AML-A311D-CC Alta
800 08:44:35.540909 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 08:44:35.564282 DRAM: 2 GiB (effective 3.8 GiB)
802 08:44:35.707242 Core: 408 devices, 31 uclasses, devicetree: separate
803 08:44:35.713090 WDT: Not starting watchdog@f0d0
804 08:44:35.745392 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 08:44:35.757912 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 08:44:35.762841 ** Bad device specification mmc 0 **
807 08:44:35.773249 Card did not respond to voltage select! : -110
808 08:44:35.780802 ** Bad device specification mmc 0 **
809 08:44:35.781282 Couldn't find partition mmc 0
810 08:44:35.789215 Card did not respond to voltage select! : -110
811 08:44:35.794672 ** Bad device specification mmc 0 **
812 08:44:35.795181 Couldn't find partition mmc 0
813 08:44:35.799724 Error: could not access storage.
814 08:44:36.142504 Net: eth0: ethernet@ff3f0000
815 08:44:36.143141 starting USB...
816 08:44:36.395152 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 08:44:36.395760 Starting the controller
818 08:44:36.401987 USB XHCI 1.10
819 08:44:38.563924 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 08:44:38.564405 bl2_stage_init 0x01
821 08:44:38.564758 bl2_stage_init 0x81
822 08:44:38.569405 hw id: 0x0000 - pwm id 0x01
823 08:44:38.569741 bl2_stage_init 0xc1
824 08:44:38.569981 bl2_stage_init 0x02
825 08:44:38.570207
826 08:44:38.574842 L0:00000000
827 08:44:38.575167 L1:20000703
828 08:44:38.575410 L2:00008067
829 08:44:38.575738 L3:14000000
830 08:44:38.580348 B2:00402000
831 08:44:38.580663 B1:e0f83180
832 08:44:38.580900
833 08:44:38.581261 TE: 58159
834 08:44:38.581597
835 08:44:38.585880 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 08:44:38.586302
837 08:44:38.586679 Board ID = 1
838 08:44:38.591430 Set A53 clk to 24M
839 08:44:38.591842 Set A73 clk to 24M
840 08:44:38.592222 Set clk81 to 24M
841 08:44:38.597069 A53 clk: 1200 MHz
842 08:44:38.597499 A73 clk: 1200 MHz
843 08:44:38.597843 CLK81: 166.6M
844 08:44:38.598175 smccc: 00012ab5
845 08:44:38.602585 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 08:44:38.608393 board id: 1
847 08:44:38.614142 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 08:44:38.626372 fw parse done
849 08:44:38.630795 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 08:44:38.673450 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 08:44:38.684326 PIEI prepare done
852 08:44:38.684926 fastboot data load
853 08:44:38.685387 fastboot data verify
854 08:44:38.690003 verify result: 266
855 08:44:38.695605 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 08:44:38.696223 LPDDR4 probe
857 08:44:38.696683 ddr clk to 1584MHz
858 08:44:38.703575 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 08:44:38.740755
860 08:44:38.741148 dmc_version 0001
861 08:44:38.747142 Check phy result
862 08:44:38.753468 INFO : End of CA training
863 08:44:38.753883 INFO : End of initialization
864 08:44:38.758918 INFO : Training has run successfully!
865 08:44:38.759312 Check phy result
866 08:44:38.764489 INFO : End of initialization
867 08:44:38.764833 INFO : End of read enable training
868 08:44:38.770145 INFO : End of fine write leveling
869 08:44:38.775914 INFO : End of Write leveling coarse delay
870 08:44:38.776329 INFO : Training has run successfully!
871 08:44:38.776582 Check phy result
872 08:44:38.781291 INFO : End of initialization
873 08:44:38.781660 INFO : End of read dq deskew training
874 08:44:38.786858 INFO : End of MPR read delay center optimization
875 08:44:38.792460 INFO : End of write delay center optimization
876 08:44:38.798038 INFO : End of read delay center optimization
877 08:44:38.798523 INFO : End of max read latency training
878 08:44:38.803729 INFO : Training has run successfully!
879 08:44:38.804273 1D training succeed
880 08:44:38.812820 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 08:44:38.860721 Check phy result
882 08:44:38.861180 INFO : End of initialization
883 08:44:38.882316 INFO : End of 2D read delay Voltage center optimization
884 08:44:38.902442 INFO : End of 2D read delay Voltage center optimization
885 08:44:38.954327 INFO : End of 2D write delay Voltage center optimization
886 08:44:39.003433 INFO : End of 2D write delay Voltage center optimization
887 08:44:39.008996 INFO : Training has run successfully!
888 08:44:39.009621
889 08:44:39.010176 channel==0
890 08:44:39.014569 RxClkDly_Margin_A0==88 ps 9
891 08:44:39.015165 TxDqDly_Margin_A0==98 ps 10
892 08:44:39.020227 RxClkDly_Margin_A1==88 ps 9
893 08:44:39.020826 TxDqDly_Margin_A1==98 ps 10
894 08:44:39.021417 TrainedVREFDQ_A0==74
895 08:44:39.025879 TrainedVREFDQ_A1==74
896 08:44:39.026529 VrefDac_Margin_A0==25
897 08:44:39.027098 DeviceVref_Margin_A0==40
898 08:44:39.031361 VrefDac_Margin_A1==25
899 08:44:39.032006 DeviceVref_Margin_A1==40
900 08:44:39.032538
901 08:44:39.033047
902 08:44:39.037007 channel==1
903 08:44:39.037569 RxClkDly_Margin_A0==98 ps 10
904 08:44:39.038081 TxDqDly_Margin_A0==98 ps 10
905 08:44:39.042599 RxClkDly_Margin_A1==88 ps 9
906 08:44:39.043162 TxDqDly_Margin_A1==88 ps 9
907 08:44:39.048232 TrainedVREFDQ_A0==77
908 08:44:39.048857 TrainedVREFDQ_A1==77
909 08:44:39.049366 VrefDac_Margin_A0==22
910 08:44:39.053799 DeviceVref_Margin_A0==37
911 08:44:39.054388 VrefDac_Margin_A1==24
912 08:44:39.059455 DeviceVref_Margin_A1==37
913 08:44:39.060156
914 08:44:39.060696 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 08:44:39.061211
916 08:44:39.093022 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
917 08:44:39.093724 2D training succeed
918 08:44:39.098559 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 08:44:39.104054 auto size-- 65535DDR cs0 size: 2048MB
920 08:44:39.104642 DDR cs1 size: 2048MB
921 08:44:39.109670 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 08:44:39.110260 cs0 DataBus test pass
923 08:44:39.115207 cs1 DataBus test pass
924 08:44:39.115763 cs0 AddrBus test pass
925 08:44:39.116317 cs1 AddrBus test pass
926 08:44:39.116847
927 08:44:39.120822 100bdlr_step_size ps== 420
928 08:44:39.121394 result report
929 08:44:39.126409 boot times 0Enable ddr reg access
930 08:44:39.131806 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 08:44:39.145294 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 08:44:39.717256 0.0;M3 CHK:0;cm4_sp_mode 0
933 08:44:39.718076 MVN_1=0x00000000
934 08:44:39.723068 MVN_2=0x00000000
935 08:44:39.728436 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 08:44:39.728808 OPS=0x10
937 08:44:39.729076 ring efuse init
938 08:44:39.729363 chipver efuse init
939 08:44:39.734044 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 08:44:39.739630 [0.018961 Inits done]
941 08:44:39.739908 secure task start!
942 08:44:39.740144 high task start!
943 08:44:39.744192 low task start!
944 08:44:39.744438 run into bl31
945 08:44:39.750878 NOTICE: BL31: v1.3(release):4fc40b1
946 08:44:39.759073 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 08:44:39.759577 NOTICE: BL31: G12A normal boot!
948 08:44:39.784210 NOTICE: BL31: BL33 decompress pass
949 08:44:39.789815 ERROR: Error initializing runtime service opteed_fast
950 08:44:41.022756
951 08:44:41.023437
952 08:44:41.031173 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 08:44:41.031768
954 08:44:41.032254 Model: Libre Computer AML-A311D-CC Alta
955 08:44:41.239767 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 08:44:41.263178 DRAM: 2 GiB (effective 3.8 GiB)
957 08:44:41.406035 Core: 408 devices, 31 uclasses, devicetree: separate
958 08:44:41.411849 WDT: Not starting watchdog@f0d0
959 08:44:41.444157 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 08:44:41.456695 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 08:44:41.461535 ** Bad device specification mmc 0 **
962 08:44:41.471888 Card did not respond to voltage select! : -110
963 08:44:41.479484 ** Bad device specification mmc 0 **
964 08:44:41.479899 Couldn't find partition mmc 0
965 08:44:41.487840 Card did not respond to voltage select! : -110
966 08:44:41.493306 ** Bad device specification mmc 0 **
967 08:44:41.493672 Couldn't find partition mmc 0
968 08:44:41.498396 Error: could not access storage.
969 08:44:41.840862 Net: eth0: ethernet@ff3f0000
970 08:44:41.841484 starting USB...
971 08:44:42.092663 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 08:44:42.093082 Starting the controller
973 08:44:42.099616 USB XHCI 1.10
974 08:44:43.653820 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 08:44:43.662047 scanning usb for storage devices... 0 Storage Device(s) found
977 08:44:43.713552 Hit any key to stop autoboot: 1
978 08:44:43.714421 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
979 08:44:43.715014 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
980 08:44:43.715488 Setting prompt string to ['=>']
981 08:44:43.715977 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
982 08:44:43.729541 0
983 08:44:43.730421 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 08:44:43.730919 Sending with 10 millisecond of delay
986 08:44:44.865471 => setenv autoload no
987 08:44:44.876256 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
988 08:44:44.881173 setenv autoload no
989 08:44:44.881897 Sending with 10 millisecond of delay
991 08:44:46.678389 => setenv initrd_high 0xffffffff
992 08:44:46.689157 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
993 08:44:46.689978 setenv initrd_high 0xffffffff
994 08:44:46.690687 Sending with 10 millisecond of delay
996 08:44:48.307101 => setenv fdt_high 0xffffffff
997 08:44:48.318420 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
998 08:44:48.319261 setenv fdt_high 0xffffffff
999 08:44:48.319972 Sending with 10 millisecond of delay
1001 08:44:48.611806 => dhcp
1002 08:44:48.622651 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1003 08:44:48.623553 dhcp
1004 08:44:48.624054 Speed: 1000, full duplex
1005 08:44:48.624488 BOOTP broadcast 1
1006 08:44:48.870377 BOOTP broadcast 2
1007 08:44:48.901235 DHCP client bound to address 192.168.6.33 (278 ms)
1008 08:44:48.901968 Sending with 10 millisecond of delay
1010 08:44:50.578492 => setenv serverip 192.168.6.2
1011 08:44:50.589273 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1012 08:44:50.590176 setenv serverip 192.168.6.2
1013 08:44:50.590870 Sending with 10 millisecond of delay
1015 08:44:54.313697 => tftpboot 0x01080000 742845/tftp-deploy-dax833k9/kernel/uImage
1016 08:44:54.324457 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1017 08:44:54.325013 tftpboot 0x01080000 742845/tftp-deploy-dax833k9/kernel/uImage
1018 08:44:54.325268 Speed: 1000, full duplex
1019 08:44:54.325497 Using ethernet@ff3f0000 device
1020 08:44:54.326952 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1021 08:44:54.332415 Filename '742845/tftp-deploy-dax833k9/kernel/uImage'.
1022 08:44:54.336376 Load address: 0x1080000
1023 08:45:04.688663 Loading: *###############################################T ### 43.6 MiB
1024 08:45:04.689345 4.2 MiB/s
1025 08:45:04.689841 done
1026 08:45:04.693080 Bytes transferred = 45724224 (2b9b240 hex)
1027 08:45:04.693938 Sending with 10 millisecond of delay
1029 08:45:09.381088 => tftpboot 0x08000000 742845/tftp-deploy-dax833k9/ramdisk/ramdisk.cpio.gz.uboot
1030 08:45:09.391926 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
1031 08:45:09.392873 tftpboot 0x08000000 742845/tftp-deploy-dax833k9/ramdisk/ramdisk.cpio.gz.uboot
1032 08:45:09.393374 Speed: 1000, full duplex
1033 08:45:09.393839 Using ethernet@ff3f0000 device
1034 08:45:09.394894 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1035 08:45:09.406638 Filename '742845/tftp-deploy-dax833k9/ramdisk/ramdisk.cpio.gz.uboot'.
1036 08:45:09.407190 Load address: 0x8000000
1037 08:45:11.776120 Loading: *################################################## 22.4 MiB
1038 08:45:11.776797 9.4 MiB/s
1039 08:45:11.777279 done
1040 08:45:11.780634 Bytes transferred = 23441950 (165b21e hex)
1041 08:45:11.781931 Sending with 10 millisecond of delay
1043 08:45:16.952078 => tftpboot 0x01070000 742845/tftp-deploy-dax833k9/dtb/meson-g12b-a311d-libretech-cc.dtb
1044 08:45:16.962893 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:54)
1045 08:45:16.963784 tftpboot 0x01070000 742845/tftp-deploy-dax833k9/dtb/meson-g12b-a311d-libretech-cc.dtb
1046 08:45:16.964324 Speed: 1000, full duplex
1047 08:45:16.964771 Using ethernet@ff3f0000 device
1048 08:45:16.968132 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1049 08:45:16.981243 Filename '742845/tftp-deploy-dax833k9/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1050 08:45:16.981779 Load address: 0x1070000
1051 08:45:16.997880 Loading: *################################################## 53.4 KiB
1052 08:45:16.998390 2.9 MiB/s
1053 08:45:16.998833 done
1054 08:45:17.004390 Bytes transferred = 54703 (d5af hex)
1055 08:45:17.005178 Sending with 10 millisecond of delay
1057 08:45:30.305336 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/742845/extract-nfsrootfs-1xjfryqp,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1058 08:45:30.316194 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:41)
1059 08:45:30.317134 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/742845/extract-nfsrootfs-1xjfryqp,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1060 08:45:30.317898 Sending with 10 millisecond of delay
1062 08:45:32.656826 => bootm 0x01080000 0x08000000 0x01070000
1063 08:45:32.667669 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1064 08:45:32.668268 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:38)
1065 08:45:32.669347 bootm 0x01080000 0x08000000 0x01070000
1066 08:45:32.669837 ## Booting kernel from Legacy Image at 01080000 ...
1067 08:45:32.672614 Image Name:
1068 08:45:32.678514 Image Type: AArch64 Linux Kernel Image (uncompressed)
1069 08:45:32.679051 Data Size: 45724160 Bytes = 43.6 MiB
1070 08:45:32.683650 Load Address: 01080000
1071 08:45:32.684173 Entry Point: 01080000
1072 08:45:32.878959 Verifying Checksum ... OK
1073 08:45:32.879576 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1074 08:45:32.884577 Image Name:
1075 08:45:32.890007 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1076 08:45:32.890494 Data Size: 23441886 Bytes = 22.4 MiB
1077 08:45:32.895589 Load Address: 00000000
1078 08:45:32.896101 Entry Point: 00000000
1079 08:45:32.997763 Verifying Checksum ... OK
1080 08:45:32.998373 ## Flattened Device Tree blob at 01070000
1081 08:45:33.002976 Booting using the fdt blob at 0x1070000
1082 08:45:33.003466 Working FDT set to 1070000
1083 08:45:33.006513 Loading Kernel Image
1084 08:45:33.158866 Loading Ramdisk to 7e9a4000, end 7ffff1de ... OK
1085 08:45:33.164573 Loading Device Tree to 000000007e993000, end 000000007e9a35ae ... OK
1086 08:45:33.165098 Working FDT set to 7e993000
1087 08:45:33.169453
1088 08:45:33.169947 Starting kernel ...
1089 08:45:33.170409
1090 08:45:33.171364 end: 2.4.3 bootloader-commands (duration 00:00:49) [common]
1091 08:45:33.172050 start: 2.4.4 auto-login-action (timeout 00:03:38) [common]
1092 08:45:33.172585 Setting prompt string to ['Linux version [0-9]']
1093 08:45:33.173090 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1094 08:45:33.173605 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1095 08:45:33.207369 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1096 08:45:33.208516 start: 2.4.4.1 login-action (timeout 00:03:38) [common]
1097 08:45:33.209090 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1098 08:45:33.209603 Setting prompt string to []
1099 08:45:33.210136 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1100 08:45:33.210639 Using line separator: #'\n'#
1101 08:45:33.211091 No login prompt set.
1102 08:45:33.211562 Parsing kernel messages
1103 08:45:33.212041 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1104 08:45:33.212944 [login-action] Waiting for messages, (timeout 00:03:38)
1105 08:45:33.213446 Waiting using forced prompt support (timeout 00:01:49)
1106 08:45:33.223731 [ 0.000000] Linux version 6.11.0-next-20240919 (KernelCI@build-j314369-arm64-gcc-12-defconfig-9mqgb) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Thu Sep 19 06:58:18 UTC 2024
1107 08:45:33.229327 [ 0.000000] KASLR disabled due to lack of seed
1108 08:45:33.234863 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1109 08:45:33.240348 [ 0.000000] efi: UEFI not found.
1110 08:45:33.245901 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1111 08:45:33.256849 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1112 08:45:33.262375 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1113 08:45:33.273400 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1114 08:45:33.284465 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1115 08:45:33.289989 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1116 08:45:33.301035 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1117 08:45:33.306573 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1118 08:45:33.312194 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1119 08:45:33.317575 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1120 08:45:33.318125 [ 0.000000] Zone ranges:
1121 08:45:33.328691 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1122 08:45:33.329238 [ 0.000000] DMA32 empty
1123 08:45:33.334120 [ 0.000000] Normal empty
1124 08:45:33.334636 [ 0.000000] Movable zone start for each node
1125 08:45:33.339647 [ 0.000000] Early memory node ranges
1126 08:45:33.345223 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1127 08:45:33.350675 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1128 08:45:33.356203 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1129 08:45:33.364775 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1130 08:45:33.389971 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1131 08:45:33.395479 [ 0.000000] psci: probing for conduit method from DT.
1132 08:45:33.396071 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1133 08:45:33.401005 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1134 08:45:33.406524 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1135 08:45:33.412052 [ 0.000000] psci: SMC Calling Convention v1.1
1136 08:45:33.417562 [ 0.000000] percpu: Embedded 25 pages/cpu s61720 r8192 d32488 u102400
1137 08:45:33.423179 [ 0.000000] Detected VIPT I-cache on CPU0
1138 08:45:33.428613 [ 0.000000] CPU features: detected: ARM erratum 845719
1139 08:45:33.434564 [ 0.000000] alternatives: applying boot alternatives
1140 08:45:33.450685 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/742845/extract-nfsrootfs-1xjfryqp,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1141 08:45:33.461727 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1142 08:45:33.467228 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1143 08:45:33.472777 <6>[ 0.000000] Fallback order for Node 0: 0
1144 08:45:33.478291 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1145 08:45:33.483810 <6>[ 0.000000] Policy zone: DMA
1146 08:45:33.489349 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1147 08:45:33.494835 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1148 08:45:33.500346 <6>[ 0.000000] software IO TLB: area num 8.
1149 08:45:33.508425 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1150 08:45:33.556068 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1151 08:45:33.561541 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1152 08:45:33.567482 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1153 08:45:33.572558 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1154 08:45:33.578077 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1155 08:45:33.583626 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1156 08:45:33.589182 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1157 08:45:33.594632 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1158 08:45:33.605684 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1159 08:45:33.616734 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1160 08:45:33.622243 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1161 08:45:33.627731 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1162 08:45:33.628249 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1163 08:45:33.636744 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1164 08:45:33.650346 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1165 08:45:33.659366 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1166 08:45:33.664880 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1167 08:45:33.670452 <6>[ 0.008793] Console: colour dummy device 80x25
1168 08:45:33.681457 <6>[ 0.012939] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1169 08:45:33.686995 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1170 08:45:33.692520 <6>[ 0.028190] LSM: initializing lsm=capability
1171 08:45:33.698033 <6>[ 0.032729] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 08:45:33.709051 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1173 08:45:33.714586 <6>[ 0.050763] rcu: Hierarchical SRCU implementation.
1174 08:45:33.720083 <6>[ 0.053267] rcu: Max phase no-delay instances is 1000.
1175 08:45:33.725613 <6>[ 0.058872] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1176 08:45:33.731225 <6>[ 0.071557] EFI services will not be available.
1177 08:45:33.736718 <6>[ 0.072088] smp: Bringing up secondary CPUs ...
1178 08:45:33.742207 <6>[ 0.077154] Detected VIPT I-cache on CPU1
1179 08:45:33.747695 <6>[ 0.077274] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1180 08:45:33.753251 <6>[ 0.078621] CPU features: detected: Spectre-v2
1181 08:45:33.753732 <6>[ 0.078636] CPU features: detected: Spectre-v4
1182 08:45:33.758706 <6>[ 0.078641] CPU features: detected: Spectre-BHB
1183 08:45:33.764265 <6>[ 0.078647] CPU features: detected: ARM erratum 858921
1184 08:45:33.769767 <6>[ 0.078654] Detected VIPT I-cache on CPU2
1185 08:45:33.775265 <6>[ 0.078728] arch_timer: Enabling local workaround for ARM erratum 858921
1186 08:45:33.780804 <6>[ 0.078746] arch_timer: CPU2: Trapping CNTVCT access
1187 08:45:33.786354 <6>[ 0.078756] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1188 08:45:33.791867 <6>[ 0.079511] Detected VIPT I-cache on CPU3
1189 08:45:33.802880 <6>[ 0.079557] arch_timer: Enabling local workaround for ARM erratum 858921
1190 08:45:33.803370 <6>[ 0.079567] arch_timer: CPU3: Trapping CNTVCT access
1191 08:45:33.813933 <6>[ 0.079574] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1192 08:45:33.814466 <6>[ 0.080280] Detected VIPT I-cache on CPU4
1193 08:45:33.824983 <6>[ 0.080327] arch_timer: Enabling local workaround for ARM erratum 858921
1194 08:45:33.830508 <6>[ 0.080337] arch_timer: CPU4: Trapping CNTVCT access
1195 08:45:33.836050 <6>[ 0.080344] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1196 08:45:33.841514 <6>[ 0.081118] Detected VIPT I-cache on CPU5
1197 08:45:33.847063 <6>[ 0.081166] arch_timer: Enabling local workaround for ARM erratum 858921
1198 08:45:33.852595 <6>[ 0.081176] arch_timer: CPU5: Trapping CNTVCT access
1199 08:45:33.858105 <6>[ 0.081183] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1200 08:45:33.863608 <6>[ 0.081303] smp: Brought up 1 node, 6 CPUs
1201 08:45:33.869212 <6>[ 0.203226] SMP: Total of 6 processors activated.
1202 08:45:33.869694 <6>[ 0.208130] CPU: All CPU(s) started at EL2
1203 08:45:33.874639 <6>[ 0.212475] CPU features: detected: 32-bit EL0 Support
1204 08:45:33.880338 <6>[ 0.217788] CPU features: detected: 32-bit EL1 Support
1205 08:45:33.885714 <6>[ 0.223149] CPU features: detected: CRC32 instructions
1206 08:45:33.891232 <6>[ 0.228543] alternatives: applying system-wide alternatives
1207 08:45:33.907768 <6>[ 0.235727] Memory: 3557424K/4012396K available (17280K kernel code, 4908K rwdata, 11880K rodata, 10432K init, 742K bss, 187808K reserved, 262144K cma-reserved)
1208 08:45:33.914711 <6>[ 0.250070] devtmpfs: initialized
1209 08:45:33.920205 <6>[ 0.259251] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1210 08:45:33.931729 <6>[ 0.263607] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1211 08:45:33.936740 <6>[ 0.274398] 21392 pages in range for non-PLT usage
1212 08:45:33.942305 <6>[ 0.274409] 512912 pages in range for PLT usage
1213 08:45:33.947787 <6>[ 0.275963] pinctrl core: initialized pinctrl subsystem
1214 08:45:33.948295 <6>[ 0.288006] DMI not present or invalid.
1215 08:45:33.953323 <6>[ 0.292330] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1216 08:45:33.964400 <6>[ 0.297076] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1217 08:45:33.969890 <6>[ 0.303847] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1218 08:45:33.980913 <6>[ 0.311951] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1219 08:45:33.986429 <6>[ 0.319439] audit: initializing netlink subsys (disabled)
1220 08:45:33.991977 <5>[ 0.325187] audit: type=2000 audit(0.244:1): state=initialized audit_enabled=0 res=1
1221 08:45:33.997486 <6>[ 0.326659] thermal_sys: Registered thermal governor 'step_wise'
1222 08:45:34.002983 <6>[ 0.332948] thermal_sys: Registered thermal governor 'power_allocator'
1223 08:45:34.013146 <6>[ 0.339205] cpuidle: using governor menu
1224 08:45:34.014365 <6>[ 0.350186] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1225 08:45:34.019663 <6>[ 0.357120] ASID allocator initialised with 65536 entries
1226 08:45:34.026503 <6>[ 0.364648] Serial: AMBA PL011 UART driver
1227 08:45:34.036985 <6>[ 0.375259] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 08:45:34.052789 <6>[ 0.390769] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1229 08:45:34.063839 <6>[ 0.393436] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1230 08:45:34.069413 <6>[ 0.406607] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1231 08:45:34.074884 <6>[ 0.409816] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1232 08:45:34.085933 <6>[ 0.418241] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1233 08:45:34.091480 <6>[ 0.425866] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1234 08:45:34.102358 <6>[ 0.439480] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1235 08:45:34.107849 <6>[ 0.441683] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1236 08:45:34.113446 <6>[ 0.448171] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1237 08:45:34.118914 <6>[ 0.455142] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1238 08:45:34.129945 <6>[ 0.461611] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1239 08:45:34.135550 <6>[ 0.468597] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1240 08:45:34.141118 <6>[ 0.475066] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1241 08:45:34.146611 <6>[ 0.482051] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1242 08:45:34.152193 <6>[ 0.490072] ACPI: Interpreter disabled.
1243 08:45:34.157670 <6>[ 0.495569] iommu: Default domain type: Translated
1244 08:45:34.163142 <6>[ 0.497584] iommu: DMA domain TLB invalidation policy: strict mode
1245 08:45:34.168664 <5>[ 0.504268] SCSI subsystem initialized
1246 08:45:34.174264 <6>[ 0.508148] usbcore: registered new interface driver usbfs
1247 08:45:34.179742 <6>[ 0.513641] usbcore: registered new interface driver hub
1248 08:45:34.185270 <6>[ 0.519166] usbcore: registered new device driver usb
1249 08:45:34.190775 <6>[ 0.525427] pps_core: LinuxPPS API ver. 1 registered
1250 08:45:34.196396 <6>[ 0.529578] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1251 08:45:34.201864 <6>[ 0.538897] PTP clock support registered
1252 08:45:34.207377 <6>[ 0.543137] EDAC MC: Ver: 3.0.0
1253 08:45:34.212861 <6>[ 0.546781] scmi_core: SCMI protocol bus registered
1254 08:45:34.213354 <6>[ 0.552411] FPGA manager framework
1255 08:45:34.218396 <6>[ 0.555159] Advanced Linux Sound Architecture Driver Initialized.
1256 08:45:34.223924 <6>[ 0.562103] vgaarb: loaded
1257 08:45:34.229438 <6>[ 0.564640] clocksource: Switched to clocksource arch_sys_counter
1258 08:45:34.234964 <5>[ 0.570817] VFS: Disk quotas dquot_6.6.0
1259 08:45:34.240465 <6>[ 0.574793] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1260 08:45:34.245981 <6>[ 0.582161] pnp: PnP ACPI: disabled
1261 08:45:34.251542 <6>[ 0.590633] NET: Registered PF_INET protocol family
1262 08:45:34.257045 <6>[ 0.590849] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1263 08:45:34.268078 <6>[ 0.600992] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1264 08:45:34.273609 <6>[ 0.606997] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1265 08:45:34.284608 <6>[ 0.614893] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1266 08:45:34.290179 <6>[ 0.623126] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1267 08:45:34.295741 <6>[ 0.630919] TCP: Hash tables configured (established 32768 bind 32768)
1268 08:45:34.301203 <6>[ 0.637398] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 08:45:34.312254 <6>[ 0.644251] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1270 08:45:34.317749 <6>[ 0.651674] NET: Registered PF_UNIX/PF_LOCAL protocol family
1271 08:45:34.323337 <6>[ 0.657809] RPC: Registered named UNIX socket transport module.
1272 08:45:34.328816 <6>[ 0.663536] RPC: Registered udp transport module.
1273 08:45:34.334319 <6>[ 0.668441] RPC: Registered tcp transport module.
1274 08:45:34.339828 <6>[ 0.673355] RPC: Registered tcp-with-tls transport module.
1275 08:45:34.345390 <6>[ 0.679047] RPC: Registered tcp NFSv4.1 backchannel transport module.
1276 08:45:34.350884 <6>[ 0.685697] PCI: CLS 0 bytes, default 64
1277 08:45:34.351372 <6>[ 0.690020] Unpacking initramfs...
1278 08:45:34.356381 <6>[ 0.696140] kvm [1]: nv: 554 coarse grained trap handlers
1279 08:45:34.361920 <6>[ 0.699367] kvm [1]: IPA Size Limit: 40 bits
1280 08:45:34.367469 <6>[ 0.704984] kvm [1]: vgic interrupt IRQ9
1281 08:45:34.372991 <6>[ 0.707708] kvm [1]: Hyp nVHE mode initialized successfully
1282 08:45:34.378550 <5>[ 0.714557] Initialise system trusted keyrings
1283 08:45:34.384058 <6>[ 0.718308] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1284 08:45:34.389507 <6>[ 0.725007] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1285 08:45:34.395112 <5>[ 0.730992] NFS: Registering the id_resolver key type
1286 08:45:34.400589 <5>[ 0.736083] Key type id_resolver registered
1287 08:45:34.406103 <5>[ 0.740460] Key type id_legacy registered
1288 08:45:34.411596 <6>[ 0.744699] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1289 08:45:34.417140 <6>[ 0.751586] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1290 08:45:34.423571 <6>[ 0.759347] 9p: Installing v9fs 9p2000 file system support
1291 08:45:34.462252 <5>[ 0.805677] Key type asymmetric registered
1292 08:45:34.467718 <5>[ 0.805721] Asymmetric key parser 'x509' registered
1293 08:45:34.478710 <6>[ 0.809580] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1294 08:45:34.479204 <6>[ 0.817103] io scheduler mq-deadline registered
1295 08:45:34.484239 <6>[ 0.821837] io scheduler kyber registered
1296 08:45:34.489806 <6>[ 0.826104] io scheduler bfq registered
1297 08:45:34.495412 <6>[ 0.834389] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1298 08:45:34.511977 <6>[ 0.852536] ledtrig-cpu: registered to indicate activity on CPUs
1299 08:45:34.544546 <6>[ 0.883934] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1300 08:45:34.565272 <6>[ 0.897465] Serial: 8250/16550 driver, 4 ports<6>[ 0.902090] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1301 08:45:34.570794 <6>[ 0.911726] printk: legacy console [ttyAML0] enabled
1302 08:45:34.576360 <6>[ 0.911726] printk: legacy console [ttyAML0] enabled
1303 08:45:34.581887 <6>[ 0.916519] printk: legacy bootconsole [meson0] disabled
1304 08:45:34.587401 <6>[ 0.916519] printk: legacy bootconsole [meson0] disabled
1305 08:45:34.592990 <6>[ 0.929431] msm_serial: driver initialized
1306 08:45:34.598496 <6>[ 0.932489] SuperH (H)SCI(F) driver initialized
1307 08:45:34.598985 <6>[ 0.936997] STM32 USART driver initialized
1308 08:45:34.604044 <5>[ 0.943200] random: crng init done
1309 08:45:34.611113 <6>[ 0.948955] loop: module loaded
1310 08:45:34.611662 <6>[ 0.950220] megasas: 07.727.03.00-rc1
1311 08:45:34.616650 <6>[ 0.959055] tun: Universal TUN/TAP device driver, 1.6
1312 08:45:34.622196 <6>[ 0.960251] thunder_xcv, ver 1.0
1313 08:45:34.627708 <6>[ 0.962241] thunder_bgx, ver 1.0
1314 08:45:34.628228 <6>[ 0.965696] nicpf, ver 1.0
1315 08:45:34.633384 <6>[ 0.970237] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1316 08:45:34.638822 <6>[ 0.976085] hns3: Copyright (c) 2017 Huawei Corporation.
1317 08:45:34.644347 <6>[ 0.981670] hclge is initializing
1318 08:45:34.649916 <6>[ 0.985204] e1000: Intel(R) PRO/1000 Network Driver
1319 08:45:34.655463 <6>[ 0.990288] e1000: Copyright (c) 1999-2006 Intel Corporation.
1320 08:45:34.661019 <6>[ 0.996321] e1000e: Intel(R) PRO/1000 Network Driver
1321 08:45:34.666527 <6>[ 1.001468] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1322 08:45:34.672105 <6>[ 1.007653] igb: Intel(R) Gigabit Ethernet Network Driver
1323 08:45:34.677632 <6>[ 1.013254] igb: Copyright (c) 2007-2014 Intel Corporation.
1324 08:45:34.683179 <6>[ 1.019104] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1325 08:45:34.688770 <6>[ 1.025562] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1326 08:45:34.694272 <6>[ 1.032333] sky2: driver version 1.30
1327 08:45:34.699909 <6>[ 1.037400] VFIO - User Level meta-driver version: 0.3
1328 08:45:34.705390 <6>[ 1.044925] usbcore: registered new interface driver usb-storage
1329 08:45:34.711508 <6>[ 1.051139] i2c_dev: i2c /dev entries driver
1330 08:45:34.724244 <6>[ 1.062119] sdhci: Secure Digital Host Controller Interface driver
1331 08:45:34.724748 <6>[ 1.062925] sdhci: Copyright(c) Pierre Ossman
1332 08:45:34.735300 <6>[ 1.068663] Synopsys Designware Multimedia Card Interface Driver
1333 08:45:34.740840 <6>[ 1.075208] sdhci-pltfm: SDHCI platform and OF driver helper
1334 08:45:34.741331 <6>[ 1.082832] meson-sm: secure-monitor enabled
1335 08:45:34.752856 <6>[ 1.085422] usbcore: registered new interface driver usbhid
1336 08:45:34.753343 <6>[ 1.089993] usbhid: USB HID core driver
1337 08:45:34.761302 <6>[ 1.104687] NET: Registered PF_PACKET protocol family
1338 08:45:34.766750 <6>[ 1.104780] 9pnet: Installing 9P2000 support
1339 08:45:34.773857 <5>[ 1.108930] Key type dns_resolver registered
1340 08:45:34.779389 <6>[ 1.120481] registered taskstats version 1
1341 08:45:34.784877 <5>[ 1.120654] Loading compiled-in X.509 certificates
1342 08:45:34.787823 <6>[ 1.129325] Demotion targets for Node 0: null
1343 08:45:34.818096 <6>[ 1.161496] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1344 08:45:34.823561 <6>[ 1.161537] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1345 08:45:34.832536 <4>[ 1.170750] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1346 08:45:34.843592 <4>[ 1.174297] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1347 08:45:34.849146 <6>[ 1.181821] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1348 08:45:34.852653 <6>[ 1.191123] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1349 08:45:34.863720 <6>[ 1.194587] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1350 08:45:34.869280 <6>[ 1.202574] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1351 08:45:34.878336 <6>[ 1.212099] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1352 08:45:34.883799 <6>[ 1.218329] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1353 08:45:34.889395 <6>[ 1.223946] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1354 08:45:34.898377 <6>[ 1.231832] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1355 08:45:34.903899 <6>[ 1.239136] hub 1-0:1.0: USB hub found
1356 08:45:34.904414 <6>[ 1.242594] hub 1-0:1.0: 2 ports detected
1357 08:45:34.912950 <6>[ 1.248671] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1358 08:45:34.918466 <6>[ 1.255562] hub 2-0:1.0: USB hub found
1359 08:45:34.922063 <6>[ 1.259143] hub 2-0:1.0: 1 port detected
1360 08:45:34.948910 <6>[ 1.290200] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1361 08:45:34.961212 <6>[ 1.301283] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1362 08:45:34.995215 <6>[ 1.335885] Trying to probe devices needed for running init ...
1363 08:45:35.152552 <6>[ 1.492673] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1364 08:45:35.302144 <6>[ 1.639990] mmc0: new ultra high speed SDR104 SDXC card at address e624
1365 08:45:35.307346 <6>[ 1.641807] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1366 08:45:35.307887 <6>[ 1.647608] mmcblk0: p1
1367 08:45:35.328826 <6>[ 1.670413] Freeing initrd memory: 22892K
1368 08:45:35.343487 <6>[ 1.686939] hub 1-1:1.0: USB hub found
1369 08:45:35.348277 <6>[ 1.687241] hub 1-1:1.0: 4 ports detected
1370 08:45:35.408876 <6>[ 1.748781] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1371 08:45:35.456157 <6>[ 1.799584] hub 2-1:1.0: USB hub found
1372 08:45:35.461541 <6>[ 1.800404] hub 2-1:1.0: 4 ports detected
1373 08:45:47.273610 <6>[ 13.616706] clk: Disabling unused clocks
1374 08:45:47.278896 <6>[ 13.616875] PM: genpd: Disabling unused power domains
1375 08:45:47.287294 <6>[ 13.620568] ALSA device list:
1376 08:45:47.287795 <6>[ 13.623772] No soundcards found.
1377 08:45:47.292749 <6>[ 13.636141] Freeing unused kernel memory: 10432K
1378 08:45:47.303773 <6>[ 13.636240] Run /init as init process
1379 08:45:47.304278 Loading, please wait...
1380 08:45:47.342329 Starting systemd-udevd version 252.22-1~deb12u1
1381 08:45:47.754148 <4>[ 14.091994] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1382 08:45:47.759759 <3>[ 14.097339] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1383 08:45:47.768857 <6>[ 14.103246] mc: Linux media interface: v0.10
1384 08:45:47.774550 <6>[ 14.111012] meson-vrtc ff8000a8.rtc: registered as rtc0
1385 08:45:47.780888 <6>[ 14.112784] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1386 08:45:47.800469 <6>[ 14.140551] videodev: Linux video capture interface: v2.00
1387 08:45:47.821733 <6>[ 14.159525] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1388 08:45:47.827253 <6>[ 14.160897] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1389 08:45:47.836131 <4>[ 14.161574] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1390 08:45:47.841748 <6>[ 14.167202] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1391 08:45:47.847093 <6>[ 14.183430] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1392 08:45:47.858236 <6>[ 14.194274] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1393 08:45:47.863775 <6>[ 14.197189] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1394 08:45:47.869337 <6>[ 14.200750] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1395 08:45:47.874900 <6>[ 14.202428] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1396 08:45:47.880420 <6>[ 14.205600] Registered IR keymap rc-empty
1397 08:45:47.885971 <6>[ 14.205738] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1398 08:45:47.897054 <6>[ 14.205888] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1399 08:45:47.897531 <6>[ 14.209567] rc rc0: sw decoder init
1400 08:45:47.908210 <6>[ 14.215912] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1401 08:45:47.913715 <6>[ 14.220758] meson-ir ff808000.ir: receiver initialized
1402 08:45:47.919259 <6>[ 14.228230] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1403 08:45:47.930339 <6>[ 14.242180] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1404 08:45:47.935892 <6>[ 14.248243] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1405 08:45:47.941419 <6>[ 14.248254] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1406 08:45:47.946998 <6>[ 14.284022] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1407 08:45:47.958055 <6>[ 14.290120] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1408 08:45:47.963611 <6>[ 14.296161] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1409 08:45:47.969157 <6>[ 14.305745] panfrost ffe40000.gpu: clock rate = 24000000
1410 08:45:47.980260 <3>[ 14.310279] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1411 08:45:47.985802 <6>[ 14.323682] usbcore: registered new device driver onboard-usb-dev
1412 08:45:47.991368 <6>[ 14.325812] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1413 08:45:48.002435 <6>[ 14.333459] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1414 08:45:48.013571 <6>[ 14.343452] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1415 08:45:48.024634 <6>[ 14.351961] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1416 08:45:48.030182 <6>[ 14.352459] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1417 08:45:48.035730 <6>[ 14.359054] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1418 08:45:48.046828 <6>[ 14.363748] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1419 08:45:48.052358 <6>[ 14.369793] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 1
1420 08:45:48.057895 <6>[ 14.372412] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1421 08:45:48.068999 <3>[ 14.401065] meson-drm ff900000.vpu: DSI transceiver device is disabled
1422 08:45:48.074083 <6>[ 14.408085] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 0
1423 08:45:48.253562 <6>[ 14.574200] Console: switching to colour frame buffer device 128x48
1424 08:45:48.259433 <6>[ 14.592403] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1425 08:45:48.495559 <6>[ 14.839037] hub 1-1:1.0: USB hub found
1426 08:45:48.500317 <6>[ 14.839347] hub 1-1:1.0: 4 ports detected
1427 08:45:48.642673 <4>[ 14.980656] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1428 08:45:48.648213 <3>[ 14.983014] onboard-usb-dev 1-1: Failed to suspend device, error -32
1429 08:45:48.654760 <3>[ 14.989455] onboard-usb-dev 1-1: can't set config #1, error -71
1430 08:45:48.666241 Begin: Loading essential drivers ... done.
1431 08:45:48.677263 <4>[ 15.012660] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1432 08:45:48.682808 Be<3>[ 15.015893] onboard-usb-dev 1-1: Failed to suspend device, error -32
1433 08:45:48.688326 <6>[ 15.015892] onboard-usb-dev 1-1: USB disconnect, device number 2
1434 08:45:48.693883 gin: Running /scripts/init-premount ... done.
1435 08:45:48.699413 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1436 08:45:48.704997 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1437 08:45:48.710518 Device /sys/class/net/end0 found
1438 08:45:48.710992 done.
1439 08:45:48.718907 Begin: Waiting up to 180 secs for any network device to become available ... done.
1440 08:45:48.775628 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.111474] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1441 08:45:48.776190
1442 08:45:48.803862 <6>[ 15.142908] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1443 08:45:48.862876 <6>[ 15.200816] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=29)
1444 08:45:48.871857 <6>[ 15.210923] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1445 08:45:48.877345 <6>[ 15.213711] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1446 08:45:48.887618 <6>[ 15.221205] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1447 08:45:48.936630 <6>[ 15.276692] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1448 08:45:49.033215 <4>[ 15.376647] rc rc0: two consecutive events of type space
1449 08:45:49.135647 <6>[ 15.479074] hub 1-1:1.0: USB hub found
1450 08:45:49.141425 <6>[ 15.479422] hub 1-1:1.0: 4 ports detected
1451 08:45:50.271201 IP-Config: no response after 2 secs - giving up
1452 08:45:50.320421 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1453 08:45:51.841475 <6>[ 18.179658] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1454 08:45:53.522418 IP-Config: no response after 3 secs - giving up
1455 08:45:53.565051 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1456 08:45:56.776541 IP-Config: end0 guessed broadcast address 192.168.6.255
1457 08:45:56.781798 IP-Config: end0 complete (dhcp from 192.168.6.1):
1458 08:45:56.787600 address: 192.168.6.33 broadcast: 192.168.6.255 netmask: 255.255.255.0
1459 08:45:56.796434 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1460 08:45:56.801155 rootserver: 192.168.6.1 rootpath:
1461 08:45:56.801685 filename :
1462 08:45:56.904741 done.
1463 08:45:56.915882 Begin: Running /scripts/nfs-bottom ... done.
1464 08:45:56.926025 Begin: Running /scripts/init-bottom ... done.
1465 08:45:57.276573 <30>[ 23.616237] systemd[1]: System time before build time, advancing clock.
1466 08:45:57.336259 <6>[ 23.679629] NET: Registered PF_INET6 protocol family
1467 08:45:57.341773 <6>[ 23.681120] Segment Routing with IPv6
1468 08:45:57.346766 <6>[ 23.683136] In-situ OAM (IOAM) with IPv6
1469 08:45:57.428254 <30>[ 23.740509] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1470 08:45:57.433860 <30>[ 23.767895] systemd[1]: Detected architecture arm64.
1471 08:45:57.434388
1472 08:45:57.437377 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1473 08:45:57.437913
1474 08:45:57.446084 <30>[ 23.786410] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1475 08:45:58.154733 <30>[ 24.493739] systemd[1]: Queued start job for default target graphical.target.
1476 08:45:58.201223 <30>[ 24.539035] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1477 08:45:58.207967 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1478 08:45:58.219872 <30>[ 24.557639] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1479 08:45:58.227837 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1480 08:45:58.239824 <30>[ 24.577723] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1481 08:45:58.248834 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1482 08:45:58.259865 <30>[ 24.597415] systemd[1]: Created slice user.slice - User and Session Slice.
1483 08:45:58.266344 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1484 08:45:58.280213 <30>[ 24.612912] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1485 08:45:58.286025 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1486 08:45:58.297073 <30>[ 24.632867] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1487 08:45:58.309052 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1488 08:45:58.325738 <30>[ 24.652816] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1489 08:45:58.331249 <30>[ 24.666872] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1490 08:45:58.344492 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1491 08:45:58.350041 <30>[ 24.688736] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1492 08:45:58.358533 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1493 08:45:58.374834 <30>[ 24.712761] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1494 08:45:58.383269 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1495 08:45:58.394920 <30>[ 24.732789] systemd[1]: Reached target paths.target - Path Units.
1496 08:45:58.399619 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1497 08:45:58.410828 <30>[ 24.748757] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1498 08:45:58.417124 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1499 08:45:58.422596 <30>[ 24.764734] systemd[1]: Reached target slices.target - Slice Units.
1500 08:45:58.436243 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1501 08:45:58.441811 <30>[ 24.780747] systemd[1]: Reached target swap.target - Swaps.
1502 08:45:58.446343 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1503 08:45:58.458849 <30>[ 24.796766] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1504 08:45:58.467564 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1505 08:45:58.482980 <30>[ 24.820926] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1506 08:45:58.492190 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1507 08:45:58.504251 <30>[ 24.842164] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1508 08:45:58.513086 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1509 08:45:58.527698 <30>[ 24.865645] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1510 08:45:58.537016 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1511 08:45:58.551163 <30>[ 24.889072] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1512 08:45:58.558050 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1513 08:45:58.569150 <30>[ 24.905791] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1514 08:45:58.577109 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1515 08:45:58.588803 <30>[ 24.926701] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1516 08:45:58.594310 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1517 08:45:58.607132 <30>[ 24.944979] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1518 08:45:58.614790 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1519 08:45:58.654942 <30>[ 24.992878] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1520 08:45:58.660835 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1521 08:45:58.676252 <30>[ 25.014153] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1522 08:45:58.683001 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1523 08:45:58.700833 <30>[ 25.038699] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1524 08:45:58.707447 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1525 08:45:58.724682 <30>[ 25.057064] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1526 08:45:58.735798 <30>[ 25.070322] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1527 08:45:58.742694 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1528 08:45:58.761744 <30>[ 25.099585] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1529 08:45:58.769215 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1530 08:45:58.781642 <30>[ 25.119481] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1531 08:45:58.788385 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1532 08:45:58.800962 <30>[ 25.138902] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1533 08:45:58.812067 Starting [0;1;39mmodprob<6>[ 25.144803] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1534 08:45:58.816102 e@drm.service[0m - Load Kernel Module drm...
1535 08:45:58.829924 <30>[ 25.167681] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1536 08:45:58.837745 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1537 08:45:58.849504 <30>[ 25.187415] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1538 08:45:58.856373 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1539 08:45:58.873406 <6>[ 25.216817] fuse: init (API version 7.41)
1540 08:45:58.884453 <30>[ 25.218722] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1541 08:45:58.888498 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1542 08:45:58.913086 <30>[ 25.251039] systemd[1]: Starting systemd-journald.service - Journal Service...
1543 08:45:58.919527 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1544 08:45:58.947080 <30>[ 25.284990] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1545 08:45:58.954389 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1546 08:45:58.972497 <30>[ 25.310427] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1547 08:45:58.982198 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1548 08:45:58.999456 <30>[ 25.337396] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1549 08:45:59.008302 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1550 08:45:59.021065 <30>[ 25.358980] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1551 08:45:59.028534 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1552 08:45:59.041496 <30>[ 25.379446] systemd[1]: Started systemd-journald.service - Journal Service.
1553 08:45:59.047721 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1554 08:45:59.060105 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1555 08:45:59.070944 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1556 08:45:59.087239 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1557 08:45:59.103167 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1558 08:45:59.119628 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1559 08:45:59.133406 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1560 08:45:59.145246 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1561 08:45:59.157323 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1562 08:45:59.169093 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1563 08:45:59.180609 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1564 08:45:59.192696 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1565 08:45:59.204750 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1566 08:45:59.216385 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1567 08:45:59.229740 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1568 08:45:59.270692 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1569 08:45:59.285788 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1570 08:45:59.301597 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1571 08:45:59.318147 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1572 08:45:59.339766 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1573 08:45:59.346387 <46>[ 25.684779] systemd-journald[230]: Received client request to flush runtime journal.
1574 08:45:59.354353 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1575 08:45:59.385879 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1576 08:45:59.392599 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1577 08:45:59.404273 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1578 08:45:59.415559 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1579 08:45:59.492433 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1580 08:45:59.508694 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1581 08:45:59.542157 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1582 08:45:59.644131 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1583 08:45:59.658527 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1584 08:45:59.671450 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1585 08:45:59.681550 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1586 08:45:59.714096 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1587 08:45:59.728887 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1588 08:45:59.955649 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1589 08:45:59.971582 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1590 08:46:00.033845 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1591 08:46:00.050960 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1592 08:46:00.064324 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1593 08:46:00.108201 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1594 08:46:00.147857 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1595 08:46:00.209040 <5>[ 26.547178] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1596 08:46:00.250351 <5>[ 26.588312] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1597 08:46:00.255874 <5>[ 26.589452] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1598 08:46:00.261412 <4>[ 26.597234] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1599 08:46:00.266996 [<6>[ 26.605855] cfg80211: failed to load regulatory.db
1600 08:46:00.279593 [0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1601 08:46:00.286637 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1602 08:46:00.302863 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1603 08:46:00.323387 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1604 08:46:00.340016 <46>[ 26.667938] systemd-journald[230]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1605 08:46:00.355044 <46>[ 26.681660] systemd-journald[230]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1606 08:46:00.376471 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1607 08:46:00.402970 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1608 08:46:00.403504 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1609 08:46:00.474341 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1610 08:46:00.485061 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1611 08:46:00.497364 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1612 08:46:00.514535 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1613 08:46:00.529145 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1614 08:46:00.540949 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1615 08:46:00.585482 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1616 08:46:00.621746 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1617 08:46:00.648911 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1618 08:46:00.660472 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1619 08:46:00.723684 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1620 08:46:00.730109 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1621 08:46:00.738547 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1622 08:46:00.755388 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1623 08:46:00.785925 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1624 08:46:00.796115 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1625 08:46:00.805777 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1626 08:46:00.819077 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1627 08:46:00.835466 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1628 08:46:00.845591 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1629 08:46:00.897457 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1630 08:46:00.911009 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1631 08:46:00.918007 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1632 08:46:00.927321 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1633 08:46:00.939373 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1634 08:46:00.954356 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1635 08:46:01.002721 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1636 08:46:01.044441 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1637 08:46:01.096976
1638 08:46:01.097523 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1639 08:46:01.097952
1640 08:46:01.103636 debian-bookworm-arm64 login: root (automatic login)
1641 08:46:01.104122
1642 08:46:01.277453 Linux debian-bookworm-arm64 6.11.0-next-20240919 #1 SMP PREEMPT Thu Sep 19 06:58:18 UTC 2024 aarch64
1643 08:46:01.278037
1644 08:46:01.283301 The programs included with the Debian GNU/Linux system are free software;
1645 08:46:01.291873 the exact distribution terms for each program are described in the
1646 08:46:01.297442 individual files in /usr/share/doc/*/copyright.
1647 08:46:01.297983
1648 08:46:01.302770 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1649 08:46:01.303301 permitted by applicable law.
1650 08:46:01.967966 Matched prompt #10: / #
1652 08:46:01.969540 Setting prompt string to ['/ #']
1653 08:46:01.970090 end: 2.4.4.1 login-action (duration 00:00:29) [common]
1655 08:46:01.971442 end: 2.4.4 auto-login-action (duration 00:00:29) [common]
1656 08:46:01.971968 start: 2.4.5 expect-shell-connection (timeout 00:03:09) [common]
1657 08:46:01.972441 Setting prompt string to ['/ #']
1658 08:46:01.972848 Forcing a shell prompt, looking for ['/ #']
1660 08:46:02.023776 / #
1661 08:46:02.024375 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1662 08:46:02.024813 Waiting using forced prompt support (timeout 00:02:30)
1663 08:46:02.029683
1664 08:46:02.030442 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1665 08:46:02.030977 start: 2.4.6 export-device-env (timeout 00:03:09) [common]
1666 08:46:02.031437 Sending with 10 millisecond of delay
1668 08:46:07.024314 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/742845/extract-nfsrootfs-1xjfryqp'
1669 08:46:07.035320 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/742845/extract-nfsrootfs-1xjfryqp'
1670 08:46:07.036140 Sending with 10 millisecond of delay
1672 08:46:09.136182 / # export NFS_SERVER_IP='192.168.6.2'
1673 08:46:09.147414 export NFS_SERVER_IP='192.168.6.2'
1674 08:46:09.148568 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1675 08:46:09.149287 end: 2.4 uboot-commands (duration 00:01:58) [common]
1676 08:46:09.149958 end: 2 uboot-action (duration 00:01:58) [common]
1677 08:46:09.150612 start: 3 lava-test-retry (timeout 00:06:41) [common]
1678 08:46:09.151274 start: 3.1 lava-test-shell (timeout 00:06:41) [common]
1679 08:46:09.151808 Using namespace: common
1681 08:46:09.253181 / # #
1682 08:46:09.253931 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1683 08:46:09.258321 #
1684 08:46:09.259330 Using /lava-742845
1686 08:46:09.360878 / # export SHELL=/bin/bash
1687 08:46:09.366241 export SHELL=/bin/bash
1689 08:46:09.468126 / # . /lava-742845/environment
1690 08:46:09.471951 . /lava-742845/environment
1692 08:46:09.577457 / # /lava-742845/bin/lava-test-runner /lava-742845/0
1693 08:46:09.578197 Test shell timeout: 10s (minimum of the action and connection timeout)
1694 08:46:09.581380 /lava-742845/bin/lava-test-runner /lava-742845/0
1695 08:46:09.788429 + export TESTRUN_ID=0_timesync-off
1696 08:46:09.795901 + TESTRUN_ID=0_timesync-off
1697 08:46:09.796498 + cd /lava-742845/0/tests/0_timesync-off
1698 08:46:09.796992 ++ cat uuid
1699 08:46:09.806631 + UUID=742845_1.6.2.4.1
1700 08:46:09.807196 + set +x
1701 08:46:09.814925 <LAVA_SIGNAL_STARTRUN 0_timesync-off 742845_1.6.2.4.1>
1702 08:46:09.815479 + systemctl stop systemd-timesyncd
1703 08:46:09.816265 Received signal: <STARTRUN> 0_timesync-off 742845_1.6.2.4.1
1704 08:46:09.816780 Starting test lava.0_timesync-off (742845_1.6.2.4.1)
1705 08:46:09.817375 Skipping test definition patterns.
1706 08:46:09.872551 + set +x
1707 08:46:09.873207 <LAVA_SIGNAL_ENDRUN 0_timesync-off 742845_1.6.2.4.1>
1708 08:46:09.873952 Received signal: <ENDRUN> 0_timesync-off 742845_1.6.2.4.1
1709 08:46:09.874505 Ending use of test pattern.
1710 08:46:09.874980 Ending test lava.0_timesync-off (742845_1.6.2.4.1), duration 0.06
1712 08:46:09.961270 + export TESTRUN_ID=1_kselftest-alsa
1713 08:46:09.969006 + TESTRUN_ID=1_kselftest-alsa
1714 08:46:09.969577 + cd /lava-742845/0/tests/1_kselftest-alsa
1715 08:46:09.970065 ++ cat uuid
1716 08:46:09.983589 + UUID=742845_1.6.2.4.5
1717 08:46:09.984210 + set +x
1718 08:46:09.989077 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 742845_1.6.2.4.5>
1719 08:46:09.989620 + cd ./automated/linux/kselftest/
1720 08:46:09.990362 Received signal: <STARTRUN> 1_kselftest-alsa 742845_1.6.2.4.5
1721 08:46:09.990838 Starting test lava.1_kselftest-alsa (742845_1.6.2.4.5)
1722 08:46:09.991372 Skipping test definition patterns.
1723 08:46:10.015925 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1724 08:46:10.066232 INFO: install_deps skipped
1725 08:46:10.192812 --2024-09-19 08:46:10-- http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/kselftest.tar.xz
1726 08:46:10.225101 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1727 08:46:10.373265 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1728 08:46:10.518416 HTTP request sent, awaiting response... 200 OK
1729 08:46:10.519064 Length: 6732780 (6.4M) [application/octet-stream]
1730 08:46:10.523898 Saving to: 'kselftest_armhf.tar.gz'
1731 08:46:10.524493
1732 08:46:11.722298
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 163KB/s
kselftest_armhf.tar 3%[ ] 218.67K 376KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.00MB/s
kselftest_armhf.tar 54%[=========> ] 3.51M 3.02MB/s
kselftest_armhf.tar 100%[===================>] 6.42M 5.35MB/s in 1.2s
1733 08:46:11.722696
1734 08:46:11.810062 2024-09-19 08:46:11 (5.35 MB/s) - 'kselftest_armhf.tar.gz' saved [6732780/6732780]
1735 08:46:11.810958
1736 08:46:21.042208 skiplist:
1737 08:46:21.042872 ========================================
1738 08:46:21.047823 ========================================
1739 08:46:21.091774 alsa:mixer-test
1740 08:46:21.092386 alsa:pcm-test
1741 08:46:21.092837 alsa:test-pcmtest-driver
1742 08:46:21.095786 alsa:utimer-test
1743 08:46:21.109063 ============== Tests to run ===============
1744 08:46:21.109550 alsa:mixer-test
1745 08:46:21.114542 alsa:pcm-test
1746 08:46:21.115014 alsa:test-pcmtest-driver
1747 08:46:21.115456 alsa:utimer-test
1748 08:46:21.122728 ===========End Tests to run ===============
1749 08:46:21.123202 shardfile-alsa pass
1750 08:46:21.245803 <12>[ 47.587099] kselftest: Running tests in alsa
1751 08:46:21.252288 TAP version 13
1752 08:46:21.261856 1..4
1753 08:46:21.299697 # timeout set to 45
1754 08:46:21.300246 # selftests: alsa: mixer-test
1755 08:46:21.468805 # TAP version 13
1756 08:46:21.469402 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1757 08:46:21.474250 # 1..427
1758 08:46:21.474729 # ok 1 get_value.LCALTA.60
1759 08:46:21.475169 # # LCALTA.60 TDMOUT_A SRC SEL
1760 08:46:21.479776 # ok 2 name.LCALTA.60
1761 08:46:21.480298 # ok 3 write_default.LCALTA.60
1762 08:46:21.485343 # ok 4 write_valid.LCALTA.60
1763 08:46:21.485813 # ok 5 write_invalid.LCALTA.60
1764 08:46:21.490888 # ok 6 event_missing.LCALTA.60
1765 08:46:21.491361 # ok 7 event_spurious.LCALTA.60
1766 08:46:21.496546 # ok 8 get_value.LCALTA.59
1767 08:46:21.497011 # # LCALTA.59 TDMOUT_B SRC SEL
1768 08:46:21.502006 # ok 9 name.LCALTA.59
1769 08:46:21.502472 # ok 10 write_default.LCALTA.59
1770 08:46:21.507607 # ok 11 write_valid.LCALTA.59
1771 08:46:21.508107 # ok 12 write_invalid.LCALTA.59
1772 08:46:21.513198 # ok 13 event_missing.LCALTA.59
1773 08:46:21.513667 # ok 14 event_spurious.LCALTA.59
1774 08:46:21.518759 # ok 15 get_value.LCALTA.58
1775 08:46:21.519225 # # LCALTA.58 TDMOUT_C SRC SEL
1776 08:46:21.524280 # ok 16 name.LCALTA.58
1777 08:46:21.524741 # ok 17 write_default.LCALTA.58
1778 08:46:21.529764 # ok 18 write_valid.LCALTA.58
1779 08:46:21.530225 # ok 19 write_invalid.LCALTA.58
1780 08:46:21.535308 # ok 20 event_missing.LCALTA.58
1781 08:46:21.535771 # ok 21 event_spurious.LCALTA.58
1782 08:46:21.540879 # ok 22 get_value.LCALTA.57
1783 08:46:21.541345 # # LCALTA.57 TDMIN_A SRC SEL
1784 08:46:21.541789 # ok 23 name.LCALTA.57
1785 08:46:21.546405 # ok 24 write_default.LCALTA.57
1786 08:46:21.546875 # ok 25 write_valid.LCALTA.57
1787 08:46:21.551971 # ok 26 write_invalid.LCALTA.57
1788 08:46:21.552464 # ok 27 event_missing.LCALTA.57
1789 08:46:21.557556 # ok 28 event_spurious.LCALTA.57
1790 08:46:21.558021 # ok 29 get_value.LCALTA.56
1791 08:46:21.563131 # # LCALTA.56 TDMIN_B SRC SEL
1792 08:46:21.563655 # ok 30 name.LCALTA.56
1793 08:46:21.568601 # ok 31 write_default.LCALTA.56
1794 08:46:21.569086 # ok 32 write_valid.LCALTA.56
1795 08:46:21.574155 # ok 33 write_invalid.LCALTA.56
1796 08:46:21.585412 # ok 34 event_missing.LCALTA.<3>[ 47.917747] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1797 08:46:21.586047 56
1798 08:46:21.590818 # ok 35 event_spurious.LCALTA.56
1799 08:46:21.591305 # ok 36 get_value.LCALTA.55
1800 08:46:21.596297 # # LCALTA.55 TDMIN_C SRC SEL
1801 08:46:21.596783 # ok 37 name.LCALTA.55
1802 08:46:21.601893 # ok 38 write_default.LCALTA.55
1803 08:46:21.602379 # ok 39 write_valid.LCALTA.55
1804 08:46:21.607405 # ok 40 write_invalid.LCALTA.55
1805 08:46:21.607880 # ok 41 event_missing.LCALTA.55
1806 08:46:21.612954 # ok 42 event_spurious.LCALTA.55
1807 08:46:21.613428 # ok 43 get_value.LCALTA.54
1808 08:46:21.618510 # # LCALTA.54 ACODEC Left DAC Sel
1809 08:46:21.618979 # ok 44 name.LCALTA.54
1810 08:46:21.624072 # ok 45 write_default.LCALTA.54
1811 08:46:21.624548 # ok 46 write_valid.LCALTA.54
1812 08:46:21.629603 # ok 47 write_invalid.LCALTA.54
1813 08:46:21.630071 # ok 48 event_missing.LCALTA.54
1814 08:46:21.635204 # ok 49 event_spurious.LCALTA.54
1815 08:46:21.635671 # ok 50 get_value.LCALTA.53
1816 08:46:21.640796 # # LCALTA.53 ACODEC Right DAC Sel
1817 08:46:21.641259 # ok 51 name.LCALTA.53
1818 08:46:21.646257 # ok 52 write_default.LCALTA.53
1819 08:46:21.646722 # ok 53 write_valid.LCALTA.53
1820 08:46:21.651781 # ok 54 write_invalid.LCALTA.53
1821 08:46:21.652314 # ok 55 event_missing.LCALTA.53
1822 08:46:21.657383 # ok 56 event_spurious.LCALTA.53
1823 08:46:21.657851 # ok 57 get_value.LCALTA.52
1824 08:46:21.662936 # # LCALTA.52 TOACODEC OUT EN Switch
1825 08:46:21.663462 # ok 58 name.LCALTA.52
1826 08:46:21.668444 # ok 59 write_default.LCALTA.52
1827 08:46:21.668914 # ok 60 write_valid.LCALTA.52
1828 08:46:21.674051 # ok 61 write_invalid.LCALTA.52
1829 08:46:21.674522 # ok 62 event_missing.LCALTA.52
1830 08:46:21.679600 # ok 63 event_spurious.LCALTA.52
1831 08:46:21.680113 # ok 64 get_value.LCALTA.51
1832 08:46:21.685116 # # LCALTA.51 TOACODEC SRC
1833 08:46:21.685581 # ok 65 name.LCALTA.51
1834 08:46:21.690601 # ok 66 write_default.LCALTA.51
1835 08:46:21.691063 # ok 67 write_valid.LCALTA.51
1836 08:46:21.696211 # ok 68 write_invalid.LCALTA.51
1837 08:46:21.696672 # ok 69 event_missing.LCALTA.51
1838 08:46:21.701827 # ok 70 event_spurious.LCALTA.51
1839 08:46:21.702318 # ok 71 get_value.LCALTA.50
1840 08:46:21.707263 # # LCALTA.50 TOHDMITX SPDIF SRC
1841 08:46:21.707731 # ok 72 name.LCALTA.50
1842 08:46:21.708223 # ok 73 write_default.LCALTA.50
1843 08:46:21.712799 # ok 74 write_valid.LCALTA.50
1844 08:46:21.713264 # ok 75 write_invalid.LCALTA.50
1845 08:46:21.718357 # ok 76 event_missing.LCALTA.50
1846 08:46:21.723931 # ok 77 event_spurious.LCALTA.50
1847 08:46:21.724468 # ok 78 get_value.LCALTA.49
1848 08:46:21.724908 # # LCALTA.49 TOHDMITX Switch
1849 08:46:21.729461 # ok 79 name.LCALTA.49
1850 08:46:21.729931 # ok 80 write_default.LCALTA.49
1851 08:46:21.735064 # ok 81 write_valid.LCALTA.49
1852 08:46:21.735537 # ok 82 write_invalid.LCALTA.49
1853 08:46:21.740597 # ok 83 event_missing.LCALTA.49
1854 08:46:21.741066 # ok 84 event_spurious.LCALTA.49
1855 08:46:21.746083 # ok 85 get_value.LCALTA.48
1856 08:46:21.746545 # # LCALTA.48 TOHDMITX I2S SRC
1857 08:46:21.751647 # ok 86 name.LCALTA.48
1858 08:46:21.752141 # ok 87 write_default.LCALTA.48
1859 08:46:21.757198 # ok 88 write_valid.LCALTA.48
1860 08:46:21.757667 # ok 89 write_invalid.LCALTA.48
1861 08:46:21.762803 # ok 90 event_missing.LCALTA.48
1862 08:46:21.768281 # ok 91 eve<4>[ 48.105563] coredump: 545(utimer-test): over coredump resource limit, skipping core dump
1863 08:46:21.779371 <4>[ 48.111415] coredump: 545(utimer-test): coredump has not been created, error -7
1864 08:46:21.779848 nt_spurious.LCALTA.48
1865 08:46:21.784930 # ok 92 get_value.LCALTA.47
1866 08:46:21.785401 # # LCALTA.47 TODDR_C SRC SEL
1867 08:46:21.785841 # ok 93 name.LCALTA.47
1868 08:46:21.790467 # ok 94 write_default.LCALTA.47
1869 08:46:21.790937 # ok 95 write_valid.LCALTA.47
1870 08:46:21.796057 # ok 96 write_invalid.LCALTA.47
1871 08:46:21.796523 # ok 97 event_missing.LCALTA.47
1872 08:46:21.801613 # ok 98 event_spurious.LCALTA.47
1873 08:46:21.802078 # ok 99 get_value.LCALTA.46
1874 08:46:21.807135 # # LCALTA.46 TODDR_B SRC SEL
1875 08:46:21.807598 # ok 100 name.LCALTA.46
1876 08:46:21.812639 # ok 101 write_default.LCALTA.46
1877 08:46:21.813106 # ok 102 write_valid.LCALTA.46
1878 08:46:21.818271 # ok 103 write_invalid.LCALTA.46
1879 08:46:21.818729 # ok 104 event_missing.LCALTA.46
1880 08:46:21.823844 # ok 105 event_spurious.LCALTA.46
1881 08:46:21.824334 # ok 106 get_value.LCALTA.45
1882 08:46:21.829298 # # LCALTA.45 TODDR_A SRC SEL
1883 08:46:21.829758 # ok 107 name.LCALTA.45
1884 08:46:21.834886 # ok 108 write_default.LCALTA.45
1885 08:46:21.835347 # ok 109 write_valid.LCALTA.45
1886 08:46:21.840425 # ok 110 write_invalid.LCALTA.45
1887 08:46:21.840887 # ok 111 event_missing.LCALTA.45
1888 08:46:21.845930 # ok 112 event_spurious.LCALTA.45
1889 08:46:21.846388 # ok 113 get_value.LCALTA.44
1890 08:46:21.851504 # # LCALTA.44 FRDDR_C SINK 3 SEL
1891 08:46:21.851964 # ok 114 name.LCALTA.44
1892 08:46:21.857066 # ok 115 write_default.LCALTA.44
1893 08:46:21.857524 # ok 116 write_valid.LCALTA.44
1894 08:46:21.862662 # ok 117 write_invalid.LCALTA.44
1895 08:46:21.863177 # ok 118 event_missing.LCALTA.44
1896 08:46:21.868187 # ok 119 event_spurious.LCALTA.44
1897 08:46:21.868655 # ok 120 get_value.LCALTA.43
1898 08:46:21.873692 # # LCALTA.43 FRDDR_C SINK 2 SEL
1899 08:46:21.874154 # ok 121 name.LCALTA.43
1900 08:46:21.879211 # ok 122 write_default.LCALTA.43
1901 08:46:21.879668 # ok 123 write_valid.LCALTA.43
1902 08:46:21.884826 # ok 124 write_invalid.LCALTA.43
1903 08:46:21.885286 # ok 125 event_missing.LCALTA.43
1904 08:46:21.890296 # ok 126 event_spurious.LCALTA.43
1905 08:46:21.895949 # ok 127 get_value.LCALTA.42
1906 08:46:21.896440 # # LCALTA.42 FRDDR_C SINK 1 SEL
1907 08:46:21.896871 # ok 128 name.LCALTA.42
1908 08:46:21.901426 # ok 129 write_default.LCALTA.42
1909 08:46:21.901885 # ok 130 write_valid.LCALTA.42
1910 08:46:21.906974 # ok 131 write_invalid.LCALTA.42
1911 08:46:21.912531 # ok 132 event_missing.LCALTA.42
1912 08:46:21.912990 # ok 133 event_spurious.LCALTA.42
1913 08:46:21.918082 # ok 134 get_value.LCALTA.41
1914 08:46:21.918539 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1915 08:46:21.923597 # ok 135 name.LCALTA.41
1916 08:46:21.924080 # ok 136 write_default.LCALTA.41
1917 08:46:21.929162 # ok 137 write_valid.LCALTA.41
1918 08:46:21.929617 # ok 138 write_invalid.LCALTA.41
1919 08:46:21.934718 # ok 139 event_missing.LCALTA.41
1920 08:46:21.935178 # ok 140 event_spurious.LCALTA.41
1921 08:46:21.940217 # ok 141 get_value.LCALTA.40
1922 08:46:21.940677 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1923 08:46:21.945843 # ok 142 name.LCALTA.40
1924 08:46:21.946297 # ok 143 write_default.LCALTA.40
1925 08:46:21.951321 # ok 144 write_valid.LCALTA.40
1926 08:46:21.951778 # ok 145 write_invalid.LCALTA.40
1927 08:46:21.956877 # ok 146 event_missing.LCALTA.40
1928 08:46:21.957335 # ok 147 event_spurious.LCALTA.40
1929 08:46:21.962462 # ok 148 get_value.LCALTA.39
1930 08:46:21.962975 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1931 08:46:21.968007 # ok 149 name.LCALTA.39
1932 08:46:21.968485 # ok 150 write_default.LCALTA.39
1933 08:46:21.973507 # ok 151 write_valid.LCALTA.39
1934 08:46:21.973973 # ok 152 write_invalid.LCALTA.39
1935 08:46:21.979038 # ok 153 event_missing.LCALTA.39
1936 08:46:21.979500 # ok 154 event_spurious.LCALTA.39
1937 08:46:21.984609 # ok 155 get_value.LCALTA.38
1938 08:46:21.985072 # # LCALTA.38 FRDDR_B SINK 3 SEL
1939 08:46:21.990145 # ok 156 name.LCALTA.38
1940 08:46:21.990614 # ok 157 write_default.LCALTA.38
1941 08:46:21.995704 # ok 158 write_valid.LCALTA.38
1942 08:46:21.996215 # ok 159 write_invalid.LCALTA.38
1943 08:46:22.001237 # ok 160 event_missing.LCALTA.38
1944 08:46:22.001702 # ok 161 event_spurious.LCALTA.38
1945 08:46:22.006937 # ok 162 get_value.LCALTA.37
1946 08:46:22.007399 # # LCALTA.37 FRDDR_B SINK 2 SEL
1947 08:46:22.012356 # ok 163 name.LCALTA.37
1948 08:46:22.012819 # ok 164 write_default.LCALTA.37
1949 08:46:22.017909 # ok 165 write_valid.LCALTA.37
1950 08:46:22.018373 # ok 166 write_invalid.LCALTA.37
1951 08:46:22.023421 # ok 167 event_missing.LCALTA.37
1952 08:46:22.023896 # ok 168 event_spurious.LCALTA.37
1953 08:46:22.029051 # ok 169 get_value.LCALTA.36
1954 08:46:22.029516 # # LCALTA.36 FRDDR_B SINK 1 SEL
1955 08:46:22.034530 # ok 170 name.LCALTA.36
1956 08:46:22.034994 # ok 171 write_default.LCALTA.36
1957 08:46:22.040086 # ok 172 write_valid.LCALTA.36
1958 08:46:22.040549 # ok 173 write_invalid.LCALTA.36
1959 08:46:22.045637 # ok 174 event_missing.LCALTA.36
1960 08:46:22.046106 # ok 175 event_spurious.LCALTA.36
1961 08:46:22.051184 # ok 176 get_value.LCALTA.35
1962 08:46:22.056720 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1963 08:46:22.057198 # ok 177 name.LCALTA.35
1964 08:46:22.057649 # ok 178 write_default.LCALTA.35
1965 08:46:22.062310 # ok 179 write_valid.LCALTA.35
1966 08:46:22.067907 # ok 180 write_invalid.LCALTA.35
1967 08:46:22.068451 # ok 181 event_missing.LCALTA.35
1968 08:46:22.073386 # ok 182 event_spurious.LCALTA.35
1969 08:46:22.073871 # ok 183 get_value.LCALTA.34
1970 08:46:22.078917 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1971 08:46:22.079402 # ok 184 name.LCALTA.34
1972 08:46:22.084465 # ok 185 write_default.LCALTA.34
1973 08:46:22.084948 # ok 186 write_valid.LCALTA.34
1974 08:46:22.090010 # ok 187 write_invalid.LCALTA.34
1975 08:46:22.090487 # ok 188 event_missing.LCALTA.34
1976 08:46:22.095570 # ok 189 event_spurious.LCALTA.34
1977 08:46:22.096086 # ok 190 get_value.LCALTA.33
1978 08:46:22.101122 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1979 08:46:22.101602 # ok 191 name.LCALTA.33
1980 08:46:22.106623 # ok 192 write_default.LCALTA.33
1981 08:46:22.107098 # ok 193 write_valid.LCALTA.33
1982 08:46:22.112222 # ok 194 write_invalid.LCALTA.33
1983 08:46:22.112700 # ok 195 event_missing.LCALTA.33
1984 08:46:22.117780 # ok 196 event_spurious.LCALTA.33
1985 08:46:22.118257 # ok 197 get_value.LCALTA.32
1986 08:46:22.123307 # # LCALTA.32 FRDDR_A SINK 3 SEL
1987 08:46:22.123783 # ok 198 name.LCALTA.32
1988 08:46:22.128862 # ok 199 write_default.LCALTA.32
1989 08:46:22.129343 # ok 200 write_valid.LCALTA.32
1990 08:46:22.134492 # ok 201 write_invalid.LCALTA.32
1991 08:46:22.134969 # ok 202 event_missing.LCALTA.32
1992 08:46:22.140089 # ok 203 event_spurious.LCALTA.32
1993 08:46:22.140571 # ok 204 get_value.LCALTA.31
1994 08:46:22.145502 # # LCALTA.31 FRDDR_A SINK 2 SEL
1995 08:46:22.145980 # ok 205 name.LCALTA.31
1996 08:46:22.151020 # ok 206 write_default.LCALTA.31
1997 08:46:22.151496 # ok 207 write_valid.LCALTA.31
1998 08:46:22.156582 # ok 208 write_invalid.LCALTA.31
1999 08:46:22.157062 # ok 209 event_missing.LCALTA.31
2000 08:46:22.162138 # ok 210 event_spurious.LCALTA.31
2001 08:46:22.162641 # ok 211 get_value.LCALTA.30
2002 08:46:22.167692 # # LCALTA.30 FRDDR_A SINK 1 SEL
2003 08:46:22.168292 # ok 212 name.LCALTA.30
2004 08:46:22.173337 # ok 213 write_default.LCALTA.30
2005 08:46:22.173819 # ok 214 write_valid.LCALTA.30
2006 08:46:22.178779 # ok 215 write_invalid.LCALTA.30
2007 08:46:22.179253 # ok 216 event_missing.LCALTA.30
2008 08:46:22.184326 # ok 217 event_spurious.LCALTA.30
2009 08:46:22.184804 # ok 218 get_value.LCALTA.29
2010 08:46:22.189899 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2011 08:46:22.190374 # ok 219 name.LCALTA.29
2012 08:46:22.195421 # ok 220 write_default.LCALTA.29
2013 08:46:22.195901 # ok 221 write_valid.LCALTA.29
2014 08:46:22.200971 # ok 222 write_invalid.LCALTA.29
2015 08:46:22.201454 # ok 223 event_missing.LCALTA.29
2016 08:46:22.206546 # ok 224 event_spurious.LCALTA.29
2017 08:46:22.207026 # ok 225 get_value.LCALTA.28
2018 08:46:22.212073 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2019 08:46:22.212558 # ok 226 name.LCALTA.28
2020 08:46:22.217636 # ok 227 write_default.LCALTA.28
2021 08:46:22.223283 # ok 228 write_valid.LCALTA.28
2022 08:46:22.223762 # ok 229 write_invalid.LCALTA.28
2023 08:46:22.228698 # ok 230 event_missing.LCALTA.28
2024 08:46:22.229195 # ok 231 event_spurious.LCALTA.28
2025 08:46:22.234243 # ok 232 get_value.LCALTA.27
2026 08:46:22.234724 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2027 08:46:22.239744 # ok 233 name.LCALTA.27
2028 08:46:22.240267 # ok 234 write_default.LCALTA.27
2029 08:46:22.245340 # ok 235 write_valid.LCALTA.27
2030 08:46:22.245820 # ok 236 write_invalid.LCALTA.27
2031 08:46:22.250982 # ok 237 event_missing.LCALTA.27
2032 08:46:22.251470 # ok 238 event_spurious.LCALTA.27
2033 08:46:22.256400 # ok 239 get_value.LCALTA.26
2034 08:46:22.256883 # # LCALTA.26 ELD
2035 08:46:22.257334 # ok 240 name.LCALTA.26
2036 08:46:22.261894 # # ELD is not writeable
2037 08:46:22.262373 # ok 241 # SKIP write_default.LCALTA.26
2038 08:46:22.267549 # # ELD is not writeable
2039 08:46:22.268116 # ok 242 # SKIP write_valid.LCALTA.26
2040 08:46:22.273094 # # ELD is not writeable
2041 08:46:22.278613 # ok 243 # SKIP write_invalid.LCALTA.26
2042 08:46:22.279102 # ok 244 event_missing.LCALTA.26
2043 08:46:22.284283 # ok 245 event_spurious.LCALTA.26
2044 08:46:22.284767 # ok 246 get_value.LCALTA.25
2045 08:46:22.289728 # # LCALTA.25 IEC958 Playback Default
2046 08:46:22.290221 # ok 247 name.LCALTA.25
2047 08:46:22.295235 # ok 248 write_default.LCALTA.25
2048 08:46:22.295710 # ok 249 # SKIP write_valid.LCALTA.25
2049 08:46:22.300783 # ok 250 # SKIP write_invalid.LCALTA.25
2050 08:46:22.301269 # ok 251 event_missing.LCALTA.25
2051 08:46:22.306385 # ok 252 event_spurious.LCALTA.25
2052 08:46:22.306858 # ok 253 get_value.LCALTA.24
2053 08:46:22.311947 # # LCALTA.24 IEC958 Playback Mask
2054 08:46:22.312458 # ok 254 name.LCALTA.24
2055 08:46:22.317399 # # IEC958 Playback Mask is not writeable
2056 08:46:22.322951 # ok 255 # SKIP write_default.LCALTA.24
2057 08:46:22.323428 # # IEC958 Playback Mask is not writeable
2058 08:46:22.328558 # ok 256 # SKIP write_valid.LCALTA.24
2059 08:46:22.334037 # # IEC958 Playback Mask is not writeable
2060 08:46:22.334513 # ok 257 # SKIP write_invalid.LCALTA.24
2061 08:46:22.339636 # ok 258 event_missing.LCALTA.24
2062 08:46:22.340138 # ok 259 event_spurious.LCALTA.24
2063 08:46:22.345181 # ok 260 get_value.LCALTA.23
2064 08:46:22.345657 # # LCALTA.23 Playback Channel Map
2065 08:46:22.350698 # ok 261 name.LCALTA.23
2066 08:46:22.351173 # # Playback Channel Map is not writeable
2067 08:46:22.356324 # ok 262 # SKIP write_default.LCALTA.23
2068 08:46:22.361765 # # Playback Channel Map is not writeable
2069 08:46:22.362239 # ok 263 # SKIP write_valid.LCALTA.23
2070 08:46:22.367365 # # Playback Channel Map is not writeable
2071 08:46:22.372968 # ok 264 # SKIP write_invalid.LCALTA.23
2072 08:46:22.373459 # ok 265 event_missing.LCALTA.23
2073 08:46:22.378469 # ok 266 event_spurious.LCALTA.23
2074 08:46:22.378952 # ok 267 get_value.LCALTA.22
2075 08:46:22.384077 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2076 08:46:22.384556 # ok 268 name.LCALTA.22
2077 08:46:22.389508 # ok 269 write_default.LCALTA.22
2078 08:46:22.390001 # ok 270 write_valid.LCALTA.22
2079 08:46:22.395116 # ok 271 write_invalid.LCALTA.22
2080 08:46:22.395599 # ok 272 event_missing.LCALTA.22
2081 08:46:22.400676 # ok 273 event_spurious.LCALTA.22
2082 08:46:22.401158 # ok 274 get_value.LCALTA.21
2083 08:46:22.406209 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2084 08:46:22.406693 # ok 275 name.LCALTA.21
2085 08:46:22.411749 # ok 276 write_default.LCALTA.21
2086 08:46:22.412265 # ok 277 write_valid.LCALTA.21
2087 08:46:22.417288 # ok 278 write_invalid.LCALTA.21
2088 08:46:22.417760 # ok 279 event_missing.LCALTA.21
2089 08:46:22.422851 # ok 280 event_spurious.LCALTA.21
2090 08:46:22.423328 # ok 281 get_value.LCALTA.20
2091 08:46:22.428394 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2092 08:46:22.428874 # ok 282 name.LCALTA.20
2093 08:46:22.434021 # ok 283 write_default.LCALTA.20
2094 08:46:22.434502 # ok 284 write_valid.LCALTA.20
2095 08:46:22.439503 # ok 285 write_invalid.LCALTA.20
2096 08:46:22.445046 # ok 286 event_missing.LCALTA.20
2097 08:46:22.445526 # ok 287 event_spurious.LCALTA.20
2098 08:46:22.450517 # ok 288 get_value.LCALTA.19
2099 08:46:22.450998 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2100 08:46:22.456075 # ok 289 name.LCALTA.19
2101 08:46:22.456553 # ok 290 write_default.LCALTA.19
2102 08:46:22.461602 # ok 291 write_valid.LCALTA.19
2103 08:46:22.462074 # ok 292 write_invalid.LCALTA.19
2104 08:46:22.467185 # ok 293 event_missing.LCALTA.19
2105 08:46:22.467716 # ok 294 event_spurious.LCALTA.19
2106 08:46:22.472738 # ok 295 get_value.LCALTA.18
2107 08:46:22.473220 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2108 08:46:22.478314 # ok 296 name.LCALTA.18
2109 08:46:22.478795 # ok 297 write_default.LCALTA.18
2110 08:46:22.483845 # ok 298 write_valid.LCALTA.18
2111 08:46:22.484353 # ok 299 write_invalid.LCALTA.18
2112 08:46:22.489324 # ok 300 event_missing.LCALTA.18
2113 08:46:22.489804 # ok 301 event_spurious.LCALTA.18
2114 08:46:22.494923 # ok 302 get_value.LCALTA.17
2115 08:46:22.495392 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2116 08:46:22.500450 # ok 303 name.LCALTA.17
2117 08:46:22.500939 # ok 304 write_default.LCALTA.17
2118 08:46:22.506032 # ok 305 write_valid.LCALTA.17
2119 08:46:22.506510 # ok 306 write_invalid.LCALTA.17
2120 08:46:22.511626 # ok 307 event_missing.LCALTA.17
2121 08:46:22.512143 # ok 308 event_spurious.LCALTA.17
2122 08:46:22.517124 # ok 309 get_value.LCALTA.16
2123 08:46:22.522646 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2124 08:46:22.523128 # ok 310 name.LCALTA.16
2125 08:46:22.523579 # ok 311 write_default.LCALTA.16
2126 08:46:22.528252 # ok 312 write_valid.LCALTA.16
2127 08:46:22.528743 # ok 313 write_invalid.LCALTA.16
2128 08:46:22.533795 # ok 314 event_missing.LCALTA.16
2129 08:46:22.539308 # ok 315 event_spurious.LCALTA.16
2130 08:46:22.539804 # ok 316 get_value.LCALTA.15
2131 08:46:22.544847 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2132 08:46:22.545330 # ok 317 name.LCALTA.15
2133 08:46:22.550381 # ok 318 write_default.LCALTA.15
2134 08:46:22.550858 # ok 319 write_valid.LCALTA.15
2135 08:46:22.555913 # ok 320 write_invalid.LCALTA.15
2136 08:46:22.556422 # ok 321 event_missing.LCALTA.15
2137 08:46:22.561455 # ok 322 event_spurious.LCALTA.15
2138 08:46:22.561929 # ok 323 get_value.LCALTA.14
2139 08:46:22.567061 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2140 08:46:22.567587 # ok 324 name.LCALTA.14
2141 08:46:22.572596 # ok 325 write_default.LCALTA.14
2142 08:46:22.573085 # ok 326 write_valid.LCALTA.14
2143 08:46:22.578080 # ok 327 write_invalid.LCALTA.14
2144 08:46:22.578557 # ok 328 event_missing.LCALTA.14
2145 08:46:22.583667 # ok 329 event_spurious.LCALTA.14
2146 08:46:22.584180 # ok 330 get_value.LCALTA.13
2147 08:46:22.589262 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2148 08:46:22.589745 # ok 331 name.LCALTA.13
2149 08:46:22.594788 # ok 332 write_default.LCALTA.13
2150 08:46:22.595263 # ok 333 write_valid.LCALTA.13
2151 08:46:22.600371 # ok 334 write_invalid.LCALTA.13
2152 08:46:22.600854 # ok 335 event_missing.LCALTA.13
2153 08:46:22.605802 # ok 336 event_spurious.LCALTA.13
2154 08:46:22.606279 # ok 337 get_value.LCALTA.12
2155 08:46:22.611374 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2156 08:46:22.611854 # ok 338 name.LCALTA.12
2157 08:46:22.616931 # ok 339 write_default.LCALTA.12
2158 08:46:22.617413 # ok 340 write_valid.LCALTA.12
2159 08:46:22.622507 # ok 341 write_invalid.LCALTA.12
2160 08:46:22.622993 # ok 342 event_missing.LCALTA.12
2161 08:46:22.628158 # ok 343 event_spurious.LCALTA.12
2162 08:46:22.628646 # ok 344 get_value.LCALTA.11
2163 08:46:22.633592 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2164 08:46:22.634087 # ok 345 name.LCALTA.11
2165 08:46:22.639127 # ok 346 write_default.LCALTA.11
2166 08:46:22.639636 # ok 347 write_valid.LCALTA.11
2167 08:46:22.644693 # ok 348 write_invalid.LCALTA.11
2168 08:46:22.650234 # ok 349 event_missing.LCALTA.11
2169 08:46:22.650714 # ok 350 event_spurious.LCALTA.11
2170 08:46:22.655812 # ok 351 get_value.LCALTA.10
2171 08:46:22.656328 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2172 08:46:22.661385 # ok 352 name.LCALTA.10
2173 08:46:22.661860 # ok 353 write_default.LCALTA.10
2174 08:46:22.666885 # ok 354 write_valid.LCALTA.10
2175 08:46:22.667404 # ok 355 write_invalid.LCALTA.10
2176 08:46:22.672377 # ok 356 event_missing.LCALTA.10
2177 08:46:22.672861 # ok 357 event_spurious.LCALTA.10
2178 08:46:22.677961 # ok 358 get_value.LCALTA.9
2179 08:46:22.678443 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2180 08:46:22.683493 # ok 359 name.LCALTA.9
2181 08:46:22.683969 # ok 360 write_default.LCALTA.9
2182 08:46:22.689112 # ok 361 write_valid.LCALTA.9
2183 08:46:22.689591 # ok 362 write_invalid.LCALTA.9
2184 08:46:22.694568 # ok 363 event_missing.LCALTA.9
2185 08:46:22.695043 # ok 364 event_spurious.LCALTA.9
2186 08:46:22.700128 # ok 365 get_value.LCALTA.8
2187 08:46:22.700600 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2188 08:46:22.705721 # ok 366 name.LCALTA.8
2189 08:46:22.706195 # ok 367 write_default.LCALTA.8
2190 08:46:22.711292 # ok 368 write_valid.LCALTA.8
2191 08:46:22.711764 # ok 369 write_invalid.LCALTA.8
2192 08:46:22.716748 # ok 370 event_missing.LCALTA.8
2193 08:46:22.717227 # ok 371 event_spurious.LCALTA.8
2194 08:46:22.722412 # ok 372 get_value.LCALTA.7
2195 08:46:22.722907 # # LCALTA.7 ACODEC Unmute Ramp Switch
2196 08:46:22.727922 # ok 373 name.LCALTA.7
2197 08:46:22.728430 # ok 374 write_default.LCALTA.7
2198 08:46:22.733426 # ok 375 write_valid.LCALTA.7
2199 08:46:22.733905 # ok 376 write_invalid.LCALTA.7
2200 08:46:22.739019 # ok 377 event_missing.LCALTA.7
2201 08:46:22.739501 # ok 378 event_spurious.LCALTA.7
2202 08:46:22.744531 # ok 379 get_value.LCALTA.6
2203 08:46:22.745008 # # LCALTA.6 ACODEC Mute Ramp Switch
2204 08:46:22.750094 # ok 380 name.LCALTA.6
2205 08:46:22.750572 # ok 381 write_default.LCALTA.6
2206 08:46:22.755564 # ok 382 write_valid.LCALTA.6
2207 08:46:22.756067 # ok 383 write_invalid.LCALTA.6
2208 08:46:22.761254 # ok 384 event_missing.LCALTA.6
2209 08:46:22.761726 # ok 385 event_spurious.LCALTA.6
2210 08:46:22.766801 # ok 386 get_value.LCALTA.5
2211 08:46:22.767313 # # LCALTA.5 ACODEC Volume Ramp Switch
2212 08:46:22.772284 # ok 387 name.LCALTA.5
2213 08:46:22.772770 # ok 388 write_default.LCALTA.5
2214 08:46:22.777756 # ok 389 write_valid.LCALTA.5
2215 08:46:22.778229 # ok 390 write_invalid.LCALTA.5
2216 08:46:22.783344 # ok 391 event_missing.LCALTA.5
2217 08:46:22.783819 # ok 392 event_spurious.LCALTA.5
2218 08:46:22.789084 # ok 393 get_value.LCALTA.4
2219 08:46:22.789571 # # LCALTA.4 ACODEC Ramp Rate
2220 08:46:22.790018 # ok 394 name.LCALTA.4
2221 08:46:22.794424 # ok 395 write_default.LCALTA.4
2222 08:46:22.794901 # ok 396 write_valid.LCALTA.4
2223 08:46:22.799975 # ok 397 write_invalid.LCALTA.4
2224 08:46:22.800482 # ok 398 event_missing.LCALTA.4
2225 08:46:22.805484 # ok 399 event_spurious.LCALTA.4
2226 08:46:22.805962 # ok 400 get_value.LCALTA.3
2227 08:46:22.811071 # # LCALTA.3 ACODEC Playback Volume
2228 08:46:22.811546 # ok 401 name.LCALTA.3
2229 08:46:22.816665 # ok 402 write_default.LCALTA.3
2230 08:46:22.817150 # ok 403 write_valid.LCALTA.3
2231 08:46:22.822195 # ok 404 write_invalid.LCALTA.3
2232 08:46:22.822677 # ok 405 event_missing.LCALTA.3
2233 08:46:22.827707 # ok 406 event_spurious.LCALTA.3
2234 08:46:22.828216 # ok 407 get_value.LCALTA.2
2235 08:46:22.833309 # # LCALTA.2 ACODEC Playback Switch
2236 08:46:22.833785 # ok 408 name.LCALTA.2
2237 08:46:22.838820 # ok 409 write_default.LCALTA.2
2238 08:46:22.839320 # ok 410 write_valid.LCALTA.2
2239 08:46:22.844404 # ok 411 write_invalid.LCALTA.2
2240 08:46:22.844884 # ok 412 event_missing.LCALTA.2
2241 08:46:22.850023 # ok 413 event_spurious.LCALTA.2
2242 08:46:22.850503 # ok 414 get_value.LCALTA.1
2243 08:46:22.855497 # # LCALTA.1 ACODEC Playback Channel Mode
2244 08:46:22.855971 # ok 415 name.LCALTA.1
2245 08:46:22.860983 # ok 416 write_default.LCALTA.1
2246 08:46:22.861460 # ok 417 write_valid.LCALTA.1
2247 08:46:22.866587 # ok 418 write_invalid.LCALTA.1
2248 08:46:22.867141 # ok 419 event_missing.LCALTA.1
2249 08:46:22.872163 # ok 420 event_spurious.LCALTA.1
2250 08:46:22.872656 # ok 421 get_value.LCALTA.0
2251 08:46:22.877662 # # LCALTA.0 TOACODEC Lane Select
2252 08:46:22.878146 # ok 422 name.LCALTA.0
2253 08:46:22.883165 # ok 423 write_default.LCALTA.0
2254 08:46:22.883644 # ok 424 write_valid.LCALTA.0
2255 08:46:22.888756 # ok 425 write_invalid.LCALTA.0
2256 08:46:22.889232 # ok 426 event_missing.LCALTA.0
2257 08:46:22.894301 # ok 427 event_spurious.LCALTA.0
2258 08:46:22.899849 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2259 08:46:22.900366 ok 1 selftests: alsa: mixer-test
2260 08:46:22.905334 # timeout set to 45
2261 08:46:22.905813 # selftests: alsa: pcm-test
2262 08:46:22.906265 # TAP version 13
2263 08:46:22.911022 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2264 08:46:22.916429 # # LCALTA.0 - fe.dai-link-0 (*)
2265 08:46:22.916904 # # LCALTA.0 - fe.dai-link-1 (*)
2266 08:46:22.922000 # # LCALTA.0 - fe.dai-link-2 (*)
2267 08:46:22.922483 # # LCALTA.0 - fe.dai-link-3 (*)
2268 08:46:22.927548 # # LCALTA.0 - fe.dai-link-4 (*)
2269 08:46:22.928063 # # LCALTA.0 - fe.dai-link-5 (*)
2270 08:46:22.928522 # 1..42
2271 08:46:22.933106 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2272 08:46:22.938687 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2273 08:46:22.944218 # # snd_pcm_hw_params: Invalid argument
2274 08:46:22.949811 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2275 08:46:22.955250 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2276 08:46:22.955732 # # snd_pcm_hw_params: Invalid argument
2277 08:46:22.960850 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2278 08:46:22.966397 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2279 08:46:22.972063 # # snd_pcm_hw_params: Invalid argument
2280 08:46:22.977455 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2281 08:46:22.983003 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2282 08:46:22.983482 # # snd_pcm_hw_params: Invalid argument
2283 08:46:22.988617 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2284 08:46:22.994089 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2285 08:46:22.999682 # # snd_pcm_hw_params: Invalid argument
2286 08:46:23.005269 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2287 08:46:23.005753 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2288 08:46:23.010763 # # snd_pcm_hw_params: Invalid argument
2289 08:46:23.016358 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2290 08:46:23.021864 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2291 08:46:23.027357 # # snd_pcm_hw_params: Invalid argument
2292 08:46:23.032970 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2293 08:46:23.033451 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2294 08:46:23.038543 # # snd_pcm_hw_params: Invalid argument
2295 08:46:23.044086 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2296 08:46:23.049537 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2297 08:46:23.050018 # # snd_pcm_hw_params: Invalid argument
2298 08:46:23.055164 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2299 08:46:23.060691 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2300 08:46:23.066228 # # snd_pcm_hw_params: Invalid argument
2301 08:46:23.071790 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2302 08:46:23.077303 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2303 08:46:23.077789 # # snd_pcm_hw_params: Invalid argument
2304 08:46:23.082871 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2305 08:46:23.088399 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2306 08:46:23.094027 # # snd_pcm_hw_params: Invalid argument
2307 08:46:23.099516 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2308 08:46:23.105021 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2309 08:46:23.105502 # # snd_pcm_hw_params: Invalid argument
2310 08:46:23.110600 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2311 08:46:23.116114 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2312 08:46:23.121646 # # snd_pcm_hw_params: Invalid argument
2313 08:46:23.127248 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2314 08:46:23.127729 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2315 08:46:23.132754 # # snd_pcm_hw_params: Invalid argument
2316 08:46:23.138258 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2317 08:46:23.143848 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2318 08:46:23.149365 # # snd_pcm_hw_params: Invalid argument
2319 08:46:23.154986 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2320 08:46:23.155468 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2321 08:46:23.160513 # # snd_pcm_hw_params: Invalid argument
2322 08:46:23.166054 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2323 08:46:23.171664 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2324 08:46:23.172258 # # snd_pcm_hw_params: Invalid argument
2325 08:46:23.177166 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2326 08:46:23.182689 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2327 08:46:23.188403 # # snd_pcm_hw_params: Invalid argument
2328 08:46:23.193879 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2329 08:46:23.199406 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2330 08:46:23.199907 # # snd_pcm_hw_params: Invalid argument
2331 08:46:23.205009 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2332 08:46:23.210530 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2333 08:46:23.216078 # # snd_pcm_hw_params: Invalid argument
2334 08:46:23.221525 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2335 08:46:23.227070 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2336 08:46:23.227551 # # snd_pcm_hw_params: Invalid argument
2337 08:46:23.232654 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2338 08:46:23.238161 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2339 08:46:23.243700 # # snd_pcm_hw_params: Invalid argument
2340 08:46:23.249272 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2341 08:46:23.254785 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2342 08:46:23.255275 # # snd_pcm_hw_params: Invalid argument
2343 08:46:23.260320 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2344 08:46:23.265876 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2345 08:46:23.271525 # # snd_pcm_hw_params: Invalid argument
2346 08:46:23.277079 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2347 08:46:23.282558 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2348 08:46:23.283040 # # snd_pcm_hw_params: Invalid argument
2349 08:46:23.288161 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2350 08:46:23.293628 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2351 08:46:23.299165 # # snd_pcm_hw_params: Invalid argument
2352 08:46:23.304741 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2353 08:46:23.310310 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2354 08:46:23.310785 # # snd_pcm_hw_params: Invalid argument
2355 08:46:23.315852 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2356 08:46:23.321341 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2357 08:46:23.326927 # # snd_pcm_hw_params: Invalid argument
2358 08:46:23.332453 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2359 08:46:23.338087 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2360 08:46:23.338588 # # snd_pcm_hw_params: Invalid argument
2361 08:46:23.343539 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2362 08:46:23.349111 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2363 08:46:23.354718 # # snd_pcm_hw_params: Invalid argument
2364 08:46:23.360212 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2365 08:46:23.365762 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2366 08:46:23.366243 # # snd_pcm_hw_params: Invalid argument
2367 08:46:23.371401 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2368 08:46:23.376877 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2369 08:46:23.382385 # # snd_pcm_hw_params: Invalid argument
2370 08:46:23.387938 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2371 08:46:23.393505 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2372 08:46:23.393990 # # snd_pcm_hw_params: Invalid argument
2373 08:46:23.399070 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2374 08:46:23.404600 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2375 08:46:23.410061 # # snd_pcm_hw_params: Invalid argument
2376 08:46:23.415700 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2377 08:46:23.416226 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2378 08:46:23.421275 # # snd_pcm_hw_params: Invalid argument
2379 08:46:23.426756 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2380 08:46:23.432328 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2381 08:46:23.437873 # # snd_pcm_hw_params: Invalid argument
2382 08:46:23.443402 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2383 08:46:23.443890 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2384 08:46:23.448949 # # snd_pcm_hw_params: Invalid argument
2385 08:46:23.454469 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2386 08:46:23.460223 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2387 08:46:23.465591 # # snd_pcm_hw_params: Invalid argument
2388 08:46:23.471231 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2389 08:46:23.471752 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2390 08:46:23.476743 # # snd_pcm_hw_params: Invalid argument
2391 08:46:23.482276 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2392 08:46:23.487788 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2393 08:46:23.493436 # # snd_pcm_hw_params: Invalid argument
2394 08:46:23.498848 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2395 08:46:23.499335 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2396 08:46:23.504412 # # snd_pcm_hw_params: Invalid argument
2397 08:46:23.509940 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2398 08:46:23.510419 ok 2 selftests: alsa: pcm-test
2399 08:46:23.515508 # timeout set to 45
2400 08:46:23.516008 # selftests: alsa: test-pcmtest-driver
2401 08:46:23.521112 # TAP version 13
2402 08:46:23.521601 # 1..5
2403 08:46:23.522064 # # Starting 5 tests from 1 test cases.
2404 08:46:23.526556 # # RUN pcmtest.playback ...
2405 08:46:23.532252 # # SKIP Can't read patterns. Probably, module isn't loaded
2406 08:46:23.537753 # # OK pcmtest.playback
2407 08:46:23.543294 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2408 08:46:23.548875 # # RUN pcmtest.capture ...
2409 08:46:23.554401 # # SKIP Can't read patterns. Probably, module isn't loaded
2410 08:46:23.554912 # # OK pcmtest.capture
2411 08:46:23.565582 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2412 08:46:23.566082 # # RUN pcmtest.ni_capture ...
2413 08:46:23.571024 # # SKIP Can't read patterns. Probably, module isn't loaded
2414 08:46:23.576668 # # OK pcmtest.ni_capture
2415 08:46:23.582155 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2416 08:46:23.588351 # # RUN pcmtest.ni_playback ...
2417 08:46:23.593306 # # SKIP Can't read patterns. Probably, module isn't loaded
2418 08:46:23.598766 # # OK pcmtest.ni_playback
2419 08:46:23.604327 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2420 08:46:23.609837 # # RUN pcmtest.reset_ioctl ...
2421 08:46:23.615404 # # SKIP Can't read patterns. Probably, module isn't loaded
2422 08:46:23.621017 # # OK pcmtest.reset_ioctl
2423 08:46:23.626548 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2424 08:46:23.627056 # # PASSED: 5 / 5 tests passed.
2425 08:46:23.632032 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2426 08:46:23.637567 ok 3 selftests: alsa: test-pcmtest-driver
2427 08:46:23.638054 # timeout set to 45
2428 08:46:23.643075 # selftests: alsa: utimer-test
2429 08:46:23.643565 # TAP version 13
2430 08:46:23.644076 # 1..2
2431 08:46:23.648628 # # Starting 2 tests from 2 test cases.
2432 08:46:23.654229 # # RUN global.wrong_timers_test ...
2433 08:46:23.654720 # # OK global.wrong_timers_test
2434 08:46:23.659757 # ok 1 global.wrong_timers_test
2435 08:46:23.665227 # # RUN timer_f.utimer ...
2436 08:46:23.670804 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2437 08:46:23.676508 # # utimer: Test terminated by assertion
2438 08:46:23.681912 # # FAIL timer_f.utimer
2439 08:46:23.682389 # not ok 2 timer_f.utimer
2440 08:46:23.682845 # # FAILED: 1 / 2 tests passed.
2441 08:46:23.687499 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2442 08:46:23.694113 not ok 4 selftests: alsa: utimer-test # exit=1
2443 08:46:24.244271 alsa_mixer-test_get_value_LCALTA_60 pass
2444 08:46:24.249596 alsa_mixer-test_name_LCALTA_60 pass
2445 08:46:24.250104 alsa_mixer-test_write_default_LCALTA_60 pass
2446 08:46:24.255155 alsa_mixer-test_write_valid_LCALTA_60 pass
2447 08:46:24.260672 alsa_mixer-test_write_invalid_LCALTA_60 pass
2448 08:46:24.266215 alsa_mixer-test_event_missing_LCALTA_60 pass
2449 08:46:24.266697 alsa_mixer-test_event_spurious_LCALTA_60 pass
2450 08:46:24.271769 alsa_mixer-test_get_value_LCALTA_59 pass
2451 08:46:24.277271 alsa_mixer-test_name_LCALTA_59 pass
2452 08:46:24.277754 alsa_mixer-test_write_default_LCALTA_59 pass
2453 08:46:24.282820 alsa_mixer-test_write_valid_LCALTA_59 pass
2454 08:46:24.288347 alsa_mixer-test_write_invalid_LCALTA_59 pass
2455 08:46:24.288852 alsa_mixer-test_event_missing_LCALTA_59 pass
2456 08:46:24.293841 alsa_mixer-test_event_spurious_LCALTA_59 pass
2457 08:46:24.299409 alsa_mixer-test_get_value_LCALTA_58 pass
2458 08:46:24.299885 alsa_mixer-test_name_LCALTA_58 pass
2459 08:46:24.305038 alsa_mixer-test_write_default_LCALTA_58 pass
2460 08:46:24.310596 alsa_mixer-test_write_valid_LCALTA_58 pass
2461 08:46:24.311076 alsa_mixer-test_write_invalid_LCALTA_58 pass
2462 08:46:24.316214 alsa_mixer-test_event_missing_LCALTA_58 pass
2463 08:46:24.321712 alsa_mixer-test_event_spurious_LCALTA_58 pass
2464 08:46:24.327204 alsa_mixer-test_get_value_LCALTA_57 pass
2465 08:46:24.327684 alsa_mixer-test_name_LCALTA_57 pass
2466 08:46:24.332756 alsa_mixer-test_write_default_LCALTA_57 pass
2467 08:46:24.338303 alsa_mixer-test_write_valid_LCALTA_57 pass
2468 08:46:24.338786 alsa_mixer-test_write_invalid_LCALTA_57 pass
2469 08:46:24.343835 alsa_mixer-test_event_missing_LCALTA_57 pass
2470 08:46:24.349414 alsa_mixer-test_event_spurious_LCALTA_57 pass
2471 08:46:24.349899 alsa_mixer-test_get_value_LCALTA_56 pass
2472 08:46:24.355013 alsa_mixer-test_name_LCALTA_56 pass
2473 08:46:24.360503 alsa_mixer-test_write_default_LCALTA_56 pass
2474 08:46:24.360979 alsa_mixer-test_write_valid_LCALTA_56 pass
2475 08:46:24.366074 alsa_mixer-test_write_invalid_LCALTA_56 pass
2476 08:46:24.371613 alsa_mixer-test_event_missing_LCALTA_56 pass
2477 08:46:24.377236 alsa_mixer-test_event_spurious_LCALTA_56 pass
2478 08:46:24.377715 alsa_mixer-test_get_value_LCALTA_55 pass
2479 08:46:24.382749 alsa_mixer-test_name_LCALTA_55 pass
2480 08:46:24.388308 alsa_mixer-test_write_default_LCALTA_55 pass
2481 08:46:24.388783 alsa_mixer-test_write_valid_LCALTA_55 pass
2482 08:46:24.393718 alsa_mixer-test_write_invalid_LCALTA_55 pass
2483 08:46:24.399298 alsa_mixer-test_event_missing_LCALTA_55 pass
2484 08:46:24.399776 alsa_mixer-test_event_spurious_LCALTA_55 pass
2485 08:46:24.404870 alsa_mixer-test_get_value_LCALTA_54 pass
2486 08:46:24.410462 alsa_mixer-test_name_LCALTA_54 pass
2487 08:46:24.410943 alsa_mixer-test_write_default_LCALTA_54 pass
2488 08:46:24.416049 alsa_mixer-test_write_valid_LCALTA_54 pass
2489 08:46:24.421480 alsa_mixer-test_write_invalid_LCALTA_54 pass
2490 08:46:24.421955 alsa_mixer-test_event_missing_LCALTA_54 pass
2491 08:46:24.427048 alsa_mixer-test_event_spurious_LCALTA_54 pass
2492 08:46:24.432617 alsa_mixer-test_get_value_LCALTA_53 pass
2493 08:46:24.433097 alsa_mixer-test_name_LCALTA_53 pass
2494 08:46:24.438195 alsa_mixer-test_write_default_LCALTA_53 pass
2495 08:46:24.443742 alsa_mixer-test_write_valid_LCALTA_53 pass
2496 08:46:24.449266 alsa_mixer-test_write_invalid_LCALTA_53 pass
2497 08:46:24.449747 alsa_mixer-test_event_missing_LCALTA_53 pass
2498 08:46:24.454769 alsa_mixer-test_event_spurious_LCALTA_53 pass
2499 08:46:24.460327 alsa_mixer-test_get_value_LCALTA_52 pass
2500 08:46:24.460824 alsa_mixer-test_name_LCALTA_52 pass
2501 08:46:24.465863 alsa_mixer-test_write_default_LCALTA_52 pass
2502 08:46:24.471437 alsa_mixer-test_write_valid_LCALTA_52 pass
2503 08:46:24.471914 alsa_mixer-test_write_invalid_LCALTA_52 pass
2504 08:46:24.477078 alsa_mixer-test_event_missing_LCALTA_52 pass
2505 08:46:24.482528 alsa_mixer-test_event_spurious_LCALTA_52 pass
2506 08:46:24.483008 alsa_mixer-test_get_value_LCALTA_51 pass
2507 08:46:24.488136 alsa_mixer-test_name_LCALTA_51 pass
2508 08:46:24.493576 alsa_mixer-test_write_default_LCALTA_51 pass
2509 08:46:24.494052 alsa_mixer-test_write_valid_LCALTA_51 pass
2510 08:46:24.499202 alsa_mixer-test_write_invalid_LCALTA_51 pass
2511 08:46:24.504763 alsa_mixer-test_event_missing_LCALTA_51 pass
2512 08:46:24.510263 alsa_mixer-test_event_spurious_LCALTA_51 pass
2513 08:46:24.510746 alsa_mixer-test_get_value_LCALTA_50 pass
2514 08:46:24.515833 alsa_mixer-test_name_LCALTA_50 pass
2515 08:46:24.521342 alsa_mixer-test_write_default_LCALTA_50 pass
2516 08:46:24.521825 alsa_mixer-test_write_valid_LCALTA_50 pass
2517 08:46:24.526892 alsa_mixer-test_write_invalid_LCALTA_50 pass
2518 08:46:24.532471 alsa_mixer-test_event_missing_LCALTA_50 pass
2519 08:46:24.532948 alsa_mixer-test_event_spurious_LCALTA_50 pass
2520 08:46:24.537981 alsa_mixer-test_get_value_LCALTA_49 pass
2521 08:46:24.543527 alsa_mixer-test_name_LCALTA_49 pass
2522 08:46:24.544029 alsa_mixer-test_write_default_LCALTA_49 pass
2523 08:46:24.549086 alsa_mixer-test_write_valid_LCALTA_49 pass
2524 08:46:24.554578 alsa_mixer-test_write_invalid_LCALTA_49 pass
2525 08:46:24.560312 alsa_mixer-test_event_missing_LCALTA_49 pass
2526 08:46:24.560788 alsa_mixer-test_event_spurious_LCALTA_49 pass
2527 08:46:24.565710 alsa_mixer-test_get_value_LCALTA_48 pass
2528 08:46:24.566190 alsa_mixer-test_name_LCALTA_48 pass
2529 08:46:24.571254 alsa_mixer-test_write_default_LCALTA_48 pass
2530 08:46:24.576864 alsa_mixer-test_write_valid_LCALTA_48 pass
2531 08:46:24.582344 alsa_mixer-test_write_invalid_LCALTA_48 pass
2532 08:46:24.582824 alsa_mixer-test_event_missing_LCALTA_48 pass
2533 08:46:24.587880 alsa_mixer-test_event_spurious_LCALTA_48 pass
2534 08:46:24.593462 alsa_mixer-test_get_value_LCALTA_47 pass
2535 08:46:24.593938 alsa_mixer-test_name_LCALTA_47 pass
2536 08:46:24.598996 alsa_mixer-test_write_default_LCALTA_47 pass
2537 08:46:24.604524 alsa_mixer-test_write_valid_LCALTA_47 pass
2538 08:46:24.605008 alsa_mixer-test_write_invalid_LCALTA_47 pass
2539 08:46:24.610109 alsa_mixer-test_event_missing_LCALTA_47 pass
2540 08:46:24.615649 alsa_mixer-test_event_spurious_LCALTA_47 pass
2541 08:46:24.621206 alsa_mixer-test_get_value_LCALTA_46 pass
2542 08:46:24.621684 alsa_mixer-test_name_LCALTA_46 pass
2543 08:46:24.626718 alsa_mixer-test_write_default_LCALTA_46 pass
2544 08:46:24.632286 alsa_mixer-test_write_valid_LCALTA_46 pass
2545 08:46:24.632765 alsa_mixer-test_write_invalid_LCALTA_46 pass
2546 08:46:24.637874 alsa_mixer-test_event_missing_LCALTA_46 pass
2547 08:46:24.643348 alsa_mixer-test_event_spurious_LCALTA_46 pass
2548 08:46:24.643838 alsa_mixer-test_get_value_LCALTA_45 pass
2549 08:46:24.648899 alsa_mixer-test_name_LCALTA_45 pass
2550 08:46:24.654464 alsa_mixer-test_write_default_LCALTA_45 pass
2551 08:46:24.654938 alsa_mixer-test_write_valid_LCALTA_45 pass
2552 08:46:24.660063 alsa_mixer-test_write_invalid_LCALTA_45 pass
2553 08:46:24.665575 alsa_mixer-test_event_missing_LCALTA_45 pass
2554 08:46:24.666049 alsa_mixer-test_event_spurious_LCALTA_45 pass
2555 08:46:24.671127 alsa_mixer-test_get_value_LCALTA_44 pass
2556 08:46:24.677556 alsa_mixer-test_name_LCALTA_44 pass
2557 08:46:24.678037 alsa_mixer-test_write_default_LCALTA_44 pass
2558 08:46:24.682205 alsa_mixer-test_write_valid_LCALTA_44 pass
2559 08:46:24.687803 alsa_mixer-test_write_invalid_LCALTA_44 pass
2560 08:46:24.693266 alsa_mixer-test_event_missing_LCALTA_44 pass
2561 08:46:24.693747 alsa_mixer-test_event_spurious_LCALTA_44 pass
2562 08:46:24.698837 alsa_mixer-test_get_value_LCALTA_43 pass
2563 08:46:24.704393 alsa_mixer-test_name_LCALTA_43 pass
2564 08:46:24.704871 alsa_mixer-test_write_default_LCALTA_43 pass
2565 08:46:24.709951 alsa_mixer-test_write_valid_LCALTA_43 pass
2566 08:46:24.715480 alsa_mixer-test_write_invalid_LCALTA_43 pass
2567 08:46:24.715954 alsa_mixer-test_event_missing_LCALTA_43 pass
2568 08:46:24.721017 alsa_mixer-test_event_spurious_LCALTA_43 pass
2569 08:46:24.726543 alsa_mixer-test_get_value_LCALTA_42 pass
2570 08:46:24.727022 alsa_mixer-test_name_LCALTA_42 pass
2571 08:46:24.732152 alsa_mixer-test_write_default_LCALTA_42 pass
2572 08:46:24.737681 alsa_mixer-test_write_valid_LCALTA_42 pass
2573 08:46:24.738160 alsa_mixer-test_write_invalid_LCALTA_42 pass
2574 08:46:24.743244 alsa_mixer-test_event_missing_LCALTA_42 pass
2575 08:46:24.748762 alsa_mixer-test_event_spurious_LCALTA_42 pass
2576 08:46:24.754286 alsa_mixer-test_get_value_LCALTA_41 pass
2577 08:46:24.754767 alsa_mixer-test_name_LCALTA_41 pass
2578 08:46:24.759874 alsa_mixer-test_write_default_LCALTA_41 pass
2579 08:46:24.765386 alsa_mixer-test_write_valid_LCALTA_41 pass
2580 08:46:24.765860 alsa_mixer-test_write_invalid_LCALTA_41 pass
2581 08:46:24.770954 alsa_mixer-test_event_missing_LCALTA_41 pass
2582 08:46:24.776587 alsa_mixer-test_event_spurious_LCALTA_41 pass
2583 08:46:24.777059 alsa_mixer-test_get_value_LCALTA_40 pass
2584 08:46:24.782095 alsa_mixer-test_name_LCALTA_40 pass
2585 08:46:24.787604 alsa_mixer-test_write_default_LCALTA_40 pass
2586 08:46:24.788123 alsa_mixer-test_write_valid_LCALTA_40 pass
2587 08:46:24.793130 alsa_mixer-test_write_invalid_LCALTA_40 pass
2588 08:46:24.798639 alsa_mixer-test_event_missing_LCALTA_40 pass
2589 08:46:24.804240 alsa_mixer-test_event_spurious_LCALTA_40 pass
2590 08:46:24.804713 alsa_mixer-test_get_value_LCALTA_39 pass
2591 08:46:24.809760 alsa_mixer-test_name_LCALTA_39 pass
2592 08:46:24.815299 alsa_mixer-test_write_default_LCALTA_39 pass
2593 08:46:24.815774 alsa_mixer-test_write_valid_LCALTA_39 pass
2594 08:46:24.820859 alsa_mixer-test_write_invalid_LCALTA_39 pass
2595 08:46:24.826418 alsa_mixer-test_event_missing_LCALTA_39 pass
2596 08:46:24.826899 alsa_mixer-test_event_spurious_LCALTA_39 pass
2597 08:46:24.831962 alsa_mixer-test_get_value_LCALTA_38 pass
2598 08:46:24.837498 alsa_mixer-test_name_LCALTA_38 pass
2599 08:46:24.837975 alsa_mixer-test_write_default_LCALTA_38 pass
2600 08:46:24.843030 alsa_mixer-test_write_valid_LCALTA_38 pass
2601 08:46:24.848606 alsa_mixer-test_write_invalid_LCALTA_38 pass
2602 08:46:24.849084 alsa_mixer-test_event_missing_LCALTA_38 pass
2603 08:46:24.854138 alsa_mixer-test_event_spurious_LCALTA_38 pass
2604 08:46:24.859671 alsa_mixer-test_get_value_LCALTA_37 pass
2605 08:46:24.860173 alsa_mixer-test_name_LCALTA_37 pass
2606 08:46:24.865397 alsa_mixer-test_write_default_LCALTA_37 pass
2607 08:46:24.870823 alsa_mixer-test_write_valid_LCALTA_37 pass
2608 08:46:24.876436 alsa_mixer-test_write_invalid_LCALTA_37 pass
2609 08:46:24.876932 alsa_mixer-test_event_missing_LCALTA_37 pass
2610 08:46:24.881902 alsa_mixer-test_event_spurious_LCALTA_37 pass
2611 08:46:24.887410 alsa_mixer-test_get_value_LCALTA_36 pass
2612 08:46:24.887897 alsa_mixer-test_name_LCALTA_36 pass
2613 08:46:24.892971 alsa_mixer-test_write_default_LCALTA_36 pass
2614 08:46:24.898503 alsa_mixer-test_write_valid_LCALTA_36 pass
2615 08:46:24.898983 alsa_mixer-test_write_invalid_LCALTA_36 pass
2616 08:46:24.904071 alsa_mixer-test_event_missing_LCALTA_36 pass
2617 08:46:24.909669 alsa_mixer-test_event_spurious_LCALTA_36 pass
2618 08:46:24.910152 alsa_mixer-test_get_value_LCALTA_35 pass
2619 08:46:24.915143 alsa_mixer-test_name_LCALTA_35 pass
2620 08:46:24.920690 alsa_mixer-test_write_default_LCALTA_35 pass
2621 08:46:24.921167 alsa_mixer-test_write_valid_LCALTA_35 pass
2622 08:46:24.926229 alsa_mixer-test_write_invalid_LCALTA_35 pass
2623 08:46:24.931770 alsa_mixer-test_event_missing_LCALTA_35 pass
2624 08:46:24.937328 alsa_mixer-test_event_spurious_LCALTA_35 pass
2625 08:46:24.937809 alsa_mixer-test_get_value_LCALTA_34 pass
2626 08:46:24.942916 alsa_mixer-test_name_LCALTA_34 pass
2627 08:46:24.948412 alsa_mixer-test_write_default_LCALTA_34 pass
2628 08:46:24.948900 alsa_mixer-test_write_valid_LCALTA_34 pass
2629 08:46:24.953968 alsa_mixer-test_write_invalid_LCALTA_34 pass
2630 08:46:24.959525 alsa_mixer-test_event_missing_LCALTA_34 pass
2631 08:46:24.960039 alsa_mixer-test_event_spurious_LCALTA_34 pass
2632 08:46:24.965092 alsa_mixer-test_get_value_LCALTA_33 pass
2633 08:46:24.970637 alsa_mixer-test_name_LCALTA_33 pass
2634 08:46:24.971118 alsa_mixer-test_write_default_LCALTA_33 pass
2635 08:46:24.976168 alsa_mixer-test_write_valid_LCALTA_33 pass
2636 08:46:24.981747 alsa_mixer-test_write_invalid_LCALTA_33 pass
2637 08:46:24.987267 alsa_mixer-test_event_missing_LCALTA_33 pass
2638 08:46:24.987747 alsa_mixer-test_event_spurious_LCALTA_33 pass
2639 08:46:24.992808 alsa_mixer-test_get_value_LCALTA_32 pass
2640 08:46:24.993323 alsa_mixer-test_name_LCALTA_32 pass
2641 08:46:24.998378 alsa_mixer-test_write_default_LCALTA_32 pass
2642 08:46:25.003906 alsa_mixer-test_write_valid_LCALTA_32 pass
2643 08:46:25.009453 alsa_mixer-test_write_invalid_LCALTA_32 pass
2644 08:46:25.009939 alsa_mixer-test_event_missing_LCALTA_32 pass
2645 08:46:25.014967 alsa_mixer-test_event_spurious_LCALTA_32 pass
2646 08:46:25.020547 alsa_mixer-test_get_value_LCALTA_31 pass
2647 08:46:25.021022 alsa_mixer-test_name_LCALTA_31 pass
2648 08:46:25.026100 alsa_mixer-test_write_default_LCALTA_31 pass
2649 08:46:25.031660 alsa_mixer-test_write_valid_LCALTA_31 pass
2650 08:46:25.032172 alsa_mixer-test_write_invalid_LCALTA_31 pass
2651 08:46:25.037300 alsa_mixer-test_event_missing_LCALTA_31 pass
2652 08:46:25.042715 alsa_mixer-test_event_spurious_LCALTA_31 pass
2653 08:46:25.048254 alsa_mixer-test_get_value_LCALTA_30 pass
2654 08:46:25.048732 alsa_mixer-test_name_LCALTA_30 pass
2655 08:46:25.053860 alsa_mixer-test_write_default_LCALTA_30 pass
2656 08:46:25.059357 alsa_mixer-test_write_valid_LCALTA_30 pass
2657 08:46:25.059836 alsa_mixer-test_write_invalid_LCALTA_30 pass
2658 08:46:25.064919 alsa_mixer-test_event_missing_LCALTA_30 pass
2659 08:46:25.070456 alsa_mixer-test_event_spurious_LCALTA_30 pass
2660 08:46:25.070936 alsa_mixer-test_get_value_LCALTA_29 pass
2661 08:46:25.076013 alsa_mixer-test_name_LCALTA_29 pass
2662 08:46:25.081570 alsa_mixer-test_write_default_LCALTA_29 pass
2663 08:46:25.082046 alsa_mixer-test_write_valid_LCALTA_29 pass
2664 08:46:25.087107 alsa_mixer-test_write_invalid_LCALTA_29 pass
2665 08:46:25.092678 alsa_mixer-test_event_missing_LCALTA_29 pass
2666 08:46:25.093157 alsa_mixer-test_event_spurious_LCALTA_29 pass
2667 08:46:25.098166 alsa_mixer-test_get_value_LCALTA_28 pass
2668 08:46:25.103756 alsa_mixer-test_name_LCALTA_28 pass
2669 08:46:25.104274 alsa_mixer-test_write_default_LCALTA_28 pass
2670 08:46:25.109300 alsa_mixer-test_write_valid_LCALTA_28 pass
2671 08:46:25.114843 alsa_mixer-test_write_invalid_LCALTA_28 pass
2672 08:46:25.120371 alsa_mixer-test_event_missing_LCALTA_28 pass
2673 08:46:25.120844 alsa_mixer-test_event_spurious_LCALTA_28 pass
2674 08:46:25.125911 alsa_mixer-test_get_value_LCALTA_27 pass
2675 08:46:25.131474 alsa_mixer-test_name_LCALTA_27 pass
2676 08:46:25.131948 alsa_mixer-test_write_default_LCALTA_27 pass
2677 08:46:25.137032 alsa_mixer-test_write_valid_LCALTA_27 pass
2678 08:46:25.142581 alsa_mixer-test_write_invalid_LCALTA_27 pass
2679 08:46:25.143059 alsa_mixer-test_event_missing_LCALTA_27 pass
2680 08:46:25.148168 alsa_mixer-test_event_spurious_LCALTA_27 pass
2681 08:46:25.153664 alsa_mixer-test_get_value_LCALTA_26 pass
2682 08:46:25.154146 alsa_mixer-test_name_LCALTA_26 pass
2683 08:46:25.159201 alsa_mixer-test_write_default_LCALTA_26 skip
2684 08:46:25.164763 alsa_mixer-test_write_valid_LCALTA_26 skip
2685 08:46:25.165250 alsa_mixer-test_write_invalid_LCALTA_26 skip
2686 08:46:25.170359 alsa_mixer-test_event_missing_LCALTA_26 pass
2687 08:46:25.175842 alsa_mixer-test_event_spurious_LCALTA_26 pass
2688 08:46:25.181461 alsa_mixer-test_get_value_LCALTA_25 pass
2689 08:46:25.181940 alsa_mixer-test_name_LCALTA_25 pass
2690 08:46:25.186913 alsa_mixer-test_write_default_LCALTA_25 pass
2691 08:46:25.192463 alsa_mixer-test_write_valid_LCALTA_25 skip
2692 08:46:25.192940 alsa_mixer-test_write_invalid_LCALTA_25 skip
2693 08:46:25.198040 alsa_mixer-test_event_missing_LCALTA_25 pass
2694 08:46:25.203556 alsa_mixer-test_event_spurious_LCALTA_25 pass
2695 08:46:25.204110 alsa_mixer-test_get_value_LCALTA_24 pass
2696 08:46:25.209144 alsa_mixer-test_name_LCALTA_24 pass
2697 08:46:25.214719 alsa_mixer-test_write_default_LCALTA_24 skip
2698 08:46:25.215195 alsa_mixer-test_write_valid_LCALTA_24 skip
2699 08:46:25.220213 alsa_mixer-test_write_invalid_LCALTA_24 skip
2700 08:46:25.225748 alsa_mixer-test_event_missing_LCALTA_24 pass
2701 08:46:25.231281 alsa_mixer-test_event_spurious_LCALTA_24 pass
2702 08:46:25.231759 alsa_mixer-test_get_value_LCALTA_23 pass
2703 08:46:25.236862 alsa_mixer-test_name_LCALTA_23 pass
2704 08:46:25.242389 alsa_mixer-test_write_default_LCALTA_23 skip
2705 08:46:25.242865 alsa_mixer-test_write_valid_LCALTA_23 skip
2706 08:46:25.247907 alsa_mixer-test_write_invalid_LCALTA_23 skip
2707 08:46:25.253504 alsa_mixer-test_event_missing_LCALTA_23 pass
2708 08:46:25.253983 alsa_mixer-test_event_spurious_LCALTA_23 pass
2709 08:46:25.259065 alsa_mixer-test_get_value_LCALTA_22 pass
2710 08:46:25.264569 alsa_mixer-test_name_LCALTA_22 pass
2711 08:46:25.265048 alsa_mixer-test_write_default_LCALTA_22 pass
2712 08:46:25.270115 alsa_mixer-test_write_valid_LCALTA_22 pass
2713 08:46:25.275693 alsa_mixer-test_write_invalid_LCALTA_22 pass
2714 08:46:25.276201 alsa_mixer-test_event_missing_LCALTA_22 pass
2715 08:46:25.281221 alsa_mixer-test_event_spurious_LCALTA_22 pass
2716 08:46:25.286775 alsa_mixer-test_get_value_LCALTA_21 pass
2717 08:46:25.287252 alsa_mixer-test_name_LCALTA_21 pass
2718 08:46:25.292385 alsa_mixer-test_write_default_LCALTA_21 pass
2719 08:46:25.297872 alsa_mixer-test_write_valid_LCALTA_21 pass
2720 08:46:25.303461 alsa_mixer-test_write_invalid_LCALTA_21 pass
2721 08:46:25.303935 alsa_mixer-test_event_missing_LCALTA_21 pass
2722 08:46:25.308969 alsa_mixer-test_event_spurious_LCALTA_21 pass
2723 08:46:25.314511 alsa_mixer-test_get_value_LCALTA_20 pass
2724 08:46:25.314983 alsa_mixer-test_name_LCALTA_20 pass
2725 08:46:25.320083 alsa_mixer-test_write_default_LCALTA_20 pass
2726 08:46:25.325614 alsa_mixer-test_write_valid_LCALTA_20 pass
2727 08:46:25.326094 alsa_mixer-test_write_invalid_LCALTA_20 pass
2728 08:46:25.331171 alsa_mixer-test_event_missing_LCALTA_20 pass
2729 08:46:25.336699 alsa_mixer-test_event_spurious_LCALTA_20 pass
2730 08:46:25.337177 alsa_mixer-test_get_value_LCALTA_19 pass
2731 08:46:25.342340 alsa_mixer-test_name_LCALTA_19 pass
2732 08:46:25.347811 alsa_mixer-test_write_default_LCALTA_19 pass
2733 08:46:25.348337 alsa_mixer-test_write_valid_LCALTA_19 pass
2734 08:46:25.353391 alsa_mixer-test_write_invalid_LCALTA_19 pass
2735 08:46:25.358894 alsa_mixer-test_event_missing_LCALTA_19 pass
2736 08:46:25.364452 alsa_mixer-test_event_spurious_LCALTA_19 pass
2737 08:46:25.364924 alsa_mixer-test_get_value_LCALTA_18 pass
2738 08:46:25.369995 alsa_mixer-test_name_LCALTA_18 pass
2739 08:46:25.375546 alsa_mixer-test_write_default_LCALTA_18 pass
2740 08:46:25.376053 alsa_mixer-test_write_valid_LCALTA_18 pass
2741 08:46:25.381062 alsa_mixer-test_write_invalid_LCALTA_18 pass
2742 08:46:25.386579 alsa_mixer-test_event_missing_LCALTA_18 pass
2743 08:46:25.387056 alsa_mixer-test_event_spurious_LCALTA_18 pass
2744 08:46:25.392111 alsa_mixer-test_get_value_LCALTA_17 pass
2745 08:46:25.397700 alsa_mixer-test_name_LCALTA_17 pass
2746 08:46:25.398173 alsa_mixer-test_write_default_LCALTA_17 pass
2747 08:46:25.403339 alsa_mixer-test_write_valid_LCALTA_17 pass
2748 08:46:25.408856 alsa_mixer-test_write_invalid_LCALTA_17 pass
2749 08:46:25.414361 alsa_mixer-test_event_missing_LCALTA_17 pass
2750 08:46:25.414833 alsa_mixer-test_event_spurious_LCALTA_17 pass
2751 08:46:25.419899 alsa_mixer-test_get_value_LCALTA_16 pass
2752 08:46:25.420417 alsa_mixer-test_name_LCALTA_16 pass
2753 08:46:25.425440 alsa_mixer-test_write_default_LCALTA_16 pass
2754 08:46:25.430962 alsa_mixer-test_write_valid_LCALTA_16 pass
2755 08:46:25.436524 alsa_mixer-test_write_invalid_LCALTA_16 pass
2756 08:46:25.436996 alsa_mixer-test_event_missing_LCALTA_16 pass
2757 08:46:25.442084 alsa_mixer-test_event_spurious_LCALTA_16 pass
2758 08:46:25.447669 alsa_mixer-test_get_value_LCALTA_15 pass
2759 08:46:25.448193 alsa_mixer-test_name_LCALTA_15 pass
2760 08:46:25.453178 alsa_mixer-test_write_default_LCALTA_15 pass
2761 08:46:25.458733 alsa_mixer-test_write_valid_LCALTA_15 pass
2762 08:46:25.459212 alsa_mixer-test_write_invalid_LCALTA_15 pass
2763 08:46:25.464338 alsa_mixer-test_event_missing_LCALTA_15 pass
2764 08:46:25.469814 alsa_mixer-test_event_spurious_LCALTA_15 pass
2765 08:46:25.475385 alsa_mixer-test_get_value_LCALTA_14 pass
2766 08:46:25.475865 alsa_mixer-test_name_LCALTA_14 pass
2767 08:46:25.480910 alsa_mixer-test_write_default_LCALTA_14 pass
2768 08:46:25.486461 alsa_mixer-test_write_valid_LCALTA_14 pass
2769 08:46:25.486938 alsa_mixer-test_write_invalid_LCALTA_14 pass
2770 08:46:25.492014 alsa_mixer-test_event_missing_LCALTA_14 pass
2771 08:46:25.497563 alsa_mixer-test_event_spurious_LCALTA_14 pass
2772 08:46:25.498041 alsa_mixer-test_get_value_LCALTA_13 pass
2773 08:46:25.503396 alsa_mixer-test_name_LCALTA_13 pass
2774 08:46:25.508705 alsa_mixer-test_write_default_LCALTA_13 pass
2775 08:46:25.509183 alsa_mixer-test_write_valid_LCALTA_13 pass
2776 08:46:25.514214 alsa_mixer-test_write_invalid_LCALTA_13 pass
2777 08:46:25.519737 alsa_mixer-test_event_missing_LCALTA_13 pass
2778 08:46:25.520249 alsa_mixer-test_event_spurious_LCALTA_13 pass
2779 08:46:25.525414 alsa_mixer-test_get_value_LCALTA_12 pass
2780 08:46:25.530825 alsa_mixer-test_name_LCALTA_12 pass
2781 08:46:25.531296 alsa_mixer-test_write_default_LCALTA_12 pass
2782 08:46:25.536406 alsa_mixer-test_write_valid_LCALTA_12 pass
2783 08:46:25.541956 alsa_mixer-test_write_invalid_LCALTA_12 pass
2784 08:46:25.547501 alsa_mixer-test_event_missing_LCALTA_12 pass
2785 08:46:25.548011 alsa_mixer-test_event_spurious_LCALTA_12 pass
2786 08:46:25.553004 alsa_mixer-test_get_value_LCALTA_11 pass
2787 08:46:25.558557 alsa_mixer-test_name_LCALTA_11 pass
2788 08:46:25.559029 alsa_mixer-test_write_default_LCALTA_11 pass
2789 08:46:25.564249 alsa_mixer-test_write_valid_LCALTA_11 pass
2790 08:46:25.569687 alsa_mixer-test_write_invalid_LCALTA_11 pass
2791 08:46:25.570164 alsa_mixer-test_event_missing_LCALTA_11 pass
2792 08:46:25.575232 alsa_mixer-test_event_spurious_LCALTA_11 pass
2793 08:46:25.580744 alsa_mixer-test_get_value_LCALTA_10 pass
2794 08:46:25.581221 alsa_mixer-test_name_LCALTA_10 pass
2795 08:46:25.586384 alsa_mixer-test_write_default_LCALTA_10 pass
2796 08:46:25.591859 alsa_mixer-test_write_valid_LCALTA_10 pass
2797 08:46:25.592360 alsa_mixer-test_write_invalid_LCALTA_10 pass
2798 08:46:25.597414 alsa_mixer-test_event_missing_LCALTA_10 pass
2799 08:46:25.602969 alsa_mixer-test_event_spurious_LCALTA_10 pass
2800 08:46:25.608477 alsa_mixer-test_get_value_LCALTA_9 pass
2801 08:46:25.608948 alsa_mixer-test_name_LCALTA_9 pass
2802 08:46:25.614057 alsa_mixer-test_write_default_LCALTA_9 pass
2803 08:46:25.619547 alsa_mixer-test_write_valid_LCALTA_9 pass
2804 08:46:25.620051 alsa_mixer-test_write_invalid_LCALTA_9 pass
2805 08:46:25.625123 alsa_mixer-test_event_missing_LCALTA_9 pass
2806 08:46:25.630666 alsa_mixer-test_event_spurious_LCALTA_9 pass
2807 08:46:25.631145 alsa_mixer-test_get_value_LCALTA_8 pass
2808 08:46:25.636276 alsa_mixer-test_name_LCALTA_8 pass
2809 08:46:25.641740 alsa_mixer-test_write_default_LCALTA_8 pass
2810 08:46:25.642216 alsa_mixer-test_write_valid_LCALTA_8 pass
2811 08:46:25.647374 alsa_mixer-test_write_invalid_LCALTA_8 pass
2812 08:46:25.652873 alsa_mixer-test_event_missing_LCALTA_8 pass
2813 08:46:25.653355 alsa_mixer-test_event_spurious_LCALTA_8 pass
2814 08:46:25.658401 alsa_mixer-test_get_value_LCALTA_7 pass
2815 08:46:25.663914 alsa_mixer-test_name_LCALTA_7 pass
2816 08:46:25.664414 alsa_mixer-test_write_default_LCALTA_7 pass
2817 08:46:25.669528 alsa_mixer-test_write_valid_LCALTA_7 pass
2818 08:46:25.675035 alsa_mixer-test_write_invalid_LCALTA_7 pass
2819 08:46:25.675507 alsa_mixer-test_event_missing_LCALTA_7 pass
2820 08:46:25.680610 alsa_mixer-test_event_spurious_LCALTA_7 pass
2821 08:46:25.686154 alsa_mixer-test_get_value_LCALTA_6 pass
2822 08:46:25.686629 alsa_mixer-test_name_LCALTA_6 pass
2823 08:46:25.691685 alsa_mixer-test_write_default_LCALTA_6 pass
2824 08:46:25.697258 alsa_mixer-test_write_valid_LCALTA_6 pass
2825 08:46:25.697752 alsa_mixer-test_write_invalid_LCALTA_6 pass
2826 08:46:25.702757 alsa_mixer-test_event_missing_LCALTA_6 pass
2827 08:46:25.708363 alsa_mixer-test_event_spurious_LCALTA_6 pass
2828 08:46:25.708844 alsa_mixer-test_get_value_LCALTA_5 pass
2829 08:46:25.713871 alsa_mixer-test_name_LCALTA_5 pass
2830 08:46:25.719434 alsa_mixer-test_write_default_LCALTA_5 pass
2831 08:46:25.719908 alsa_mixer-test_write_valid_LCALTA_5 pass
2832 08:46:25.725011 alsa_mixer-test_write_invalid_LCALTA_5 pass
2833 08:46:25.730507 alsa_mixer-test_event_missing_LCALTA_5 pass
2834 08:46:25.730979 alsa_mixer-test_event_spurious_LCALTA_5 pass
2835 08:46:25.736082 alsa_mixer-test_get_value_LCALTA_4 pass
2836 08:46:25.741635 alsa_mixer-test_name_LCALTA_4 pass
2837 08:46:25.742109 alsa_mixer-test_write_default_LCALTA_4 pass
2838 08:46:25.747139 alsa_mixer-test_write_valid_LCALTA_4 pass
2839 08:46:25.752723 alsa_mixer-test_write_invalid_LCALTA_4 pass
2840 08:46:25.753206 alsa_mixer-test_event_missing_LCALTA_4 pass
2841 08:46:25.758259 alsa_mixer-test_event_spurious_LCALTA_4 pass
2842 08:46:25.763786 alsa_mixer-test_get_value_LCALTA_3 pass
2843 08:46:25.764286 alsa_mixer-test_name_LCALTA_3 pass
2844 08:46:25.769364 alsa_mixer-test_write_default_LCALTA_3 pass
2845 08:46:25.774885 alsa_mixer-test_write_valid_LCALTA_3 pass
2846 08:46:25.775358 alsa_mixer-test_write_invalid_LCALTA_3 pass
2847 08:46:25.780413 alsa_mixer-test_event_missing_LCALTA_3 pass
2848 08:46:25.785992 alsa_mixer-test_event_spurious_LCALTA_3 pass
2849 08:46:25.786474 alsa_mixer-test_get_value_LCALTA_2 pass
2850 08:46:25.791533 alsa_mixer-test_name_LCALTA_2 pass
2851 08:46:25.797048 alsa_mixer-test_write_default_LCALTA_2 pass
2852 08:46:25.797521 alsa_mixer-test_write_valid_LCALTA_2 pass
2853 08:46:25.802685 alsa_mixer-test_write_invalid_LCALTA_2 pass
2854 08:46:25.808211 alsa_mixer-test_event_missing_LCALTA_2 pass
2855 08:46:25.813704 alsa_mixer-test_event_spurious_LCALTA_2 pass
2856 08:46:25.814176 alsa_mixer-test_get_value_LCALTA_1 pass
2857 08:46:25.819260 alsa_mixer-test_name_LCALTA_1 pass
2858 08:46:25.819735 alsa_mixer-test_write_default_LCALTA_1 pass
2859 08:46:25.824850 alsa_mixer-test_write_valid_LCALTA_1 pass
2860 08:46:25.830437 alsa_mixer-test_write_invalid_LCALTA_1 pass
2861 08:46:25.835876 alsa_mixer-test_event_missing_LCALTA_1 pass
2862 08:46:25.836389 alsa_mixer-test_event_spurious_LCALTA_1 pass
2863 08:46:25.841441 alsa_mixer-test_get_value_LCALTA_0 pass
2864 08:46:25.841921 alsa_mixer-test_name_LCALTA_0 pass
2865 08:46:25.847051 alsa_mixer-test_write_default_LCALTA_0 pass
2866 08:46:25.852554 alsa_mixer-test_write_valid_LCALTA_0 pass
2867 08:46:25.858120 alsa_mixer-test_write_invalid_LCALTA_0 pass
2868 08:46:25.858598 alsa_mixer-test_event_missing_LCALTA_0 pass
2869 08:46:25.863718 alsa_mixer-test_event_spurious_LCALTA_0 pass
2870 08:46:25.864220 alsa_mixer-test pass
2871 08:46:25.869185 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2872 08:46:25.874739 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2873 08:46:25.880313 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2874 08:46:25.885895 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2875 08:46:25.886373 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2876 08:46:25.891402 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2877 08:46:25.896948 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2878 08:46:25.902474 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2879 08:46:25.908055 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2880 08:46:25.913584 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2881 08:46:25.914078 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2882 08:46:25.919128 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2883 08:46:25.924707 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2884 08:46:25.930242 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2885 08:46:25.935797 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2886 08:46:25.941373 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2887 08:46:25.941845 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2888 08:46:25.946835 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2889 08:46:25.952469 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2890 08:46:25.957916 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2891 08:46:25.963517 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2892 08:46:25.969008 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2893 08:46:25.969468 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2894 08:46:25.974549 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2895 08:46:25.980221 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2896 08:46:25.985717 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2897 08:46:25.991259 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2898 08:46:25.996883 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2899 08:46:25.997352 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2900 08:46:26.002612 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2901 08:46:26.007902 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2902 08:46:26.013430 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2903 08:46:26.018943 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2904 08:46:26.024532 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2905 08:46:26.030049 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2906 08:46:26.030507 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2907 08:46:26.035601 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2908 08:46:26.041091 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2909 08:46:26.046640 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2910 08:46:26.052230 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2911 08:46:26.057863 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2912 08:46:26.058325 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2913 08:46:26.063345 alsa_pcm-test pass
2914 08:46:26.068840 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2915 08:46:26.080008 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2916 08:46:26.085538 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2917 08:46:26.096606 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2918 08:46:26.102155 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2919 08:46:26.107726 alsa_test-pcmtest-driver pass
2920 08:46:26.113234 alsa_utimer-test_global_wrong_timers_test pass
2921 08:46:26.113690 alsa_utimer-test_timer_f_utimer fail
2922 08:46:26.118770 alsa_utimer-test fail
2923 08:46:26.119225 + ../../utils/send-to-lava.sh ./output/result.txt
2924 08:46:26.124387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2925 08:46:26.125308 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2927 08:46:26.135446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2928 08:46:26.136181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2930 08:46:26.141193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2931 08:46:26.141916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2933 08:46:26.176814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2934 08:46:26.177567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2936 08:46:26.229243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2937 08:46:26.230072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2939 08:46:26.278152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2940 08:46:26.279211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2942 08:46:26.326238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2943 08:46:26.327134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2945 08:46:26.380430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2946 08:46:26.381611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2948 08:46:26.425164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2949 08:46:26.426085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2951 08:46:26.471776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2952 08:46:26.472959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2954 08:46:26.535702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2955 08:46:26.537002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2957 08:46:26.599690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2958 08:46:26.600857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2960 08:46:26.652393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2961 08:46:26.653515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2963 08:46:26.705346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2964 08:46:26.706346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2966 08:46:26.754887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2967 08:46:26.755792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2969 08:46:26.803717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2970 08:46:26.804902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2972 08:46:26.858348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2973 08:46:26.859236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2975 08:46:26.911872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2976 08:46:26.912780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2978 08:46:26.958365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2979 08:46:26.959229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2981 08:46:27.009840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2982 08:46:27.010789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2984 08:46:27.061210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2985 08:46:27.062079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2987 08:46:27.108174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2988 08:46:27.109317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2990 08:46:27.160587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2991 08:46:27.161627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2993 08:46:27.206074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2994 08:46:27.207194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2996 08:46:27.259370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2997 08:46:27.260305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2999 08:46:27.307127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3000 08:46:27.308048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3002 08:46:27.366157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3003 08:46:27.367268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3005 08:46:27.412267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3006 08:46:27.413175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3008 08:46:27.468339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3009 08:46:27.469237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3011 08:46:27.512886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3012 08:46:27.513948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3014 08:46:27.574007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3015 08:46:27.574894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3017 08:46:27.628293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3018 08:46:27.629242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3020 08:46:27.681398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3021 08:46:27.682568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3023 08:46:27.737090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3024 08:46:27.738007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3026 08:46:27.782948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3027 08:46:27.784115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3029 08:46:27.840828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3030 08:46:27.841969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3032 08:46:27.894003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3033 08:46:27.895134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3035 08:46:27.939972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3036 08:46:27.941128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3038 08:46:27.997381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3039 08:46:27.998400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3041 08:46:28.045093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3042 08:46:28.046203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3044 08:46:28.093734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3045 08:46:28.094760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3047 08:46:28.144672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3048 08:46:28.145263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3050 08:46:28.195189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3051 08:46:28.195747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3053 08:46:28.250342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3054 08:46:28.250923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3056 08:46:28.300903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3057 08:46:28.301480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3059 08:46:28.345867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3060 08:46:28.346419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3062 08:46:28.396382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3063 08:46:28.396998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3065 08:46:28.453075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3066 08:46:28.453625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3068 08:46:28.502758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3069 08:46:28.503307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3071 08:46:28.549664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3072 08:46:28.550201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3074 08:46:28.602389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3075 08:46:28.602961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3077 08:46:28.647805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3078 08:46:28.648568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3080 08:46:28.703726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3081 08:46:28.704358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3083 08:46:28.753159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3084 08:46:28.753709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3086 08:46:28.806739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3087 08:46:28.807277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3089 08:46:28.854424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3090 08:46:28.855282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3092 08:46:28.905871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3093 08:46:28.906724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3095 08:46:28.949839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3096 08:46:28.950710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3098 08:46:28.998554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3099 08:46:28.999385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3101 08:46:29.053397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3102 08:46:29.054257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3104 08:46:29.097654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3105 08:46:29.098502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3107 08:46:29.151187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3108 08:46:29.152066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3110 08:46:29.204245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3111 08:46:29.205149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3113 08:46:29.272108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3114 08:46:29.272921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3116 08:46:29.320502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3117 08:46:29.321334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3119 08:46:29.377919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3120 08:46:29.378728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3122 08:46:29.426558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3123 08:46:29.427399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3125 08:46:29.476896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3126 08:46:29.477752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3128 08:46:29.531410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3129 08:46:29.532284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3131 08:46:29.585971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3132 08:46:29.586767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3134 08:46:29.641129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3135 08:46:29.642015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3137 08:46:29.687594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3138 08:46:29.688401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3140 08:46:29.752816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3141 08:46:29.753604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3143 08:46:29.804470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3144 08:46:29.805239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3146 08:46:29.863074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3147 08:46:29.863859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3149 08:46:29.920500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3150 08:46:29.921356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3152 08:46:29.976988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3153 08:46:29.977782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3155 08:46:30.026261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3156 08:46:30.027027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3158 08:46:30.070333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3159 08:46:30.071154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3161 08:46:30.134808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3162 08:46:30.135570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3164 08:46:30.193652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3165 08:46:30.194415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3167 08:46:30.245017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3168 08:46:30.245784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3170 08:46:30.291638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3171 08:46:30.292432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3173 08:46:30.347827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3174 08:46:30.348639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3176 08:46:30.400182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3177 08:46:30.400952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3179 08:46:30.457167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3180 08:46:30.457961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3182 08:46:30.514933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3183 08:46:30.515732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3185 08:46:30.565231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3186 08:46:30.566028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3188 08:46:30.621379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3189 08:46:30.622188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3191 08:46:30.674323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3192 08:46:30.675108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3194 08:46:30.718101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3195 08:46:30.718898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3197 08:46:30.766759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3198 08:46:30.767541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3200 08:46:30.826466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3201 08:46:30.827249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3203 08:46:30.875249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3204 08:46:30.876065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3206 08:46:30.937595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3207 08:46:30.938411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3209 08:46:30.985868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3210 08:46:30.986717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3212 08:46:31.032657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3213 08:46:31.033431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3215 08:46:31.093223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3216 08:46:31.094077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3218 08:46:31.156235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3219 08:46:31.157070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3221 08:46:31.210306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3222 08:46:31.211133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3224 08:46:31.255824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3225 08:46:31.256685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3227 08:46:31.301792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3228 08:46:31.302717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3230 08:46:31.356236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3231 08:46:31.357071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3233 08:46:31.415068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3234 08:46:31.416032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3236 08:46:31.469238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3237 08:46:31.470083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3239 08:46:31.517450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3240 08:46:31.518335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3242 08:46:31.575358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3243 08:46:31.576166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3245 08:46:31.620015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3246 08:46:31.620847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3248 08:46:31.673589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3249 08:46:31.674388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3251 08:46:31.726979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3252 08:46:31.727760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3254 08:46:31.779872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3255 08:46:31.780693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3257 08:46:31.825497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3258 08:46:31.826287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3260 08:46:31.873576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3261 08:46:31.874358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3263 08:46:31.924794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3264 08:46:31.925555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3266 08:46:31.972264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3267 08:46:31.973130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3269 08:46:32.030251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3270 08:46:32.031047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3272 08:46:32.080882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3273 08:46:32.081657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3275 08:46:32.133845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3276 08:46:32.134633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3278 08:46:32.188892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3279 08:46:32.189673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3281 08:46:32.235346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3282 08:46:32.236104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3284 08:46:32.291088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3285 08:46:32.291844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3287 08:46:32.336176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3288 08:46:32.336964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3290 08:46:32.386744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3291 08:46:32.387520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3293 08:46:32.440442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3294 08:46:32.441206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3296 08:46:32.485652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3297 08:46:32.486496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3299 08:46:32.543779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3300 08:46:32.544595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3302 08:46:32.594878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3303 08:46:32.595646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3305 08:46:32.648851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3306 08:46:32.649662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3308 08:46:32.701891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3309 08:46:32.702669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3311 08:46:32.757530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3312 08:46:32.758290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3314 08:46:32.801944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3315 08:46:32.802732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3317 08:46:32.868775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3318 08:46:32.869706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3320 08:46:32.922863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3321 08:46:32.923797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3323 08:46:32.975592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3324 08:46:32.976596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3326 08:46:33.027065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3327 08:46:33.027898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3329 08:46:33.072313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3330 08:46:33.073273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3332 08:46:33.126789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3333 08:46:33.127600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3335 08:46:33.181098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3336 08:46:33.181963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3338 08:46:33.235089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3339 08:46:33.235872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3341 08:46:33.299671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3342 08:46:33.300484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3344 08:46:33.345211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3345 08:46:33.345986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3347 08:46:33.400538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3348 08:46:33.401364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3350 08:46:33.446089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3351 08:46:33.446856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3353 08:46:33.509007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3354 08:46:33.509806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3356 08:46:33.555936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3357 08:46:33.556747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3359 08:46:33.619905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3360 08:46:33.620705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3362 08:46:33.670630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3363 08:46:33.671409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3365 08:46:33.717764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3366 08:46:33.718546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3368 08:46:33.772995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3369 08:46:33.773775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3371 08:46:33.824494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3372 08:46:33.825253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3374 08:46:33.873657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3375 08:46:33.874406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3377 08:46:33.921663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3378 08:46:33.922447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3380 08:46:33.970041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3381 08:46:33.970830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3383 08:46:34.024624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3384 08:46:34.025387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3386 08:46:34.076952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3387 08:46:34.077741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3389 08:46:34.131708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3390 08:46:34.132525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3392 08:46:34.183388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3393 08:46:34.184202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3395 08:46:34.237006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3396 08:46:34.237789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3398 08:46:34.282792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3399 08:46:34.283570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3401 08:46:34.343902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3402 08:46:34.344699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3404 08:46:34.406352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3405 08:46:34.407119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3407 08:46:34.460891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3408 08:46:34.461684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3410 08:46:34.504762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3411 08:46:34.505538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3413 08:46:34.561256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3414 08:46:34.562015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3416 08:46:34.609031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3417 08:46:34.609818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3419 08:46:34.661099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3420 08:46:34.661897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3422 08:46:34.712491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3423 08:46:34.713239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3425 08:46:34.766266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3426 08:46:34.767032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3428 08:46:34.820102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3429 08:46:34.820876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3431 08:46:34.867391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3432 08:46:34.868142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3434 08:46:34.918817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3435 08:46:34.919591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3437 08:46:34.972011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3438 08:46:34.972797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3440 08:46:35.024278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3441 08:46:35.025021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3443 08:46:35.072031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3444 08:46:35.072809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3446 08:46:35.132848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3447 08:46:35.133628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3449 08:46:35.183529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3450 08:46:35.184315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3452 08:46:35.235139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3453 08:46:35.235892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3455 08:46:35.286011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3456 08:46:35.286783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3458 08:46:35.341418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3459 08:46:35.342234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3461 08:46:35.389126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3462 08:46:35.389902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3464 08:46:35.442893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3465 08:46:35.443664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3467 08:46:35.495885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3468 08:46:35.496811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3470 08:46:35.542969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3471 08:46:35.543768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3473 08:46:35.600412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3474 08:46:35.601288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3476 08:46:35.654754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3477 08:46:35.655589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3479 08:46:35.710522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3480 08:46:35.711344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3482 08:46:35.756806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3483 08:46:35.757595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3485 08:46:35.804238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3486 08:46:35.805018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3488 08:46:35.856648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3489 08:46:35.857465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3491 08:46:35.908985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3492 08:46:35.909812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3494 08:46:35.960191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3495 08:46:35.961078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3497 08:46:36.014305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3498 08:46:36.015182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3500 08:46:36.061979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3501 08:46:36.062794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3503 08:46:36.312413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3504 08:46:36.313363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3506 08:46:36.358641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3507 08:46:36.359520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3509 08:46:36.406371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3510 08:46:36.407082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3512 08:46:36.458804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3513 08:46:36.459653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3515 08:46:36.515503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3516 08:46:36.516354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3518 08:46:36.559926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3519 08:46:36.560733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3521 08:46:36.610139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3522 08:46:36.610923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3524 08:46:36.669281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3525 08:46:36.670069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3527 08:46:36.726988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3528 08:46:36.727777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3530 08:46:36.775571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3531 08:46:36.776375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3533 08:46:36.821293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3534 08:46:36.822083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3536 08:46:36.872031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3537 08:46:36.872941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3539 08:46:36.929555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3540 08:46:36.930442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3542 08:46:36.977876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3543 08:46:36.978530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3545 08:46:37.025090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3546 08:46:37.025761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3548 08:46:37.077653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3549 08:46:37.078300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3551 08:46:37.129953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3552 08:46:37.130639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3554 08:46:37.178638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3555 08:46:37.179283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3557 08:46:37.224063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3558 08:46:37.224701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3560 08:46:37.288204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3561 08:46:37.288819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3563 08:46:37.337645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3564 08:46:37.338228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3566 08:46:37.383941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3567 08:46:37.384815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3569 08:46:37.435288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3570 08:46:37.436111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3572 08:46:37.483821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3573 08:46:37.484688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3575 08:46:37.547423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3576 08:46:37.548279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3578 08:46:37.599501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3579 08:46:37.600355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3581 08:46:37.646422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3582 08:46:37.647260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3584 08:46:37.695158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3585 08:46:37.695966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3587 08:46:37.753416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3588 08:46:37.754227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3590 08:46:37.804538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3591 08:46:37.805325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3593 08:46:37.857580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3594 08:46:37.858392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3596 08:46:37.912504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3597 08:46:37.913306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3599 08:46:37.969770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3600 08:46:37.970574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3602 08:46:38.017840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3603 08:46:38.018680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3605 08:46:38.065947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3606 08:46:38.066788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3608 08:46:38.113902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3609 08:46:38.114697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3611 08:46:38.167750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3612 08:46:38.168592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3614 08:46:38.213719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3615 08:46:38.214511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3617 08:46:38.266381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3618 08:46:38.267172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3620 08:46:38.312090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3621 08:46:38.312885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3623 08:46:38.373839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3624 08:46:38.374632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3626 08:46:38.427301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3627 08:46:38.428097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3629 08:46:38.474660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3630 08:46:38.475463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3632 08:46:38.524075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3633 08:46:38.524912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3635 08:46:38.582280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3636 08:46:38.583091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3638 08:46:38.629776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3639 08:46:38.630578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3641 08:46:38.685340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3642 08:46:38.686145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3644 08:46:38.745279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3645 08:46:38.746124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3647 08:46:38.801592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3648 08:46:38.802409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3650 08:46:38.854840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3651 08:46:38.855658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3653 08:46:38.907107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3654 08:46:38.907901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3656 08:46:38.959626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3657 08:46:38.960377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3659 08:46:39.018407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3660 08:46:39.018991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3662 08:46:39.072568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3663 08:46:39.073267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3665 08:46:39.125816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3666 08:46:39.126521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3668 08:46:39.170875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3669 08:46:39.171610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3671 08:46:39.221892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3672 08:46:39.222519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3674 08:46:39.276173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3675 08:46:39.277019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3677 08:46:39.330817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3678 08:46:39.331621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3680 08:46:39.385094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3681 08:46:39.385924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3683 08:46:39.431185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3684 08:46:39.431965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3686 08:46:39.485563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3687 08:46:39.486397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3689 08:46:39.541632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3690 08:46:39.542401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3692 08:46:39.595224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3693 08:46:39.596078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3695 08:46:39.648714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3696 08:46:39.649621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3698 08:46:39.710993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3699 08:46:39.711890 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3701 08:46:39.757284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3702 08:46:39.758136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3704 08:46:39.814642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3705 08:46:39.815508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3707 08:46:39.890354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3708 08:46:39.891006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3710 08:46:39.945508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3711 08:46:39.946235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3713 08:46:40.003479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3714 08:46:40.004433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3716 08:46:40.065423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3717 08:46:40.066340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3719 08:46:40.122314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3720 08:46:40.123157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3722 08:46:40.182151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3723 08:46:40.182993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3725 08:46:40.243535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3726 08:46:40.244359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3728 08:46:40.287174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3729 08:46:40.287756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3731 08:46:40.333345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3732 08:46:40.333994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3734 08:46:40.391238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3735 08:46:40.392074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3737 08:46:40.449405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3738 08:46:40.450190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3740 08:46:40.504587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3741 08:46:40.505440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3743 08:46:40.563796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3744 08:46:40.564601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3746 08:46:40.615711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3747 08:46:40.616504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3749 08:46:40.667094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3750 08:46:40.667840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3752 08:46:40.719999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3753 08:46:40.720743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3755 08:46:40.767009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3756 08:46:40.767757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3758 08:46:40.814487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3759 08:46:40.815229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3761 08:46:40.861995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3762 08:46:40.862744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3764 08:46:40.911480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3765 08:46:40.912292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3767 08:46:40.965915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3768 08:46:40.966682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3770 08:46:41.023862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3771 08:46:41.024672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3773 08:46:41.073216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3774 08:46:41.074034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3776 08:46:41.131934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3777 08:46:41.132721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3779 08:46:41.182464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3780 08:46:41.183271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3782 08:46:41.240350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3783 08:46:41.241111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3785 08:46:41.292959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3786 08:46:41.293726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3788 08:46:41.351016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3789 08:46:41.351787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3791 08:46:41.414421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3792 08:46:41.415243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3794 08:46:41.465475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3795 08:46:41.466305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3797 08:46:41.519820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3798 08:46:41.520750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3800 08:46:41.569871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3801 08:46:41.570742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3803 08:46:41.629437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3804 08:46:41.630536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3806 08:46:41.680436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3807 08:46:41.681143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3809 08:46:41.735162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3810 08:46:41.735842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3812 08:46:41.782825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3813 08:46:41.783536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3815 08:46:41.832172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3816 08:46:41.832882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3818 08:46:41.880287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3819 08:46:41.880966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3821 08:46:41.930745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3822 08:46:41.931416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3824 08:46:41.988254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3825 08:46:41.988935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3827 08:46:42.041330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3828 08:46:42.042007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3830 08:46:42.092540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3831 08:46:42.093204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3833 08:46:42.146995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3834 08:46:42.147644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3836 08:46:42.198724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3837 08:46:42.199338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3839 08:46:42.253626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3840 08:46:42.254234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3842 08:46:42.301796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3843 08:46:42.302409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3845 08:46:42.349058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3846 08:46:42.349728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3848 08:46:42.409972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3849 08:46:42.410587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3851 08:46:42.464406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3852 08:46:42.465018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3854 08:46:42.519857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3855 08:46:42.520477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3857 08:46:42.575814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3858 08:46:42.576433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3860 08:46:42.631123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3861 08:46:42.631708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3863 08:46:42.685630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3864 08:46:42.686266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3866 08:46:42.732641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3867 08:46:42.733262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3869 08:46:42.787699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3870 08:46:42.788359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3872 08:46:42.839018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3873 08:46:42.839632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3875 08:46:42.890463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3876 08:46:42.891100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3878 08:46:42.939256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3879 08:46:42.939865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3881 08:46:42.987230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3882 08:46:42.987856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3884 08:46:43.045893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3885 08:46:43.046505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3887 08:46:43.106685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3888 08:46:43.107345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3890 08:46:43.157177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3891 08:46:43.157805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3893 08:46:43.214880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3894 08:46:43.215519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3896 08:46:43.263435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3897 08:46:43.264064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3899 08:46:43.312282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3900 08:46:43.312942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3902 08:46:43.374693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3903 08:46:43.375654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3905 08:46:43.420674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3906 08:46:43.421523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3908 08:46:43.472719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3909 08:46:43.473569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3911 08:46:43.527182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3912 08:46:43.528082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3914 08:46:43.575203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3915 08:46:43.576123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3917 08:46:43.621749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3918 08:46:43.622604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3920 08:46:43.677627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3921 08:46:43.678561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3923 08:46:43.722412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3924 08:46:43.723295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3926 08:46:43.781204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3927 08:46:43.782089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3929 08:46:43.836405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3930 08:46:43.837282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3932 08:46:43.886943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3933 08:46:43.887797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3935 08:46:43.934191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3936 08:46:43.935092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3938 08:46:43.983777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3939 08:46:43.984674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3941 08:46:44.028567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3942 08:46:44.029484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3944 08:46:44.085628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3945 08:46:44.086495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3947 08:46:44.129305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3948 08:46:44.130149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3950 08:46:44.185382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3951 08:46:44.186304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3953 08:46:44.238636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3954 08:46:44.239494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3956 08:46:44.297424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3957 08:46:44.298232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3959 08:46:44.344260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3960 08:46:44.345040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3962 08:46:44.390440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3963 08:46:44.391263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3965 08:46:44.445029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3966 08:46:44.445873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3968 08:46:44.499814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3969 08:46:44.500750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3971 08:46:44.561585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3972 08:46:44.562426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3974 08:46:44.610531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3975 08:46:44.611343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3977 08:46:44.676476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3978 08:46:44.677270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3980 08:46:44.736081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3981 08:46:44.736932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3983 08:46:44.794921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3984 08:46:44.795746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3986 08:46:44.840197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3987 08:46:44.841003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3989 08:46:44.895113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3990 08:46:44.895930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3992 08:46:44.943098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3993 08:46:44.943998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3995 08:46:44.993197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3996 08:46:44.994101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3998 08:46:45.049474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3999 08:46:45.050357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4001 08:46:45.104846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4002 08:46:45.105680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4004 08:46:45.162510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4005 08:46:45.163282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4007 08:46:45.217557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4008 08:46:45.218322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4010 08:46:45.267143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4011 08:46:45.267903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4013 08:46:45.325776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4014 08:46:45.326525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4016 08:46:45.377845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4017 08:46:45.378606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4019 08:46:45.423167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4020 08:46:45.423942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4022 08:46:45.468935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4023 08:46:45.469518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4025 08:46:45.516784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4026 08:46:45.517383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4028 08:46:45.569676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4029 08:46:45.570291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4031 08:46:45.628274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4032 08:46:45.628809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4034 08:46:45.679519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4035 08:46:45.680348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4037 08:46:45.728346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4038 08:46:45.729111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4040 08:46:45.775128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4041 08:46:45.775877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4043 08:46:45.825018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4044 08:46:45.825785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4046 08:46:45.880464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4047 08:46:45.881238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4049 08:46:45.934419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4050 08:46:45.935200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4052 08:46:45.985777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4053 08:46:45.986520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4055 08:46:46.037757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4056 08:46:46.038505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4058 08:46:46.086474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4059 08:46:46.087223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4061 08:46:46.143452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4062 08:46:46.144049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4064 08:46:46.199502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4065 08:46:46.200070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4067 08:46:46.246321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4068 08:46:46.246920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4070 08:46:46.301076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4071 08:46:46.302006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4073 08:46:46.349946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4074 08:46:46.350799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4076 08:46:46.401434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4077 08:46:46.402344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4079 08:46:46.463244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4080 08:46:46.464086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4082 08:46:46.517586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4083 08:46:46.518394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4085 08:46:46.566567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4086 08:46:46.567433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4088 08:46:46.622911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4089 08:46:46.623718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4091 08:46:46.683175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4092 08:46:46.683947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4094 08:46:46.729513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4095 08:46:46.730302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4097 08:46:46.793770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4098 08:46:46.794652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4100 08:46:46.851077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4101 08:46:46.851858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4103 08:46:46.903183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4104 08:46:46.904024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4106 08:46:46.947560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4107 08:46:46.948456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4109 08:46:47.003212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4110 08:46:47.003773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4112 08:46:47.050390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4113 08:46:47.051203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4115 08:46:47.103081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4116 08:46:47.103743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4118 08:46:47.152856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4119 08:46:47.153739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4121 08:46:47.199280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4122 08:46:47.200149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4124 08:46:47.246478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4125 08:46:47.247345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4127 08:46:47.303830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4128 08:46:47.304747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4130 08:46:47.355086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4131 08:46:47.355960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4133 08:46:47.415438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4134 08:46:47.416433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4136 08:46:47.467360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4137 08:46:47.467953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4139 08:46:47.515395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4140 08:46:47.516324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4142 08:46:47.560411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4143 08:46:47.561315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4145 08:46:47.614971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4146 08:46:47.615819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4148 08:46:47.661821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4149 08:46:47.662715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4151 08:46:47.716380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4152 08:46:47.717278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4154 08:46:47.773849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4155 08:46:47.774494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4157 08:46:47.821139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4158 08:46:47.821772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4160 08:46:47.873796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4161 08:46:47.874648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4163 08:46:47.919806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4164 08:46:47.920652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4166 08:46:47.972914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4167 08:46:47.973594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4169 08:46:48.019321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4170 08:46:48.019968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4172 08:46:48.064438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4173 08:46:48.065064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4175 08:46:48.117740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4176 08:46:48.118359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4178 08:46:48.173022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4179 08:46:48.173948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4181 08:46:48.223733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4182 08:46:48.224671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4184 08:46:48.269036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4185 08:46:48.269943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4187 08:46:48.321015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4188 08:46:48.321857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4190 08:46:48.379399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4191 08:46:48.380399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4193 08:46:48.432402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4194 08:46:48.433307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4196 08:46:48.485131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4197 08:46:48.486064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4199 08:46:48.544286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4200 08:46:48.545228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4202 08:46:48.593496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4203 08:46:48.594398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4205 08:46:48.650191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4206 08:46:48.651249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4208 08:46:48.701396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4210 08:46:48.704350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4211 08:46:48.763054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4212 08:46:48.764043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4214 08:46:48.821484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4215 08:46:48.822395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4217 08:46:48.879085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4218 08:46:48.880168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4220 08:46:48.932317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4221 08:46:48.933353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4223 08:46:48.988726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4224 08:46:48.989741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4226 08:46:49.048859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4227 08:46:49.049842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4229 08:46:49.103073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4230 08:46:49.104096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4232 08:46:49.155606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4233 08:46:49.156510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4235 08:46:49.206834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4236 08:46:49.207791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4238 08:46:49.259895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4239 08:46:49.260880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4241 08:46:49.315201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4242 08:46:49.316113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4244 08:46:49.369186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4245 08:46:49.370126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4247 08:46:49.428343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4248 08:46:49.429257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4250 08:46:49.475767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4251 08:46:49.476713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4253 08:46:49.534999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4254 08:46:49.535945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4256 08:46:49.588897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4257 08:46:49.589799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4259 08:46:49.637775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4260 08:46:49.638675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4262 08:46:49.692152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4263 08:46:49.693092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4265 08:46:49.750697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4266 08:46:49.751650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4268 08:46:49.804934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4269 08:46:49.805737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4271 08:46:49.855219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4272 08:46:49.856024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4274 08:46:49.909582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4275 08:46:49.910355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4277 08:46:49.961217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4278 08:46:49.961967 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4280 08:46:50.016006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4281 08:46:50.016759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4283 08:46:50.071593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4284 08:46:50.072366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4286 08:46:50.126527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4287 08:46:50.127285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4289 08:46:50.172581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4290 08:46:50.173339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4292 08:46:50.221724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4293 08:46:50.222559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4295 08:46:50.279769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4296 08:46:50.280570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4298 08:46:50.345114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4299 08:46:50.345858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4301 08:46:50.396398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4302 08:46:50.397137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4304 08:46:50.440598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4305 08:46:50.441312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4307 08:46:50.494678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4308 08:46:50.495738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4310 08:46:50.546783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4311 08:46:50.547815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4313 08:46:50.598873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4314 08:46:50.599685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4316 08:46:50.653715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4317 08:46:50.654525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4319 08:46:50.701592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4320 08:46:50.702326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4322 08:46:50.761939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4323 08:46:50.762644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4325 08:46:50.822704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4326 08:46:50.823528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4328 08:46:50.874448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4329 08:46:50.875019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4331 08:46:50.924231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4332 08:46:50.924855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4334 08:46:50.973700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4335 08:46:50.974526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4337 08:46:51.031900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4338 08:46:51.032761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4340 08:46:51.090592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4341 08:46:51.091398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4343 08:46:51.148446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4344 08:46:51.149195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4346 08:46:51.205182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4347 08:46:51.205963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4349 08:46:51.260243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4350 08:46:51.260956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4352 08:46:51.315660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4353 08:46:51.316507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4355 08:46:51.362434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4356 08:46:51.363241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4358 08:46:51.418363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4359 08:46:51.419102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4361 08:46:51.474550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4362 08:46:51.475329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4364 08:46:51.533447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4366 08:46:51.538631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4367 08:46:51.539088 + set +x
4368 08:46:51.543316 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 742845_1.6.2.4.5>
4369 08:46:51.543759 <LAVA_TEST_RUNNER EXIT>
4370 08:46:51.544461 Received signal: <ENDRUN> 1_kselftest-alsa 742845_1.6.2.4.5
4371 08:46:51.544917 Ending use of test pattern.
4372 08:46:51.545325 Ending test lava.1_kselftest-alsa (742845_1.6.2.4.5), duration 41.55
4374 08:46:51.546817 ok: lava_test_shell seems to have completed
4375 08:46:51.569237 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4376 08:46:51.571001 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4377 08:46:51.571581 end: 3 lava-test-retry (duration 00:00:42) [common]
4378 08:46:51.572175 start: 4 finalize (timeout 00:05:59) [common]
4379 08:46:51.572750 start: 4.1 power-off (timeout 00:00:30) [common]
4380 08:46:51.573716 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4381 08:46:51.608367 >> OK - accepted request
4382 08:46:51.610303 Returned 0 in 0 seconds
4383 08:46:51.711414 end: 4.1 power-off (duration 00:00:00) [common]
4385 08:46:51.713142 start: 4.2 read-feedback (timeout 00:05:59) [common]
4386 08:46:51.714335 Listened to connection for namespace 'common' for up to 1s
4387 08:46:51.715243 Listened to connection for namespace 'common' for up to 1s
4388 08:46:52.715074 Finalising connection for namespace 'common'
4389 08:46:52.715771 Disconnecting from shell: Finalise
4390 08:46:52.716376 / #
4391 08:46:52.817323 end: 4.2 read-feedback (duration 00:00:01) [common]
4392 08:46:52.817975 end: 4 finalize (duration 00:00:01) [common]
4393 08:46:52.818634 Cleaning after the job
4394 08:46:52.819242 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/ramdisk
4395 08:46:52.822341 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/kernel
4396 08:46:52.850485 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/dtb
4397 08:46:52.852052 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/nfsrootfs
4398 08:46:52.901866 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742845/tftp-deploy-dax833k9/modules
4399 08:46:52.905501 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/742845
4400 08:46:56.292626 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/742845
4401 08:46:56.293196 Job finished correctly