Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:13:49.540586 lava-dispatcher, installed at version: 2024.01
2 08:13:49.541367 start: 0 validate
3 08:13:49.541879 Start time: 2024-09-19 08:13:49.541848+00:00 (UTC)
4 08:13:49.542423 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:13:49.542967 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 08:13:49.589762 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:13:49.590329 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:13:49.625857 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:13:49.626497 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:13:49.660704 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:13:49.661215 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:13:49.703512 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:13:49.704069 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20240919%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 08:13:49.747728 validate duration: 0.21
16 08:13:49.749306 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:13:49.749965 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:13:49.750599 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:13:49.751548 Not decompressing ramdisk as can be used compressed.
20 08:13:49.752334 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 08:13:49.752847 saving as /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/ramdisk/initrd.cpio.gz
22 08:13:49.753352 total size: 5628140 (5 MB)
23 08:13:49.796676 progress 0 % (0 MB)
24 08:13:49.804783 progress 5 % (0 MB)
25 08:13:49.813413 progress 10 % (0 MB)
26 08:13:49.821450 progress 15 % (0 MB)
27 08:13:49.829980 progress 20 % (1 MB)
28 08:13:49.836493 progress 25 % (1 MB)
29 08:13:49.840550 progress 30 % (1 MB)
30 08:13:49.844538 progress 35 % (1 MB)
31 08:13:49.848096 progress 40 % (2 MB)
32 08:13:49.852206 progress 45 % (2 MB)
33 08:13:49.855902 progress 50 % (2 MB)
34 08:13:49.859850 progress 55 % (2 MB)
35 08:13:49.863765 progress 60 % (3 MB)
36 08:13:49.867294 progress 65 % (3 MB)
37 08:13:49.871204 progress 70 % (3 MB)
38 08:13:49.874724 progress 75 % (4 MB)
39 08:13:49.878751 progress 80 % (4 MB)
40 08:13:49.882282 progress 85 % (4 MB)
41 08:13:49.886216 progress 90 % (4 MB)
42 08:13:49.889945 progress 95 % (5 MB)
43 08:13:49.893192 progress 100 % (5 MB)
44 08:13:49.893838 5 MB downloaded in 0.14 s (38.21 MB/s)
45 08:13:49.894385 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:13:49.895279 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:13:49.895575 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:13:49.895845 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:13:49.896348 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/kernel/Image
51 08:13:49.896593 saving as /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/kernel/Image
52 08:13:49.896803 total size: 45724160 (43 MB)
53 08:13:49.897015 No compression specified
54 08:13:49.936805 progress 0 % (0 MB)
55 08:13:49.964539 progress 5 % (2 MB)
56 08:13:49.994212 progress 10 % (4 MB)
57 08:13:50.022394 progress 15 % (6 MB)
58 08:13:50.050452 progress 20 % (8 MB)
59 08:13:50.078650 progress 25 % (10 MB)
60 08:13:50.106524 progress 30 % (13 MB)
61 08:13:50.134512 progress 35 % (15 MB)
62 08:13:50.162485 progress 40 % (17 MB)
63 08:13:50.190301 progress 45 % (19 MB)
64 08:13:50.218238 progress 50 % (21 MB)
65 08:13:50.246201 progress 55 % (24 MB)
66 08:13:50.274499 progress 60 % (26 MB)
67 08:13:50.302514 progress 65 % (28 MB)
68 08:13:50.330100 progress 70 % (30 MB)
69 08:13:50.358122 progress 75 % (32 MB)
70 08:13:50.386959 progress 80 % (34 MB)
71 08:13:50.415297 progress 85 % (37 MB)
72 08:13:50.443145 progress 90 % (39 MB)
73 08:13:50.472434 progress 95 % (41 MB)
74 08:13:50.500931 progress 100 % (43 MB)
75 08:13:50.501544 43 MB downloaded in 0.60 s (72.11 MB/s)
76 08:13:50.502058 end: 1.2.1 http-download (duration 00:00:01) [common]
78 08:13:50.502967 end: 1.2 download-retry (duration 00:00:01) [common]
79 08:13:50.503272 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:13:50.503559 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:13:50.504079 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 08:13:50.504369 saving as /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/dtb/meson-g12b-a311d-libretech-cc.dtb
83 08:13:50.504589 total size: 54703 (0 MB)
84 08:13:50.504809 No compression specified
85 08:13:50.547780 progress 59 % (0 MB)
86 08:13:50.548686 progress 100 % (0 MB)
87 08:13:50.549244 0 MB downloaded in 0.04 s (1.17 MB/s)
88 08:13:50.549725 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:13:50.550547 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:13:50.550814 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:13:50.551080 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:13:50.551548 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 08:13:50.551791 saving as /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/nfsrootfs/full.rootfs.tar
95 08:13:50.552020 total size: 474398908 (452 MB)
96 08:13:50.552242 Using unxz to decompress xz
97 08:13:50.586017 progress 0 % (0 MB)
98 08:13:51.686911 progress 5 % (22 MB)
99 08:13:53.179405 progress 10 % (45 MB)
100 08:13:53.638601 progress 15 % (67 MB)
101 08:13:54.502541 progress 20 % (90 MB)
102 08:13:55.050813 progress 25 % (113 MB)
103 08:13:55.418112 progress 30 % (135 MB)
104 08:13:56.020444 progress 35 % (158 MB)
105 08:13:56.847073 progress 40 % (181 MB)
106 08:13:57.600355 progress 45 % (203 MB)
107 08:13:58.245735 progress 50 % (226 MB)
108 08:13:58.924937 progress 55 % (248 MB)
109 08:14:00.145230 progress 60 % (271 MB)
110 08:14:01.639731 progress 65 % (294 MB)
111 08:14:03.242632 progress 70 % (316 MB)
112 08:14:06.345145 progress 75 % (339 MB)
113 08:14:08.779724 progress 80 % (361 MB)
114 08:14:11.727442 progress 85 % (384 MB)
115 08:14:14.938100 progress 90 % (407 MB)
116 08:14:18.210806 progress 95 % (429 MB)
117 08:14:21.381605 progress 100 % (452 MB)
118 08:14:21.395843 452 MB downloaded in 30.84 s (14.67 MB/s)
119 08:14:21.396784 end: 1.4.1 http-download (duration 00:00:31) [common]
121 08:14:21.398442 end: 1.4 download-retry (duration 00:00:31) [common]
122 08:14:21.398982 start: 1.5 download-retry (timeout 00:09:28) [common]
123 08:14:21.399511 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 08:14:21.400378 downloading http://storage.kernelci.org/next/master/next-20240919/arm64/defconfig/gcc-12/modules.tar.xz
125 08:14:21.400888 saving as /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/modules/modules.tar
126 08:14:21.401354 total size: 11604668 (11 MB)
127 08:14:21.401786 Using unxz to decompress xz
128 08:14:21.444211 progress 0 % (0 MB)
129 08:14:21.511910 progress 5 % (0 MB)
130 08:14:21.596835 progress 10 % (1 MB)
131 08:14:21.683666 progress 15 % (1 MB)
132 08:14:21.764731 progress 20 % (2 MB)
133 08:14:21.841802 progress 25 % (2 MB)
134 08:14:21.920392 progress 30 % (3 MB)
135 08:14:21.992518 progress 35 % (3 MB)
136 08:14:22.071559 progress 40 % (4 MB)
137 08:14:22.153515 progress 45 % (5 MB)
138 08:14:22.232897 progress 50 % (5 MB)
139 08:14:22.312931 progress 55 % (6 MB)
140 08:14:22.390916 progress 60 % (6 MB)
141 08:14:22.476014 progress 65 % (7 MB)
142 08:14:22.550388 progress 70 % (7 MB)
143 08:14:22.633641 progress 75 % (8 MB)
144 08:14:22.729343 progress 80 % (8 MB)
145 08:14:22.828942 progress 85 % (9 MB)
146 08:14:22.898028 progress 90 % (9 MB)
147 08:14:22.975761 progress 95 % (10 MB)
148 08:14:23.050594 progress 100 % (11 MB)
149 08:14:23.062725 11 MB downloaded in 1.66 s (6.66 MB/s)
150 08:14:23.063670 end: 1.5.1 http-download (duration 00:00:02) [common]
152 08:14:23.065496 end: 1.5 download-retry (duration 00:00:02) [common]
153 08:14:23.066072 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 08:14:23.066645 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 08:14:38.743088 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/742785/extract-nfsrootfs-l450x7w0
156 08:14:38.743682 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 08:14:38.743974 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 08:14:38.744647 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc
159 08:14:38.745105 makedir: /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin
160 08:14:38.745463 makedir: /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/tests
161 08:14:38.745788 makedir: /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/results
162 08:14:38.746118 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-add-keys
163 08:14:38.746687 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-add-sources
164 08:14:38.747280 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-background-process-start
165 08:14:38.747806 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-background-process-stop
166 08:14:38.748375 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-common-functions
167 08:14:38.748910 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-echo-ipv4
168 08:14:38.749433 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-install-packages
169 08:14:38.749990 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-installed-packages
170 08:14:38.750528 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-os-build
171 08:14:38.751019 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-probe-channel
172 08:14:38.751514 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-probe-ip
173 08:14:38.752024 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-target-ip
174 08:14:38.752543 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-target-mac
175 08:14:38.753042 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-target-storage
176 08:14:38.753541 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-test-case
177 08:14:38.754048 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-test-event
178 08:14:38.754538 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-test-feedback
179 08:14:38.755063 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-test-raise
180 08:14:38.755729 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-test-reference
181 08:14:38.756283 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-test-runner
182 08:14:38.756807 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-test-set
183 08:14:38.757298 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-test-shell
184 08:14:38.757803 Updating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-install-packages (oe)
185 08:14:38.758385 Updating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/bin/lava-installed-packages (oe)
186 08:14:38.758850 Creating /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/environment
187 08:14:38.759224 LAVA metadata
188 08:14:38.759482 - LAVA_JOB_ID=742785
189 08:14:38.759696 - LAVA_DISPATCHER_IP=192.168.6.2
190 08:14:38.760076 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 08:14:38.761035 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 08:14:38.761342 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 08:14:38.761548 skipped lava-vland-overlay
194 08:14:38.761790 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 08:14:38.762043 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 08:14:38.762258 skipped lava-multinode-overlay
197 08:14:38.762498 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 08:14:38.762749 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 08:14:38.762998 Loading test definitions
200 08:14:38.763286 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 08:14:38.763506 Using /lava-742785 at stage 0
202 08:14:38.764729 uuid=742785_1.6.2.4.1 testdef=None
203 08:14:38.765040 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 08:14:38.765301 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 08:14:38.767017 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 08:14:38.767809 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 08:14:38.770017 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 08:14:38.770843 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 08:14:38.773086 runner path: /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 742785_1.6.2.4.1
212 08:14:38.773686 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 08:14:38.774452 Creating lava-test-runner.conf files
215 08:14:38.774653 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/742785/lava-overlay-1_wz3afc/lava-742785/0 for stage 0
216 08:14:38.775028 - 0_v4l2-decoder-conformance-vp9
217 08:14:38.775376 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 08:14:38.775652 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 08:14:38.797731 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 08:14:38.798118 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 08:14:38.798380 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 08:14:38.798647 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 08:14:38.798911 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 08:14:39.512099 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 08:14:39.512592 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 08:14:39.512858 extracting modules file /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742785/extract-nfsrootfs-l450x7w0
227 08:14:41.164425 extracting modules file /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/742785/extract-overlay-ramdisk-p9ltz0k1/ramdisk
228 08:14:42.596390 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 08:14:42.596864 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 08:14:42.597179 [common] Applying overlay to NFS
231 08:14:42.597415 [common] Applying overlay /var/lib/lava/dispatcher/tmp/742785/compress-overlay-tav7h07w/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/742785/extract-nfsrootfs-l450x7w0
232 08:14:42.627415 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 08:14:42.627852 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 08:14:42.628187 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 08:14:42.628441 Converting downloaded kernel to a uImage
236 08:14:42.628773 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/kernel/Image /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/kernel/uImage
237 08:14:43.095414 output: Image Name:
238 08:14:43.095838 output: Created: Thu Sep 19 08:14:42 2024
239 08:14:43.096089 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 08:14:43.096302 output: Data Size: 45724160 Bytes = 44652.50 KiB = 43.61 MiB
241 08:14:43.096506 output: Load Address: 01080000
242 08:14:43.096709 output: Entry Point: 01080000
243 08:14:43.096908 output:
244 08:14:43.097246 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 08:14:43.097517 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 08:14:43.097786 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 08:14:43.098044 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 08:14:43.098305 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 08:14:43.098560 Building ramdisk /var/lib/lava/dispatcher/tmp/742785/extract-overlay-ramdisk-p9ltz0k1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/742785/extract-overlay-ramdisk-p9ltz0k1/ramdisk
250 08:14:45.452810 >> 166871 blocks
251 08:14:53.206614 Adding RAMdisk u-boot header.
252 08:14:53.207272 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/742785/extract-overlay-ramdisk-p9ltz0k1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/742785/extract-overlay-ramdisk-p9ltz0k1/ramdisk.cpio.gz.uboot
253 08:14:53.448151 output: Image Name:
254 08:14:53.448577 output: Created: Thu Sep 19 08:14:53 2024
255 08:14:53.448797 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 08:14:53.449007 output: Data Size: 23440827 Bytes = 22891.43 KiB = 22.35 MiB
257 08:14:53.449212 output: Load Address: 00000000
258 08:14:53.449413 output: Entry Point: 00000000
259 08:14:53.449612 output:
260 08:14:53.450276 rename /var/lib/lava/dispatcher/tmp/742785/extract-overlay-ramdisk-p9ltz0k1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/ramdisk/ramdisk.cpio.gz.uboot
261 08:14:53.450718 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 08:14:53.451011 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 08:14:53.451287 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 08:14:53.451539 No LXC device requested
265 08:14:53.451799 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 08:14:53.452201 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 08:14:53.452712 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 08:14:53.453142 Checking files for TFTP limit of 4294967296 bytes.
269 08:14:53.455812 end: 1 tftp-deploy (duration 00:01:04) [common]
270 08:14:53.456443 start: 2 uboot-action (timeout 00:05:00) [common]
271 08:14:53.456973 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 08:14:53.457470 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 08:14:53.457975 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 08:14:53.458506 Using kernel file from prepare-kernel: 742785/tftp-deploy-fxargv8v/kernel/uImage
275 08:14:53.459139 substitutions:
276 08:14:53.459546 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 08:14:53.459949 - {DTB_ADDR}: 0x01070000
278 08:14:53.460382 - {DTB}: 742785/tftp-deploy-fxargv8v/dtb/meson-g12b-a311d-libretech-cc.dtb
279 08:14:53.460779 - {INITRD}: 742785/tftp-deploy-fxargv8v/ramdisk/ramdisk.cpio.gz.uboot
280 08:14:53.461177 - {KERNEL_ADDR}: 0x01080000
281 08:14:53.461571 - {KERNEL}: 742785/tftp-deploy-fxargv8v/kernel/uImage
282 08:14:53.461965 - {LAVA_MAC}: None
283 08:14:53.462397 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/742785/extract-nfsrootfs-l450x7w0
284 08:14:53.462796 - {NFS_SERVER_IP}: 192.168.6.2
285 08:14:53.463189 - {PRESEED_CONFIG}: None
286 08:14:53.463582 - {PRESEED_LOCAL}: None
287 08:14:53.463972 - {RAMDISK_ADDR}: 0x08000000
288 08:14:53.464416 - {RAMDISK}: 742785/tftp-deploy-fxargv8v/ramdisk/ramdisk.cpio.gz.uboot
289 08:14:53.464809 - {ROOT_PART}: None
290 08:14:53.465201 - {ROOT}: None
291 08:14:53.465591 - {SERVER_IP}: 192.168.6.2
292 08:14:53.465982 - {TEE_ADDR}: 0x83000000
293 08:14:53.466376 - {TEE}: None
294 08:14:53.466769 Parsed boot commands:
295 08:14:53.467152 - setenv autoload no
296 08:14:53.467540 - setenv initrd_high 0xffffffff
297 08:14:53.467931 - setenv fdt_high 0xffffffff
298 08:14:53.468354 - dhcp
299 08:14:53.468751 - setenv serverip 192.168.6.2
300 08:14:53.469140 - tftpboot 0x01080000 742785/tftp-deploy-fxargv8v/kernel/uImage
301 08:14:53.469534 - tftpboot 0x08000000 742785/tftp-deploy-fxargv8v/ramdisk/ramdisk.cpio.gz.uboot
302 08:14:53.469925 - tftpboot 0x01070000 742785/tftp-deploy-fxargv8v/dtb/meson-g12b-a311d-libretech-cc.dtb
303 08:14:53.470318 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/742785/extract-nfsrootfs-l450x7w0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 08:14:53.470724 - bootm 0x01080000 0x08000000 0x01070000
305 08:14:53.471245 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 08:14:53.472777 start: 2.3 connect-device (timeout 00:05:00) [common]
308 08:14:53.473206 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 08:14:53.488681 Setting prompt string to ['lava-test: # ']
310 08:14:53.490198 end: 2.3 connect-device (duration 00:00:00) [common]
311 08:14:53.490782 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 08:14:53.491315 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 08:14:53.491833 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 08:14:53.493025 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 08:14:53.533203 >> OK - accepted request
316 08:14:53.536163 Returned 0 in 0 seconds
317 08:14:53.637518 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 08:14:53.639110 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 08:14:53.639662 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 08:14:53.640236 Setting prompt string to ['Hit any key to stop autoboot']
322 08:14:53.640698 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 08:14:53.642304 Trying 192.168.56.21...
324 08:14:53.642826 Connected to conserv1.
325 08:14:53.643253 Escape character is '^]'.
326 08:14:53.643671
327 08:14:53.644130 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 08:14:53.644569
329 08:15:05.223523 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 08:15:05.223940 bl2_stage_init 0x01
331 08:15:05.224201 bl2_stage_init 0x81
332 08:15:05.229157 hw id: 0x0000 - pwm id 0x01
333 08:15:05.229435 bl2_stage_init 0xc1
334 08:15:05.229640 bl2_stage_init 0x02
335 08:15:05.229840
336 08:15:05.234694 L0:00000000
337 08:15:05.234958 L1:20000703
338 08:15:05.235160 L2:00008067
339 08:15:05.235355 L3:14000000
340 08:15:05.237648 B2:00402000
341 08:15:05.237887 B1:e0f83180
342 08:15:05.238089
343 08:15:05.238288 TE: 58167
344 08:15:05.238486
345 08:15:05.248728 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 08:15:05.249014
347 08:15:05.249218 Board ID = 1
348 08:15:05.249415 Set A53 clk to 24M
349 08:15:05.249610 Set A73 clk to 24M
350 08:15:05.254424 Set clk81 to 24M
351 08:15:05.254664 A53 clk: 1200 MHz
352 08:15:05.254866 A73 clk: 1200 MHz
353 08:15:05.257910 CLK81: 166.6M
354 08:15:05.258165 smccc: 00012abe
355 08:15:05.263444 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 08:15:05.269130 board id: 1
357 08:15:05.274178 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 08:15:05.284860 fw parse done
359 08:15:05.290838 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 08:15:05.333428 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 08:15:05.344243 PIEI prepare done
362 08:15:05.344680 fastboot data load
363 08:15:05.345077 fastboot data verify
364 08:15:05.349807 verify result: 266
365 08:15:05.355420 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 08:15:05.355848 LPDDR4 probe
367 08:15:05.356292 ddr clk to 1584MHz
368 08:15:05.363433 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 08:15:05.400674
370 08:15:05.401122 dmc_version 0001
371 08:15:05.407428 Check phy result
372 08:15:05.413227 INFO : End of CA training
373 08:15:05.413734 INFO : End of initialization
374 08:15:05.418757 INFO : Training has run successfully!
375 08:15:05.419208 Check phy result
376 08:15:05.424376 INFO : End of initialization
377 08:15:05.424845 INFO : End of read enable training
378 08:15:05.429932 INFO : End of fine write leveling
379 08:15:05.435581 INFO : End of Write leveling coarse delay
380 08:15:05.436047 INFO : Training has run successfully!
381 08:15:05.436459 Check phy result
382 08:15:05.441180 INFO : End of initialization
383 08:15:05.441621 INFO : End of read dq deskew training
384 08:15:05.446798 INFO : End of MPR read delay center optimization
385 08:15:05.452377 INFO : End of write delay center optimization
386 08:15:05.457992 INFO : End of read delay center optimization
387 08:15:05.458493 INFO : End of max read latency training
388 08:15:05.463587 INFO : Training has run successfully!
389 08:15:05.463882 1D training succeed
390 08:15:05.472771 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 08:15:05.520535 Check phy result
392 08:15:05.521107 INFO : End of initialization
393 08:15:05.541991 INFO : End of 2D read delay Voltage center optimization
394 08:15:05.561220 INFO : End of 2D read delay Voltage center optimization
395 08:15:05.613189 INFO : End of 2D write delay Voltage center optimization
396 08:15:05.662437 INFO : End of 2D write delay Voltage center optimization
397 08:15:05.667938 INFO : Training has run successfully!
398 08:15:05.668298
399 08:15:05.668566 channel==0
400 08:15:05.673542 RxClkDly_Margin_A0==88 ps 9
401 08:15:05.673863 TxDqDly_Margin_A0==98 ps 10
402 08:15:05.679156 RxClkDly_Margin_A1==88 ps 9
403 08:15:05.679532 TxDqDly_Margin_A1==98 ps 10
404 08:15:05.679794 TrainedVREFDQ_A0==74
405 08:15:05.684746 TrainedVREFDQ_A1==74
406 08:15:05.685094 VrefDac_Margin_A0==25
407 08:15:05.685351 DeviceVref_Margin_A0==40
408 08:15:05.690379 VrefDac_Margin_A1==25
409 08:15:05.690698 DeviceVref_Margin_A1==40
410 08:15:05.690944
411 08:15:05.691182
412 08:15:05.695918 channel==1
413 08:15:05.696262 RxClkDly_Margin_A0==88 ps 9
414 08:15:05.696523 TxDqDly_Margin_A0==88 ps 9
415 08:15:05.701526 RxClkDly_Margin_A1==88 ps 9
416 08:15:05.701842 TxDqDly_Margin_A1==88 ps 9
417 08:15:05.707120 TrainedVREFDQ_A0==77
418 08:15:05.707438 TrainedVREFDQ_A1==77
419 08:15:05.707690 VrefDac_Margin_A0==23
420 08:15:05.712727 DeviceVref_Margin_A0==37
421 08:15:05.713049 VrefDac_Margin_A1==24
422 08:15:05.718365 DeviceVref_Margin_A1==37
423 08:15:05.718683
424 08:15:05.718942 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 08:15:05.719179
426 08:15:05.751928 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 08:15:05.752374 2D training succeed
428 08:15:05.757525 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 08:15:05.763131 auto size-- 65535DDR cs0 size: 2048MB
430 08:15:05.763451 DDR cs1 size: 2048MB
431 08:15:05.768762 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 08:15:05.769126 cs0 DataBus test pass
433 08:15:05.774388 cs1 DataBus test pass
434 08:15:05.774703 cs0 AddrBus test pass
435 08:15:05.774948 cs1 AddrBus test pass
436 08:15:05.775187
437 08:15:05.779926 100bdlr_step_size ps== 420
438 08:15:05.780280 result report
439 08:15:05.785531 boot times 0Enable ddr reg access
440 08:15:05.790713 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 08:15:05.804197 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 08:15:06.376271 0.0;M3 CHK:0;cm4_sp_mode 0
443 08:15:06.376708 MVN_1=0x00000000
444 08:15:06.381725 MVN_2=0x00000000
445 08:15:06.387412 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 08:15:06.387694 OPS=0x10
447 08:15:06.387904 ring efuse init
448 08:15:06.388140 chipver efuse init
449 08:15:06.395764 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 08:15:06.396087 [0.018960 Inits done]
451 08:15:06.396298 secure task start!
452 08:15:06.403283 high task start!
453 08:15:06.403607 low task start!
454 08:15:06.403814 run into bl31
455 08:15:06.409932 NOTICE: BL31: v1.3(release):4fc40b1
456 08:15:06.417785 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 08:15:06.418149 NOTICE: BL31: G12A normal boot!
458 08:15:06.443037 NOTICE: BL31: BL33 decompress pass
459 08:15:06.448726 ERROR: Error initializing runtime service opteed_fast
460 08:15:07.681751
461 08:15:07.682163
462 08:15:07.690083 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 08:15:07.690356
464 08:15:07.690576 Model: Libre Computer AML-A311D-CC Alta
465 08:15:07.898544 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 08:15:07.921898 DRAM: 2 GiB (effective 3.8 GiB)
467 08:15:08.064924 Core: 408 devices, 31 uclasses, devicetree: separate
468 08:15:08.070890 WDT: Not starting watchdog@f0d0
469 08:15:08.103085 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 08:15:08.115505 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 08:15:08.120468 ** Bad device specification mmc 0 **
472 08:15:08.130889 Card did not respond to voltage select! : -110
473 08:15:08.138494 ** Bad device specification mmc 0 **
474 08:15:08.139017 Couldn't find partition mmc 0
475 08:15:08.146828 Card did not respond to voltage select! : -110
476 08:15:08.152353 ** Bad device specification mmc 0 **
477 08:15:08.152869 Couldn't find partition mmc 0
478 08:15:08.157413 Error: could not access storage.
479 08:15:09.424213 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 08:15:09.425091 bl2_stage_init 0x01
481 08:15:09.425750 bl2_stage_init 0x81
482 08:15:09.429680 hw id: 0x0000 - pwm id 0x01
483 08:15:09.430369 bl2_stage_init 0xc1
484 08:15:09.431045 bl2_stage_init 0x02
485 08:15:09.431799
486 08:15:09.435306 L0:00000000
487 08:15:09.436040 L1:20000703
488 08:15:09.436635 L2:00008067
489 08:15:09.437280 L3:14000000
490 08:15:09.440955 B2:00402000
491 08:15:09.441264 B1:e0f83180
492 08:15:09.441495
493 08:15:09.441724 TE: 58159
494 08:15:09.441949
495 08:15:09.446506 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 08:15:09.446804
497 08:15:09.447016 Board ID = 1
498 08:15:09.452103 Set A53 clk to 24M
499 08:15:09.452552 Set A73 clk to 24M
500 08:15:09.452955 Set clk81 to 24M
501 08:15:09.457764 A53 clk: 1200 MHz
502 08:15:09.458203 A73 clk: 1200 MHz
503 08:15:09.458606 CLK81: 166.6M
504 08:15:09.459001 smccc: 00012ab5
505 08:15:09.463352 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 08:15:09.469022 board id: 1
507 08:15:09.474919 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 08:15:09.485422 fw parse done
509 08:15:09.491363 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 08:15:09.534091 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 08:15:09.544961 PIEI prepare done
512 08:15:09.545698 fastboot data load
513 08:15:09.546409 fastboot data verify
514 08:15:09.550680 verify result: 266
515 08:15:09.556397 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 08:15:09.557155 LPDDR4 probe
517 08:15:09.557800 ddr clk to 1584MHz
518 08:15:09.564322 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 08:15:09.601490
520 08:15:09.602309 dmc_version 0001
521 08:15:09.608289 Check phy result
522 08:15:09.614101 INFO : End of CA training
523 08:15:09.614804 INFO : End of initialization
524 08:15:09.619717 INFO : Training has run successfully!
525 08:15:09.620583 Check phy result
526 08:15:09.625343 INFO : End of initialization
527 08:15:09.626062 INFO : End of read enable training
528 08:15:09.630902 INFO : End of fine write leveling
529 08:15:09.636475 INFO : End of Write leveling coarse delay
530 08:15:09.637188 INFO : Training has run successfully!
531 08:15:09.637829 Check phy result
532 08:15:09.642096 INFO : End of initialization
533 08:15:09.642791 INFO : End of read dq deskew training
534 08:15:09.647678 INFO : End of MPR read delay center optimization
535 08:15:09.653266 INFO : End of write delay center optimization
536 08:15:09.658804 INFO : End of read delay center optimization
537 08:15:09.659394 INFO : End of max read latency training
538 08:15:09.664381 INFO : Training has run successfully!
539 08:15:09.664958 1D training succeed
540 08:15:09.673553 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 08:15:09.721246 Check phy result
542 08:15:09.721914 INFO : End of initialization
543 08:15:09.742816 INFO : End of 2D read delay Voltage center optimization
544 08:15:09.762899 INFO : End of 2D read delay Voltage center optimization
545 08:15:09.814792 INFO : End of 2D write delay Voltage center optimization
546 08:15:09.864818 INFO : End of 2D write delay Voltage center optimization
547 08:15:09.869571 INFO : Training has run successfully!
548 08:15:09.870138
549 08:15:09.870629 channel==0
550 08:15:09.875196 RxClkDly_Margin_A0==88 ps 9
551 08:15:09.875788 TxDqDly_Margin_A0==98 ps 10
552 08:15:09.880781 RxClkDly_Margin_A1==88 ps 9
553 08:15:09.881365 TxDqDly_Margin_A1==88 ps 9
554 08:15:09.881863 TrainedVREFDQ_A0==74
555 08:15:09.886382 TrainedVREFDQ_A1==74
556 08:15:09.886960 VrefDac_Margin_A0==25
557 08:15:09.887445 DeviceVref_Margin_A0==40
558 08:15:09.892129 VrefDac_Margin_A1==25
559 08:15:09.892687 DeviceVref_Margin_A1==40
560 08:15:09.893170
561 08:15:09.893646
562 08:15:09.894120 channel==1
563 08:15:09.897587 RxClkDly_Margin_A0==98 ps 10
564 08:15:09.898136 TxDqDly_Margin_A0==88 ps 9
565 08:15:09.903175 RxClkDly_Margin_A1==98 ps 10
566 08:15:09.903728 TxDqDly_Margin_A1==98 ps 10
567 08:15:09.908750 TrainedVREFDQ_A0==77
568 08:15:09.909311 TrainedVREFDQ_A1==77
569 08:15:09.909797 VrefDac_Margin_A0==22
570 08:15:09.914372 DeviceVref_Margin_A0==37
571 08:15:09.914923 VrefDac_Margin_A1==22
572 08:15:09.920133 DeviceVref_Margin_A1==37
573 08:15:09.920707
574 08:15:09.921189 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 08:15:09.921661
576 08:15:09.953565 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
577 08:15:09.954217 2D training succeed
578 08:15:09.959167 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 08:15:09.964755 auto size-- 65535DDR cs0 size: 2048MB
580 08:15:09.965331 DDR cs1 size: 2048MB
581 08:15:09.970369 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 08:15:09.970949 cs0 DataBus test pass
583 08:15:09.976098 cs1 DataBus test pass
584 08:15:09.976691 cs0 AddrBus test pass
585 08:15:09.977181 cs1 AddrBus test pass
586 08:15:09.977649
587 08:15:09.981571 100bdlr_step_size ps== 420
588 08:15:09.982161 result report
589 08:15:09.987191 boot times 0Enable ddr reg access
590 08:15:09.992502 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 08:15:10.005994 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 08:15:10.578117 0.0;M3 CHK:0;cm4_sp_mode 0
593 08:15:10.578791 MVN_1=0x00000000
594 08:15:10.583667 MVN_2=0x00000000
595 08:15:10.589316 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 08:15:10.589900 OPS=0x10
597 08:15:10.590427 ring efuse init
598 08:15:10.590912 chipver efuse init
599 08:15:10.597861 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 08:15:10.598715 [0.018961 Inits done]
601 08:15:10.599345 secure task start!
602 08:15:10.605365 high task start!
603 08:15:10.606001 low task start!
604 08:15:10.606515 run into bl31
605 08:15:10.611745 NOTICE: BL31: v1.3(release):4fc40b1
606 08:15:10.619719 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 08:15:10.620541 NOTICE: BL31: G12A normal boot!
608 08:15:10.644840 NOTICE: BL31: BL33 decompress pass
609 08:15:10.650536 ERROR: Error initializing runtime service opteed_fast
610 08:15:11.883607
611 08:15:11.884330
612 08:15:11.891867 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 08:15:11.892456
614 08:15:11.892917 Model: Libre Computer AML-A311D-CC Alta
615 08:15:12.100364 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 08:15:12.123690 DRAM: 2 GiB (effective 3.8 GiB)
617 08:15:12.266802 Core: 408 devices, 31 uclasses, devicetree: separate
618 08:15:12.272555 WDT: Not starting watchdog@f0d0
619 08:15:12.304719 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 08:15:12.317259 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 08:15:12.322260 ** Bad device specification mmc 0 **
622 08:15:12.332540 Card did not respond to voltage select! : -110
623 08:15:12.340248 ** Bad device specification mmc 0 **
624 08:15:12.340798 Couldn't find partition mmc 0
625 08:15:12.348531 Card did not respond to voltage select! : -110
626 08:15:12.354048 ** Bad device specification mmc 0 **
627 08:15:12.354569 Couldn't find partition mmc 0
628 08:15:12.359110 Error: could not access storage.
629 08:15:12.700847 Net: eth0: ethernet@ff3f0000
630 08:15:12.701485 starting USB...
631 08:15:12.953552 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 08:15:12.954219 Starting the controller
633 08:15:12.960458 USB XHCI 1.10
634 08:15:14.672833 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 08:15:14.673487 bl2_stage_init 0x01
636 08:15:14.673937 bl2_stage_init 0x81
637 08:15:14.678412 hw id: 0x0000 - pwm id 0x01
638 08:15:14.678930 bl2_stage_init 0xc1
639 08:15:14.679375 bl2_stage_init 0x02
640 08:15:14.679813
641 08:15:14.684134 L0:00000000
642 08:15:14.684656 L1:20000703
643 08:15:14.685098 L2:00008067
644 08:15:14.685534 L3:14000000
645 08:15:14.689493 B2:00402000
646 08:15:14.690008 B1:e0f83180
647 08:15:14.690443
648 08:15:14.690877 TE: 58124
649 08:15:14.691311
650 08:15:14.695084 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 08:15:14.695601
652 08:15:14.696072 Board ID = 1
653 08:15:14.700869 Set A53 clk to 24M
654 08:15:14.701377 Set A73 clk to 24M
655 08:15:14.701811 Set clk81 to 24M
656 08:15:14.706256 A53 clk: 1200 MHz
657 08:15:14.706763 A73 clk: 1200 MHz
658 08:15:14.707200 CLK81: 166.6M
659 08:15:14.707633 smccc: 00012a92
660 08:15:14.711947 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 08:15:14.717557 board id: 1
662 08:15:14.723619 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 08:15:14.733954 fw parse done
664 08:15:14.739915 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 08:15:14.782564 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 08:15:14.793412 PIEI prepare done
667 08:15:14.794128 fastboot data load
668 08:15:14.794592 fastboot data verify
669 08:15:14.799110 verify result: 266
670 08:15:14.804706 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 08:15:14.805379 LPDDR4 probe
672 08:15:14.805829 ddr clk to 1584MHz
673 08:15:14.812759 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 08:15:14.849939
675 08:15:14.850532 dmc_version 0001
676 08:15:14.856707 Check phy result
677 08:15:14.862538 INFO : End of CA training
678 08:15:14.863054 INFO : End of initialization
679 08:15:14.868134 INFO : Training has run successfully!
680 08:15:14.868653 Check phy result
681 08:15:14.873754 INFO : End of initialization
682 08:15:14.874266 INFO : End of read enable training
683 08:15:14.879324 INFO : End of fine write leveling
684 08:15:14.884939 INFO : End of Write leveling coarse delay
685 08:15:14.885448 INFO : Training has run successfully!
686 08:15:14.885888 Check phy result
687 08:15:14.890486 INFO : End of initialization
688 08:15:14.891167 INFO : End of read dq deskew training
689 08:15:14.896117 INFO : End of MPR read delay center optimization
690 08:15:14.901758 INFO : End of write delay center optimization
691 08:15:14.907283 INFO : End of read delay center optimization
692 08:15:14.907959 INFO : End of max read latency training
693 08:15:14.912944 INFO : Training has run successfully!
694 08:15:14.913466 1D training succeed
695 08:15:14.922220 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 08:15:14.969781 Check phy result
697 08:15:14.970358 INFO : End of initialization
698 08:15:14.991484 INFO : End of 2D read delay Voltage center optimization
699 08:15:15.010886 INFO : End of 2D read delay Voltage center optimization
700 08:15:15.062929 INFO : End of 2D write delay Voltage center optimization
701 08:15:15.112277 INFO : End of 2D write delay Voltage center optimization
702 08:15:15.117878 INFO : Training has run successfully!
703 08:15:15.118401
704 08:15:15.118842 channel==0
705 08:15:15.123450 RxClkDly_Margin_A0==88 ps 9
706 08:15:15.123970 TxDqDly_Margin_A0==98 ps 10
707 08:15:15.126841 RxClkDly_Margin_A1==88 ps 9
708 08:15:15.127366 TxDqDly_Margin_A1==98 ps 10
709 08:15:15.132382 TrainedVREFDQ_A0==74
710 08:15:15.132934 TrainedVREFDQ_A1==74
711 08:15:15.133378 VrefDac_Margin_A0==24
712 08:15:15.137998 DeviceVref_Margin_A0==40
713 08:15:15.138526 VrefDac_Margin_A1==25
714 08:15:15.143550 DeviceVref_Margin_A1==40
715 08:15:15.144117
716 08:15:15.144565
717 08:15:15.144998 channel==1
718 08:15:15.145429 RxClkDly_Margin_A0==98 ps 10
719 08:15:15.149178 TxDqDly_Margin_A0==88 ps 9
720 08:15:15.149707 RxClkDly_Margin_A1==88 ps 9
721 08:15:15.154784 TxDqDly_Margin_A1==88 ps 9
722 08:15:15.155324 TrainedVREFDQ_A0==77
723 08:15:15.155767 TrainedVREFDQ_A1==77
724 08:15:15.160394 VrefDac_Margin_A0==23
725 08:15:15.160922 DeviceVref_Margin_A0==37
726 08:15:15.165987 VrefDac_Margin_A1==24
727 08:15:15.166505 DeviceVref_Margin_A1==37
728 08:15:15.166941
729 08:15:15.171570 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 08:15:15.172132
731 08:15:15.199524 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
732 08:15:15.205219 2D training succeed
733 08:15:15.210812 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 08:15:15.211347 auto size-- 65535DDR cs0 size: 2048MB
735 08:15:15.216387 DDR cs1 size: 2048MB
736 08:15:15.216923 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 08:15:15.221977 cs0 DataBus test pass
738 08:15:15.222505 cs1 DataBus test pass
739 08:15:15.222946 cs0 AddrBus test pass
740 08:15:15.227586 cs1 AddrBus test pass
741 08:15:15.228151
742 08:15:15.228594 100bdlr_step_size ps== 420
743 08:15:15.229038 result report
744 08:15:15.233172 boot times 0Enable ddr reg access
745 08:15:15.240778 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 08:15:15.254099 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 08:15:15.827221 0.0;M3 CHK:0;cm4_sp_mode 0
748 08:15:15.827902 MVN_1=0x00000000
749 08:15:15.832679 MVN_2=0x00000000
750 08:15:15.838439 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 08:15:15.838956 OPS=0x10
752 08:15:15.839400 ring efuse init
753 08:15:15.839833 chipver efuse init
754 08:15:15.844081 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 08:15:15.849672 [0.018961 Inits done]
756 08:15:15.850189 secure task start!
757 08:15:15.850628 high task start!
758 08:15:15.854236 low task start!
759 08:15:15.854749 run into bl31
760 08:15:15.860856 NOTICE: BL31: v1.3(release):4fc40b1
761 08:15:15.868627 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 08:15:15.869140 NOTICE: BL31: G12A normal boot!
763 08:15:15.894043 NOTICE: BL31: BL33 decompress pass
764 08:15:15.899659 ERROR: Error initializing runtime service opteed_fast
765 08:15:17.132515
766 08:15:17.133154
767 08:15:17.140990 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 08:15:17.141559
769 08:15:17.142042 Model: Libre Computer AML-A311D-CC Alta
770 08:15:17.349324 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 08:15:17.372764 DRAM: 2 GiB (effective 3.8 GiB)
772 08:15:17.515711 Core: 408 devices, 31 uclasses, devicetree: separate
773 08:15:17.521612 WDT: Not starting watchdog@f0d0
774 08:15:17.553936 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 08:15:17.566291 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 08:15:17.571321 ** Bad device specification mmc 0 **
777 08:15:17.581634 Card did not respond to voltage select! : -110
778 08:15:17.589284 ** Bad device specification mmc 0 **
779 08:15:17.589816 Couldn't find partition mmc 0
780 08:15:17.597637 Card did not respond to voltage select! : -110
781 08:15:17.603143 ** Bad device specification mmc 0 **
782 08:15:17.603665 Couldn't find partition mmc 0
783 08:15:17.608221 Error: could not access storage.
784 08:15:17.951749 Net: eth0: ethernet@ff3f0000
785 08:15:17.952189 starting USB...
786 08:15:18.203514 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 08:15:18.204215 Starting the controller
788 08:15:18.210443 USB XHCI 1.10
789 08:15:20.373091 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 08:15:20.373770 bl2_stage_init 0x01
791 08:15:20.374249 bl2_stage_init 0x81
792 08:15:20.378612 hw id: 0x0000 - pwm id 0x01
793 08:15:20.379141 bl2_stage_init 0xc1
794 08:15:20.379606 bl2_stage_init 0x02
795 08:15:20.380110
796 08:15:20.384139 L0:00000000
797 08:15:20.384661 L1:20000703
798 08:15:20.385123 L2:00008067
799 08:15:20.385572 L3:14000000
800 08:15:20.387127 B2:00402000
801 08:15:20.387619 B1:e0f83180
802 08:15:20.388106
803 08:15:20.388561 TE: 58167
804 08:15:20.389007
805 08:15:20.398401 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 08:15:20.399067
807 08:15:20.399567 Board ID = 1
808 08:15:20.400064 Set A53 clk to 24M
809 08:15:20.400519 Set A73 clk to 24M
810 08:15:20.403852 Set clk81 to 24M
811 08:15:20.404429 A53 clk: 1200 MHz
812 08:15:20.404898 A73 clk: 1200 MHz
813 08:15:20.407411 CLK81: 166.6M
814 08:15:20.407933 smccc: 00012abd
815 08:15:20.412944 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 08:15:20.418575 board id: 1
817 08:15:20.423668 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 08:15:20.434290 fw parse done
819 08:15:20.440316 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 08:15:20.482850 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 08:15:20.493871 PIEI prepare done
822 08:15:20.494474 fastboot data load
823 08:15:20.494953 fastboot data verify
824 08:15:20.499439 verify result: 266
825 08:15:20.505079 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 08:15:20.505648 LPDDR4 probe
827 08:15:20.506107 ddr clk to 1584MHz
828 08:15:20.513101 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 08:15:20.550306
830 08:15:20.550891 dmc_version 0001
831 08:15:20.556973 Check phy result
832 08:15:20.562823 INFO : End of CA training
833 08:15:20.563345 INFO : End of initialization
834 08:15:20.568469 INFO : Training has run successfully!
835 08:15:20.568990 Check phy result
836 08:15:20.574055 INFO : End of initialization
837 08:15:20.574621 INFO : End of read enable training
838 08:15:20.577374 INFO : End of fine write leveling
839 08:15:20.582935 INFO : End of Write leveling coarse delay
840 08:15:20.588513 INFO : Training has run successfully!
841 08:15:20.589037 Check phy result
842 08:15:20.589492 INFO : End of initialization
843 08:15:20.594128 INFO : End of read dq deskew training
844 08:15:20.597497 INFO : End of MPR read delay center optimization
845 08:15:20.603069 INFO : End of write delay center optimization
846 08:15:20.608606 INFO : End of read delay center optimization
847 08:15:20.609133 INFO : End of max read latency training
848 08:15:20.614210 INFO : Training has run successfully!
849 08:15:20.614730 1D training succeed
850 08:15:20.622492 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 08:15:20.670044 Check phy result
852 08:15:20.670625 INFO : End of initialization
853 08:15:20.691770 INFO : End of 2D read delay Voltage center optimization
854 08:15:20.711206 INFO : End of 2D read delay Voltage center optimization
855 08:15:20.763225 INFO : End of 2D write delay Voltage center optimization
856 08:15:20.812587 INFO : End of 2D write delay Voltage center optimization
857 08:15:20.818236 INFO : Training has run successfully!
858 08:15:20.818808
859 08:15:20.819308 channel==0
860 08:15:20.823662 RxClkDly_Margin_A0==88 ps 9
861 08:15:20.824275 TxDqDly_Margin_A0==98 ps 10
862 08:15:20.829273 RxClkDly_Margin_A1==88 ps 9
863 08:15:20.829818 TxDqDly_Margin_A1==98 ps 10
864 08:15:20.830308 TrainedVREFDQ_A0==74
865 08:15:20.835050 TrainedVREFDQ_A1==74
866 08:15:20.835598 VrefDac_Margin_A0==25
867 08:15:20.836099 DeviceVref_Margin_A0==40
868 08:15:20.840677 VrefDac_Margin_A1==25
869 08:15:20.841203 DeviceVref_Margin_A1==40
870 08:15:20.841635
871 08:15:20.842067
872 08:15:20.846036 channel==1
873 08:15:20.846545 RxClkDly_Margin_A0==98 ps 10
874 08:15:20.846987 TxDqDly_Margin_A0==88 ps 9
875 08:15:20.851616 RxClkDly_Margin_A1==88 ps 9
876 08:15:20.852164 TxDqDly_Margin_A1==88 ps 9
877 08:15:20.857394 TrainedVREFDQ_A0==77
878 08:15:20.857909 TrainedVREFDQ_A1==77
879 08:15:20.858349 VrefDac_Margin_A0==23
880 08:15:20.862994 DeviceVref_Margin_A0==37
881 08:15:20.863521 VrefDac_Margin_A1==23
882 08:15:20.868585 DeviceVref_Margin_A1==37
883 08:15:20.869089
884 08:15:20.869523 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 08:15:20.869952
886 08:15:20.902064 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
887 08:15:20.902672 2D training succeed
888 08:15:20.907742 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 08:15:20.913231 auto size-- 65535DDR cs0 size: 2048MB
890 08:15:20.913741 DDR cs1 size: 2048MB
891 08:15:20.918866 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 08:15:20.919393 cs0 DataBus test pass
893 08:15:20.924487 cs1 DataBus test pass
894 08:15:20.925008 cs0 AddrBus test pass
895 08:15:20.925445 cs1 AddrBus test pass
896 08:15:20.925871
897 08:15:20.930030 100bdlr_step_size ps== 420
898 08:15:20.930546 result report
899 08:15:20.935624 boot times 0Enable ddr reg access
900 08:15:20.940900 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 08:15:20.954431 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 08:15:21.527952 0.0;M3 CHK:0;cm4_sp_mode 0
903 08:15:21.528660 MVN_1=0x00000000
904 08:15:21.533491 MVN_2=0x00000000
905 08:15:21.539241 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 08:15:21.539760 OPS=0x10
907 08:15:21.540261 ring efuse init
908 08:15:21.540714 chipver efuse init
909 08:15:21.544848 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 08:15:21.550444 [0.018961 Inits done]
911 08:15:21.550983 secure task start!
912 08:15:21.551438 high task start!
913 08:15:21.554997 low task start!
914 08:15:21.555508 run into bl31
915 08:15:21.561668 NOTICE: BL31: v1.3(release):4fc40b1
916 08:15:21.569524 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 08:15:21.570251 NOTICE: BL31: G12A normal boot!
918 08:15:21.594771 NOTICE: BL31: BL33 decompress pass
919 08:15:21.600545 ERROR: Error initializing runtime service opteed_fast
920 08:15:22.833362
921 08:15:22.834003
922 08:15:22.841838 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 08:15:22.842365
924 08:15:22.842833 Model: Libre Computer AML-A311D-CC Alta
925 08:15:23.050344 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 08:15:23.073609 DRAM: 2 GiB (effective 3.8 GiB)
927 08:15:23.216620 Core: 408 devices, 31 uclasses, devicetree: separate
928 08:15:23.222467 WDT: Not starting watchdog@f0d0
929 08:15:23.254724 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 08:15:23.267149 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 08:15:23.272154 ** Bad device specification mmc 0 **
932 08:15:23.282536 Card did not respond to voltage select! : -110
933 08:15:23.290159 ** Bad device specification mmc 0 **
934 08:15:23.290688 Couldn't find partition mmc 0
935 08:15:23.298494 Card did not respond to voltage select! : -110
936 08:15:23.304022 ** Bad device specification mmc 0 **
937 08:15:23.304554 Couldn't find partition mmc 0
938 08:15:23.309051 Error: could not access storage.
939 08:15:23.651552 Net: eth0: ethernet@ff3f0000
940 08:15:23.652275 starting USB...
941 08:15:23.904455 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 08:15:23.905133 Starting the controller
943 08:15:23.910651 USB XHCI 1.10
944 08:15:25.464380 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 08:15:25.472674 scanning usb for storage devices... 0 Storage Device(s) found
947 08:15:25.524291 Hit any key to stop autoboot: 1
948 08:15:25.525242 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 08:15:25.525916 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 08:15:25.526456 Setting prompt string to ['=>']
951 08:15:25.526993 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 08:15:25.540205 0
953 08:15:25.541192 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 08:15:25.541735 Sending with 10 millisecond of delay
956 08:15:26.677025 => setenv autoload no
957 08:15:26.688850 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 08:15:26.695527 setenv autoload no
959 08:15:26.696526 Sending with 10 millisecond of delay
961 08:15:28.494364 => setenv initrd_high 0xffffffff
962 08:15:28.505154 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 08:15:28.506021 setenv initrd_high 0xffffffff
964 08:15:28.506735 Sending with 10 millisecond of delay
966 08:15:30.124367 => setenv fdt_high 0xffffffff
967 08:15:30.134950 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 08:15:30.135596 setenv fdt_high 0xffffffff
969 08:15:30.136120 Sending with 10 millisecond of delay
971 08:15:30.427762 => dhcp
972 08:15:30.438354 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 08:15:30.438944 dhcp
974 08:15:30.439206 Speed: 1000, full duplex
975 08:15:30.439429 BOOTP broadcast 1
976 08:15:30.679020 DHCP client bound to address 192.168.6.33 (240 ms)
977 08:15:30.680025 Sending with 10 millisecond of delay
979 08:15:32.357136 => setenv serverip 192.168.6.2
980 08:15:32.368074 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 08:15:32.369150 setenv serverip 192.168.6.2
982 08:15:32.369921 Sending with 10 millisecond of delay
984 08:15:36.097887 => tftpboot 0x01080000 742785/tftp-deploy-fxargv8v/kernel/uImage
985 08:15:36.108723 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
986 08:15:36.109638 tftpboot 0x01080000 742785/tftp-deploy-fxargv8v/kernel/uImage
987 08:15:36.110107 Speed: 1000, full duplex
988 08:15:36.110522 Using ethernet@ff3f0000 device
989 08:15:36.111754 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
990 08:15:36.117416 Filename '742785/tftp-deploy-fxargv8v/kernel/uImage'.
991 08:15:36.121091 Load address: 0x1080000
992 08:15:39.767019 Loading: *################################################## 43.6 MiB
993 08:15:39.767489 12 MiB/s
994 08:15:39.767729 done
995 08:15:39.768538 Bytes transferred = 45724224 (2b9b240 hex)
996 08:15:39.769126 Sending with 10 millisecond of delay
998 08:15:44.457888 => tftpboot 0x08000000 742785/tftp-deploy-fxargv8v/ramdisk/ramdisk.cpio.gz.uboot
999 08:15:44.468802 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
1000 08:15:44.469368 tftpboot 0x08000000 742785/tftp-deploy-fxargv8v/ramdisk/ramdisk.cpio.gz.uboot
1001 08:15:44.469681 Speed: 1000, full duplex
1002 08:15:44.469915 Using ethernet@ff3f0000 device
1003 08:15:44.471322 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1004 08:15:44.479918 Filename '742785/tftp-deploy-fxargv8v/ramdisk/ramdisk.cpio.gz.uboot'.
1005 08:15:44.480379 Load address: 0x8000000
1006 08:15:46.866096 Loading: *################################################# UDP wrong checksum 00000005 0000337f
1007 08:15:51.866347 T UDP wrong checksum 00000005 0000337f
1008 08:16:01.869106 T T UDP wrong checksum 00000005 0000337f
1009 08:16:21.872464 T T T UDP wrong checksum 00000005 0000337f
1010 08:16:23.927642 T UDP wrong checksum 000000ff 0000684f
1011 08:16:23.948602 UDP wrong checksum 000000ff 00000542
1012 08:16:41.879324 T T T
1013 08:16:41.879749 Retry count exceeded; starting again
1015 08:16:41.880783 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1018 08:16:41.881933 end: 2.4 uboot-commands (duration 00:01:48) [common]
1020 08:16:41.882741 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1022 08:16:41.883539 end: 2 uboot-action (duration 00:01:48) [common]
1024 08:16:41.884754 Cleaning after the job
1025 08:16:41.885118 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/ramdisk
1026 08:16:41.885901 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/kernel
1027 08:16:41.889864 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/dtb
1028 08:16:41.890548 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/nfsrootfs
1029 08:16:41.941536 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/742785/tftp-deploy-fxargv8v/modules
1030 08:16:41.948108 start: 4.1 power-off (timeout 00:00:30) [common]
1031 08:16:41.948687 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1032 08:16:41.980809 >> OK - accepted request
1033 08:16:41.982730 Returned 0 in 0 seconds
1034 08:16:42.083437 end: 4.1 power-off (duration 00:00:00) [common]
1036 08:16:42.084435 start: 4.2 read-feedback (timeout 00:10:00) [common]
1037 08:16:42.085082 Listened to connection for namespace 'common' for up to 1s
1038 08:16:43.086026 Finalising connection for namespace 'common'
1039 08:16:43.086496 Disconnecting from shell: Finalise
1040 08:16:43.086807 =>
1041 08:16:43.187531 end: 4.2 read-feedback (duration 00:00:01) [common]
1042 08:16:43.188252 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/742785
1043 08:16:45.807481 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/742785
1044 08:16:45.808281 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.