Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:31:22.501264 lava-dispatcher, installed at version: 2024.01
2 06:31:22.502052 start: 0 validate
3 06:31:22.502518 Start time: 2024-10-01 06:31:22.502488+00:00 (UTC)
4 06:31:22.503056 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:31:22.503581 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 06:31:22.546979 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:31:22.547575 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 06:31:22.574318 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:31:22.574945 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 06:31:23.623242 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:31:23.623735 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 06:31:23.667679 validate duration: 1.17
14 06:31:23.668556 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:31:23.668899 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:31:23.669214 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:31:23.669803 Not decompressing ramdisk as can be used compressed.
18 06:31:23.670232 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 06:31:23.670509 saving as /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/ramdisk/rootfs.cpio.gz
20 06:31:23.670787 total size: 8181887 (7 MB)
21 06:31:23.712611 progress 0 % (0 MB)
22 06:31:23.724416 progress 5 % (0 MB)
23 06:31:23.735636 progress 10 % (0 MB)
24 06:31:23.743581 progress 15 % (1 MB)
25 06:31:23.748984 progress 20 % (1 MB)
26 06:31:23.754767 progress 25 % (1 MB)
27 06:31:23.760107 progress 30 % (2 MB)
28 06:31:23.765924 progress 35 % (2 MB)
29 06:31:23.771288 progress 40 % (3 MB)
30 06:31:23.777143 progress 45 % (3 MB)
31 06:31:23.782493 progress 50 % (3 MB)
32 06:31:23.788382 progress 55 % (4 MB)
33 06:31:23.793737 progress 60 % (4 MB)
34 06:31:23.799492 progress 65 % (5 MB)
35 06:31:23.804779 progress 70 % (5 MB)
36 06:31:23.810555 progress 75 % (5 MB)
37 06:31:23.816114 progress 80 % (6 MB)
38 06:31:23.821785 progress 85 % (6 MB)
39 06:31:23.827162 progress 90 % (7 MB)
40 06:31:23.832780 progress 95 % (7 MB)
41 06:31:23.837565 progress 100 % (7 MB)
42 06:31:23.838213 7 MB downloaded in 0.17 s (46.61 MB/s)
43 06:31:23.838803 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:31:23.839764 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:31:23.840109 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:31:23.840420 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:31:23.840928 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
49 06:31:23.841202 saving as /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/kernel/Image
50 06:31:23.841428 total size: 45998592 (43 MB)
51 06:31:23.841650 No compression specified
52 06:31:23.879311 progress 0 % (0 MB)
53 06:31:23.907446 progress 5 % (2 MB)
54 06:31:23.935854 progress 10 % (4 MB)
55 06:31:23.963559 progress 15 % (6 MB)
56 06:31:23.991519 progress 20 % (8 MB)
57 06:31:24.019838 progress 25 % (10 MB)
58 06:31:24.048476 progress 30 % (13 MB)
59 06:31:24.076470 progress 35 % (15 MB)
60 06:31:24.104336 progress 40 % (17 MB)
61 06:31:24.132465 progress 45 % (19 MB)
62 06:31:24.160342 progress 50 % (21 MB)
63 06:31:24.188706 progress 55 % (24 MB)
64 06:31:24.216711 progress 60 % (26 MB)
65 06:31:24.244791 progress 65 % (28 MB)
66 06:31:24.272722 progress 70 % (30 MB)
67 06:31:24.300627 progress 75 % (32 MB)
68 06:31:24.329371 progress 80 % (35 MB)
69 06:31:24.357366 progress 85 % (37 MB)
70 06:31:24.385327 progress 90 % (39 MB)
71 06:31:24.413538 progress 95 % (41 MB)
72 06:31:24.441014 progress 100 % (43 MB)
73 06:31:24.441751 43 MB downloaded in 0.60 s (73.08 MB/s)
74 06:31:24.442274 end: 1.2.1 http-download (duration 00:00:01) [common]
76 06:31:24.443149 end: 1.2 download-retry (duration 00:00:01) [common]
77 06:31:24.443457 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:31:24.443748 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:31:24.444273 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 06:31:24.444578 saving as /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 06:31:24.444806 total size: 53209 (0 MB)
82 06:31:24.445030 No compression specified
83 06:31:24.480732 progress 61 % (0 MB)
84 06:31:24.481594 progress 100 % (0 MB)
85 06:31:24.482155 0 MB downloaded in 0.04 s (1.36 MB/s)
86 06:31:24.482641 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:31:24.483504 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:31:24.483791 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:31:24.484102 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:31:24.484600 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
92 06:31:24.484861 saving as /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/modules/modules.tar
93 06:31:24.485081 total size: 11615768 (11 MB)
94 06:31:24.485306 Using unxz to decompress xz
95 06:31:24.523851 progress 0 % (0 MB)
96 06:31:24.594220 progress 5 % (0 MB)
97 06:31:24.674235 progress 10 % (1 MB)
98 06:31:24.762845 progress 15 % (1 MB)
99 06:31:24.841981 progress 20 % (2 MB)
100 06:31:24.925107 progress 25 % (2 MB)
101 06:31:25.005244 progress 30 % (3 MB)
102 06:31:25.085703 progress 35 % (3 MB)
103 06:31:25.158907 progress 40 % (4 MB)
104 06:31:25.236012 progress 45 % (5 MB)
105 06:31:25.313382 progress 50 % (5 MB)
106 06:31:25.384315 progress 55 % (6 MB)
107 06:31:25.468623 progress 60 % (6 MB)
108 06:31:25.554444 progress 65 % (7 MB)
109 06:31:25.637561 progress 70 % (7 MB)
110 06:31:25.732571 progress 75 % (8 MB)
111 06:31:25.828481 progress 80 % (8 MB)
112 06:31:25.911806 progress 85 % (9 MB)
113 06:31:25.987501 progress 90 % (10 MB)
114 06:31:26.060458 progress 95 % (10 MB)
115 06:31:26.140262 progress 100 % (11 MB)
116 06:31:26.153507 11 MB downloaded in 1.67 s (6.64 MB/s)
117 06:31:26.154297 end: 1.4.1 http-download (duration 00:00:02) [common]
119 06:31:26.155958 end: 1.4 download-retry (duration 00:00:02) [common]
120 06:31:26.156571 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 06:31:26.157115 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 06:31:26.157636 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:31:26.158157 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 06:31:26.159132 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h
125 06:31:26.160049 makedir: /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin
126 06:31:26.160798 makedir: /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/tests
127 06:31:26.161469 makedir: /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/results
128 06:31:26.162114 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-add-keys
129 06:31:26.163119 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-add-sources
130 06:31:26.164155 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-background-process-start
131 06:31:26.165185 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-background-process-stop
132 06:31:26.166230 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-common-functions
133 06:31:26.167208 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-echo-ipv4
134 06:31:26.168212 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-install-packages
135 06:31:26.169226 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-installed-packages
136 06:31:26.170327 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-os-build
137 06:31:26.171298 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-probe-channel
138 06:31:26.172301 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-probe-ip
139 06:31:26.173266 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-target-ip
140 06:31:26.174215 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-target-mac
141 06:31:26.175169 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-target-storage
142 06:31:26.176163 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-test-case
143 06:31:26.177193 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-test-event
144 06:31:26.178200 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-test-feedback
145 06:31:26.179181 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-test-raise
146 06:31:26.180113 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-test-reference
147 06:31:26.180685 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-test-runner
148 06:31:26.181265 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-test-set
149 06:31:26.181828 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-test-shell
150 06:31:26.182396 Updating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-install-packages (oe)
151 06:31:26.182997 Updating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/bin/lava-installed-packages (oe)
152 06:31:26.183506 Creating /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/environment
153 06:31:26.183959 LAVA metadata
154 06:31:26.184286 - LAVA_JOB_ID=784855
155 06:31:26.184530 - LAVA_DISPATCHER_IP=192.168.6.2
156 06:31:26.184927 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 06:31:26.185996 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 06:31:26.186371 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 06:31:26.186610 skipped lava-vland-overlay
160 06:31:26.186875 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 06:31:26.187155 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 06:31:26.187395 skipped lava-multinode-overlay
163 06:31:26.187665 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 06:31:26.187943 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 06:31:26.188286 Loading test definitions
166 06:31:26.188607 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 06:31:26.188860 Using /lava-784855 at stage 0
168 06:31:26.190154 uuid=784855_1.5.2.4.1 testdef=None
169 06:31:26.190511 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 06:31:26.190810 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 06:31:26.193057 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 06:31:26.193954 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 06:31:26.196411 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 06:31:26.197318 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 06:31:26.199621 runner path: /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/0/tests/0_dmesg test_uuid 784855_1.5.2.4.1
178 06:31:26.200260 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 06:31:26.201096 Creating lava-test-runner.conf files
181 06:31:26.201319 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/784855/lava-overlay-ohu8qs3h/lava-784855/0 for stage 0
182 06:31:26.201701 - 0_dmesg
183 06:31:26.202098 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 06:31:26.202406 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 06:31:26.226832 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 06:31:26.227261 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 06:31:26.227567 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 06:31:26.227864 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 06:31:26.228181 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 06:31:27.146807 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 06:31:27.147286 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 06:31:27.147564 extracting modules file /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/modules/modules.tar to /var/lib/lava/dispatcher/tmp/784855/extract-overlay-ramdisk-qfm7ghw2/ramdisk
193 06:31:28.639029 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 06:31:28.639602 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 06:31:28.639940 [common] Applying overlay /var/lib/lava/dispatcher/tmp/784855/compress-overlay-ws8ygj2g/overlay-1.5.2.5.tar.gz to ramdisk
196 06:31:28.640240 [common] Applying overlay /var/lib/lava/dispatcher/tmp/784855/compress-overlay-ws8ygj2g/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/784855/extract-overlay-ramdisk-qfm7ghw2/ramdisk
197 06:31:28.677212 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 06:31:28.677708 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 06:31:28.678043 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 06:31:28.678316 Converting downloaded kernel to a uImage
201 06:31:28.678706 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/kernel/Image /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/kernel/uImage
202 06:31:29.138555 output: Image Name:
203 06:31:29.138979 output: Created: Tue Oct 1 06:31:28 2024
204 06:31:29.139192 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 06:31:29.139400 output: Data Size: 45998592 Bytes = 44920.50 KiB = 43.87 MiB
206 06:31:29.139603 output: Load Address: 01080000
207 06:31:29.139803 output: Entry Point: 01080000
208 06:31:29.140032 output:
209 06:31:29.140377 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 06:31:29.140647 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 06:31:29.140918 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 06:31:29.141172 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 06:31:29.141429 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 06:31:29.141696 Building ramdisk /var/lib/lava/dispatcher/tmp/784855/extract-overlay-ramdisk-qfm7ghw2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/784855/extract-overlay-ramdisk-qfm7ghw2/ramdisk
215 06:31:32.009804 >> 181626 blocks
216 06:31:40.475289 Adding RAMdisk u-boot header.
217 06:31:40.476076 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/784855/extract-overlay-ramdisk-qfm7ghw2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/784855/extract-overlay-ramdisk-qfm7ghw2/ramdisk.cpio.gz.uboot
218 06:31:40.739052 output: Image Name:
219 06:31:40.739525 output: Created: Tue Oct 1 06:31:40 2024
220 06:31:40.739779 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 06:31:40.740191 output: Data Size: 26051247 Bytes = 25440.67 KiB = 24.84 MiB
222 06:31:40.740738 output: Load Address: 00000000
223 06:31:40.741274 output: Entry Point: 00000000
224 06:31:40.741783 output:
225 06:31:40.742939 rename /var/lib/lava/dispatcher/tmp/784855/extract-overlay-ramdisk-qfm7ghw2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/ramdisk/ramdisk.cpio.gz.uboot
226 06:31:40.743829 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 06:31:40.744633 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 06:31:40.745374 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 06:31:40.745961 No LXC device requested
230 06:31:40.746604 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 06:31:40.747251 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 06:31:40.747886 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 06:31:40.748453 Checking files for TFTP limit of 4294967296 bytes.
234 06:31:40.751886 end: 1 tftp-deploy (duration 00:00:17) [common]
235 06:31:40.752657 start: 2 uboot-action (timeout 00:05:00) [common]
236 06:31:40.753324 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 06:31:40.753974 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 06:31:40.754613 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 06:31:40.755288 Using kernel file from prepare-kernel: 784855/tftp-deploy-uvgty2ra/kernel/uImage
240 06:31:40.756080 substitutions:
241 06:31:40.756616 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 06:31:40.757134 - {DTB_ADDR}: 0x01070000
243 06:31:40.757654 - {DTB}: 784855/tftp-deploy-uvgty2ra/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 06:31:40.758165 - {INITRD}: 784855/tftp-deploy-uvgty2ra/ramdisk/ramdisk.cpio.gz.uboot
245 06:31:40.758675 - {KERNEL_ADDR}: 0x01080000
246 06:31:40.759184 - {KERNEL}: 784855/tftp-deploy-uvgty2ra/kernel/uImage
247 06:31:40.759690 - {LAVA_MAC}: None
248 06:31:40.760282 - {PRESEED_CONFIG}: None
249 06:31:40.760796 - {PRESEED_LOCAL}: None
250 06:31:40.761302 - {RAMDISK_ADDR}: 0x08000000
251 06:31:40.761804 - {RAMDISK}: 784855/tftp-deploy-uvgty2ra/ramdisk/ramdisk.cpio.gz.uboot
252 06:31:40.762314 - {ROOT_PART}: None
253 06:31:40.762818 - {ROOT}: None
254 06:31:40.763319 - {SERVER_IP}: 192.168.6.2
255 06:31:40.763822 - {TEE_ADDR}: 0x83000000
256 06:31:40.764360 - {TEE}: None
257 06:31:40.764865 Parsed boot commands:
258 06:31:40.765348 - setenv autoload no
259 06:31:40.765850 - setenv initrd_high 0xffffffff
260 06:31:40.766350 - setenv fdt_high 0xffffffff
261 06:31:40.766848 - dhcp
262 06:31:40.767336 - setenv serverip 192.168.6.2
263 06:31:40.767835 - tftpboot 0x01080000 784855/tftp-deploy-uvgty2ra/kernel/uImage
264 06:31:40.768360 - tftpboot 0x08000000 784855/tftp-deploy-uvgty2ra/ramdisk/ramdisk.cpio.gz.uboot
265 06:31:40.768863 - tftpboot 0x01070000 784855/tftp-deploy-uvgty2ra/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 06:31:40.769362 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 06:31:40.769868 - bootm 0x01080000 0x08000000 0x01070000
268 06:31:40.770494 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 06:31:40.772462 start: 2.3 connect-device (timeout 00:05:00) [common]
271 06:31:40.773066 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 06:31:40.789369 Setting prompt string to ['lava-test: # ']
273 06:31:40.791220 end: 2.3 connect-device (duration 00:00:00) [common]
274 06:31:40.792010 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 06:31:40.792965 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 06:31:40.793665 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 06:31:40.795123 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 06:31:40.836640 >> OK - accepted request
279 06:31:40.838800 Returned 0 in 0 seconds
280 06:31:40.940121 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 06:31:40.942121 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 06:31:40.942837 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 06:31:40.943487 Setting prompt string to ['Hit any key to stop autoboot']
285 06:31:40.944086 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 06:31:40.946076 Trying 192.168.56.21...
287 06:31:40.946687 Connected to conserv1.
288 06:31:40.947212 Escape character is '^]'.
289 06:31:40.947755
290 06:31:40.948331 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 06:31:40.948885
292 06:31:48.277273 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 06:31:48.278058 bl2_stage_init 0x01
294 06:31:48.278626 bl2_stage_init 0x81
295 06:31:48.282972 hw id: 0x0000 - pwm id 0x01
296 06:31:48.283564 bl2_stage_init 0xc1
297 06:31:48.288514 bl2_stage_init 0x02
298 06:31:48.289093
299 06:31:48.289613 L0:00000000
300 06:31:48.290120 L1:00000703
301 06:31:48.290633 L2:00008067
302 06:31:48.291137 L3:15000000
303 06:31:48.294086 S1:00000000
304 06:31:48.294631 B2:20282000
305 06:31:48.295140 B1:a0f83180
306 06:31:48.295645
307 06:31:48.296185 TE: 72391
308 06:31:48.296693
309 06:31:48.299664 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 06:31:48.300264
311 06:31:48.305182 Board ID = 1
312 06:31:48.305737 Set cpu clk to 24M
313 06:31:48.306255 Set clk81 to 24M
314 06:31:48.310935 Use GP1_pll as DSU clk.
315 06:31:48.311478 DSU clk: 1200 Mhz
316 06:31:48.312031 CPU clk: 1200 MHz
317 06:31:48.316507 Set clk81 to 166.6M
318 06:31:48.322239 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 06:31:48.322784 board id: 1
320 06:31:48.328566 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 06:31:48.339873 fw parse done
322 06:31:48.345841 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 06:31:48.388443 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 06:31:48.399406 PIEI prepare done
325 06:31:48.400013 fastboot data load
326 06:31:48.400537 fastboot data verify
327 06:31:48.404979 verify result: 266
328 06:31:48.410547 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 06:31:48.411097 LPDDR4 probe
330 06:31:48.411624 ddr clk to 1584MHz
331 06:31:48.417673 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 06:31:48.455913
333 06:31:48.456559 dmc_version 0001
334 06:31:48.462619 Check phy result
335 06:31:48.468450 INFO : End of CA training
336 06:31:48.469051 INFO : End of initialization
337 06:31:48.474108 INFO : Training has run successfully!
338 06:31:48.474669 Check phy result
339 06:31:48.479646 INFO : End of initialization
340 06:31:48.480232 INFO : End of read enable training
341 06:31:48.483058 INFO : End of fine write leveling
342 06:31:48.488629 INFO : End of Write leveling coarse delay
343 06:31:48.494197 INFO : Training has run successfully!
344 06:31:48.494743 Check phy result
345 06:31:48.495267 INFO : End of initialization
346 06:31:48.499844 INFO : End of read dq deskew training
347 06:31:48.503285 INFO : End of MPR read delay center optimization
348 06:31:48.508761 INFO : End of write delay center optimization
349 06:31:48.514369 INFO : End of read delay center optimization
350 06:31:48.514912 INFO : End of max read latency training
351 06:31:48.520026 INFO : Training has run successfully!
352 06:31:48.520572 1D training succeed
353 06:31:48.528164 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 06:31:48.575671 Check phy result
355 06:31:48.576265 INFO : End of initialization
356 06:31:48.598094 INFO : End of 2D read delay Voltage center optimization
357 06:31:48.617105 INFO : End of 2D read delay Voltage center optimization
358 06:31:48.669056 INFO : End of 2D write delay Voltage center optimization
359 06:31:48.718208 INFO : End of 2D write delay Voltage center optimization
360 06:31:48.723780 INFO : Training has run successfully!
361 06:31:48.724363
362 06:31:48.724887 channel==0
363 06:31:48.729295 RxClkDly_Margin_A0==78 ps 8
364 06:31:48.729851 TxDqDly_Margin_A0==98 ps 10
365 06:31:48.735040 RxClkDly_Margin_A1==88 ps 9
366 06:31:48.735577 TxDqDly_Margin_A1==98 ps 10
367 06:31:48.736122 TrainedVREFDQ_A0==74
368 06:31:48.740545 TrainedVREFDQ_A1==75
369 06:31:48.741093 VrefDac_Margin_A0==23
370 06:31:48.741595 DeviceVref_Margin_A0==40
371 06:31:48.746143 VrefDac_Margin_A1==23
372 06:31:48.746668 DeviceVref_Margin_A1==39
373 06:31:48.747174
374 06:31:48.747677
375 06:31:48.751676 channel==1
376 06:31:48.752233 RxClkDly_Margin_A0==88 ps 9
377 06:31:48.752744 TxDqDly_Margin_A0==98 ps 10
378 06:31:48.756169 RxClkDly_Margin_A1==78 ps 8
379 06:31:48.759439 TxDqDly_Margin_A1==78 ps 8
380 06:31:48.759961 TrainedVREFDQ_A0==78
381 06:31:48.765102 TrainedVREFDQ_A1==75
382 06:31:48.765653 VrefDac_Margin_A0==23
383 06:31:48.766172 DeviceVref_Margin_A0==36
384 06:31:48.770680 VrefDac_Margin_A1==22
385 06:31:48.771218 DeviceVref_Margin_A1==38
386 06:31:48.771725
387 06:31:48.776192 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 06:31:48.776736
389 06:31:48.804199 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 06:31:48.809736 2D training succeed
391 06:31:48.815350 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 06:31:48.820956 auto size-- 65535DDR cs0 size: 2048MB
393 06:31:48.821501 DDR cs1 size: 2048MB
394 06:31:48.826614 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 06:31:48.827138 cs0 DataBus test pass
396 06:31:48.827644 cs1 DataBus test pass
397 06:31:48.832192 cs0 AddrBus test pass
398 06:31:48.832734 cs1 AddrBus test pass
399 06:31:48.833242
400 06:31:48.833745 100bdlr_step_size ps== 478
401 06:31:48.837737 result report
402 06:31:48.838261 boot times 0Enable ddr reg access
403 06:31:48.846499 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 06:31:48.860337 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 06:31:49.514398 bl2z: ptr: 05129330, size: 00001e40
406 06:31:49.521245 0.0;M3 CHK:0;cm4_sp_mode 0
407 06:31:49.521860 MVN_1=0x00000000
408 06:31:49.522407 MVN_2=0x00000000
409 06:31:49.532735 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 06:31:49.533314 OPS=0x04
411 06:31:49.533841 ring efuse init
412 06:31:49.538365 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 06:31:49.538962 [0.017319 Inits done]
414 06:31:49.539487 secure task start!
415 06:31:49.546445 high task start!
416 06:31:49.547003 low task start!
417 06:31:49.547518 run into bl31
418 06:31:49.555036 NOTICE: BL31: v1.3(release):4fc40b1
419 06:31:49.561898 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 06:31:49.562466 NOTICE: BL31: G12A normal boot!
421 06:31:49.578322 NOTICE: BL31: BL33 decompress pass
422 06:31:49.584087 ERROR: Error initializing runtime service opteed_fast
423 06:31:52.324734 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 06:31:52.325544 bl2_stage_init 0x01
425 06:31:52.326130 bl2_stage_init 0x81
426 06:31:52.330382 hw id: 0x0000 - pwm id 0x01
427 06:31:52.330986 bl2_stage_init 0xc1
428 06:31:52.335935 bl2_stage_init 0x02
429 06:31:52.336621
430 06:31:52.337140 L0:00000000
431 06:31:52.337646 L1:00000703
432 06:31:52.338150 L2:00008067
433 06:31:52.338651 L3:15000000
434 06:31:52.341453 S1:00000000
435 06:31:52.342012 B2:20282000
436 06:31:52.342526 B1:a0f83180
437 06:31:52.343031
438 06:31:52.343530 TE: 70022
439 06:31:52.344070
440 06:31:52.347058 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 06:31:52.347583
442 06:31:52.352655 Board ID = 1
443 06:31:52.353203 Set cpu clk to 24M
444 06:31:52.353712 Set clk81 to 24M
445 06:31:52.358370 Use GP1_pll as DSU clk.
446 06:31:52.358937 DSU clk: 1200 Mhz
447 06:31:52.359445 CPU clk: 1200 MHz
448 06:31:52.363863 Set clk81 to 166.6M
449 06:31:52.369433 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 06:31:52.369986 board id: 1
451 06:31:52.376659 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 06:31:52.387678 fw parse done
453 06:31:52.393554 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 06:31:52.436668 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 06:31:52.447816 PIEI prepare done
456 06:31:52.448430 fastboot data load
457 06:31:52.448956 fastboot data verify
458 06:31:52.453446 verify result: 266
459 06:31:52.459015 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 06:31:52.459559 LPDDR4 probe
461 06:31:52.460086 ddr clk to 1584MHz
462 06:31:52.466976 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 06:31:52.504749
464 06:31:52.505349 dmc_version 0001
465 06:31:52.511758 Check phy result
466 06:31:52.517729 INFO : End of CA training
467 06:31:52.518280 INFO : End of initialization
468 06:31:52.523360 INFO : Training has run successfully!
469 06:31:52.523907 Check phy result
470 06:31:52.528931 INFO : End of initialization
471 06:31:52.529494 INFO : End of read enable training
472 06:31:52.534522 INFO : End of fine write leveling
473 06:31:52.540203 INFO : End of Write leveling coarse delay
474 06:31:52.540751 INFO : Training has run successfully!
475 06:31:52.541270 Check phy result
476 06:31:52.545716 INFO : End of initialization
477 06:31:52.546255 INFO : End of read dq deskew training
478 06:31:52.551349 INFO : End of MPR read delay center optimization
479 06:31:52.556924 INFO : End of write delay center optimization
480 06:31:52.562521 INFO : End of read delay center optimization
481 06:31:52.563059 INFO : End of max read latency training
482 06:31:52.568199 INFO : Training has run successfully!
483 06:31:52.568746 1D training succeed
484 06:31:52.577304 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 06:31:52.624712 Check phy result
486 06:31:52.625335 INFO : End of initialization
487 06:31:52.652998 INFO : End of 2D read delay Voltage center optimization
488 06:31:52.677236 INFO : End of 2D read delay Voltage center optimization
489 06:31:52.733934 INFO : End of 2D write delay Voltage center optimization
490 06:31:52.788386 INFO : End of 2D write delay Voltage center optimization
491 06:31:52.794033 INFO : Training has run successfully!
492 06:31:52.794626
493 06:31:52.795158 channel==0
494 06:31:52.799474 RxClkDly_Margin_A0==78 ps 8
495 06:31:52.800091 TxDqDly_Margin_A0==98 ps 10
496 06:31:52.804780 RxClkDly_Margin_A1==78 ps 8
497 06:31:52.805433 TxDqDly_Margin_A1==98 ps 10
498 06:31:52.805966 TrainedVREFDQ_A0==74
499 06:31:52.810950 TrainedVREFDQ_A1==75
500 06:31:52.811556 VrefDac_Margin_A0==23
501 06:31:52.812114 DeviceVref_Margin_A0==40
502 06:31:52.815894 VrefDac_Margin_A1==23
503 06:31:52.816498 DeviceVref_Margin_A1==39
504 06:31:52.817030
505 06:31:52.817541
506 06:31:52.821629 channel==1
507 06:31:52.822220 RxClkDly_Margin_A0==88 ps 9
508 06:31:52.822739 TxDqDly_Margin_A0==98 ps 10
509 06:31:52.827152 RxClkDly_Margin_A1==78 ps 8
510 06:31:52.827744 TxDqDly_Margin_A1==88 ps 9
511 06:31:52.832665 TrainedVREFDQ_A0==78
512 06:31:52.833242 TrainedVREFDQ_A1==75
513 06:31:52.833758 VrefDac_Margin_A0==23
514 06:31:52.838275 DeviceVref_Margin_A0==36
515 06:31:52.838835 VrefDac_Margin_A1==22
516 06:31:52.843908 DeviceVref_Margin_A1==39
517 06:31:52.844549
518 06:31:52.845068 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 06:31:52.845582
520 06:31:52.877506 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000014 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
521 06:31:52.878204 2D training succeed
522 06:31:52.883052 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 06:31:52.888661 auto size-- 65535DDR cs0 size: 2048MB
524 06:31:52.889257 DDR cs1 size: 2048MB
525 06:31:52.894175 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 06:31:52.894727 cs0 DataBus test pass
527 06:31:52.899824 cs1 DataBus test pass
528 06:31:52.900437 cs0 AddrBus test pass
529 06:31:52.900949 cs1 AddrBus test pass
530 06:31:52.901450
531 06:31:52.905555 100bdlr_step_size ps== 471
532 06:31:52.906129 result report
533 06:31:52.911041 boot times 0Enable ddr reg access
534 06:31:52.916278 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 06:31:52.929184 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 06:31:53.589776 bl2z: ptr: 05129330, size: 00001e40
537 06:31:53.598583 0.0;M3 CHK:0;cm4_sp_mode 0
538 06:31:53.599168 MVN_1=0x00000000
539 06:31:53.599681 MVN_2=0x00000000
540 06:31:53.609987 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 06:31:53.610551 OPS=0x04
542 06:31:53.611077 ring efuse init
543 06:31:53.615605 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 06:31:53.616202 [0.017354 Inits done]
545 06:31:53.616731 secure task start!
546 06:31:53.623721 high task start!
547 06:31:53.624292 low task start!
548 06:31:53.624815 run into bl31
549 06:31:53.632397 NOTICE: BL31: v1.3(release):4fc40b1
550 06:31:53.639209 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 06:31:53.639766 NOTICE: BL31: G12A normal boot!
552 06:31:53.655799 NOTICE: BL31: BL33 decompress pass
553 06:31:53.660616 ERROR: Error initializing runtime service opteed_fast
554 06:31:55.024855 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 06:31:55.025596 bl2_stage_init 0x01
556 06:31:55.026156 bl2_stage_init 0x81
557 06:31:55.030488 hw id: 0x0000 - pwm id 0x01
558 06:31:55.031065 bl2_stage_init 0xc1
559 06:31:55.036096 bl2_stage_init 0x02
560 06:31:55.036667
561 06:31:55.037213 L0:00000000
562 06:31:55.037743 L1:00000703
563 06:31:55.038270 L2:00008067
564 06:31:55.038799 L3:15000000
565 06:31:55.042027 S1:00000000
566 06:31:55.042598 B2:20282000
567 06:31:55.043134 B1:a0f83180
568 06:31:55.043660
569 06:31:55.044240 TE: 69731
570 06:31:55.044779
571 06:31:55.047694 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 06:31:55.048285
573 06:31:55.053306 Board ID = 1
574 06:31:55.053870 Set cpu clk to 24M
575 06:31:55.054389 Set clk81 to 24M
576 06:31:55.056627 Use GP1_pll as DSU clk.
577 06:31:55.057183 DSU clk: 1200 Mhz
578 06:31:55.062192 CPU clk: 1200 MHz
579 06:31:55.062741 Set clk81 to 166.6M
580 06:31:55.067837 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 06:31:55.068433 board id: 1
582 06:31:55.076930 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 06:31:55.087448 fw parse done
584 06:31:55.093549 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 06:31:55.136152 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 06:31:55.147002 PIEI prepare done
587 06:31:55.147560 fastboot data load
588 06:31:55.148145 fastboot data verify
589 06:31:55.152644 verify result: 266
590 06:31:55.158226 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 06:31:55.158785 LPDDR4 probe
592 06:31:55.159307 ddr clk to 1584MHz
593 06:31:55.166204 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 06:31:55.203454
595 06:31:55.204053 dmc_version 0001
596 06:31:55.210127 Check phy result
597 06:31:55.216049 INFO : End of CA training
598 06:31:55.216608 INFO : End of initialization
599 06:31:55.221684 INFO : Training has run successfully!
600 06:31:55.222241 Check phy result
601 06:31:55.227228 INFO : End of initialization
602 06:31:55.227782 INFO : End of read enable training
603 06:31:55.232867 INFO : End of fine write leveling
604 06:31:55.238486 INFO : End of Write leveling coarse delay
605 06:31:55.239042 INFO : Training has run successfully!
606 06:31:55.239572 Check phy result
607 06:31:55.244057 INFO : End of initialization
608 06:31:55.244616 INFO : End of read dq deskew training
609 06:31:55.249636 INFO : End of MPR read delay center optimization
610 06:31:55.255259 INFO : End of write delay center optimization
611 06:31:55.260882 INFO : End of read delay center optimization
612 06:31:55.261445 INFO : End of max read latency training
613 06:31:55.266469 INFO : Training has run successfully!
614 06:31:55.267024 1D training succeed
615 06:31:55.275598 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 06:31:55.322365 Check phy result
617 06:31:55.323021 INFO : End of initialization
618 06:31:55.344629 INFO : End of 2D read delay Voltage center optimization
619 06:31:55.364747 INFO : End of 2D read delay Voltage center optimization
620 06:31:55.416640 INFO : End of 2D write delay Voltage center optimization
621 06:31:55.465967 INFO : End of 2D write delay Voltage center optimization
622 06:31:55.471303 INFO : Training has run successfully!
623 06:31:55.471861
624 06:31:55.472466 channel==0
625 06:31:55.476986 RxClkDly_Margin_A0==88 ps 9
626 06:31:55.477540 TxDqDly_Margin_A0==98 ps 10
627 06:31:55.480295 RxClkDly_Margin_A1==88 ps 9
628 06:31:55.480844 TxDqDly_Margin_A1==98 ps 10
629 06:31:55.485895 TrainedVREFDQ_A0==74
630 06:31:55.486464 TrainedVREFDQ_A1==74
631 06:31:55.491407 VrefDac_Margin_A0==24
632 06:31:55.491964 DeviceVref_Margin_A0==40
633 06:31:55.492526 VrefDac_Margin_A1==23
634 06:31:55.496991 DeviceVref_Margin_A1==40
635 06:31:55.497542
636 06:31:55.498065
637 06:31:55.498588 channel==1
638 06:31:55.499094 RxClkDly_Margin_A0==78 ps 8
639 06:31:55.502560 TxDqDly_Margin_A0==98 ps 10
640 06:31:55.503112 RxClkDly_Margin_A1==78 ps 8
641 06:31:55.508216 TxDqDly_Margin_A1==78 ps 8
642 06:31:55.508777 TrainedVREFDQ_A0==78
643 06:31:55.509311 TrainedVREFDQ_A1==75
644 06:31:55.513917 VrefDac_Margin_A0==22
645 06:31:55.514469 DeviceVref_Margin_A0==36
646 06:31:55.519358 VrefDac_Margin_A1==22
647 06:31:55.519910 DeviceVref_Margin_A1==39
648 06:31:55.520480
649 06:31:55.524979 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 06:31:55.525546
651 06:31:55.552973 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 06:31:55.558548 2D training succeed
653 06:31:55.564209 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 06:31:55.564760 auto size-- 65535DDR cs0 size: 2048MB
655 06:31:55.569911 DDR cs1 size: 2048MB
656 06:31:55.570460 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 06:31:55.575397 cs0 DataBus test pass
658 06:31:55.575969 cs1 DataBus test pass
659 06:31:55.576543 cs0 AddrBus test pass
660 06:31:55.580983 cs1 AddrBus test pass
661 06:31:55.581537
662 06:31:55.582064 100bdlr_step_size ps== 464
663 06:31:55.582599 result report
664 06:31:55.586589 boot times 0Enable ddr reg access
665 06:31:55.594225 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 06:31:55.608061 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 06:31:56.262957 bl2z: ptr: 05129330, size: 00001e40
668 06:31:56.269118 0.0;M3 CHK:0;cm4_sp_mode 0
669 06:31:56.269710 MVN_1=0x00000000
670 06:31:56.270250 MVN_2=0x00000000
671 06:31:56.280606 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 06:31:56.281175 OPS=0x04
673 06:31:56.281713 ring efuse init
674 06:31:56.283576 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 06:31:56.289953 [0.017319 Inits done]
676 06:31:56.290528 secure task start!
677 06:31:56.291066 high task start!
678 06:31:56.291595 low task start!
679 06:31:56.294162 run into bl31
680 06:31:56.302768 NOTICE: BL31: v1.3(release):4fc40b1
681 06:31:56.310636 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 06:31:56.311207 NOTICE: BL31: G12A normal boot!
683 06:31:56.326234 NOTICE: BL31: BL33 decompress pass
684 06:31:56.332042 ERROR: Error initializing runtime service opteed_fast
685 06:31:57.127344
686 06:31:57.128102
687 06:31:57.132707 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 06:31:57.133289
689 06:31:57.136216 Model: Libre Computer AML-S905D3-CC Solitude
690 06:31:57.283272 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 06:31:57.298619 DRAM: 2 GiB (effective 3.8 GiB)
692 06:31:57.399606 Core: 406 devices, 33 uclasses, devicetree: separate
693 06:31:57.405513 WDT: Not starting watchdog@f0d0
694 06:31:57.430570 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 06:31:57.442784 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 06:31:57.447789 ** Bad device specification mmc 0 **
697 06:31:57.457841 Card did not respond to voltage select! : -110
698 06:31:57.465456 ** Bad device specification mmc 0 **
699 06:31:57.466010 Couldn't find partition mmc 0
700 06:31:57.473791 Card did not respond to voltage select! : -110
701 06:31:57.479330 ** Bad device specification mmc 0 **
702 06:31:57.479881 Couldn't find partition mmc 0
703 06:31:57.483544 Error: could not access storage.
704 06:31:57.779804 Net: eth0: ethernet@ff3f0000
705 06:31:57.780561 starting USB...
706 06:31:58.025440 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 06:31:58.026076 Starting the controller
708 06:31:58.032372 USB XHCI 1.10
709 06:31:59.585777 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 06:31:59.594102 scanning usb for storage devices... 0 Storage Device(s) found
712 06:31:59.645872 Hit any key to stop autoboot: 1
713 06:31:59.646845 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 06:31:59.647586 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 06:31:59.648251 Setting prompt string to ['=>']
716 06:31:59.648882 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 06:31:59.660124 0
718 06:31:59.661157 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 06:31:59.762655 => setenv autoload no
721 06:31:59.763446 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 06:31:59.769620 setenv autoload no
724 06:31:59.871375 => setenv initrd_high 0xffffffff
725 06:31:59.872184 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 06:31:59.876531 setenv initrd_high 0xffffffff
728 06:31:59.978205 => setenv fdt_high 0xffffffff
729 06:31:59.978944 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 06:31:59.983282 setenv fdt_high 0xffffffff
732 06:32:00.084991 => dhcp
733 06:32:00.085746 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 06:32:00.089006 dhcp
735 06:32:01.095202 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 06:32:01.095811 Speed: 1000, full duplex
737 06:32:01.096291 BOOTP broadcast 1
738 06:32:01.344454 BOOTP broadcast 2
739 06:32:01.845523 BOOTP broadcast 3
740 06:32:02.846524 BOOTP broadcast 4
741 06:32:04.847532 BOOTP broadcast 5
742 06:32:04.859378 DHCP client bound to address 192.168.6.12 (3762 ms)
744 06:32:04.960801 => setenv serverip 192.168.6.2
745 06:32:04.961412 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
746 06:32:04.965857 setenv serverip 192.168.6.2
748 06:32:05.067234 => tftpboot 0x01080000 784855/tftp-deploy-uvgty2ra/kernel/uImage
749 06:32:05.067850 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
750 06:32:05.074639 tftpboot 0x01080000 784855/tftp-deploy-uvgty2ra/kernel/uImage
751 06:32:05.075105 Speed: 1000, full duplex
752 06:32:05.075516 Using ethernet@ff3f0000 device
753 06:32:05.079951 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 06:32:05.085504 Filename '784855/tftp-deploy-uvgty2ra/kernel/uImage'.
755 06:32:05.089304 Load address: 0x1080000
756 06:32:10.111084 Loading: *################################################## 43.9 MiB
757 06:32:10.111672 8.7 MiB/s
758 06:32:10.112122 done
759 06:32:10.114334 Bytes transferred = 45998656 (2bde240 hex)
761 06:32:10.215776 => tftpboot 0x08000000 784855/tftp-deploy-uvgty2ra/ramdisk/ramdisk.cpio.gz.uboot
762 06:32:10.216440 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
763 06:32:10.223092 tftpboot 0x08000000 784855/tftp-deploy-uvgty2ra/ramdisk/ramdisk.cpio.gz.uboot
764 06:32:10.223571 Speed: 1000, full duplex
765 06:32:10.223977 Using ethernet@ff3f0000 device
766 06:32:10.228601 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
767 06:32:10.237446 Filename '784855/tftp-deploy-uvgty2ra/ramdisk/ramdisk.cpio.gz.uboot'.
768 06:32:10.237923 Load address: 0x8000000
769 06:32:12.738727 Loading: *################################################# UDP wrong checksum 00000005 0000edb6
770 06:32:17.739352 T UDP wrong checksum 00000005 0000edb6
771 06:32:27.741563 T T UDP wrong checksum 00000005 0000edb6
772 06:32:47.744304 T T T UDP wrong checksum 00000005 0000edb6
773 06:33:07.751261 T T T T
774 06:33:07.751694 Retry count exceeded; starting again
776 06:33:07.754630 end: 2.4.3 bootloader-commands (duration 00:01:08) [common]
779 06:33:07.755603 end: 2.4 uboot-commands (duration 00:01:27) [common]
781 06:33:07.756355 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
783 06:33:07.756915 end: 2 uboot-action (duration 00:01:27) [common]
785 06:33:07.757720 Cleaning after the job
786 06:33:07.758033 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/ramdisk
787 06:33:07.758808 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/kernel
788 06:33:07.785689 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/dtb
789 06:33:07.786466 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784855/tftp-deploy-uvgty2ra/modules
790 06:33:07.808055 start: 4.1 power-off (timeout 00:00:30) [common]
791 06:33:07.808713 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
792 06:33:07.841943 >> OK - accepted request
793 06:33:07.844824 Returned 0 in 0 seconds
794 06:33:07.945517 end: 4.1 power-off (duration 00:00:00) [common]
796 06:33:07.946417 start: 4.2 read-feedback (timeout 00:10:00) [common]
797 06:33:07.947054 Listened to connection for namespace 'common' for up to 1s
798 06:33:08.947622 Finalising connection for namespace 'common'
799 06:33:08.948306 Disconnecting from shell: Finalise
800 06:33:08.948811 =>
801 06:33:09.049738 end: 4.2 read-feedback (duration 00:00:01) [common]
802 06:33:09.050302 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/784855
803 06:33:09.343104 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/784855
804 06:33:09.343702 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.