Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:14:41.760183 lava-dispatcher, installed at version: 2024.01
2 06:14:41.760985 start: 0 validate
3 06:14:41.761464 Start time: 2024-10-01 06:14:41.761434+00:00 (UTC)
4 06:14:41.761992 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:14:41.762533 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 06:14:41.801994 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:14:41.802575 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 06:14:41.833700 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:14:41.834329 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:14:41.863312 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:14:41.863812 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:14:41.893442 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 06:14:41.893928 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
14 06:14:41.930683 validate duration: 0.17
16 06:14:41.931781 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:14:41.932169 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:14:41.932525 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:14:41.933109 Not decompressing ramdisk as can be used compressed.
20 06:14:41.933579 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 06:14:41.933879 saving as /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/ramdisk/initrd.cpio.gz
22 06:14:41.934164 total size: 5628182 (5 MB)
23 06:14:41.970288 progress 0 % (0 MB)
24 06:14:41.979005 progress 5 % (0 MB)
25 06:14:41.987445 progress 10 % (0 MB)
26 06:14:41.994325 progress 15 % (0 MB)
27 06:14:41.999057 progress 20 % (1 MB)
28 06:14:42.002587 progress 25 % (1 MB)
29 06:14:42.006478 progress 30 % (1 MB)
30 06:14:42.010378 progress 35 % (1 MB)
31 06:14:42.013841 progress 40 % (2 MB)
32 06:14:42.017654 progress 45 % (2 MB)
33 06:14:42.021142 progress 50 % (2 MB)
34 06:14:42.025037 progress 55 % (2 MB)
35 06:14:42.028936 progress 60 % (3 MB)
36 06:14:42.032419 progress 65 % (3 MB)
37 06:14:42.036255 progress 70 % (3 MB)
38 06:14:42.039707 progress 75 % (4 MB)
39 06:14:42.043571 progress 80 % (4 MB)
40 06:14:42.046888 progress 85 % (4 MB)
41 06:14:42.050442 progress 90 % (4 MB)
42 06:14:42.054013 progress 95 % (5 MB)
43 06:14:42.057217 progress 100 % (5 MB)
44 06:14:42.057877 5 MB downloaded in 0.12 s (43.39 MB/s)
45 06:14:42.058449 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:14:42.059358 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:14:42.059657 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:14:42.059934 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:14:42.060446 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/kernel/Image
51 06:14:42.060705 saving as /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/kernel/Image
52 06:14:42.060915 total size: 47391232 (45 MB)
53 06:14:42.061125 No compression specified
54 06:14:42.096293 progress 0 % (0 MB)
55 06:14:42.131181 progress 5 % (2 MB)
56 06:14:42.166443 progress 10 % (4 MB)
57 06:14:42.201717 progress 15 % (6 MB)
58 06:14:42.237471 progress 20 % (9 MB)
59 06:14:42.272854 progress 25 % (11 MB)
60 06:14:42.308429 progress 30 % (13 MB)
61 06:14:42.340119 progress 35 % (15 MB)
62 06:14:42.369657 progress 40 % (18 MB)
63 06:14:42.399100 progress 45 % (20 MB)
64 06:14:42.428638 progress 50 % (22 MB)
65 06:14:42.457826 progress 55 % (24 MB)
66 06:14:42.486793 progress 60 % (27 MB)
67 06:14:42.516293 progress 65 % (29 MB)
68 06:14:42.545360 progress 70 % (31 MB)
69 06:14:42.574289 progress 75 % (33 MB)
70 06:14:42.603858 progress 80 % (36 MB)
71 06:14:42.633314 progress 85 % (38 MB)
72 06:14:42.662528 progress 90 % (40 MB)
73 06:14:42.692006 progress 95 % (42 MB)
74 06:14:42.720782 progress 100 % (45 MB)
75 06:14:42.721367 45 MB downloaded in 0.66 s (68.43 MB/s)
76 06:14:42.721858 end: 1.2.1 http-download (duration 00:00:01) [common]
78 06:14:42.722686 end: 1.2 download-retry (duration 00:00:01) [common]
79 06:14:42.722965 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:14:42.723234 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:14:42.723735 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 06:14:42.724051 saving as /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/dtb/meson-g12b-a311d-libretech-cc.dtb
83 06:14:42.724268 total size: 54703 (0 MB)
84 06:14:42.724479 No compression specified
85 06:14:42.759544 progress 59 % (0 MB)
86 06:14:42.760608 progress 100 % (0 MB)
87 06:14:42.761315 0 MB downloaded in 0.04 s (1.41 MB/s)
88 06:14:42.761902 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:14:42.762911 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:14:42.763241 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:14:42.763569 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:14:42.764159 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 06:14:42.764509 saving as /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/nfsrootfs/full.rootfs.tar
95 06:14:42.764762 total size: 107552908 (102 MB)
96 06:14:42.765018 Using unxz to decompress xz
97 06:14:42.801332 progress 0 % (0 MB)
98 06:14:43.463784 progress 5 % (5 MB)
99 06:14:44.231244 progress 10 % (10 MB)
100 06:14:44.976285 progress 15 % (15 MB)
101 06:14:45.754900 progress 20 % (20 MB)
102 06:14:46.327867 progress 25 % (25 MB)
103 06:14:46.994116 progress 30 % (30 MB)
104 06:14:47.811768 progress 35 % (35 MB)
105 06:14:48.208075 progress 40 % (41 MB)
106 06:14:48.679500 progress 45 % (46 MB)
107 06:14:49.438034 progress 50 % (51 MB)
108 06:14:50.118646 progress 55 % (56 MB)
109 06:14:50.872985 progress 60 % (61 MB)
110 06:14:51.627234 progress 65 % (66 MB)
111 06:14:52.370551 progress 70 % (71 MB)
112 06:14:53.137247 progress 75 % (76 MB)
113 06:14:53.812455 progress 80 % (82 MB)
114 06:14:54.511201 progress 85 % (87 MB)
115 06:14:55.230864 progress 90 % (92 MB)
116 06:14:55.933814 progress 95 % (97 MB)
117 06:14:56.682546 progress 100 % (102 MB)
118 06:14:56.695911 102 MB downloaded in 13.93 s (7.36 MB/s)
119 06:14:56.696835 end: 1.4.1 http-download (duration 00:00:14) [common]
121 06:14:56.698445 end: 1.4 download-retry (duration 00:00:14) [common]
122 06:14:56.698954 start: 1.5 download-retry (timeout 00:09:45) [common]
123 06:14:56.699461 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 06:14:56.700303 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/modules.tar.xz
125 06:14:56.700763 saving as /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/modules/modules.tar
126 06:14:56.701171 total size: 11607920 (11 MB)
127 06:14:56.701584 Using unxz to decompress xz
128 06:14:56.741155 progress 0 % (0 MB)
129 06:14:56.811822 progress 5 % (0 MB)
130 06:14:56.892521 progress 10 % (1 MB)
131 06:14:56.980708 progress 15 % (1 MB)
132 06:14:57.057894 progress 20 % (2 MB)
133 06:14:57.141731 progress 25 % (2 MB)
134 06:14:57.222904 progress 30 % (3 MB)
135 06:14:57.300225 progress 35 % (3 MB)
136 06:14:57.381702 progress 40 % (4 MB)
137 06:14:57.463970 progress 45 % (5 MB)
138 06:14:57.546447 progress 50 % (5 MB)
139 06:14:57.621069 progress 55 % (6 MB)
140 06:14:57.708968 progress 60 % (6 MB)
141 06:14:57.798153 progress 65 % (7 MB)
142 06:14:57.880249 progress 70 % (7 MB)
143 06:14:57.981281 progress 75 % (8 MB)
144 06:14:58.080901 progress 80 % (8 MB)
145 06:14:58.164896 progress 85 % (9 MB)
146 06:14:58.238280 progress 90 % (9 MB)
147 06:14:58.318065 progress 95 % (10 MB)
148 06:14:58.397061 progress 100 % (11 MB)
149 06:14:58.409056 11 MB downloaded in 1.71 s (6.48 MB/s)
150 06:14:58.409780 end: 1.5.1 http-download (duration 00:00:02) [common]
152 06:14:58.410775 end: 1.5 download-retry (duration 00:00:02) [common]
153 06:14:58.411119 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 06:14:58.411463 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 06:15:08.174943 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/784744/extract-nfsrootfs-x5t87q65
156 06:15:08.175548 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 06:15:08.175841 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 06:15:08.176587 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp
159 06:15:08.177053 makedir: /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin
160 06:15:08.177388 makedir: /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/tests
161 06:15:08.177710 makedir: /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/results
162 06:15:08.178056 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-add-keys
163 06:15:08.178622 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-add-sources
164 06:15:08.179162 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-background-process-start
165 06:15:08.179671 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-background-process-stop
166 06:15:08.180280 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-common-functions
167 06:15:08.180802 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-echo-ipv4
168 06:15:08.181297 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-install-packages
169 06:15:08.181791 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-installed-packages
170 06:15:08.182278 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-os-build
171 06:15:08.182785 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-probe-channel
172 06:15:08.183296 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-probe-ip
173 06:15:08.183787 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-target-ip
174 06:15:08.184304 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-target-mac
175 06:15:08.184792 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-target-storage
176 06:15:08.185278 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-test-case
177 06:15:08.185764 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-test-event
178 06:15:08.186252 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-test-feedback
179 06:15:08.186764 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-test-raise
180 06:15:08.187267 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-test-reference
181 06:15:08.187752 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-test-runner
182 06:15:08.188279 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-test-set
183 06:15:08.188778 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-test-shell
184 06:15:08.189271 Updating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-install-packages (oe)
185 06:15:08.189815 Updating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/bin/lava-installed-packages (oe)
186 06:15:08.190266 Creating /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/environment
187 06:15:08.190649 LAVA metadata
188 06:15:08.190915 - LAVA_JOB_ID=784744
189 06:15:08.191135 - LAVA_DISPATCHER_IP=192.168.6.2
190 06:15:08.191506 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 06:15:08.192573 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 06:15:08.192908 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 06:15:08.193121 skipped lava-vland-overlay
194 06:15:08.193368 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 06:15:08.193626 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 06:15:08.193850 skipped lava-multinode-overlay
197 06:15:08.194097 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 06:15:08.194357 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 06:15:08.194616 Loading test definitions
200 06:15:08.194900 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 06:15:08.195129 Using /lava-784744 at stage 0
202 06:15:08.196367 uuid=784744_1.6.2.4.1 testdef=None
203 06:15:08.196696 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 06:15:08.196967 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 06:15:08.198815 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 06:15:08.199618 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 06:15:08.201943 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 06:15:08.202783 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 06:15:08.205003 runner path: /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/0/tests/0_dmesg test_uuid 784744_1.6.2.4.1
212 06:15:08.205574 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 06:15:08.206342 Creating lava-test-runner.conf files
215 06:15:08.206549 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/784744/lava-overlay-dtuv5cgp/lava-784744/0 for stage 0
216 06:15:08.206887 - 0_dmesg
217 06:15:08.207231 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 06:15:08.207513 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 06:15:08.229175 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 06:15:08.229583 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 06:15:08.229851 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 06:15:08.230125 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 06:15:08.230395 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 06:15:08.846236 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 06:15:08.846701 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 06:15:08.846979 extracting modules file /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/modules/modules.tar to /var/lib/lava/dispatcher/tmp/784744/extract-nfsrootfs-x5t87q65
227 06:15:10.210342 extracting modules file /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/modules/modules.tar to /var/lib/lava/dispatcher/tmp/784744/extract-overlay-ramdisk-teel_pen/ramdisk
228 06:15:11.616257 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 06:15:11.616771 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 06:15:11.617074 [common] Applying overlay to NFS
231 06:15:11.617293 [common] Applying overlay /var/lib/lava/dispatcher/tmp/784744/compress-overlay-piz3i9da/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/784744/extract-nfsrootfs-x5t87q65
232 06:15:11.647274 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 06:15:11.647715 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 06:15:11.648019 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 06:15:11.648267 Converting downloaded kernel to a uImage
236 06:15:11.648584 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/kernel/Image /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/kernel/uImage
237 06:15:12.163574 output: Image Name:
238 06:15:12.164031 output: Created: Tue Oct 1 06:15:11 2024
239 06:15:12.164252 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 06:15:12.164462 output: Data Size: 47391232 Bytes = 46280.50 KiB = 45.20 MiB
241 06:15:12.164668 output: Load Address: 01080000
242 06:15:12.164872 output: Entry Point: 01080000
243 06:15:12.165074 output:
244 06:15:12.165419 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 06:15:12.165690 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 06:15:12.165960 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 06:15:12.166215 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 06:15:12.166475 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 06:15:12.166732 Building ramdisk /var/lib/lava/dispatcher/tmp/784744/extract-overlay-ramdisk-teel_pen/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/784744/extract-overlay-ramdisk-teel_pen/ramdisk
250 06:15:14.325110 >> 166922 blocks
251 06:15:22.051295 Adding RAMdisk u-boot header.
252 06:15:22.051959 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/784744/extract-overlay-ramdisk-teel_pen/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/784744/extract-overlay-ramdisk-teel_pen/ramdisk.cpio.gz.uboot
253 06:15:22.304017 output: Image Name:
254 06:15:22.304650 output: Created: Tue Oct 1 06:15:22 2024
255 06:15:22.305068 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 06:15:22.305474 output: Data Size: 23416801 Bytes = 22867.97 KiB = 22.33 MiB
257 06:15:22.305870 output: Load Address: 00000000
258 06:15:22.306264 output: Entry Point: 00000000
259 06:15:22.306656 output:
260 06:15:22.307746 rename /var/lib/lava/dispatcher/tmp/784744/extract-overlay-ramdisk-teel_pen/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/ramdisk/ramdisk.cpio.gz.uboot
261 06:15:22.308496 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 06:15:22.309042 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 06:15:22.309601 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 06:15:22.310056 No LXC device requested
265 06:15:22.310553 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 06:15:22.311060 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 06:15:22.311551 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 06:15:22.311964 Checking files for TFTP limit of 4294967296 bytes.
269 06:15:22.314662 end: 1 tftp-deploy (duration 00:00:40) [common]
270 06:15:22.315233 start: 2 uboot-action (timeout 00:05:00) [common]
271 06:15:22.315759 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 06:15:22.316298 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 06:15:22.316807 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 06:15:22.317333 Using kernel file from prepare-kernel: 784744/tftp-deploy-j6s2hdke/kernel/uImage
275 06:15:22.317963 substitutions:
276 06:15:22.318370 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 06:15:22.318774 - {DTB_ADDR}: 0x01070000
278 06:15:22.319174 - {DTB}: 784744/tftp-deploy-j6s2hdke/dtb/meson-g12b-a311d-libretech-cc.dtb
279 06:15:22.319573 - {INITRD}: 784744/tftp-deploy-j6s2hdke/ramdisk/ramdisk.cpio.gz.uboot
280 06:15:22.319971 - {KERNEL_ADDR}: 0x01080000
281 06:15:22.320439 - {KERNEL}: 784744/tftp-deploy-j6s2hdke/kernel/uImage
282 06:15:22.320839 - {LAVA_MAC}: None
283 06:15:22.321271 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/784744/extract-nfsrootfs-x5t87q65
284 06:15:22.321668 - {NFS_SERVER_IP}: 192.168.6.2
285 06:15:22.322058 - {PRESEED_CONFIG}: None
286 06:15:22.322448 - {PRESEED_LOCAL}: None
287 06:15:22.322836 - {RAMDISK_ADDR}: 0x08000000
288 06:15:22.323221 - {RAMDISK}: 784744/tftp-deploy-j6s2hdke/ramdisk/ramdisk.cpio.gz.uboot
289 06:15:22.323611 - {ROOT_PART}: None
290 06:15:22.324023 - {ROOT}: None
291 06:15:22.324469 - {SERVER_IP}: 192.168.6.2
292 06:15:22.324860 - {TEE_ADDR}: 0x83000000
293 06:15:22.325248 - {TEE}: None
294 06:15:22.325639 Parsed boot commands:
295 06:15:22.326019 - setenv autoload no
296 06:15:22.326404 - setenv initrd_high 0xffffffff
297 06:15:22.326790 - setenv fdt_high 0xffffffff
298 06:15:22.327178 - dhcp
299 06:15:22.327563 - setenv serverip 192.168.6.2
300 06:15:22.327948 - tftpboot 0x01080000 784744/tftp-deploy-j6s2hdke/kernel/uImage
301 06:15:22.328362 - tftpboot 0x08000000 784744/tftp-deploy-j6s2hdke/ramdisk/ramdisk.cpio.gz.uboot
302 06:15:22.328750 - tftpboot 0x01070000 784744/tftp-deploy-j6s2hdke/dtb/meson-g12b-a311d-libretech-cc.dtb
303 06:15:22.329134 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/784744/extract-nfsrootfs-x5t87q65,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 06:15:22.329531 - bootm 0x01080000 0x08000000 0x01070000
305 06:15:22.330025 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 06:15:22.331497 start: 2.3 connect-device (timeout 00:05:00) [common]
308 06:15:22.331910 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 06:15:22.346392 Setting prompt string to ['lava-test: # ']
310 06:15:22.347855 end: 2.3 connect-device (duration 00:00:00) [common]
311 06:15:22.348501 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 06:15:22.349052 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 06:15:22.349579 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 06:15:22.350736 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 06:15:22.388008 >> OK - accepted request
316 06:15:22.390362 Returned 0 in 0 seconds
317 06:15:22.491400 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 06:15:22.493035 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 06:15:22.493588 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 06:15:22.494093 Setting prompt string to ['Hit any key to stop autoboot']
322 06:15:22.494547 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 06:15:22.496149 Trying 192.168.56.21...
324 06:15:22.496645 Connected to conserv1.
325 06:15:22.497074 Escape character is '^]'.
326 06:15:22.497498
327 06:15:22.497922 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 06:15:22.498352
329 06:15:34.234671 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 06:15:34.235306 bl2_stage_init 0x01
331 06:15:34.235725 bl2_stage_init 0x81
332 06:15:34.240089 hw id: 0x0000 - pwm id 0x01
333 06:15:34.240547 bl2_stage_init 0xc1
334 06:15:34.240958 bl2_stage_init 0x02
335 06:15:34.241353
336 06:15:34.245634 L0:00000000
337 06:15:34.246066 L1:20000703
338 06:15:34.246464 L2:00008067
339 06:15:34.246868 L3:14000000
340 06:15:34.248543 B2:00402000
341 06:15:34.248977 B1:e0f83180
342 06:15:34.249370
343 06:15:34.249764 TE: 58124
344 06:15:34.250159
345 06:15:34.259656 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 06:15:34.260143
347 06:15:34.260554 Board ID = 1
348 06:15:34.260944 Set A53 clk to 24M
349 06:15:34.261336 Set A73 clk to 24M
350 06:15:34.265379 Set clk81 to 24M
351 06:15:34.265815 A53 clk: 1200 MHz
352 06:15:34.266210 A73 clk: 1200 MHz
353 06:15:34.270945 CLK81: 166.6M
354 06:15:34.271379 smccc: 00012a91
355 06:15:34.276534 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 06:15:34.276975 board id: 1
357 06:15:34.285162 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 06:15:34.295945 fw parse done
359 06:15:34.301789 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 06:15:34.344202 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 06:15:34.355110 PIEI prepare done
362 06:15:34.355584 fastboot data load
363 06:15:34.356039 fastboot data verify
364 06:15:34.360844 verify result: 266
365 06:15:34.366350 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 06:15:34.366828 LPDDR4 probe
367 06:15:34.367237 ddr clk to 1584MHz
368 06:15:34.374335 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 06:15:34.411600
370 06:15:34.412204 dmc_version 0001
371 06:15:34.418290 Check phy result
372 06:15:34.424173 INFO : End of CA training
373 06:15:34.424686 INFO : End of initialization
374 06:15:34.429820 INFO : Training has run successfully!
375 06:15:34.430284 Check phy result
376 06:15:34.435338 INFO : End of initialization
377 06:15:34.435799 INFO : End of read enable training
378 06:15:34.440934 INFO : End of fine write leveling
379 06:15:34.446523 INFO : End of Write leveling coarse delay
380 06:15:34.446979 INFO : Training has run successfully!
381 06:15:34.447379 Check phy result
382 06:15:34.452118 INFO : End of initialization
383 06:15:34.452597 INFO : End of read dq deskew training
384 06:15:34.457786 INFO : End of MPR read delay center optimization
385 06:15:34.463363 INFO : End of write delay center optimization
386 06:15:34.468963 INFO : End of read delay center optimization
387 06:15:34.469450 INFO : End of max read latency training
388 06:15:34.474520 INFO : Training has run successfully!
389 06:15:34.474968 1D training succeed
390 06:15:34.483711 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 06:15:34.531325 Check phy result
392 06:15:34.531892 INFO : End of initialization
393 06:15:34.553951 INFO : End of 2D read delay Voltage center optimization
394 06:15:34.574084 INFO : End of 2D read delay Voltage center optimization
395 06:15:34.626121 INFO : End of 2D write delay Voltage center optimization
396 06:15:34.675770 INFO : End of 2D write delay Voltage center optimization
397 06:15:34.681050 INFO : Training has run successfully!
398 06:15:34.681538
399 06:15:34.681957 channel==0
400 06:15:34.686700 RxClkDly_Margin_A0==88 ps 9
401 06:15:34.687289 TxDqDly_Margin_A0==98 ps 10
402 06:15:34.692254 RxClkDly_Margin_A1==88 ps 9
403 06:15:34.692830 TxDqDly_Margin_A1==88 ps 9
404 06:15:34.693415 TrainedVREFDQ_A0==74
405 06:15:34.697876 TrainedVREFDQ_A1==74
406 06:15:34.698409 VrefDac_Margin_A0==24
407 06:15:34.698866 DeviceVref_Margin_A0==40
408 06:15:34.703514 VrefDac_Margin_A1==24
409 06:15:34.704012 DeviceVref_Margin_A1==40
410 06:15:34.704420
411 06:15:34.704824
412 06:15:34.705287 channel==1
413 06:15:34.709051 RxClkDly_Margin_A0==98 ps 10
414 06:15:34.709514 TxDqDly_Margin_A0==98 ps 10
415 06:15:34.714615 RxClkDly_Margin_A1==98 ps 10
416 06:15:34.715048 TxDqDly_Margin_A1==88 ps 9
417 06:15:34.720216 TrainedVREFDQ_A0==77
418 06:15:34.720644 TrainedVREFDQ_A1==77
419 06:15:34.721041 VrefDac_Margin_A0==22
420 06:15:34.725846 DeviceVref_Margin_A0==37
421 06:15:34.726274 VrefDac_Margin_A1==22
422 06:15:34.731478 DeviceVref_Margin_A1==37
423 06:15:34.731917
424 06:15:34.732348 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 06:15:34.732747
426 06:15:34.765115 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 06:15:34.765862 2D training succeed
428 06:15:34.770777 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 06:15:34.776353 auto size-- 65535DDR cs0 size: 2048MB
430 06:15:34.776905 DDR cs1 size: 2048MB
431 06:15:34.782005 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 06:15:34.782547 cs0 DataBus test pass
433 06:15:34.787620 cs1 DataBus test pass
434 06:15:34.788215 cs0 AddrBus test pass
435 06:15:34.788668 cs1 AddrBus test pass
436 06:15:34.789111
437 06:15:34.793168 100bdlr_step_size ps== 420
438 06:15:34.793719 result report
439 06:15:34.798756 boot times 0Enable ddr reg access
440 06:15:34.804152 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 06:15:34.817559 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 06:15:35.391273 0.0;M3 CHK:0;cm4_sp_mode 0
443 06:15:35.391920 MVN_1=0x00000000
444 06:15:35.396727 MVN_2=0x00000000
445 06:15:35.402436 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 06:15:35.402943 OPS=0x10
447 06:15:35.403414 ring efuse init
448 06:15:35.403859 chipver efuse init
449 06:15:35.408142 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 06:15:35.413629 [0.018961 Inits done]
451 06:15:35.414123 secure task start!
452 06:15:35.414566 high task start!
453 06:15:35.418252 low task start!
454 06:15:35.418753 run into bl31
455 06:15:35.424950 NOTICE: BL31: v1.3(release):4fc40b1
456 06:15:35.432694 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 06:15:35.433206 NOTICE: BL31: G12A normal boot!
458 06:15:35.458045 NOTICE: BL31: BL33 decompress pass
459 06:15:35.463769 ERROR: Error initializing runtime service opteed_fast
460 06:15:36.696670
461 06:15:36.697325
462 06:15:36.705041 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 06:15:36.705319
464 06:15:36.705527 Model: Libre Computer AML-A311D-CC Alta
465 06:15:36.913423 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 06:15:36.936914 DRAM: 2 GiB (effective 3.8 GiB)
467 06:15:37.079829 Core: 408 devices, 31 uclasses, devicetree: separate
468 06:15:37.085722 WDT: Not starting watchdog@f0d0
469 06:15:37.117936 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 06:15:37.130446 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 06:15:37.134412 ** Bad device specification mmc 0 **
472 06:15:37.145846 Card did not respond to voltage select! : -110
473 06:15:37.153387 ** Bad device specification mmc 0 **
474 06:15:37.153900 Couldn't find partition mmc 0
475 06:15:37.161723 Card did not respond to voltage select! : -110
476 06:15:37.167273 ** Bad device specification mmc 0 **
477 06:15:37.167781 Couldn't find partition mmc 0
478 06:15:37.172284 Error: could not access storage.
479 06:15:38.435143 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 06:15:38.435569 bl2_stage_init 0x01
481 06:15:38.435807 bl2_stage_init 0x81
482 06:15:38.440770 hw id: 0x0000 - pwm id 0x01
483 06:15:38.441377 bl2_stage_init 0xc1
484 06:15:38.441852 bl2_stage_init 0x02
485 06:15:38.442304
486 06:15:38.446330 L0:00000000
487 06:15:38.446908 L1:20000703
488 06:15:38.447377 L2:00008067
489 06:15:38.447831 L3:14000000
490 06:15:38.451937 B2:00402000
491 06:15:38.452609 B1:e0f83180
492 06:15:38.453086
493 06:15:38.453587 TE: 58124
494 06:15:38.454076
495 06:15:38.457664 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 06:15:38.458307
497 06:15:38.458783 Board ID = 1
498 06:15:38.463157 Set A53 clk to 24M
499 06:15:38.463725 Set A73 clk to 24M
500 06:15:38.464230 Set clk81 to 24M
501 06:15:38.469293 A53 clk: 1200 MHz
502 06:15:38.469973 A73 clk: 1200 MHz
503 06:15:38.470450 CLK81: 166.6M
504 06:15:38.470923 smccc: 00012a92
505 06:15:38.474446 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 06:15:38.480102 board id: 1
507 06:15:38.485893 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 06:15:38.496575 fw parse done
509 06:15:38.502450 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 06:15:38.544996 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 06:15:38.556053 PIEI prepare done
512 06:15:38.556726 fastboot data load
513 06:15:38.557205 fastboot data verify
514 06:15:38.561728 verify result: 266
515 06:15:38.567293 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 06:15:38.567999 LPDDR4 probe
517 06:15:38.568627 ddr clk to 1584MHz
518 06:15:38.575195 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 06:15:38.612626
520 06:15:38.613310 dmc_version 0001
521 06:15:38.619112 Check phy result
522 06:15:38.625081 INFO : End of CA training
523 06:15:38.625931 INFO : End of initialization
524 06:15:38.630404 INFO : Training has run successfully!
525 06:15:38.630992 Check phy result
526 06:15:38.636095 INFO : End of initialization
527 06:15:38.636664 INFO : End of read enable training
528 06:15:38.639475 INFO : End of fine write leveling
529 06:15:38.645111 INFO : End of Write leveling coarse delay
530 06:15:38.650581 INFO : Training has run successfully!
531 06:15:38.650918 Check phy result
532 06:15:38.651170 INFO : End of initialization
533 06:15:38.656236 INFO : End of read dq deskew training
534 06:15:38.661778 INFO : End of MPR read delay center optimization
535 06:15:38.662267 INFO : End of write delay center optimization
536 06:15:38.667360 INFO : End of read delay center optimization
537 06:15:38.673034 INFO : End of max read latency training
538 06:15:38.673588 INFO : Training has run successfully!
539 06:15:38.678595 1D training succeed
540 06:15:38.684752 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 06:15:38.732195 Check phy result
542 06:15:38.732826 INFO : End of initialization
543 06:15:38.753633 INFO : End of 2D read delay Voltage center optimization
544 06:15:38.772937 INFO : End of 2D read delay Voltage center optimization
545 06:15:38.824721 INFO : End of 2D write delay Voltage center optimization
546 06:15:38.873868 INFO : End of 2D write delay Voltage center optimization
547 06:15:38.879423 INFO : Training has run successfully!
548 06:15:38.879900
549 06:15:38.880378 channel==0
550 06:15:38.885665 RxClkDly_Margin_A0==88 ps 9
551 06:15:38.886133 TxDqDly_Margin_A0==98 ps 10
552 06:15:38.888566 RxClkDly_Margin_A1==88 ps 9
553 06:15:38.889276 TxDqDly_Margin_A1==88 ps 9
554 06:15:38.894172 TrainedVREFDQ_A0==74
555 06:15:38.894813 TrainedVREFDQ_A1==74
556 06:15:38.895370 VrefDac_Margin_A0==25
557 06:15:38.900892 DeviceVref_Margin_A0==40
558 06:15:38.901524 VrefDac_Margin_A1==25
559 06:15:38.906775 DeviceVref_Margin_A1==40
560 06:15:38.907437
561 06:15:38.908091
562 06:15:38.908729 channel==1
563 06:15:38.909302 RxClkDly_Margin_A0==88 ps 9
564 06:15:38.910817 TxDqDly_Margin_A0==98 ps 10
565 06:15:38.911462 RxClkDly_Margin_A1==88 ps 9
566 06:15:38.916528 TxDqDly_Margin_A1==88 ps 9
567 06:15:38.917170 TrainedVREFDQ_A0==77
568 06:15:38.917842 TrainedVREFDQ_A1==76
569 06:15:38.922315 VrefDac_Margin_A0==23
570 06:15:38.922693 DeviceVref_Margin_A0==37
571 06:15:38.927821 VrefDac_Margin_A1==24
572 06:15:38.928257 DeviceVref_Margin_A1==38
573 06:15:38.928521
574 06:15:38.933188 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 06:15:38.933593
576 06:15:38.961181 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 06:15:38.967021 2D training succeed
578 06:15:38.972436 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 06:15:38.972965 auto size-- 65535DDR cs0 size: 2048MB
580 06:15:38.977949 DDR cs1 size: 2048MB
581 06:15:38.978470 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 06:15:38.985828 cs0 DataBus test pass
583 06:15:38.986365 cs1 DataBus test pass
584 06:15:38.986789 cs0 AddrBus test pass
585 06:15:38.989683 cs1 AddrBus test pass
586 06:15:38.990184
587 06:15:38.990609 100bdlr_step_size ps== 420
588 06:15:38.991038 result report
589 06:15:38.994895 boot times 0Enable ddr reg access
590 06:15:39.002271 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 06:15:39.016555 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 06:15:39.588058 0.0;M3 CHK:0;cm4_sp_mode 0
593 06:15:39.588513 MVN_1=0x00000000
594 06:15:39.593475 MVN_2=0x00000000
595 06:15:39.599384 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 06:15:39.599788 OPS=0x10
597 06:15:39.600035 ring efuse init
598 06:15:39.600287 chipver efuse init
599 06:15:39.607466 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 06:15:39.608005 [0.018961 Inits done]
601 06:15:39.608388 secure task start!
602 06:15:39.615234 high task start!
603 06:15:39.615693 low task start!
604 06:15:39.616068 run into bl31
605 06:15:39.621802 NOTICE: BL31: v1.3(release):4fc40b1
606 06:15:39.630303 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 06:15:39.630702 NOTICE: BL31: G12A normal boot!
608 06:15:39.654753 NOTICE: BL31: BL33 decompress pass
609 06:15:39.660358 ERROR: Error initializing runtime service opteed_fast
610 06:15:40.893373
611 06:15:40.894033
612 06:15:40.901712 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 06:15:40.902175
614 06:15:40.902596 Model: Libre Computer AML-A311D-CC Alta
615 06:15:41.110151 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 06:15:41.133568 DRAM: 2 GiB (effective 3.8 GiB)
617 06:15:41.276619 Core: 408 devices, 31 uclasses, devicetree: separate
618 06:15:41.282360 WDT: Not starting watchdog@f0d0
619 06:15:41.314610 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 06:15:41.327090 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 06:15:41.332103 ** Bad device specification mmc 0 **
622 06:15:41.342375 Card did not respond to voltage select! : -110
623 06:15:41.350116 ** Bad device specification mmc 0 **
624 06:15:41.350578 Couldn't find partition mmc 0
625 06:15:41.358384 Card did not respond to voltage select! : -110
626 06:15:41.363828 ** Bad device specification mmc 0 **
627 06:15:41.364311 Couldn't find partition mmc 0
628 06:15:41.369048 Error: could not access storage.
629 06:15:41.711467 Net: eth0: ethernet@ff3f0000
630 06:15:41.712062 starting USB...
631 06:15:41.963312 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 06:15:41.963819 Starting the controller
633 06:15:41.970243 USB XHCI 1.10
634 06:15:43.683828 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
635 06:15:43.684589 bl2_stage_init 0x81
636 06:15:43.689604 hw id: 0x0000 - pwm id 0x01
637 06:15:43.690157 bl2_stage_init 0xc1
638 06:15:43.690629 bl2_stage_init 0x02
639 06:15:43.691086
640 06:15:43.695052 L0:00000000
641 06:15:43.695569 L1:20000703
642 06:15:43.696068 L2:00008067
643 06:15:43.696525 L3:14000000
644 06:15:43.696975 B2:00402000
645 06:15:43.700588 B1:e0f83180
646 06:15:43.701103
647 06:15:43.701565 TE: 58150
648 06:15:43.702017
649 06:15:43.706314 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 06:15:43.706835
651 06:15:43.707293 Board ID = 1
652 06:15:43.711902 Set A53 clk to 24M
653 06:15:43.712441 Set A73 clk to 24M
654 06:15:43.712892 Set clk81 to 24M
655 06:15:43.717448 A53 clk: 1200 MHz
656 06:15:43.717958 A73 clk: 1200 MHz
657 06:15:43.718410 CLK81: 166.6M
658 06:15:43.718855 smccc: 00012aab
659 06:15:43.722905 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 06:15:43.728528 board id: 1
661 06:15:43.734356 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 06:15:43.745035 fw parse done
663 06:15:43.750969 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 06:15:43.793584 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 06:15:43.804543 PIEI prepare done
666 06:15:43.805056 fastboot data load
667 06:15:43.805521 fastboot data verify
668 06:15:43.810114 verify result: 266
669 06:15:43.815695 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 06:15:43.816258 LPDDR4 probe
671 06:15:43.816725 ddr clk to 1584MHz
672 06:15:43.823716 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 06:15:43.861058
674 06:15:43.861606 dmc_version 0001
675 06:15:43.867647 Check phy result
676 06:15:43.873550 INFO : End of CA training
677 06:15:43.874064 INFO : End of initialization
678 06:15:43.879114 INFO : Training has run successfully!
679 06:15:43.879621 Check phy result
680 06:15:43.884687 INFO : End of initialization
681 06:15:43.885197 INFO : End of read enable training
682 06:15:43.890287 INFO : End of fine write leveling
683 06:15:43.895916 INFO : End of Write leveling coarse delay
684 06:15:43.896458 INFO : Training has run successfully!
685 06:15:43.896920 Check phy result
686 06:15:43.901550 INFO : End of initialization
687 06:15:43.902065 INFO : End of read dq deskew training
688 06:15:43.907085 INFO : End of MPR read delay center optimization
689 06:15:43.912731 INFO : End of write delay center optimization
690 06:15:43.918276 INFO : End of read delay center optimization
691 06:15:43.918788 INFO : End of max read latency training
692 06:15:43.923951 INFO : Training has run successfully!
693 06:15:43.924507 1D training succeed
694 06:15:43.933052 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 06:15:43.980684 Check phy result
696 06:15:43.981232 INFO : End of initialization
697 06:15:44.002394 INFO : End of 2D read delay Voltage center optimization
698 06:15:44.021880 INFO : End of 2D read delay Voltage center optimization
699 06:15:44.073919 INFO : End of 2D write delay Voltage center optimization
700 06:15:44.123366 INFO : End of 2D write delay Voltage center optimization
701 06:15:44.128946 INFO : Training has run successfully!
702 06:15:44.129462
703 06:15:44.129922 channel==0
704 06:15:44.134389 RxClkDly_Margin_A0==88 ps 9
705 06:15:44.134921 TxDqDly_Margin_A0==98 ps 10
706 06:15:44.137747 RxClkDly_Margin_A1==88 ps 9
707 06:15:44.138266 TxDqDly_Margin_A1==88 ps 9
708 06:15:44.143379 TrainedVREFDQ_A0==74
709 06:15:44.143914 TrainedVREFDQ_A1==74
710 06:15:44.144423 VrefDac_Margin_A0==25
711 06:15:44.149070 DeviceVref_Margin_A0==40
712 06:15:44.149595 VrefDac_Margin_A1==25
713 06:15:44.154510 DeviceVref_Margin_A1==40
714 06:15:44.155029
715 06:15:44.155488
716 06:15:44.155938 channel==1
717 06:15:44.156415 RxClkDly_Margin_A0==88 ps 9
718 06:15:44.157954 TxDqDly_Margin_A0==88 ps 9
719 06:15:44.163537 RxClkDly_Margin_A1==88 ps 9
720 06:15:44.164094 TxDqDly_Margin_A1==88 ps 9
721 06:15:44.164564 TrainedVREFDQ_A0==77
722 06:15:44.169131 TrainedVREFDQ_A1==77
723 06:15:44.169654 VrefDac_Margin_A0==23
724 06:15:44.174727 DeviceVref_Margin_A0==37
725 06:15:44.175235 VrefDac_Margin_A1==24
726 06:15:44.175689 DeviceVref_Margin_A1==37
727 06:15:44.176178
728 06:15:44.180406 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 06:15:44.180919
730 06:15:44.213871 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000018 dram_vref_reg_value 0x 00000060
731 06:15:44.214482 2D training succeed
732 06:15:44.219529 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 06:15:44.225136 auto size-- 65535DDR cs0 size: 2048MB
734 06:15:44.225686 DDR cs1 size: 2048MB
735 06:15:44.230650 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 06:15:44.231222 cs0 DataBus test pass
737 06:15:44.231686 cs1 DataBus test pass
738 06:15:44.236366 cs0 AddrBus test pass
739 06:15:44.236940 cs1 AddrBus test pass
740 06:15:44.237402
741 06:15:44.241799 100bdlr_step_size ps== 420
742 06:15:44.242385 result report
743 06:15:44.242844 boot times 0Enable ddr reg access
744 06:15:44.251355 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 06:15:44.264894 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 06:15:44.838415 0.0;M3 CHK:0;cm4_sp_mode 0
747 06:15:44.838854 MVN_1=0x00000000
748 06:15:44.843876 MVN_2=0x00000000
749 06:15:44.849676 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 06:15:44.850165 OPS=0x10
751 06:15:44.850572 ring efuse init
752 06:15:44.850969 chipver efuse init
753 06:15:44.855231 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 06:15:44.860840 [0.018961 Inits done]
755 06:15:44.861282 secure task start!
756 06:15:44.861686 high task start!
757 06:15:44.865418 low task start!
758 06:15:44.865851 run into bl31
759 06:15:44.872156 NOTICE: BL31: v1.3(release):4fc40b1
760 06:15:44.879899 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 06:15:44.880378 NOTICE: BL31: G12A normal boot!
762 06:15:44.905795 NOTICE: BL31: BL33 decompress pass
763 06:15:44.911507 ERROR: Error initializing runtime service opteed_fast
764 06:15:46.144674
765 06:15:46.145372
766 06:15:46.152980 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 06:15:46.153577
768 06:15:46.154053 Model: Libre Computer AML-A311D-CC Alta
769 06:15:46.361710 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 06:15:46.384779 DRAM: 2 GiB (effective 3.8 GiB)
771 06:15:46.527756 Core: 408 devices, 31 uclasses, devicetree: separate
772 06:15:46.533648 WDT: Not starting watchdog@f0d0
773 06:15:46.565876 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 06:15:46.578296 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 06:15:46.583338 ** Bad device specification mmc 0 **
776 06:15:46.593680 Card did not respond to voltage select! : -110
777 06:15:46.601295 ** Bad device specification mmc 0 **
778 06:15:46.601842 Couldn't find partition mmc 0
779 06:15:46.609683 Card did not respond to voltage select! : -110
780 06:15:46.615192 ** Bad device specification mmc 0 **
781 06:15:46.615756 Couldn't find partition mmc 0
782 06:15:46.620254 Error: could not access storage.
783 06:15:46.963658 Net: eth0: ethernet@ff3f0000
784 06:15:46.964292 starting USB...
785 06:15:47.215453 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 06:15:47.216026 Starting the controller
787 06:15:47.222445 USB XHCI 1.10
788 06:15:49.383800 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 06:15:49.384512 bl2_stage_init 0x01
790 06:15:49.384982 bl2_stage_init 0x81
791 06:15:49.389359 hw id: 0x0000 - pwm id 0x01
792 06:15:49.389873 bl2_stage_init 0xc1
793 06:15:49.390336 bl2_stage_init 0x02
794 06:15:49.390783
795 06:15:49.395025 L0:00000000
796 06:15:49.395529 L1:20000703
797 06:15:49.396018 L2:00008067
798 06:15:49.396476 L3:14000000
799 06:15:49.398114 B2:00402000
800 06:15:49.398617 B1:e0f83180
801 06:15:49.399064
802 06:15:49.399510 TE: 58124
803 06:15:49.399958
804 06:15:49.409264 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 06:15:49.409778
806 06:15:49.410238 Board ID = 1
807 06:15:49.410686 Set A53 clk to 24M
808 06:15:49.411130 Set A73 clk to 24M
809 06:15:49.414952 Set clk81 to 24M
810 06:15:49.415455 A53 clk: 1200 MHz
811 06:15:49.415908 A73 clk: 1200 MHz
812 06:15:49.418345 CLK81: 166.6M
813 06:15:49.418845 smccc: 00012a92
814 06:15:49.423900 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 06:15:49.429476 board id: 1
816 06:15:49.434548 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 06:15:49.445230 fw parse done
818 06:15:49.451139 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 06:15:49.493622 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 06:15:49.504676 PIEI prepare done
821 06:15:49.505183 fastboot data load
822 06:15:49.505640 fastboot data verify
823 06:15:49.510233 verify result: 266
824 06:15:49.515828 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 06:15:49.516374 LPDDR4 probe
826 06:15:49.516830 ddr clk to 1584MHz
827 06:15:49.523805 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 06:15:49.561131
829 06:15:49.561642 dmc_version 0001
830 06:15:49.567736 Check phy result
831 06:15:49.573644 INFO : End of CA training
832 06:15:49.574149 INFO : End of initialization
833 06:15:49.579195 INFO : Training has run successfully!
834 06:15:49.579698 Check phy result
835 06:15:49.584815 INFO : End of initialization
836 06:15:49.585319 INFO : End of read enable training
837 06:15:49.590471 INFO : End of fine write leveling
838 06:15:49.596085 INFO : End of Write leveling coarse delay
839 06:15:49.596591 INFO : Training has run successfully!
840 06:15:49.597052 Check phy result
841 06:15:49.601671 INFO : End of initialization
842 06:15:49.602172 INFO : End of read dq deskew training
843 06:15:49.607239 INFO : End of MPR read delay center optimization
844 06:15:49.612841 INFO : End of write delay center optimization
845 06:15:49.618471 INFO : End of read delay center optimization
846 06:15:49.618973 INFO : End of max read latency training
847 06:15:49.624077 INFO : Training has run successfully!
848 06:15:49.624584 1D training succeed
849 06:15:49.633185 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 06:15:49.680791 Check phy result
851 06:15:49.681297 INFO : End of initialization
852 06:15:49.984381 INFO : End of 2D read delay Voltage center optimization
853 06:15:49.985012 INFO : End of 2D read delay Voltage center optimization
854 06:15:49.985511 INFO : End of 2D write delay Voltage center optimization
855 06:15:49.985991 INFO : End of 2D write delay Voltage center optimization
856 06:15:49.986459 INFO : Training has run successfully!
857 06:15:49.986909
858 06:15:49.987493 channel==0
859 06:15:49.987956 RxClkDly_Margin_A0==88 ps 9
860 06:15:49.988487 TxDqDly_Margin_A0==98 ps 10
861 06:15:49.988934 RxClkDly_Margin_A1==88 ps 9
862 06:15:49.989365 TxDqDly_Margin_A1==88 ps 9
863 06:15:49.989801 TrainedVREFDQ_A0==74
864 06:15:49.990235 TrainedVREFDQ_A1==74
865 06:15:49.990678 VrefDac_Margin_A0==24
866 06:15:49.991124 DeviceVref_Margin_A0==40
867 06:15:49.991572 VrefDac_Margin_A1==24
868 06:15:49.992053 DeviceVref_Margin_A1==40
869 06:15:49.992516
870 06:15:49.992974
871 06:15:49.993419 channel==1
872 06:15:49.993839 RxClkDly_Margin_A0==88 ps 9
873 06:15:49.994258 TxDqDly_Margin_A0==98 ps 10
874 06:15:49.994684 RxClkDly_Margin_A1==88 ps 9
875 06:15:49.995105 TxDqDly_Margin_A1==88 ps 9
876 06:15:49.995530 TrainedVREFDQ_A0==77
877 06:15:49.995951 TrainedVREFDQ_A1==77
878 06:15:49.996416 VrefDac_Margin_A0==23
879 06:15:49.996836 DeviceVref_Margin_A0==37
880 06:15:49.997251 VrefDac_Margin_A1==24
881 06:15:49.997668 DeviceVref_Margin_A1==37
882 06:15:49.998086
883 06:15:49.998502 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 06:15:49.998919
885 06:15:49.999785 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
886 06:15:50.000311 2D training succeed
887 06:15:50.000761 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 06:15:50.001193 auto size-- 65535DDR cs0 size: 2048MB
889 06:15:50.001620 DDR cs1 size: 2048MB
890 06:15:50.002041 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 06:15:50.002464 cs0 DataBus test pass
892 06:15:50.002883 cs1 DataBus test pass
893 06:15:50.003301 cs0 AddrBus test pass
894 06:15:50.003726 cs1 AddrBus test pass
895 06:15:50.004169
896 06:15:50.004593 100bdlr_step_size ps== 420
897 06:15:50.005021 result report
898 06:15:50.005435 boot times 0Enable ddr reg access
899 06:15:50.005851 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 06:15:50.006272 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 06:15:50.539797 0.0;M3 CHK:0;cm4_sp_mode 0
902 06:15:50.540509 MVN_1=0x00000000
903 06:15:50.545335 MVN_2=0x00000000
904 06:15:50.551146 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 06:15:50.551665 OPS=0x10
906 06:15:50.552168 ring efuse init
907 06:15:50.552623 chipver efuse init
908 06:15:50.556618 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 06:15:50.562112 [0.018961 Inits done]
910 06:15:50.562619 secure task start!
911 06:15:50.563074 high task start!
912 06:15:50.566770 low task start!
913 06:15:50.567281 run into bl31
914 06:15:50.573414 NOTICE: BL31: v1.3(release):4fc40b1
915 06:15:50.581196 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 06:15:50.581720 NOTICE: BL31: G12A normal boot!
917 06:15:50.606514 NOTICE: BL31: BL33 decompress pass
918 06:15:50.612346 ERROR: Error initializing runtime service opteed_fast
919 06:15:51.845180
920 06:15:51.845873
921 06:15:51.853691 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 06:15:51.854222
923 06:15:51.854692 Model: Libre Computer AML-A311D-CC Alta
924 06:15:52.062045 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 06:15:52.085403 DRAM: 2 GiB (effective 3.8 GiB)
926 06:15:52.228381 Core: 408 devices, 31 uclasses, devicetree: separate
927 06:15:52.234376 WDT: Not starting watchdog@f0d0
928 06:15:52.266542 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 06:15:52.278993 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 06:15:52.284107 ** Bad device specification mmc 0 **
931 06:15:52.294244 Card did not respond to voltage select! : -110
932 06:15:52.302055 ** Bad device specification mmc 0 **
933 06:15:52.302561 Couldn't find partition mmc 0
934 06:15:52.310262 Card did not respond to voltage select! : -110
935 06:15:52.315760 ** Bad device specification mmc 0 **
936 06:15:52.316291 Couldn't find partition mmc 0
937 06:15:52.320920 Error: could not access storage.
938 06:15:52.664444 Net: eth0: ethernet@ff3f0000
939 06:15:52.664979 starting USB...
940 06:15:52.916218 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 06:15:52.916742 Starting the controller
942 06:15:52.923292 USB XHCI 1.10
943 06:15:54.477140 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
944 06:15:54.485503 scanning usb for storage devices... 0 Storage Device(s) found
946 06:15:54.537143 Hit any key to stop autoboot: 1
947 06:15:54.538211 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
948 06:15:54.538881 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
949 06:15:54.539414 Setting prompt string to ['=>']
950 06:15:54.539949 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
951 06:15:54.552892 0
952 06:15:54.553830 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
953 06:15:54.554381 Sending with 10 millisecond of delay
955 06:15:55.689835 => setenv autoload no
956 06:15:55.700707 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
957 06:15:55.706494 setenv autoload no
958 06:15:55.707314 Sending with 10 millisecond of delay
960 06:15:57.504396 => setenv initrd_high 0xffffffff
961 06:15:57.515198 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
962 06:15:57.516167 setenv initrd_high 0xffffffff
963 06:15:57.516944 Sending with 10 millisecond of delay
965 06:15:59.134306 => setenv fdt_high 0xffffffff
966 06:15:59.145128 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
967 06:15:59.146022 setenv fdt_high 0xffffffff
968 06:15:59.146799 Sending with 10 millisecond of delay
970 06:15:59.438836 => dhcp
971 06:15:59.449706 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
972 06:15:59.450688 dhcp
973 06:15:59.451187 Speed: 1000, full duplex
974 06:15:59.451648 BOOTP broadcast 1
975 06:15:59.701274 BOOTP broadcast 2
976 06:15:59.717781 DHCP client bound to address 192.168.6.33 (266 ms)
977 06:15:59.718835 Sending with 10 millisecond of delay
979 06:16:01.395607 => setenv serverip 192.168.6.2
980 06:16:01.406476 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 06:16:01.407409 setenv serverip 192.168.6.2
982 06:16:01.408144 Sending with 10 millisecond of delay
984 06:16:05.131392 => tftpboot 0x01080000 784744/tftp-deploy-j6s2hdke/kernel/uImage
985 06:16:05.142260 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
986 06:16:05.143147 tftpboot 0x01080000 784744/tftp-deploy-j6s2hdke/kernel/uImage
987 06:16:05.143634 Speed: 1000, full duplex
988 06:16:05.144129 Using ethernet@ff3f0000 device
989 06:16:05.145202 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
990 06:16:05.150862 Filename '784744/tftp-deploy-j6s2hdke/kernel/uImage'.
991 06:16:05.154545 Load address: 0x1080000
992 06:16:15.543260 Loading: *##############################################T #### 45.2 MiB
993 06:16:15.543937 4.3 MiB/s
994 06:16:15.544470 done
995 06:16:15.547669 Bytes transferred = 47391296 (2d32240 hex)
996 06:16:15.548561 Sending with 10 millisecond of delay
998 06:16:20.235113 => tftpboot 0x08000000 784744/tftp-deploy-j6s2hdke/ramdisk/ramdisk.cpio.gz.uboot
999 06:16:20.246008 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
1000 06:16:20.247032 tftpboot 0x08000000 784744/tftp-deploy-j6s2hdke/ramdisk/ramdisk.cpio.gz.uboot
1001 06:16:20.247544 Speed: 1000, full duplex
1002 06:16:20.248057 Using ethernet@ff3f0000 device
1003 06:16:20.249057 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1004 06:16:20.260732 Filename '784744/tftp-deploy-j6s2hdke/ramdisk/ramdisk.cpio.gz.uboot'.
1005 06:16:20.261390 Load address: 0x8000000
1006 06:16:22.389697 Loading: *################################################# UDP wrong checksum 00000005 0000f78b
1007 06:16:27.391164 T UDP wrong checksum 00000005 0000f78b
1008 06:16:37.393308 T T UDP wrong checksum 00000005 0000f78b
1009 06:16:57.397029 T T T T UDP wrong checksum 00000005 0000f78b
1010 06:17:14.509236 T T T UDP wrong checksum 000000ff 00005864
1011 06:17:14.539301 UDP wrong checksum 000000ff 0000f556
1012 06:17:17.402069
1013 06:17:17.402720 Retry count exceeded; starting again
1015 06:17:17.404329 end: 2.4.3 bootloader-commands (duration 00:01:23) [common]
1018 06:17:17.406382 end: 2.4 uboot-commands (duration 00:01:55) [common]
1020 06:17:17.407924 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1022 06:17:17.409150 end: 2 uboot-action (duration 00:01:55) [common]
1024 06:17:17.410848 Cleaning after the job
1025 06:17:17.411469 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/ramdisk
1026 06:17:17.413010 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/kernel
1027 06:17:17.429115 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/dtb
1028 06:17:17.430707 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/nfsrootfs
1029 06:17:17.484499 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784744/tftp-deploy-j6s2hdke/modules
1030 06:17:17.494519 start: 4.1 power-off (timeout 00:00:30) [common]
1031 06:17:17.495197 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1032 06:17:17.527028 >> OK - accepted request
1033 06:17:17.528989 Returned 0 in 0 seconds
1034 06:17:17.629791 end: 4.1 power-off (duration 00:00:00) [common]
1036 06:17:17.630806 start: 4.2 read-feedback (timeout 00:10:00) [common]
1037 06:17:17.631465 Listened to connection for namespace 'common' for up to 1s
1038 06:17:18.631750 Finalising connection for namespace 'common'
1039 06:17:18.632578 Disconnecting from shell: Finalise
1040 06:17:18.633140 =>
1041 06:17:18.734304 end: 4.2 read-feedback (duration 00:00:01) [common]
1042 06:17:18.735089 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/784744
1043 06:17:20.445515 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/784744
1044 06:17:20.446110 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.