Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:06:21.888935 lava-dispatcher, installed at version: 2024.01
2 06:06:21.889799 start: 0 validate
3 06:06:21.890307 Start time: 2024-10-01 06:06:21.890276+00:00 (UTC)
4 06:06:21.890872 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:06:21.891436 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 06:06:21.931408 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:06:21.932017 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 06:06:21.972130 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:06:21.972950 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:06:23.025025 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:06:23.025541 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 06:06:23.062525 validate duration: 1.17
14 06:06:23.063416 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:06:23.063776 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:06:23.064129 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:06:23.064766 Not decompressing ramdisk as can be used compressed.
18 06:06:23.065239 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 06:06:23.065487 saving as /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/ramdisk/rootfs.cpio.gz
20 06:06:23.065746 total size: 8181887 (7 MB)
21 06:06:23.104697 progress 0 % (0 MB)
22 06:06:23.110737 progress 5 % (0 MB)
23 06:06:23.116398 progress 10 % (0 MB)
24 06:06:23.122467 progress 15 % (1 MB)
25 06:06:23.128626 progress 20 % (1 MB)
26 06:06:23.134769 progress 25 % (1 MB)
27 06:06:23.140458 progress 30 % (2 MB)
28 06:06:23.146505 progress 35 % (2 MB)
29 06:06:23.152130 progress 40 % (3 MB)
30 06:06:23.158142 progress 45 % (3 MB)
31 06:06:23.163803 progress 50 % (3 MB)
32 06:06:23.169726 progress 55 % (4 MB)
33 06:06:23.175228 progress 60 % (4 MB)
34 06:06:23.181085 progress 65 % (5 MB)
35 06:06:23.186536 progress 70 % (5 MB)
36 06:06:23.192611 progress 75 % (5 MB)
37 06:06:23.198530 progress 80 % (6 MB)
38 06:06:23.204834 progress 85 % (6 MB)
39 06:06:23.210900 progress 90 % (7 MB)
40 06:06:23.217274 progress 95 % (7 MB)
41 06:06:23.222339 progress 100 % (7 MB)
42 06:06:23.222989 7 MB downloaded in 0.16 s (49.63 MB/s)
43 06:06:23.223535 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:06:23.224688 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:06:23.225082 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:06:23.225490 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:06:23.226044 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
49 06:06:23.226354 saving as /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/kernel/Image
50 06:06:23.226608 total size: 45779456 (43 MB)
51 06:06:23.226866 No compression specified
52 06:06:23.273567 progress 0 % (0 MB)
53 06:06:23.302157 progress 5 % (2 MB)
54 06:06:23.332297 progress 10 % (4 MB)
55 06:06:23.361306 progress 15 % (6 MB)
56 06:06:23.391274 progress 20 % (8 MB)
57 06:06:23.420494 progress 25 % (10 MB)
58 06:06:23.448670 progress 30 % (13 MB)
59 06:06:23.476454 progress 35 % (15 MB)
60 06:06:23.505337 progress 40 % (17 MB)
61 06:06:23.533751 progress 45 % (19 MB)
62 06:06:23.563394 progress 50 % (21 MB)
63 06:06:23.591715 progress 55 % (24 MB)
64 06:06:23.619942 progress 60 % (26 MB)
65 06:06:23.648203 progress 65 % (28 MB)
66 06:06:23.675942 progress 70 % (30 MB)
67 06:06:23.704226 progress 75 % (32 MB)
68 06:06:23.732547 progress 80 % (34 MB)
69 06:06:23.760923 progress 85 % (37 MB)
70 06:06:23.789079 progress 90 % (39 MB)
71 06:06:23.816804 progress 95 % (41 MB)
72 06:06:23.844366 progress 100 % (43 MB)
73 06:06:23.844903 43 MB downloaded in 0.62 s (70.61 MB/s)
74 06:06:23.845379 end: 1.2.1 http-download (duration 00:00:01) [common]
76 06:06:23.846195 end: 1.2 download-retry (duration 00:00:01) [common]
77 06:06:23.846470 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:06:23.846738 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:06:23.847239 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 06:06:23.847516 saving as /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/dtb/meson-g12b-a311d-libretech-cc.dtb
81 06:06:23.847726 total size: 54703 (0 MB)
82 06:06:23.847937 No compression specified
83 06:06:23.889516 progress 59 % (0 MB)
84 06:06:23.890804 progress 100 % (0 MB)
85 06:06:23.892175 0 MB downloaded in 0.04 s (1.17 MB/s)
86 06:06:23.892700 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:06:23.893536 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:06:23.893810 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:06:23.894086 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:06:23.894561 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
92 06:06:23.894819 saving as /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/modules/modules.tar
93 06:06:23.895029 total size: 11612736 (11 MB)
94 06:06:23.895353 Using unxz to decompress xz
95 06:06:23.937633 progress 0 % (0 MB)
96 06:06:24.006330 progress 5 % (0 MB)
97 06:06:24.092091 progress 10 % (1 MB)
98 06:06:24.179812 progress 15 % (1 MB)
99 06:06:24.262316 progress 20 % (2 MB)
100 06:06:24.341188 progress 25 % (2 MB)
101 06:06:24.420338 progress 30 % (3 MB)
102 06:06:24.497839 progress 35 % (3 MB)
103 06:06:24.573553 progress 40 % (4 MB)
104 06:06:24.656582 progress 45 % (5 MB)
105 06:06:24.737575 progress 50 % (5 MB)
106 06:06:24.819436 progress 55 % (6 MB)
107 06:06:24.899082 progress 60 % (6 MB)
108 06:06:24.984245 progress 65 % (7 MB)
109 06:06:25.068523 progress 70 % (7 MB)
110 06:06:25.147342 progress 75 % (8 MB)
111 06:06:25.244109 progress 80 % (8 MB)
112 06:06:25.344083 progress 85 % (9 MB)
113 06:06:25.414206 progress 90 % (9 MB)
114 06:06:25.493591 progress 95 % (10 MB)
115 06:06:25.569321 progress 100 % (11 MB)
116 06:06:25.582503 11 MB downloaded in 1.69 s (6.56 MB/s)
117 06:06:25.583231 end: 1.4.1 http-download (duration 00:00:02) [common]
119 06:06:25.584593 end: 1.4 download-retry (duration 00:00:02) [common]
120 06:06:25.585304 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 06:06:25.585977 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 06:06:25.586614 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:06:25.587258 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 06:06:25.588536 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0
125 06:06:25.589621 makedir: /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin
126 06:06:25.590434 makedir: /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/tests
127 06:06:25.591223 makedir: /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/results
128 06:06:25.592032 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-add-keys
129 06:06:25.593267 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-add-sources
130 06:06:25.594516 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-background-process-start
131 06:06:25.595740 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-background-process-stop
132 06:06:25.597158 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-common-functions
133 06:06:25.598385 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-echo-ipv4
134 06:06:25.599567 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-install-packages
135 06:06:25.600784 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-installed-packages
136 06:06:25.601923 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-os-build
137 06:06:25.603061 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-probe-channel
138 06:06:25.604241 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-probe-ip
139 06:06:25.605439 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-target-ip
140 06:06:25.606597 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-target-mac
141 06:06:25.607752 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-target-storage
142 06:06:25.608966 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-test-case
143 06:06:25.610128 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-test-event
144 06:06:25.611265 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-test-feedback
145 06:06:25.612445 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-test-raise
146 06:06:25.613592 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-test-reference
147 06:06:25.614739 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-test-runner
148 06:06:25.615883 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-test-set
149 06:06:25.617130 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-test-shell
150 06:06:25.618320 Updating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-install-packages (oe)
151 06:06:25.619547 Updating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/bin/lava-installed-packages (oe)
152 06:06:25.620446 Creating /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/environment
153 06:06:25.620949 LAVA metadata
154 06:06:25.621287 - LAVA_JOB_ID=784696
155 06:06:25.621559 - LAVA_DISPATCHER_IP=192.168.6.2
156 06:06:25.622015 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 06:06:25.623238 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 06:06:25.623638 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 06:06:25.623895 skipped lava-vland-overlay
160 06:06:25.624245 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 06:06:25.624573 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 06:06:25.624849 skipped lava-multinode-overlay
163 06:06:25.625146 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 06:06:25.625456 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 06:06:25.625771 Loading test definitions
166 06:06:25.626115 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 06:06:25.626393 Using /lava-784696 at stage 0
168 06:06:25.627875 uuid=784696_1.5.2.4.1 testdef=None
169 06:06:25.628291 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 06:06:25.628624 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 06:06:25.630953 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 06:06:25.632008 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 06:06:25.634924 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 06:06:25.636067 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 06:06:25.638916 runner path: /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/0/tests/0_dmesg test_uuid 784696_1.5.2.4.1
178 06:06:25.639672 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 06:06:25.640709 Creating lava-test-runner.conf files
181 06:06:25.640962 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/784696/lava-overlay-eq1yfhy0/lava-784696/0 for stage 0
182 06:06:25.641405 - 0_dmesg
183 06:06:25.641849 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 06:06:25.642196 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 06:06:25.672693 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 06:06:25.673279 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 06:06:25.673661 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 06:06:25.674005 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 06:06:25.674327 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 06:06:26.642330 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 06:06:26.642794 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 06:06:26.643039 extracting modules file /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/784696/extract-overlay-ramdisk-11rdanaz/ramdisk
193 06:06:28.079818 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 06:06:28.080324 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 06:06:28.080604 [common] Applying overlay /var/lib/lava/dispatcher/tmp/784696/compress-overlay-ffabpcga/overlay-1.5.2.5.tar.gz to ramdisk
196 06:06:28.080817 [common] Applying overlay /var/lib/lava/dispatcher/tmp/784696/compress-overlay-ffabpcga/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/784696/extract-overlay-ramdisk-11rdanaz/ramdisk
197 06:06:28.111495 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 06:06:28.111946 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 06:06:28.112401 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 06:06:28.112640 Converting downloaded kernel to a uImage
201 06:06:28.112952 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/kernel/Image /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/kernel/uImage
202 06:06:28.584033 output: Image Name:
203 06:06:28.584456 output: Created: Tue Oct 1 06:06:28 2024
204 06:06:28.584667 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 06:06:28.584872 output: Data Size: 45779456 Bytes = 44706.50 KiB = 43.66 MiB
206 06:06:28.585073 output: Load Address: 01080000
207 06:06:28.585272 output: Entry Point: 01080000
208 06:06:28.585471 output:
209 06:06:28.585802 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 06:06:28.586067 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 06:06:28.586336 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 06:06:28.586590 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 06:06:28.586847 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 06:06:28.587103 Building ramdisk /var/lib/lava/dispatcher/tmp/784696/extract-overlay-ramdisk-11rdanaz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/784696/extract-overlay-ramdisk-11rdanaz/ramdisk
215 06:06:31.168321 >> 181682 blocks
216 06:06:39.830239 Adding RAMdisk u-boot header.
217 06:06:39.830793 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/784696/extract-overlay-ramdisk-11rdanaz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/784696/extract-overlay-ramdisk-11rdanaz/ramdisk.cpio.gz.uboot
218 06:06:40.103778 output: Image Name:
219 06:06:40.104346 output: Created: Tue Oct 1 06:06:39 2024
220 06:06:40.104812 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 06:06:40.105260 output: Data Size: 26067471 Bytes = 25456.51 KiB = 24.86 MiB
222 06:06:40.105704 output: Load Address: 00000000
223 06:06:40.106142 output: Entry Point: 00000000
224 06:06:40.106574 output:
225 06:06:40.107590 rename /var/lib/lava/dispatcher/tmp/784696/extract-overlay-ramdisk-11rdanaz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/ramdisk/ramdisk.cpio.gz.uboot
226 06:06:40.108393 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 06:06:40.108986 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 06:06:40.109559 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 06:06:40.110058 No LXC device requested
230 06:06:40.110606 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 06:06:40.111159 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 06:06:40.111701 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 06:06:40.112195 Checking files for TFTP limit of 4294967296 bytes.
234 06:06:40.115103 end: 1 tftp-deploy (duration 00:00:17) [common]
235 06:06:40.115724 start: 2 uboot-action (timeout 00:05:00) [common]
236 06:06:40.116337 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 06:06:40.116889 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 06:06:40.117439 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 06:06:40.118013 Using kernel file from prepare-kernel: 784696/tftp-deploy-aih6j91n/kernel/uImage
240 06:06:40.118694 substitutions:
241 06:06:40.119149 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 06:06:40.119591 - {DTB_ADDR}: 0x01070000
243 06:06:40.120100 - {DTB}: 784696/tftp-deploy-aih6j91n/dtb/meson-g12b-a311d-libretech-cc.dtb
244 06:06:40.120554 - {INITRD}: 784696/tftp-deploy-aih6j91n/ramdisk/ramdisk.cpio.gz.uboot
245 06:06:40.120995 - {KERNEL_ADDR}: 0x01080000
246 06:06:40.121428 - {KERNEL}: 784696/tftp-deploy-aih6j91n/kernel/uImage
247 06:06:40.121866 - {LAVA_MAC}: None
248 06:06:40.122368 - {PRESEED_CONFIG}: None
249 06:06:40.122812 - {PRESEED_LOCAL}: None
250 06:06:40.123243 - {RAMDISK_ADDR}: 0x08000000
251 06:06:40.123683 - {RAMDISK}: 784696/tftp-deploy-aih6j91n/ramdisk/ramdisk.cpio.gz.uboot
252 06:06:40.124157 - {ROOT_PART}: None
253 06:06:40.124598 - {ROOT}: None
254 06:06:40.125028 - {SERVER_IP}: 192.168.6.2
255 06:06:40.125462 - {TEE_ADDR}: 0x83000000
256 06:06:40.125891 - {TEE}: None
257 06:06:40.126321 Parsed boot commands:
258 06:06:40.126737 - setenv autoload no
259 06:06:40.127160 - setenv initrd_high 0xffffffff
260 06:06:40.127586 - setenv fdt_high 0xffffffff
261 06:06:40.128032 - dhcp
262 06:06:40.128465 - setenv serverip 192.168.6.2
263 06:06:40.128892 - tftpboot 0x01080000 784696/tftp-deploy-aih6j91n/kernel/uImage
264 06:06:40.129317 - tftpboot 0x08000000 784696/tftp-deploy-aih6j91n/ramdisk/ramdisk.cpio.gz.uboot
265 06:06:40.129745 - tftpboot 0x01070000 784696/tftp-deploy-aih6j91n/dtb/meson-g12b-a311d-libretech-cc.dtb
266 06:06:40.130172 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 06:06:40.130605 - bootm 0x01080000 0x08000000 0x01070000
268 06:06:40.131149 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 06:06:40.132815 start: 2.3 connect-device (timeout 00:05:00) [common]
271 06:06:40.133299 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 06:06:40.148466 Setting prompt string to ['lava-test: # ']
273 06:06:40.150059 end: 2.3 connect-device (duration 00:00:00) [common]
274 06:06:40.150708 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 06:06:40.151301 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 06:06:40.151898 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 06:06:40.153212 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 06:06:40.191320 >> OK - accepted request
279 06:06:40.193658 Returned 0 in 0 seconds
280 06:06:40.294843 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 06:06:40.296616 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 06:06:40.297226 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 06:06:40.297772 Setting prompt string to ['Hit any key to stop autoboot']
285 06:06:40.298266 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 06:06:40.299976 Trying 192.168.56.21...
287 06:06:40.300529 Connected to conserv1.
288 06:06:40.300991 Escape character is '^]'.
289 06:06:40.301449
290 06:06:40.301910 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 06:06:40.302375
292 06:06:52.432633 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 06:06:52.433353 bl2_stage_init 0x01
294 06:06:52.433832 bl2_stage_init 0x81
295 06:06:52.436927 hw id: 0x0000 - pwm id 0x01
296 06:06:52.437513 bl2_stage_init 0xc1
297 06:06:52.437976 bl2_stage_init 0x02
298 06:06:52.438431
299 06:06:52.442689 L0:00000000
300 06:06:52.443227 L1:20000703
301 06:06:52.443670 L2:00008067
302 06:06:52.444151 L3:14000000
303 06:06:52.448082 B2:00402000
304 06:06:52.448593 B1:e0f83180
305 06:06:52.449031
306 06:06:52.449464 TE: 58159
307 06:06:52.449894
308 06:06:52.453670 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 06:06:52.454151
310 06:06:52.454582 Board ID = 1
311 06:06:52.459276 Set A53 clk to 24M
312 06:06:52.459758 Set A73 clk to 24M
313 06:06:52.460226 Set clk81 to 24M
314 06:06:52.464900 A53 clk: 1200 MHz
315 06:06:52.465410 A73 clk: 1200 MHz
316 06:06:52.465845 CLK81: 166.6M
317 06:06:52.466277 smccc: 00012ab5
318 06:06:52.470480 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 06:06:52.476013 board id: 1
320 06:06:52.482017 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 06:06:52.492680 fw parse done
322 06:06:52.498689 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 06:06:52.541207 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 06:06:52.552062 PIEI prepare done
325 06:06:52.552540 fastboot data load
326 06:06:52.552977 fastboot data verify
327 06:06:52.557643 verify result: 266
328 06:06:52.563158 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 06:06:52.563615 LPDDR4 probe
330 06:06:52.564070 ddr clk to 1584MHz
331 06:06:52.571170 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 06:06:52.608554
333 06:06:52.609057 dmc_version 0001
334 06:06:52.615190 Check phy result
335 06:06:52.621000 INFO : End of CA training
336 06:06:52.621472 INFO : End of initialization
337 06:06:52.626577 INFO : Training has run successfully!
338 06:06:52.627043 Check phy result
339 06:06:52.632224 INFO : End of initialization
340 06:06:52.632700 INFO : End of read enable training
341 06:06:52.637845 INFO : End of fine write leveling
342 06:06:52.643395 INFO : End of Write leveling coarse delay
343 06:06:52.643857 INFO : Training has run successfully!
344 06:06:52.644336 Check phy result
345 06:06:52.649035 INFO : End of initialization
346 06:06:52.649499 INFO : End of read dq deskew training
347 06:06:52.654567 INFO : End of MPR read delay center optimization
348 06:06:52.660200 INFO : End of write delay center optimization
349 06:06:52.665840 INFO : End of read delay center optimization
350 06:06:52.666326 INFO : End of max read latency training
351 06:06:52.671391 INFO : Training has run successfully!
352 06:06:52.671856 1D training succeed
353 06:06:52.680665 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 06:06:52.728224 Check phy result
355 06:06:52.728736 INFO : End of initialization
356 06:06:52.749962 INFO : End of 2D read delay Voltage center optimization
357 06:06:52.770261 INFO : End of 2D read delay Voltage center optimization
358 06:06:52.822415 INFO : End of 2D write delay Voltage center optimization
359 06:06:52.871725 INFO : End of 2D write delay Voltage center optimization
360 06:06:52.877210 INFO : Training has run successfully!
361 06:06:52.877681
362 06:06:52.878124 channel==0
363 06:06:52.882979 RxClkDly_Margin_A0==88 ps 9
364 06:06:52.883494 TxDqDly_Margin_A0==98 ps 10
365 06:06:52.886090 RxClkDly_Margin_A1==88 ps 9
366 06:06:52.886551 TxDqDly_Margin_A1==98 ps 10
367 06:06:52.891733 TrainedVREFDQ_A0==74
368 06:06:52.892255 TrainedVREFDQ_A1==75
369 06:06:52.897245 VrefDac_Margin_A0==25
370 06:06:52.897706 DeviceVref_Margin_A0==40
371 06:06:52.898141 VrefDac_Margin_A1==25
372 06:06:52.902918 DeviceVref_Margin_A1==39
373 06:06:52.903391
374 06:06:52.903833
375 06:06:52.904307 channel==1
376 06:06:52.904739 RxClkDly_Margin_A0==98 ps 10
377 06:06:52.908447 TxDqDly_Margin_A0==88 ps 9
378 06:06:52.908914 RxClkDly_Margin_A1==98 ps 10
379 06:06:52.914072 TxDqDly_Margin_A1==88 ps 9
380 06:06:52.914547 TrainedVREFDQ_A0==77
381 06:06:52.914987 TrainedVREFDQ_A1==77
382 06:06:52.919692 VrefDac_Margin_A0==22
383 06:06:52.920233 DeviceVref_Margin_A0==37
384 06:06:52.925265 VrefDac_Margin_A1==22
385 06:06:52.925755 DeviceVref_Margin_A1==37
386 06:06:52.926184
387 06:06:52.931003 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 06:06:52.931468
389 06:06:52.958898 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 06:06:52.964355 2D training succeed
391 06:06:52.969974 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 06:06:52.970436 auto size-- 65535DDR cs0 size: 2048MB
393 06:06:52.975612 DDR cs1 size: 2048MB
394 06:06:52.976112 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 06:06:52.981225 cs0 DataBus test pass
396 06:06:52.981540 cs1 DataBus test pass
397 06:06:52.981777 cs0 AddrBus test pass
398 06:06:52.986923 cs1 AddrBus test pass
399 06:06:52.987203
400 06:06:52.987436 100bdlr_step_size ps== 420
401 06:06:52.987669 result report
402 06:06:52.992361 boot times 0Enable ddr reg access
403 06:06:53.000082 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 06:06:53.013545 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 06:06:53.586730 0.0;M3 CHK:0;cm4_sp_mode 0
406 06:06:53.587389 MVN_1=0x00000000
407 06:06:53.592205 MVN_2=0x00000000
408 06:06:53.597948 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 06:06:53.598460 OPS=0x10
410 06:06:53.598909 ring efuse init
411 06:06:53.599349 chipver efuse init
412 06:06:53.603539 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 06:06:53.609125 [0.018960 Inits done]
414 06:06:53.609628 secure task start!
415 06:06:53.610073 high task start!
416 06:06:53.613771 low task start!
417 06:06:53.614270 run into bl31
418 06:06:53.620369 NOTICE: BL31: v1.3(release):4fc40b1
419 06:06:53.628214 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 06:06:53.628730 NOTICE: BL31: G12A normal boot!
421 06:06:53.653517 NOTICE: BL31: BL33 decompress pass
422 06:06:53.659211 ERROR: Error initializing runtime service opteed_fast
423 06:06:54.892330
424 06:06:54.893011
425 06:06:54.900608 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 06:06:54.901212
427 06:06:54.901687 Model: Libre Computer AML-A311D-CC Alta
428 06:06:55.108986 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 06:06:55.132300 DRAM: 2 GiB (effective 3.8 GiB)
430 06:06:55.275316 Core: 408 devices, 31 uclasses, devicetree: separate
431 06:06:55.281414 WDT: Not starting watchdog@f0d0
432 06:06:55.313501 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 06:06:55.325978 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 06:06:55.330931 ** Bad device specification mmc 0 **
435 06:06:55.341254 Card did not respond to voltage select! : -110
436 06:06:55.348921 ** Bad device specification mmc 0 **
437 06:06:55.349436 Couldn't find partition mmc 0
438 06:06:55.357254 Card did not respond to voltage select! : -110
439 06:06:55.362800 ** Bad device specification mmc 0 **
440 06:06:55.363306 Couldn't find partition mmc 0
441 06:06:55.368165 Error: could not access storage.
442 06:06:56.631856 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 06:06:56.632658 bl2_stage_init 0x01
444 06:06:56.633248 bl2_stage_init 0x81
445 06:06:56.637232 hw id: 0x0000 - pwm id 0x01
446 06:06:56.637887 bl2_stage_init 0xc1
447 06:06:56.638453 bl2_stage_init 0x02
448 06:06:56.638995
449 06:06:56.642747 L0:00000000
450 06:06:56.643371 L1:20000703
451 06:06:56.643929 L2:00008067
452 06:06:56.644525 L3:14000000
453 06:06:56.645628 B2:00402000
454 06:06:56.646214 B1:e0f83180
455 06:06:56.646759
456 06:06:56.647291 TE: 58159
457 06:06:56.647831
458 06:06:56.656811 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 06:06:56.657450
460 06:06:56.658004 Board ID = 1
461 06:06:56.658544 Set A53 clk to 24M
462 06:06:56.659081 Set A73 clk to 24M
463 06:06:56.662476 Set clk81 to 24M
464 06:06:56.663139 A53 clk: 1200 MHz
465 06:06:56.663709 A73 clk: 1200 MHz
466 06:06:56.668191 CLK81: 166.6M
467 06:06:56.668801 smccc: 00012ab5
468 06:06:56.673691 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 06:06:56.674314 board id: 1
470 06:06:56.682301 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 06:06:56.692941 fw parse done
472 06:06:56.698877 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 06:06:56.740584 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 06:06:56.752387 PIEI prepare done
475 06:06:56.753002 fastboot data load
476 06:06:56.753550 fastboot data verify
477 06:06:56.758020 verify result: 266
478 06:06:56.763622 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 06:06:56.764282 LPDDR4 probe
480 06:06:56.764838 ddr clk to 1584MHz
481 06:06:56.771697 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 06:06:56.808967
483 06:06:56.809699 dmc_version 0001
484 06:06:56.815508 Check phy result
485 06:06:56.821410 INFO : End of CA training
486 06:06:56.822038 INFO : End of initialization
487 06:06:56.827009 INFO : Training has run successfully!
488 06:06:56.827616 Check phy result
489 06:06:56.832588 INFO : End of initialization
490 06:06:56.833203 INFO : End of read enable training
491 06:06:56.838174 INFO : End of fine write leveling
492 06:06:56.843766 INFO : End of Write leveling coarse delay
493 06:06:56.844402 INFO : Training has run successfully!
494 06:06:56.844959 Check phy result
495 06:06:56.849405 INFO : End of initialization
496 06:06:56.850002 INFO : End of read dq deskew training
497 06:06:56.854980 INFO : End of MPR read delay center optimization
498 06:06:56.860570 INFO : End of write delay center optimization
499 06:06:56.866226 INFO : End of read delay center optimization
500 06:06:56.866815 INFO : End of max read latency training
501 06:06:56.871773 INFO : Training has run successfully!
502 06:06:56.872460 1D training succeed
503 06:06:56.881009 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 06:06:56.928651 Check phy result
505 06:06:56.929367 INFO : End of initialization
506 06:06:56.950300 INFO : End of 2D read delay Voltage center optimization
507 06:06:56.970449 INFO : End of 2D read delay Voltage center optimization
508 06:06:57.022342 INFO : End of 2D write delay Voltage center optimization
509 06:06:57.071593 INFO : End of 2D write delay Voltage center optimization
510 06:06:57.077029 INFO : Training has run successfully!
511 06:06:57.077701
512 06:06:57.078306 channel==0
513 06:06:57.082631 RxClkDly_Margin_A0==88 ps 9
514 06:06:57.083291 TxDqDly_Margin_A0==98 ps 10
515 06:06:57.088244 RxClkDly_Margin_A1==88 ps 9
516 06:06:57.088883 TxDqDly_Margin_A1==98 ps 10
517 06:06:57.089480 TrainedVREFDQ_A0==74
518 06:06:57.093842 TrainedVREFDQ_A1==75
519 06:06:57.094376 VrefDac_Margin_A0==25
520 06:06:57.094959 DeviceVref_Margin_A0==40
521 06:06:57.099452 VrefDac_Margin_A1==25
522 06:06:57.100126 DeviceVref_Margin_A1==39
523 06:06:57.100679
524 06:06:57.101292
525 06:06:57.105061 channel==1
526 06:06:57.105743 RxClkDly_Margin_A0==98 ps 10
527 06:06:57.106370 TxDqDly_Margin_A0==98 ps 10
528 06:06:57.110655 RxClkDly_Margin_A1==98 ps 10
529 06:06:57.111334 TxDqDly_Margin_A1==88 ps 9
530 06:06:57.116222 TrainedVREFDQ_A0==77
531 06:06:57.116852 TrainedVREFDQ_A1==77
532 06:06:57.117423 VrefDac_Margin_A0==22
533 06:06:57.121890 DeviceVref_Margin_A0==37
534 06:06:57.122557 VrefDac_Margin_A1==24
535 06:06:57.127461 DeviceVref_Margin_A1==37
536 06:06:57.128106
537 06:06:57.128676 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 06:06:57.132988
539 06:06:57.161050 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000019 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
540 06:06:57.161675 2D training succeed
541 06:06:57.166680 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 06:06:57.172274 auto size-- 65535DDR cs0 size: 2048MB
543 06:06:57.172812 DDR cs1 size: 2048MB
544 06:06:57.177853 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 06:06:57.178390 cs0 DataBus test pass
546 06:06:57.183584 cs1 DataBus test pass
547 06:06:57.184161 cs0 AddrBus test pass
548 06:06:57.184621 cs1 AddrBus test pass
549 06:06:57.185076
550 06:06:57.189116 100bdlr_step_size ps== 420
551 06:06:57.189705 result report
552 06:06:57.194798 boot times 0Enable ddr reg access
553 06:06:57.200210 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 06:06:57.213582 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 06:06:57.785643 0.0;M3 CHK:0;cm4_sp_mode 0
556 06:06:57.786292 MVN_1=0x00000000
557 06:06:57.791030 MVN_2=0x00000000
558 06:06:57.796754 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 06:06:57.797304 OPS=0x10
560 06:06:57.797768 ring efuse init
561 06:06:57.798222 chipver efuse init
562 06:06:57.802389 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 06:06:57.807905 [0.018960 Inits done]
564 06:06:57.808512 secure task start!
565 06:06:57.808977 high task start!
566 06:06:57.812555 low task start!
567 06:06:57.813102 run into bl31
568 06:06:57.819141 NOTICE: BL31: v1.3(release):4fc40b1
569 06:06:57.826926 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 06:06:57.827475 NOTICE: BL31: G12A normal boot!
571 06:06:57.852356 NOTICE: BL31: BL33 decompress pass
572 06:06:57.858046 ERROR: Error initializing runtime service opteed_fast
573 06:06:59.090981
574 06:06:59.091566
575 06:06:59.099383 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 06:06:59.099688
577 06:06:59.099907 Model: Libre Computer AML-A311D-CC Alta
578 06:06:59.307818 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 06:06:59.331442 DRAM: 2 GiB (effective 3.8 GiB)
580 06:06:59.474139 Core: 408 devices, 31 uclasses, devicetree: separate
581 06:06:59.480098 WDT: Not starting watchdog@f0d0
582 06:06:59.512401 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 06:06:59.525408 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 06:06:59.529888 ** Bad device specification mmc 0 **
585 06:06:59.540144 Card did not respond to voltage select! : -110
586 06:06:59.547756 ** Bad device specification mmc 0 **
587 06:06:59.548340 Couldn't find partition mmc 0
588 06:06:59.556253 Card did not respond to voltage select! : -110
589 06:06:59.561591 ** Bad device specification mmc 0 **
590 06:06:59.562150 Couldn't find partition mmc 0
591 06:06:59.566710 Error: could not access storage.
592 06:06:59.909230 Net: eth0: ethernet@ff3f0000
593 06:06:59.909871 starting USB...
594 06:07:00.160981 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 06:07:00.161604 Starting the controller
596 06:07:00.167847 USB XHCI 1.10
597 06:07:01.881479 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 06:07:01.882159 bl2_stage_init 0x01
599 06:07:01.882638 bl2_stage_init 0x81
600 06:07:01.887253 hw id: 0x0000 - pwm id 0x01
601 06:07:01.887760 bl2_stage_init 0xc1
602 06:07:01.888275 bl2_stage_init 0x02
603 06:07:01.888734
604 06:07:01.892670 L0:00000000
605 06:07:01.893164 L1:20000703
606 06:07:01.893621 L2:00008067
607 06:07:01.894067 L3:14000000
608 06:07:01.895830 B2:00402000
609 06:07:01.896352 B1:e0f83180
610 06:07:01.896803
611 06:07:01.897251 TE: 58124
612 06:07:01.897701
613 06:07:01.906184 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 06:07:01.906695
615 06:07:01.907149 Board ID = 1
616 06:07:01.907595 Set A53 clk to 24M
617 06:07:01.908075 Set A73 clk to 24M
618 06:07:01.912026 Set clk81 to 24M
619 06:07:01.912517 A53 clk: 1200 MHz
620 06:07:01.912968 A73 clk: 1200 MHz
621 06:07:01.917360 CLK81: 166.6M
622 06:07:01.917846 smccc: 00012a92
623 06:07:01.923131 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 06:07:01.923631 board id: 1
625 06:07:01.931612 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 06:07:01.942983 fw parse done
627 06:07:01.948755 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 06:07:01.990846 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 06:07:02.001739 PIEI prepare done
630 06:07:02.002248 fastboot data load
631 06:07:02.002704 fastboot data verify
632 06:07:02.007410 verify result: 266
633 06:07:02.012910 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 06:07:02.013407 LPDDR4 probe
635 06:07:02.013855 ddr clk to 1584MHz
636 06:07:02.020881 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 06:07:02.058193
638 06:07:02.058722 dmc_version 0001
639 06:07:02.064295 Check phy result
640 06:07:02.070156 INFO : End of CA training
641 06:07:02.070644 INFO : End of initialization
642 06:07:02.075705 INFO : Training has run successfully!
643 06:07:02.076240 Check phy result
644 06:07:02.082183 INFO : End of initialization
645 06:07:02.082673 INFO : End of read enable training
646 06:07:02.087184 INFO : End of fine write leveling
647 06:07:02.093272 INFO : End of Write leveling coarse delay
648 06:07:02.093766 INFO : Training has run successfully!
649 06:07:02.094216 Check phy result
650 06:07:02.099345 INFO : End of initialization
651 06:07:02.099821 INFO : End of read dq deskew training
652 06:07:02.105204 INFO : End of MPR read delay center optimization
653 06:07:02.110080 INFO : End of write delay center optimization
654 06:07:02.115975 INFO : End of read delay center optimization
655 06:07:02.116494 INFO : End of max read latency training
656 06:07:02.121853 INFO : Training has run successfully!
657 06:07:02.122337 1D training succeed
658 06:07:02.130578 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 06:07:02.177994 Check phy result
660 06:07:02.178536 INFO : End of initialization
661 06:07:02.199605 INFO : End of 2D read delay Voltage center optimization
662 06:07:02.219741 INFO : End of 2D read delay Voltage center optimization
663 06:07:02.271685 INFO : End of 2D write delay Voltage center optimization
664 06:07:02.320311 INFO : End of 2D write delay Voltage center optimization
665 06:07:02.325867 INFO : Training has run successfully!
666 06:07:02.326352
667 06:07:02.326805 channel==0
668 06:07:02.331437 RxClkDly_Margin_A0==88 ps 9
669 06:07:02.331924 TxDqDly_Margin_A0==98 ps 10
670 06:07:02.337020 RxClkDly_Margin_A1==88 ps 9
671 06:07:02.337511 TxDqDly_Margin_A1==98 ps 10
672 06:07:02.337974 TrainedVREFDQ_A0==74
673 06:07:02.342653 TrainedVREFDQ_A1==74
674 06:07:02.343158 VrefDac_Margin_A0==25
675 06:07:02.343606 DeviceVref_Margin_A0==40
676 06:07:02.348259 VrefDac_Margin_A1==25
677 06:07:02.348752 DeviceVref_Margin_A1==40
678 06:07:02.349198
679 06:07:02.349639
680 06:07:02.353800 channel==1
681 06:07:02.354289 RxClkDly_Margin_A0==98 ps 10
682 06:07:02.354739 TxDqDly_Margin_A0==98 ps 10
683 06:07:02.359394 RxClkDly_Margin_A1==98 ps 10
684 06:07:02.359884 TxDqDly_Margin_A1==88 ps 9
685 06:07:02.365011 TrainedVREFDQ_A0==77
686 06:07:02.365496 TrainedVREFDQ_A1==77
687 06:07:02.365946 VrefDac_Margin_A0==22
688 06:07:02.370689 DeviceVref_Margin_A0==37
689 06:07:02.371174 VrefDac_Margin_A1==24
690 06:07:02.376336 DeviceVref_Margin_A1==37
691 06:07:02.376821
692 06:07:02.377273 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 06:07:02.381837
694 06:07:02.409781 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
695 06:07:02.410344 2D training succeed
696 06:07:02.415408 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 06:07:02.420895 auto size-- 65535DDR cs0 size: 2048MB
698 06:07:02.421384 DDR cs1 size: 2048MB
699 06:07:02.426476 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 06:07:02.426964 cs0 DataBus test pass
701 06:07:02.432170 cs1 DataBus test pass
702 06:07:02.432657 cs0 AddrBus test pass
703 06:07:02.433107 cs1 AddrBus test pass
704 06:07:02.433545
705 06:07:02.437701 100bdlr_step_size ps== 420
706 06:07:02.438196 result report
707 06:07:02.443233 boot times 0Enable ddr reg access
708 06:07:02.448669 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 06:07:02.462194 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 06:07:03.034372 0.0;M3 CHK:0;cm4_sp_mode 0
711 06:07:03.035038 MVN_1=0x00000000
712 06:07:03.039667 MVN_2=0x00000000
713 06:07:03.045457 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 06:07:03.046018 OPS=0x10
715 06:07:03.046463 ring efuse init
716 06:07:03.046893 chipver efuse init
717 06:07:03.051006 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 06:07:03.057045 [0.018961 Inits done]
719 06:07:03.057523 secure task start!
720 06:07:03.057959 high task start!
721 06:07:03.061254 low task start!
722 06:07:03.061723 run into bl31
723 06:07:03.067848 NOTICE: BL31: v1.3(release):4fc40b1
724 06:07:03.075694 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 06:07:03.076290 NOTICE: BL31: G12A normal boot!
726 06:07:03.101049 NOTICE: BL31: BL33 decompress pass
727 06:07:03.106712 ERROR: Error initializing runtime service opteed_fast
728 06:07:04.339618
729 06:07:04.340295
730 06:07:04.348022 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 06:07:04.348524
732 06:07:04.348990 Model: Libre Computer AML-A311D-CC Alta
733 06:07:04.556583 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 06:07:04.579813 DRAM: 2 GiB (effective 3.8 GiB)
735 06:07:04.722754 Core: 408 devices, 31 uclasses, devicetree: separate
736 06:07:04.728756 WDT: Not starting watchdog@f0d0
737 06:07:04.760975 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 06:07:04.773475 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 06:07:04.778557 ** Bad device specification mmc 0 **
740 06:07:04.788747 Card did not respond to voltage select! : -110
741 06:07:04.796390 ** Bad device specification mmc 0 **
742 06:07:04.796869 Couldn't find partition mmc 0
743 06:07:04.805012 Card did not respond to voltage select! : -110
744 06:07:04.810267 ** Bad device specification mmc 0 **
745 06:07:04.810737 Couldn't find partition mmc 0
746 06:07:04.815356 Error: could not access storage.
747 06:07:05.158800 Net: eth0: ethernet@ff3f0000
748 06:07:05.159330 starting USB...
749 06:07:05.410619 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 06:07:05.411135 Starting the controller
751 06:07:05.417662 USB XHCI 1.10
752 06:07:07.580771 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 06:07:07.581379 bl2_stage_init 0x01
754 06:07:07.581839 bl2_stage_init 0x81
755 06:07:07.586307 hw id: 0x0000 - pwm id 0x01
756 06:07:07.586789 bl2_stage_init 0xc1
757 06:07:07.587245 bl2_stage_init 0x02
758 06:07:07.587716
759 06:07:07.592017 L0:00000000
760 06:07:07.592501 L1:20000703
761 06:07:07.592948 L2:00008067
762 06:07:07.593390 L3:14000000
763 06:07:07.597515 B2:00402000
764 06:07:07.597987 B1:e0f83180
765 06:07:07.598434
766 06:07:07.598878 TE: 58124
767 06:07:07.599322
768 06:07:07.603083 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 06:07:07.603567
770 06:07:07.604041 Board ID = 1
771 06:07:07.608676 Set A53 clk to 24M
772 06:07:07.609152 Set A73 clk to 24M
773 06:07:07.609596 Set clk81 to 24M
774 06:07:07.614214 A53 clk: 1200 MHz
775 06:07:07.614683 A73 clk: 1200 MHz
776 06:07:07.615124 CLK81: 166.6M
777 06:07:07.615563 smccc: 00012a92
778 06:07:07.619897 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 06:07:07.625453 board id: 1
780 06:07:07.631341 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 06:07:07.641924 fw parse done
782 06:07:07.648072 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 06:07:07.690618 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 06:07:07.701478 PIEI prepare done
785 06:07:07.701957 fastboot data load
786 06:07:07.702414 fastboot data verify
787 06:07:07.707058 verify result: 266
788 06:07:07.712690 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 06:07:07.713161 LPDDR4 probe
790 06:07:07.713605 ddr clk to 1584MHz
791 06:07:07.720608 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 06:07:07.757841
793 06:07:07.758314 dmc_version 0001
794 06:07:07.764547 Check phy result
795 06:07:07.770419 INFO : End of CA training
796 06:07:07.770891 INFO : End of initialization
797 06:07:07.776054 INFO : Training has run successfully!
798 06:07:07.776529 Check phy result
799 06:07:07.781597 INFO : End of initialization
800 06:07:07.782064 INFO : End of read enable training
801 06:07:07.784954 INFO : End of fine write leveling
802 06:07:07.790562 INFO : End of Write leveling coarse delay
803 06:07:07.796175 INFO : Training has run successfully!
804 06:07:07.796677 Check phy result
805 06:07:07.797138 INFO : End of initialization
806 06:07:07.801754 INFO : End of read dq deskew training
807 06:07:07.805111 INFO : End of MPR read delay center optimization
808 06:07:07.810750 INFO : End of write delay center optimization
809 06:07:07.816297 INFO : End of read delay center optimization
810 06:07:07.816777 INFO : End of max read latency training
811 06:07:07.822174 INFO : Training has run successfully!
812 06:07:07.822646 1D training succeed
813 06:07:07.830101 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 06:07:07.877585 Check phy result
815 06:07:07.878054 INFO : End of initialization
816 06:07:07.899340 INFO : End of 2D read delay Voltage center optimization
817 06:07:07.919674 INFO : End of 2D read delay Voltage center optimization
818 06:07:07.971671 INFO : End of 2D write delay Voltage center optimization
819 06:07:08.021035 INFO : End of 2D write delay Voltage center optimization
820 06:07:08.026527 INFO : Training has run successfully!
821 06:07:08.027003
822 06:07:08.027454 channel==0
823 06:07:08.032226 RxClkDly_Margin_A0==88 ps 9
824 06:07:08.032717 TxDqDly_Margin_A0==98 ps 10
825 06:07:08.037866 RxClkDly_Margin_A1==88 ps 9
826 06:07:08.038335 TxDqDly_Margin_A1==88 ps 9
827 06:07:08.038803 TrainedVREFDQ_A0==74
828 06:07:08.043361 TrainedVREFDQ_A1==74
829 06:07:08.043877 VrefDac_Margin_A0==25
830 06:07:08.044400 DeviceVref_Margin_A0==40
831 06:07:08.049054 VrefDac_Margin_A1==25
832 06:07:08.049557 DeviceVref_Margin_A1==40
833 06:07:08.049989
834 06:07:08.050414
835 06:07:08.050844 channel==1
836 06:07:08.054641 RxClkDly_Margin_A0==98 ps 10
837 06:07:08.055108 TxDqDly_Margin_A0==88 ps 9
838 06:07:08.060344 RxClkDly_Margin_A1==98 ps 10
839 06:07:08.060799 TxDqDly_Margin_A1==88 ps 9
840 06:07:08.065825 TrainedVREFDQ_A0==77
841 06:07:08.066285 TrainedVREFDQ_A1==77
842 06:07:08.066717 VrefDac_Margin_A0==22
843 06:07:08.071414 DeviceVref_Margin_A0==37
844 06:07:08.071874 VrefDac_Margin_A1==24
845 06:07:08.077042 DeviceVref_Margin_A1==37
846 06:07:08.077498
847 06:07:08.077928 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 06:07:08.078353
849 06:07:08.110642 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
850 06:07:08.111139 2D training succeed
851 06:07:08.116236 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 06:07:08.121677 auto size-- 65535DDR cs0 size: 2048MB
853 06:07:08.122133 DDR cs1 size: 2048MB
854 06:07:08.127294 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 06:07:08.127753 cs0 DataBus test pass
856 06:07:08.132931 cs1 DataBus test pass
857 06:07:08.133389 cs0 AddrBus test pass
858 06:07:08.133818 cs1 AddrBus test pass
859 06:07:08.134239
860 06:07:08.138485 100bdlr_step_size ps== 420
861 06:07:08.138952 result report
862 06:07:08.144082 boot times 0Enable ddr reg access
863 06:07:08.149367 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 06:07:08.162836 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 06:07:08.736497 0.0;M3 CHK:0;cm4_sp_mode 0
866 06:07:08.737039 MVN_1=0x00000000
867 06:07:08.741998 MVN_2=0x00000000
868 06:07:08.747746 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 06:07:08.748294 OPS=0x10
870 06:07:08.748757 ring efuse init
871 06:07:08.749204 chipver efuse init
872 06:07:08.753357 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 06:07:08.758954 [0.018961 Inits done]
874 06:07:08.759422 secure task start!
875 06:07:08.759864 high task start!
876 06:07:08.763523 low task start!
877 06:07:08.764020 run into bl31
878 06:07:08.770208 NOTICE: BL31: v1.3(release):4fc40b1
879 06:07:08.778029 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 06:07:08.778507 NOTICE: BL31: G12A normal boot!
881 06:07:08.803598 NOTICE: BL31: BL33 decompress pass
882 06:07:08.809080 ERROR: Error initializing runtime service opteed_fast
883 06:07:10.042007
884 06:07:10.042579
885 06:07:10.050343 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 06:07:10.050824
887 06:07:10.051273 Model: Libre Computer AML-A311D-CC Alta
888 06:07:10.258728 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 06:07:10.282252 DRAM: 2 GiB (effective 3.8 GiB)
890 06:07:10.425244 Core: 408 devices, 31 uclasses, devicetree: separate
891 06:07:10.431052 WDT: Not starting watchdog@f0d0
892 06:07:10.463274 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 06:07:10.475752 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 06:07:10.480702 ** Bad device specification mmc 0 **
895 06:07:10.491188 Card did not respond to voltage select! : -110
896 06:07:10.498713 ** Bad device specification mmc 0 **
897 06:07:10.499191 Couldn't find partition mmc 0
898 06:07:10.507214 Card did not respond to voltage select! : -110
899 06:07:10.512563 ** Bad device specification mmc 0 **
900 06:07:10.513041 Couldn't find partition mmc 0
901 06:07:10.517641 Error: could not access storage.
902 06:07:10.860203 Net: eth0: ethernet@ff3f0000
903 06:07:10.860759 starting USB...
904 06:07:11.111931 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 06:07:11.112564 Starting the controller
906 06:07:11.118867 USB XHCI 1.10
907 06:07:12.672923 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 06:07:12.681171 scanning usb for storage devices... 0 Storage Device(s) found
910 06:07:12.732732 Hit any key to stop autoboot: 1
911 06:07:12.733572 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 06:07:12.734210 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
913 06:07:12.734728 Setting prompt string to ['=>']
914 06:07:12.735250 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
915 06:07:12.748732 0
916 06:07:12.749665 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 06:07:12.750204 Sending with 10 millisecond of delay
919 06:07:13.884916 => setenv autoload no
920 06:07:13.895696 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
921 06:07:13.901100 setenv autoload no
922 06:07:13.901868 Sending with 10 millisecond of delay
924 06:07:15.698916 => setenv initrd_high 0xffffffff
925 06:07:15.709713 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
926 06:07:15.710586 setenv initrd_high 0xffffffff
927 06:07:15.711352 Sending with 10 millisecond of delay
929 06:07:17.327780 => setenv fdt_high 0xffffffff
930 06:07:17.338605 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 06:07:17.339455 setenv fdt_high 0xffffffff
932 06:07:17.340216 Sending with 10 millisecond of delay
934 06:07:17.632072 => dhcp
935 06:07:17.642706 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
936 06:07:17.643499 dhcp
937 06:07:17.643970 Speed: 1000, full duplex
938 06:07:17.644472 BOOTP broadcast 1
939 06:07:17.890640 BOOTP broadcast 2
940 06:07:17.963066 DHCP client bound to address 192.168.6.33 (320 ms)
941 06:07:17.963826 Sending with 10 millisecond of delay
943 06:07:19.640227 => setenv serverip 192.168.6.2
944 06:07:19.651092 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
945 06:07:19.652214 setenv serverip 192.168.6.2
946 06:07:19.652977 Sending with 10 millisecond of delay
948 06:07:23.377077 => tftpboot 0x01080000 784696/tftp-deploy-aih6j91n/kernel/uImage
949 06:07:23.387923 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
950 06:07:23.388881 tftpboot 0x01080000 784696/tftp-deploy-aih6j91n/kernel/uImage
951 06:07:23.389388 Speed: 1000, full duplex
952 06:07:23.389846 Using ethernet@ff3f0000 device
953 06:07:23.390821 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
954 06:07:23.396317 Filename '784696/tftp-deploy-aih6j91n/kernel/uImage'.
955 06:07:23.400166 Load address: 0x1080000
956 06:07:27.495666 Loading: *################################################## 43.7 MiB
957 06:07:27.496423 10.7 MiB/s
958 06:07:27.496830 done
959 06:07:27.500159 Bytes transferred = 45779520 (2ba8a40 hex)
960 06:07:27.500864 Sending with 10 millisecond of delay
962 06:07:32.187648 => tftpboot 0x08000000 784696/tftp-deploy-aih6j91n/ramdisk/ramdisk.cpio.gz.uboot
963 06:07:32.198406 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:08)
964 06:07:32.198949 tftpboot 0x08000000 784696/tftp-deploy-aih6j91n/ramdisk/ramdisk.cpio.gz.uboot
965 06:07:32.199210 Speed: 1000, full duplex
966 06:07:32.199438 Using ethernet@ff3f0000 device
967 06:07:32.200973 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
968 06:07:32.212863 Filename '784696/tftp-deploy-aih6j91n/ramdisk/ramdisk.cpio.gz.uboot'.
969 06:07:32.213202 Load address: 0x8000000
970 06:07:34.755150 Loading: *################################################# UDP wrong checksum 00000005 000029ec
971 06:07:49.759037 T T T UDP wrong checksum 00000005 000029ec
972 06:08:09.763130 T T T T UDP wrong checksum 00000005 000029ec
973 06:08:24.823349 T T T UDP wrong checksum 000000ff 00000773
974 06:08:24.853913 UDP wrong checksum 000000ff 00008e65
975 06:08:29.768240
976 06:08:29.769045 Retry count exceeded; starting again
978 06:08:29.770811 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
981 06:08:29.773247 end: 2.4 uboot-commands (duration 00:01:50) [common]
983 06:08:29.774986 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
985 06:08:29.776370 end: 2 uboot-action (duration 00:01:50) [common]
987 06:08:29.778398 Cleaning after the job
988 06:08:29.779133 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/ramdisk
989 06:08:29.780789 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/kernel
990 06:08:29.828408 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/dtb
991 06:08:29.829574 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784696/tftp-deploy-aih6j91n/modules
992 06:08:29.855139 start: 4.1 power-off (timeout 00:00:30) [common]
993 06:08:29.855930 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
994 06:08:29.891534 >> OK - accepted request
995 06:08:29.893687 Returned 0 in 0 seconds
996 06:08:29.994752 end: 4.1 power-off (duration 00:00:00) [common]
998 06:08:29.995819 start: 4.2 read-feedback (timeout 00:10:00) [common]
999 06:08:29.996584 Listened to connection for namespace 'common' for up to 1s
1000 06:08:30.996935 Finalising connection for namespace 'common'
1001 06:08:30.997659 Disconnecting from shell: Finalise
1002 06:08:30.998188 =>
1003 06:08:31.099173 end: 4.2 read-feedback (duration 00:00:01) [common]
1004 06:08:31.099895 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/784696
1005 06:08:31.418683 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/784696
1006 06:08:31.419263 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.