Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:42:43.015945 lava-dispatcher, installed at version: 2024.01
2 06:42:43.016764 start: 0 validate
3 06:42:43.017233 Start time: 2024-10-01 06:42:43.017203+00:00 (UTC)
4 06:42:43.017814 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:42:43.018362 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 06:42:43.060820 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:42:43.061363 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:42:44.105721 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:42:44.106369 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 06:42:52.192188 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:42:52.192737 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 06:42:53.257885 validate duration: 10.24
14 06:42:53.259516 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:42:53.259868 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:42:53.260204 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:42:53.261041 Not decompressing ramdisk as can be used compressed.
18 06:42:53.261863 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 06:42:53.262403 saving as /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/ramdisk/rootfs.cpio.gz
20 06:42:53.262969 total size: 8181887 (7 MB)
21 06:42:53.306023 progress 0 % (0 MB)
22 06:42:53.318554 progress 5 % (0 MB)
23 06:42:53.324811 progress 10 % (0 MB)
24 06:42:53.336554 progress 15 % (1 MB)
25 06:42:53.342315 progress 20 % (1 MB)
26 06:42:53.348120 progress 25 % (1 MB)
27 06:42:53.353487 progress 30 % (2 MB)
28 06:42:53.359235 progress 35 % (2 MB)
29 06:42:53.364610 progress 40 % (3 MB)
30 06:42:53.370381 progress 45 % (3 MB)
31 06:42:53.375805 progress 50 % (3 MB)
32 06:42:53.381537 progress 55 % (4 MB)
33 06:42:53.386927 progress 60 % (4 MB)
34 06:42:53.392724 progress 65 % (5 MB)
35 06:42:53.398116 progress 70 % (5 MB)
36 06:42:53.404061 progress 75 % (5 MB)
37 06:42:53.409414 progress 80 % (6 MB)
38 06:42:53.415172 progress 85 % (6 MB)
39 06:42:53.420503 progress 90 % (7 MB)
40 06:42:53.426230 progress 95 % (7 MB)
41 06:42:53.431266 progress 100 % (7 MB)
42 06:42:53.431949 7 MB downloaded in 0.17 s (46.18 MB/s)
43 06:42:53.432551 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:42:53.433520 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:42:53.433843 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:42:53.434128 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:42:53.434625 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig/gcc-12/kernel/Image
49 06:42:53.434875 saving as /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/kernel/Image
50 06:42:53.435094 total size: 45779456 (43 MB)
51 06:42:53.435315 No compression specified
52 06:42:53.467040 progress 0 % (0 MB)
53 06:42:53.496181 progress 5 % (2 MB)
54 06:42:53.525362 progress 10 % (4 MB)
55 06:42:53.554649 progress 15 % (6 MB)
56 06:42:53.584510 progress 20 % (8 MB)
57 06:42:53.613714 progress 25 % (10 MB)
58 06:42:53.643619 progress 30 % (13 MB)
59 06:42:53.672723 progress 35 % (15 MB)
60 06:42:53.702345 progress 40 % (17 MB)
61 06:42:53.731842 progress 45 % (19 MB)
62 06:42:53.761062 progress 50 % (21 MB)
63 06:42:53.790490 progress 55 % (24 MB)
64 06:42:53.820010 progress 60 % (26 MB)
65 06:42:53.849597 progress 65 % (28 MB)
66 06:42:53.878883 progress 70 % (30 MB)
67 06:42:53.908666 progress 75 % (32 MB)
68 06:42:53.939176 progress 80 % (34 MB)
69 06:42:53.968715 progress 85 % (37 MB)
70 06:42:53.998747 progress 90 % (39 MB)
71 06:42:54.028554 progress 95 % (41 MB)
72 06:42:54.057514 progress 100 % (43 MB)
73 06:42:54.058074 43 MB downloaded in 0.62 s (70.08 MB/s)
74 06:42:54.058557 end: 1.2.1 http-download (duration 00:00:01) [common]
76 06:42:54.059372 end: 1.2 download-retry (duration 00:00:01) [common]
77 06:42:54.059645 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:42:54.059911 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:42:54.060430 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 06:42:54.060675 saving as /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 06:42:54.060880 total size: 53209 (0 MB)
82 06:42:54.061089 No compression specified
83 06:42:54.099464 progress 61 % (0 MB)
84 06:42:54.100409 progress 100 % (0 MB)
85 06:42:54.101026 0 MB downloaded in 0.04 s (1.26 MB/s)
86 06:42:54.101569 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:42:54.102526 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:42:54.102858 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:42:54.103185 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:42:54.103726 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig/gcc-12/modules.tar.xz
92 06:42:54.104039 saving as /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/modules/modules.tar
93 06:42:54.104295 total size: 11621212 (11 MB)
94 06:42:54.104554 Using unxz to decompress xz
95 06:42:54.148796 progress 0 % (0 MB)
96 06:42:54.262542 progress 5 % (0 MB)
97 06:42:54.345125 progress 10 % (1 MB)
98 06:42:54.434280 progress 15 % (1 MB)
99 06:42:54.513571 progress 20 % (2 MB)
100 06:42:54.599064 progress 25 % (2 MB)
101 06:42:54.680352 progress 30 % (3 MB)
102 06:42:54.761469 progress 35 % (3 MB)
103 06:42:54.837846 progress 40 % (4 MB)
104 06:42:54.916433 progress 45 % (5 MB)
105 06:42:54.996126 progress 50 % (5 MB)
106 06:42:55.077995 progress 55 % (6 MB)
107 06:42:55.161137 progress 60 % (6 MB)
108 06:42:55.251268 progress 65 % (7 MB)
109 06:42:55.334042 progress 70 % (7 MB)
110 06:42:55.427321 progress 75 % (8 MB)
111 06:42:55.523304 progress 80 % (8 MB)
112 06:42:55.605535 progress 85 % (9 MB)
113 06:42:55.690568 progress 90 % (10 MB)
114 06:42:55.766702 progress 95 % (10 MB)
115 06:42:55.846292 progress 100 % (11 MB)
116 06:42:55.858889 11 MB downloaded in 1.75 s (6.32 MB/s)
117 06:42:55.859551 end: 1.4.1 http-download (duration 00:00:02) [common]
119 06:42:55.860479 end: 1.4 download-retry (duration 00:00:02) [common]
120 06:42:55.860784 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 06:42:55.861075 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 06:42:55.861349 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:42:55.861629 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 06:42:55.862260 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw
125 06:42:55.862751 makedir: /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin
126 06:42:55.863134 makedir: /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/tests
127 06:42:55.863501 makedir: /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/results
128 06:42:55.863885 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-add-keys
129 06:42:55.864504 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-add-sources
130 06:42:55.865071 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-background-process-start
131 06:42:55.865663 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-background-process-stop
132 06:42:55.866284 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-common-functions
133 06:42:55.866861 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-echo-ipv4
134 06:42:55.867458 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-install-packages
135 06:42:55.868048 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-installed-packages
136 06:42:55.868615 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-os-build
137 06:42:55.869192 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-probe-channel
138 06:42:55.869763 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-probe-ip
139 06:42:55.870341 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-target-ip
140 06:42:55.870890 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-target-mac
141 06:42:55.871441 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-target-storage
142 06:42:55.872045 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-test-case
143 06:42:55.872619 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-test-event
144 06:42:55.873165 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-test-feedback
145 06:42:55.873772 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-test-raise
146 06:42:55.874866 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-test-reference
147 06:42:55.875522 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-test-runner
148 06:42:55.876278 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-test-set
149 06:42:55.876876 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-test-shell
150 06:42:55.877464 Updating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-install-packages (oe)
151 06:42:55.878080 Updating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/bin/lava-installed-packages (oe)
152 06:42:55.878698 Creating /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/environment
153 06:42:55.879170 LAVA metadata
154 06:42:55.879470 - LAVA_JOB_ID=784917
155 06:42:55.879725 - LAVA_DISPATCHER_IP=192.168.6.2
156 06:42:55.880166 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 06:42:55.881389 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 06:42:55.881790 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 06:42:55.882044 skipped lava-vland-overlay
160 06:42:55.882330 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 06:42:55.882653 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 06:42:55.882970 skipped lava-multinode-overlay
163 06:42:55.883343 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 06:42:55.883664 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 06:42:55.883961 Loading test definitions
166 06:42:55.884309 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 06:42:55.884547 Using /lava-784917 at stage 0
168 06:42:55.885864 uuid=784917_1.5.2.4.1 testdef=None
169 06:42:55.886212 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 06:42:55.886495 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 06:42:55.888597 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 06:42:55.889519 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 06:42:55.892122 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 06:42:55.893053 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 06:42:55.895455 runner path: /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/0/tests/0_dmesg test_uuid 784917_1.5.2.4.1
178 06:42:55.896117 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 06:42:55.896928 Creating lava-test-runner.conf files
181 06:42:55.897134 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/784917/lava-overlay-8zuqi8lw/lava-784917/0 for stage 0
182 06:42:55.897489 - 0_dmesg
183 06:42:55.897856 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 06:42:55.898144 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 06:42:55.943727 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 06:42:55.944358 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 06:42:55.944788 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 06:42:55.945144 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 06:42:55.945477 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 06:42:56.862578 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 06:42:56.863054 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 06:42:56.863299 extracting modules file /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/784917/extract-overlay-ramdisk-lf227s4p/ramdisk
193 06:42:58.180240 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 06:42:58.180729 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 06:42:58.181009 [common] Applying overlay /var/lib/lava/dispatcher/tmp/784917/compress-overlay-vf742exk/overlay-1.5.2.5.tar.gz to ramdisk
196 06:42:58.181225 [common] Applying overlay /var/lib/lava/dispatcher/tmp/784917/compress-overlay-vf742exk/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/784917/extract-overlay-ramdisk-lf227s4p/ramdisk
197 06:42:58.211140 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 06:42:58.211549 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 06:42:58.211820 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 06:42:58.212077 Converting downloaded kernel to a uImage
201 06:42:58.212388 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/kernel/Image /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/kernel/uImage
202 06:42:58.675530 output: Image Name:
203 06:42:58.676071 output: Created: Tue Oct 1 06:42:58 2024
204 06:42:58.676336 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 06:42:58.676585 output: Data Size: 45779456 Bytes = 44706.50 KiB = 43.66 MiB
206 06:42:58.676830 output: Load Address: 01080000
207 06:42:58.677074 output: Entry Point: 01080000
208 06:42:58.677316 output:
209 06:42:58.677714 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 06:42:58.678039 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 06:42:58.678368 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 06:42:58.678670 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 06:42:58.678981 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 06:42:58.679319 Building ramdisk /var/lib/lava/dispatcher/tmp/784917/extract-overlay-ramdisk-lf227s4p/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/784917/extract-overlay-ramdisk-lf227s4p/ramdisk
215 06:43:01.007451 >> 181682 blocks
216 06:43:09.580397 Adding RAMdisk u-boot header.
217 06:43:09.581063 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/784917/extract-overlay-ramdisk-lf227s4p/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/784917/extract-overlay-ramdisk-lf227s4p/ramdisk.cpio.gz.uboot
218 06:43:09.874905 output: Image Name:
219 06:43:09.875332 output: Created: Tue Oct 1 06:43:09 2024
220 06:43:09.875542 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 06:43:09.875745 output: Data Size: 26065241 Bytes = 25454.34 KiB = 24.86 MiB
222 06:43:09.875944 output: Load Address: 00000000
223 06:43:09.876400 output: Entry Point: 00000000
224 06:43:09.876842 output:
225 06:43:09.877920 rename /var/lib/lava/dispatcher/tmp/784917/extract-overlay-ramdisk-lf227s4p/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/ramdisk/ramdisk.cpio.gz.uboot
226 06:43:09.878699 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 06:43:09.879293 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 06:43:09.879868 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 06:43:09.880404 No LXC device requested
230 06:43:09.880959 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 06:43:09.881517 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 06:43:09.882058 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 06:43:09.882512 Checking files for TFTP limit of 4294967296 bytes.
234 06:43:09.885503 end: 1 tftp-deploy (duration 00:00:17) [common]
235 06:43:09.886155 start: 2 uboot-action (timeout 00:05:00) [common]
236 06:43:09.886728 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 06:43:09.887274 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 06:43:09.887824 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 06:43:09.888449 Using kernel file from prepare-kernel: 784917/tftp-deploy-l2oce41t/kernel/uImage
240 06:43:09.889113 substitutions:
241 06:43:09.889565 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 06:43:09.890007 - {DTB_ADDR}: 0x01070000
243 06:43:09.890446 - {DTB}: 784917/tftp-deploy-l2oce41t/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 06:43:09.890887 - {INITRD}: 784917/tftp-deploy-l2oce41t/ramdisk/ramdisk.cpio.gz.uboot
245 06:43:09.891328 - {KERNEL_ADDR}: 0x01080000
246 06:43:09.891763 - {KERNEL}: 784917/tftp-deploy-l2oce41t/kernel/uImage
247 06:43:09.892237 - {LAVA_MAC}: None
248 06:43:09.892717 - {PRESEED_CONFIG}: None
249 06:43:09.893152 - {PRESEED_LOCAL}: None
250 06:43:09.893585 - {RAMDISK_ADDR}: 0x08000000
251 06:43:09.894013 - {RAMDISK}: 784917/tftp-deploy-l2oce41t/ramdisk/ramdisk.cpio.gz.uboot
252 06:43:09.894450 - {ROOT_PART}: None
253 06:43:09.894880 - {ROOT}: None
254 06:43:09.895309 - {SERVER_IP}: 192.168.6.2
255 06:43:09.895743 - {TEE_ADDR}: 0x83000000
256 06:43:09.896208 - {TEE}: None
257 06:43:09.896640 Parsed boot commands:
258 06:43:09.897062 - setenv autoload no
259 06:43:09.897492 - setenv initrd_high 0xffffffff
260 06:43:09.897919 - setenv fdt_high 0xffffffff
261 06:43:09.898343 - dhcp
262 06:43:09.898768 - setenv serverip 192.168.6.2
263 06:43:09.899196 - tftpboot 0x01080000 784917/tftp-deploy-l2oce41t/kernel/uImage
264 06:43:09.899626 - tftpboot 0x08000000 784917/tftp-deploy-l2oce41t/ramdisk/ramdisk.cpio.gz.uboot
265 06:43:09.900078 - tftpboot 0x01070000 784917/tftp-deploy-l2oce41t/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 06:43:09.900514 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 06:43:09.900947 - bootm 0x01080000 0x08000000 0x01070000
268 06:43:09.901493 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 06:43:09.903115 start: 2.3 connect-device (timeout 00:05:00) [common]
271 06:43:09.903598 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 06:43:09.919061 Setting prompt string to ['lava-test: # ']
273 06:43:09.920734 end: 2.3 connect-device (duration 00:00:00) [common]
274 06:43:09.921390 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 06:43:09.921990 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 06:43:09.922563 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 06:43:09.923783 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 06:43:09.961569 >> OK - accepted request
279 06:43:09.963875 Returned 0 in 0 seconds
280 06:43:10.065259 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 06:43:10.067101 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 06:43:10.067730 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 06:43:10.068347 Setting prompt string to ['Hit any key to stop autoboot']
285 06:43:10.068844 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 06:43:10.070591 Trying 192.168.56.21...
287 06:43:10.071119 Connected to conserv1.
288 06:43:10.071698 Escape character is '^]'.
289 06:43:10.072216
290 06:43:10.072690 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 06:43:10.073179
292 06:43:16.648420 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 06:43:16.648856 bl2_stage_init 0x01
294 06:43:16.649092 bl2_stage_init 0x81
295 06:43:16.653973 hw id: 0x0000 - pwm id 0x01
296 06:43:16.654253 bl2_stage_init 0xc1
297 06:43:16.659595 bl2_stage_init 0x02
298 06:43:16.659876
299 06:43:16.660138 L0:00000000
300 06:43:16.660355 L1:00000703
301 06:43:16.660563 L2:00008067
302 06:43:16.660769 L3:15000000
303 06:43:16.665082 S1:00000000
304 06:43:16.665379 B2:20282000
305 06:43:16.665588 B1:a0f83180
306 06:43:16.665787
307 06:43:16.665994 TE: 69160
308 06:43:16.666197
309 06:43:16.670720 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 06:43:16.671005
311 06:43:16.676373 Board ID = 1
312 06:43:16.676676 Set cpu clk to 24M
313 06:43:16.676888 Set clk81 to 24M
314 06:43:16.681991 Use GP1_pll as DSU clk.
315 06:43:16.682266 DSU clk: 1200 Mhz
316 06:43:16.682481 CPU clk: 1200 MHz
317 06:43:16.687560 Set clk81 to 166.6M
318 06:43:16.693217 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 06:43:16.693499 board id: 1
320 06:43:16.699835 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 06:43:16.710895 fw parse done
322 06:43:16.716674 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 06:43:16.758813 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 06:43:16.770448 PIEI prepare done
325 06:43:16.770735 fastboot data load
326 06:43:16.770956 fastboot data verify
327 06:43:16.776029 verify result: 266
328 06:43:16.781601 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 06:43:16.781886 LPDDR4 probe
330 06:43:16.782094 ddr clk to 1584MHz
331 06:43:16.788801 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 06:43:16.825891
333 06:43:16.826214 dmc_version 0001
334 06:43:16.832824 Check phy result
335 06:43:16.839400 INFO : End of CA training
336 06:43:16.839662 INFO : End of initialization
337 06:43:16.844984 INFO : Training has run successfully!
338 06:43:16.845241 Check phy result
339 06:43:16.850612 INFO : End of initialization
340 06:43:16.850883 INFO : End of read enable training
341 06:43:16.856219 INFO : End of fine write leveling
342 06:43:16.861786 INFO : End of Write leveling coarse delay
343 06:43:16.862056 INFO : Training has run successfully!
344 06:43:16.862262 Check phy result
345 06:43:16.867427 INFO : End of initialization
346 06:43:16.867752 INFO : End of read dq deskew training
347 06:43:16.873003 INFO : End of MPR read delay center optimization
348 06:43:16.878568 INFO : End of write delay center optimization
349 06:43:16.884183 INFO : End of read delay center optimization
350 06:43:16.884436 INFO : End of max read latency training
351 06:43:16.889770 INFO : Training has run successfully!
352 06:43:16.890012 1D training succeed
353 06:43:16.898410 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 06:43:16.946431 Check phy result
355 06:43:16.946726 INFO : End of initialization
356 06:43:16.967896 INFO : End of 2D read delay Voltage center optimization
357 06:43:16.987200 INFO : End of 2D read delay Voltage center optimization
358 06:43:17.039058 INFO : End of 2D write delay Voltage center optimization
359 06:43:17.089089 INFO : End of 2D write delay Voltage center optimization
360 06:43:17.094639 INFO : Training has run successfully!
361 06:43:17.094910
362 06:43:17.095119 channel==0
363 06:43:17.100277 RxClkDly_Margin_A0==88 ps 9
364 06:43:17.100547 TxDqDly_Margin_A0==98 ps 10
365 06:43:17.105856 RxClkDly_Margin_A1==88 ps 9
366 06:43:17.106115 TxDqDly_Margin_A1==98 ps 10
367 06:43:17.106328 TrainedVREFDQ_A0==74
368 06:43:17.111444 TrainedVREFDQ_A1==75
369 06:43:17.111723 VrefDac_Margin_A0==24
370 06:43:17.111935 DeviceVref_Margin_A0==40
371 06:43:17.117194 VrefDac_Margin_A1==23
372 06:43:17.117736 DeviceVref_Margin_A1==39
373 06:43:17.118189
374 06:43:17.118641
375 06:43:17.122747 channel==1
376 06:43:17.123274 RxClkDly_Margin_A0==88 ps 9
377 06:43:17.123726 TxDqDly_Margin_A0==98 ps 10
378 06:43:17.128382 RxClkDly_Margin_A1==88 ps 9
379 06:43:17.128914 TxDqDly_Margin_A1==88 ps 9
380 06:43:17.133972 TrainedVREFDQ_A0==78
381 06:43:17.134517 TrainedVREFDQ_A1==78
382 06:43:17.134966 VrefDac_Margin_A0==22
383 06:43:17.139552 DeviceVref_Margin_A0==36
384 06:43:17.140125 VrefDac_Margin_A1==22
385 06:43:17.145139 DeviceVref_Margin_A1==36
386 06:43:17.145678
387 06:43:17.146129 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 06:43:17.146566
389 06:43:17.178720 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 06:43:17.179415 2D training succeed
391 06:43:17.184403 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 06:43:17.189970 auto size-- 65535DDR cs0 size: 2048MB
393 06:43:17.190516 DDR cs1 size: 2048MB
394 06:43:17.195554 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 06:43:17.196136 cs0 DataBus test pass
396 06:43:17.201170 cs1 DataBus test pass
397 06:43:17.201712 cs0 AddrBus test pass
398 06:43:17.202154 cs1 AddrBus test pass
399 06:43:17.202588
400 06:43:17.206785 100bdlr_step_size ps== 464
401 06:43:17.207355 result report
402 06:43:17.212381 boot times 0Enable ddr reg access
403 06:43:17.217058 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 06:43:17.231434 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 06:43:17.886275 bl2z: ptr: 05129330, size: 00001e40
406 06:43:17.893466 0.0;M3 CHK:0;cm4_sp_mode 0
407 06:43:17.894040 MVN_1=0x00000000
408 06:43:17.894489 MVN_2=0x00000000
409 06:43:17.904926 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 06:43:17.905499 OPS=0x04
411 06:43:17.905944 ring efuse init
412 06:43:17.910587 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 06:43:17.911142 [0.017319 Inits done]
414 06:43:17.911584 secure task start!
415 06:43:17.917802 high task start!
416 06:43:17.918347 low task start!
417 06:43:17.918790 run into bl31
418 06:43:17.927192 NOTICE: BL31: v1.3(release):4fc40b1
419 06:43:17.934797 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 06:43:17.935357 NOTICE: BL31: G12A normal boot!
421 06:43:17.950520 NOTICE: BL31: BL33 decompress pass
422 06:43:17.955805 ERROR: Error initializing runtime service opteed_fast
423 06:43:20.702091 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 06:43:20.702786 bl2_stage_init 0x01
425 06:43:20.703275 bl2_stage_init 0x81
426 06:43:20.707682 hw id: 0x0000 - pwm id 0x01
427 06:43:20.708272 bl2_stage_init 0xc1
428 06:43:20.712393 bl2_stage_init 0x02
429 06:43:20.712973
430 06:43:20.713430 L0:00000000
431 06:43:20.713867 L1:00000703
432 06:43:20.714300 L2:00008067
433 06:43:20.717996 L3:15000000
434 06:43:20.718532 S1:00000000
435 06:43:20.718982 B2:20282000
436 06:43:20.719421 B1:a0f83180
437 06:43:20.719855
438 06:43:20.720332 TE: 71598
439 06:43:20.720770
440 06:43:20.729080 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 06:43:20.729616
442 06:43:20.730071 Board ID = 1
443 06:43:20.730506 Set cpu clk to 24M
444 06:43:20.730936 Set clk81 to 24M
445 06:43:20.734728 Use GP1_pll as DSU clk.
446 06:43:20.735256 DSU clk: 1200 Mhz
447 06:43:20.735696 CPU clk: 1200 MHz
448 06:43:20.740360 Set clk81 to 166.6M
449 06:43:20.745928 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 06:43:20.746456 board id: 1
451 06:43:20.754036 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 06:43:20.764926 fw parse done
453 06:43:20.770942 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 06:43:20.813968 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 06:43:20.825148 PIEI prepare done
456 06:43:20.825687 fastboot data load
457 06:43:20.826134 fastboot data verify
458 06:43:20.830725 verify result: 266
459 06:43:20.836322 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 06:43:20.836852 LPDDR4 probe
461 06:43:20.837291 ddr clk to 1584MHz
462 06:43:20.844311 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 06:43:20.882060
464 06:43:20.882601 dmc_version 0001
465 06:43:20.889101 Check phy result
466 06:43:20.895166 INFO : End of CA training
467 06:43:20.895746 INFO : End of initialization
468 06:43:20.900712 INFO : Training has run successfully!
469 06:43:20.901256 Check phy result
470 06:43:20.906304 INFO : End of initialization
471 06:43:20.906841 INFO : End of read enable training
472 06:43:20.911888 INFO : End of fine write leveling
473 06:43:20.917467 INFO : End of Write leveling coarse delay
474 06:43:20.918002 INFO : Training has run successfully!
475 06:43:20.918462 Check phy result
476 06:43:20.923104 INFO : End of initialization
477 06:43:20.923636 INFO : End of read dq deskew training
478 06:43:20.928687 INFO : End of MPR read delay center optimization
479 06:43:20.934307 INFO : End of write delay center optimization
480 06:43:20.939914 INFO : End of read delay center optimization
481 06:43:20.940500 INFO : End of max read latency training
482 06:43:20.945462 INFO : Training has run successfully!
483 06:43:20.945991 1D training succeed
484 06:43:20.954604 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 06:43:21.003065 Check phy result
486 06:43:21.003669 INFO : End of initialization
487 06:43:21.030350 INFO : End of 2D read delay Voltage center optimization
488 06:43:21.054524 INFO : End of 2D read delay Voltage center optimization
489 06:43:21.111202 INFO : End of 2D write delay Voltage center optimization
490 06:43:21.165215 INFO : End of 2D write delay Voltage center optimization
491 06:43:21.170828 INFO : Training has run successfully!
492 06:43:21.171397
493 06:43:21.171860 channel==0
494 06:43:21.176381 RxClkDly_Margin_A0==88 ps 9
495 06:43:21.176924 TxDqDly_Margin_A0==98 ps 10
496 06:43:21.182007 RxClkDly_Margin_A1==69 ps 7
497 06:43:21.182537 TxDqDly_Margin_A1==98 ps 10
498 06:43:21.182996 TrainedVREFDQ_A0==74
499 06:43:21.187557 TrainedVREFDQ_A1==74
500 06:43:21.188121 VrefDac_Margin_A0==23
501 06:43:21.188582 DeviceVref_Margin_A0==40
502 06:43:21.193163 VrefDac_Margin_A1==23
503 06:43:21.193684 DeviceVref_Margin_A1==40
504 06:43:21.194143
505 06:43:21.194594
506 06:43:21.198773 channel==1
507 06:43:21.199301 RxClkDly_Margin_A0==88 ps 9
508 06:43:21.199757 TxDqDly_Margin_A0==88 ps 9
509 06:43:21.204377 RxClkDly_Margin_A1==88 ps 9
510 06:43:21.204909 TxDqDly_Margin_A1==88 ps 9
511 06:43:21.209994 TrainedVREFDQ_A0==75
512 06:43:21.210521 TrainedVREFDQ_A1==75
513 06:43:21.210976 VrefDac_Margin_A0==22
514 06:43:21.215586 DeviceVref_Margin_A0==39
515 06:43:21.216157 VrefDac_Margin_A1==22
516 06:43:21.221174 DeviceVref_Margin_A1==39
517 06:43:21.221704
518 06:43:21.222168 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 06:43:21.222618
520 06:43:21.254732 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 06:43:21.255357 2D training succeed
522 06:43:21.260411 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 06:43:21.266018 auto size-- 65535DDR cs0 size: 2048MB
524 06:43:21.266554 DDR cs1 size: 2048MB
525 06:43:21.271558 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 06:43:21.272114 cs0 DataBus test pass
527 06:43:21.277175 cs1 DataBus test pass
528 06:43:21.277698 cs0 AddrBus test pass
529 06:43:21.278154 cs1 AddrBus test pass
530 06:43:21.278598
531 06:43:21.282783 100bdlr_step_size ps== 464
532 06:43:21.283331 result report
533 06:43:21.288396 boot times 0Enable ddr reg access
534 06:43:21.293549 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 06:43:21.307337 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 06:43:21.968061 bl2z: ptr: 05129330, size: 00001e40
537 06:43:21.977446 0.0;M3 CHK:0;cm4_sp_mode 0
538 06:43:21.978049 MVN_1=0x00000000
539 06:43:21.978511 MVN_2=0x00000000
540 06:43:21.988865 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 06:43:21.989505 OPS=0x04
542 06:43:21.989982 ring efuse init
543 06:43:21.994487 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 06:43:21.995061 [0.017354 Inits done]
545 06:43:21.995526 secure task start!
546 06:43:22.002056 high task start!
547 06:43:22.002653 low task start!
548 06:43:22.003120 run into bl31
549 06:43:22.010792 NOTICE: BL31: v1.3(release):4fc40b1
550 06:43:22.018594 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 06:43:22.019175 NOTICE: BL31: G12A normal boot!
552 06:43:22.034081 NOTICE: BL31: BL33 decompress pass
553 06:43:22.039917 ERROR: Error initializing runtime service opteed_fast
554 06:43:23.397778 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 06:43:23.398412 bl2_stage_init 0x01
556 06:43:23.398884 bl2_stage_init 0x81
557 06:43:23.403430 hw id: 0x0000 - pwm id 0x01
558 06:43:23.403951 bl2_stage_init 0xc1
559 06:43:23.408960 bl2_stage_init 0x02
560 06:43:23.409480
561 06:43:23.409941 L0:00000000
562 06:43:23.410386 L1:00000703
563 06:43:23.410830 L2:00008067
564 06:43:23.411271 L3:15000000
565 06:43:23.414636 S1:00000000
566 06:43:23.415153 B2:20282000
567 06:43:23.415604 B1:a0f83180
568 06:43:23.416083
569 06:43:23.416539 TE: 68388
570 06:43:23.416985
571 06:43:23.420202 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 06:43:23.420715
573 06:43:23.425776 Board ID = 1
574 06:43:23.426287 Set cpu clk to 24M
575 06:43:23.426738 Set clk81 to 24M
576 06:43:23.431308 Use GP1_pll as DSU clk.
577 06:43:23.431816 DSU clk: 1200 Mhz
578 06:43:23.432309 CPU clk: 1200 MHz
579 06:43:23.436963 Set clk81 to 166.6M
580 06:43:23.442577 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 06:43:23.443088 board id: 1
582 06:43:23.449496 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 06:43:23.460676 fw parse done
584 06:43:23.465741 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 06:43:23.508887 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 06:43:23.520852 PIEI prepare done
587 06:43:23.521381 fastboot data load
588 06:43:23.521845 fastboot data verify
589 06:43:23.526437 verify result: 266
590 06:43:23.532080 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 06:43:23.532611 LPDDR4 probe
592 06:43:23.533066 ddr clk to 1584MHz
593 06:43:23.539831 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 06:43:23.577809
595 06:43:23.578375 dmc_version 0001
596 06:43:23.584345 Check phy result
597 06:43:23.590825 INFO : End of CA training
598 06:43:23.591355 INFO : End of initialization
599 06:43:23.596396 INFO : Training has run successfully!
600 06:43:23.596927 Check phy result
601 06:43:23.601988 INFO : End of initialization
602 06:43:23.602513 INFO : End of read enable training
603 06:43:23.605366 INFO : End of fine write leveling
604 06:43:23.610902 INFO : End of Write leveling coarse delay
605 06:43:23.616498 INFO : Training has run successfully!
606 06:43:23.617025 Check phy result
607 06:43:23.617478 INFO : End of initialization
608 06:43:23.622083 INFO : End of read dq deskew training
609 06:43:23.625499 INFO : End of MPR read delay center optimization
610 06:43:23.631011 INFO : End of write delay center optimization
611 06:43:23.636627 INFO : End of read delay center optimization
612 06:43:23.637166 INFO : End of max read latency training
613 06:43:23.642213 INFO : Training has run successfully!
614 06:43:23.642739 1D training succeed
615 06:43:23.649893 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 06:43:23.698354 Check phy result
617 06:43:23.698922 INFO : End of initialization
618 06:43:23.725569 INFO : End of 2D read delay Voltage center optimization
619 06:43:23.750171 INFO : End of 2D read delay Voltage center optimization
620 06:43:23.806116 INFO : End of 2D write delay Voltage center optimization
621 06:43:23.860956 INFO : End of 2D write delay Voltage center optimization
622 06:43:23.866540 INFO : Training has run successfully!
623 06:43:23.867061
624 06:43:23.867518 channel==0
625 06:43:23.872086 RxClkDly_Margin_A0==78 ps 8
626 06:43:23.872614 TxDqDly_Margin_A0==98 ps 10
627 06:43:23.877743 RxClkDly_Margin_A1==88 ps 9
628 06:43:23.878260 TxDqDly_Margin_A1==88 ps 9
629 06:43:23.878719 TrainedVREFDQ_A0==74
630 06:43:23.883230 TrainedVREFDQ_A1==74
631 06:43:23.883751 VrefDac_Margin_A0==23
632 06:43:23.884250 DeviceVref_Margin_A0==40
633 06:43:23.888860 VrefDac_Margin_A1==23
634 06:43:23.889380 DeviceVref_Margin_A1==40
635 06:43:23.889832
636 06:43:23.890282
637 06:43:23.890727 channel==1
638 06:43:23.894553 RxClkDly_Margin_A0==88 ps 9
639 06:43:23.895074 TxDqDly_Margin_A0==98 ps 10
640 06:43:23.900136 RxClkDly_Margin_A1==88 ps 9
641 06:43:23.900653 TxDqDly_Margin_A1==88 ps 9
642 06:43:23.905728 TrainedVREFDQ_A0==78
643 06:43:23.906249 TrainedVREFDQ_A1==75
644 06:43:23.906703 VrefDac_Margin_A0==22
645 06:43:23.911379 DeviceVref_Margin_A0==36
646 06:43:23.911891 VrefDac_Margin_A1==22
647 06:43:23.917031 DeviceVref_Margin_A1==39
648 06:43:23.917545
649 06:43:23.918001 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 06:43:23.918443
651 06:43:23.950336 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 06:43:23.950940 2D training succeed
653 06:43:23.956058 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 06:43:23.961594 auto size-- 65535DDR cs0 size: 2048MB
655 06:43:23.962112 DDR cs1 size: 2048MB
656 06:43:23.967193 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 06:43:23.967708 cs0 DataBus test pass
658 06:43:23.972797 cs1 DataBus test pass
659 06:43:23.973311 cs0 AddrBus test pass
660 06:43:23.973767 cs1 AddrBus test pass
661 06:43:23.974215
662 06:43:23.978394 100bdlr_step_size ps== 471
663 06:43:23.978924 result report
664 06:43:23.984015 boot times 0Enable ddr reg access
665 06:43:23.989137 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 06:43:24.002077 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 06:43:24.663354 bl2z: ptr: 05129330, size: 00001e40
668 06:43:24.672818 0.0;M3 CHK:0;cm4_sp_mode 0
669 06:43:24.673321 MVN_1=0x00000000
670 06:43:24.673574 MVN_2=0x00000000
671 06:43:24.684337 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 06:43:24.684709 OPS=0x04
673 06:43:24.684924 ring efuse init
674 06:43:24.689923 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 06:43:24.690380 [0.017355 Inits done]
676 06:43:24.690697 secure task start!
677 06:43:24.697453 high task start!
678 06:43:24.697899 low task start!
679 06:43:24.698240 run into bl31
680 06:43:24.706217 NOTICE: BL31: v1.3(release):4fc40b1
681 06:43:24.713230 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 06:43:24.713581 NOTICE: BL31: G12A normal boot!
683 06:43:24.729868 NOTICE: BL31: BL33 decompress pass
684 06:43:24.735039 ERROR: Error initializing runtime service opteed_fast
685 06:43:25.530704
686 06:43:25.531133
687 06:43:25.536177 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 06:43:25.536625
689 06:43:25.538963 Model: Libre Computer AML-S905D3-CC Solitude
690 06:43:25.685876 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 06:43:25.701533 DRAM: 2 GiB (effective 3.8 GiB)
692 06:43:25.803052 Core: 406 devices, 33 uclasses, devicetree: separate
693 06:43:25.810277 WDT: Not starting watchdog@f0d0
694 06:43:25.833994 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 06:43:25.846260 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 06:43:25.850541 ** Bad device specification mmc 0 **
697 06:43:25.861277 Card did not respond to voltage select! : -110
698 06:43:25.868766 ** Bad device specification mmc 0 **
699 06:43:25.869301 Couldn't find partition mmc 0
700 06:43:25.877290 Card did not respond to voltage select! : -110
701 06:43:25.883842 ** Bad device specification mmc 0 **
702 06:43:25.884528 Couldn't find partition mmc 0
703 06:43:25.887816 Error: could not access storage.
704 06:43:26.183776 Net: eth0: ethernet@ff3f0000
705 06:43:26.184501 starting USB...
706 06:43:26.429088 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 06:43:26.429766 Starting the controller
708 06:43:26.435295 USB XHCI 1.10
709 06:43:27.990173 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 06:43:27.998465 scanning usb for storage devices... 0 Storage Device(s) found
712 06:43:28.050250 Hit any key to stop autoboot: 1
713 06:43:28.051308 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
714 06:43:28.052167 start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
715 06:43:28.052767 Setting prompt string to ['=>']
716 06:43:28.053358 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:42)
717 06:43:28.064468 0
718 06:43:28.065499 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 06:43:28.166906 => setenv autoload no
721 06:43:28.168131 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
722 06:43:28.173797 setenv autoload no
724 06:43:28.275497 => setenv initrd_high 0xffffffff
725 06:43:28.276620 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
726 06:43:28.280905 setenv initrd_high 0xffffffff
728 06:43:28.382503 => setenv fdt_high 0xffffffff
729 06:43:28.383345 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
730 06:43:28.388439 setenv fdt_high 0xffffffff
732 06:43:28.490060 => dhcp
733 06:43:28.490821 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 06:43:28.493961 dhcp
735 06:43:29.000478 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 06:43:29.001135 Speed: 1000, full duplex
737 06:43:29.001604 BOOTP broadcast 1
738 06:43:29.248691 BOOTP broadcast 2
739 06:43:29.749705 BOOTP broadcast 3
740 06:43:30.750713 BOOTP broadcast 4
741 06:43:32.750708 BOOTP broadcast 5
742 06:43:32.762538 DHCP client bound to address 192.168.6.12 (3762 ms)
744 06:43:32.864058 => setenv serverip 192.168.6.2
745 06:43:32.864748 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
746 06:43:32.869026 setenv serverip 192.168.6.2
748 06:43:32.970415 => tftpboot 0x01080000 784917/tftp-deploy-l2oce41t/kernel/uImage
749 06:43:32.971250 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
750 06:43:32.977829 tftpboot 0x01080000 784917/tftp-deploy-l2oce41t/kernel/uImage
751 06:43:32.978291 Speed: 1000, full duplex
752 06:43:32.978707 Using ethernet@ff3f0000 device
753 06:43:32.983305 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 06:43:32.988796 Filename '784917/tftp-deploy-l2oce41t/kernel/uImage'.
755 06:43:32.992787 Load address: 0x1080000
756 06:43:38.084127 Loading: *################################################## 43.7 MiB
757 06:43:38.084743 8.6 MiB/s
758 06:43:38.085155 done
759 06:43:38.088409 Bytes transferred = 45779520 (2ba8a40 hex)
761 06:43:38.189951 => tftpboot 0x08000000 784917/tftp-deploy-l2oce41t/ramdisk/ramdisk.cpio.gz.uboot
762 06:43:38.190796 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
763 06:43:38.197260 tftpboot 0x08000000 784917/tftp-deploy-l2oce41t/ramdisk/ramdisk.cpio.gz.uboot
764 06:43:38.197724 Speed: 1000, full duplex
765 06:43:38.198139 Using ethernet@ff3f0000 device
766 06:43:38.202802 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
767 06:43:38.211735 Filename '784917/tftp-deploy-l2oce41t/ramdisk/ramdisk.cpio.gz.uboot'.
768 06:43:38.212283 Load address: 0x8000000
769 06:43:40.372483 Loading: *################################################# UDP wrong checksum 00000005 00005a8d
770 06:43:45.373639 T UDP wrong checksum 00000005 00005a8d
771 06:43:55.374472 T T UDP wrong checksum 00000005 00005a8d
772 06:44:15.379688 T T T T UDP wrong checksum 00000005 00005a8d
773 06:44:24.050985 T UDP wrong checksum 000000ff 00007885
774 06:44:24.081070 UDP wrong checksum 000000ff 00000e78
775 06:44:35.384482 T T
776 06:44:35.385155 Retry count exceeded; starting again
778 06:44:35.386702 end: 2.4.3 bootloader-commands (duration 00:01:07) [common]
781 06:44:35.388873 end: 2.4 uboot-commands (duration 00:01:25) [common]
783 06:44:35.390347 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
785 06:44:35.391442 end: 2 uboot-action (duration 00:01:26) [common]
787 06:44:35.393122 Cleaning after the job
788 06:44:35.393728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/ramdisk
789 06:44:35.395307 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/kernel
790 06:44:35.441948 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/dtb
791 06:44:35.442688 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784917/tftp-deploy-l2oce41t/modules
792 06:44:35.462930 start: 4.1 power-off (timeout 00:00:30) [common]
793 06:44:35.463575 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
794 06:44:35.496347 >> OK - accepted request
795 06:44:35.498516 Returned 0 in 0 seconds
796 06:44:35.599380 end: 4.1 power-off (duration 00:00:00) [common]
798 06:44:35.601095 start: 4.2 read-feedback (timeout 00:10:00) [common]
799 06:44:35.602195 Listened to connection for namespace 'common' for up to 1s
800 06:44:36.603025 Finalising connection for namespace 'common'
801 06:44:36.603767 Disconnecting from shell: Finalise
802 06:44:36.604402 =>
803 06:44:36.705403 end: 4.2 read-feedback (duration 00:00:01) [common]
804 06:44:36.706083 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/784917
805 06:44:37.003177 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/784917
806 06:44:37.003773 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.