Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:21:06.552336 lava-dispatcher, installed at version: 2024.01
2 08:21:06.553089 start: 0 validate
3 08:21:06.553569 Start time: 2024-10-01 08:21:06.553540+00:00 (UTC)
4 08:21:06.554091 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:21:06.554629 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 08:21:06.595560 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:21:06.596126 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:21:06.622342 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:21:06.622944 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:21:06.654659 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:21:06.655134 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:21:06.685981 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:21:06.686462 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241001%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 08:21:06.722534 validate duration: 0.17
16 08:21:06.723401 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:21:06.723738 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:21:06.724093 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:21:06.724695 Not decompressing ramdisk as can be used compressed.
20 08:21:06.725149 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 08:21:06.725439 saving as /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/ramdisk/initrd.cpio.gz
22 08:21:06.725719 total size: 5628140 (5 MB)
23 08:21:06.760563 progress 0 % (0 MB)
24 08:21:06.764754 progress 5 % (0 MB)
25 08:21:06.768952 progress 10 % (0 MB)
26 08:21:06.772605 progress 15 % (0 MB)
27 08:21:06.776625 progress 20 % (1 MB)
28 08:21:06.780280 progress 25 % (1 MB)
29 08:21:06.784412 progress 30 % (1 MB)
30 08:21:06.788456 progress 35 % (1 MB)
31 08:21:06.792189 progress 40 % (2 MB)
32 08:21:06.796366 progress 45 % (2 MB)
33 08:21:06.800105 progress 50 % (2 MB)
34 08:21:06.804198 progress 55 % (2 MB)
35 08:21:06.808229 progress 60 % (3 MB)
36 08:21:06.812158 progress 65 % (3 MB)
37 08:21:06.816295 progress 70 % (3 MB)
38 08:21:06.819969 progress 75 % (4 MB)
39 08:21:06.824070 progress 80 % (4 MB)
40 08:21:06.827634 progress 85 % (4 MB)
41 08:21:06.831764 progress 90 % (4 MB)
42 08:21:06.835733 progress 95 % (5 MB)
43 08:21:06.839016 progress 100 % (5 MB)
44 08:21:06.839664 5 MB downloaded in 0.11 s (47.11 MB/s)
45 08:21:06.840252 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:21:06.841178 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:21:06.841501 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:21:06.841794 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:21:06.842289 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig/gcc-12/kernel/Image
51 08:21:06.842549 saving as /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/kernel/Image
52 08:21:06.842769 total size: 45779456 (43 MB)
53 08:21:06.842990 No compression specified
54 08:21:06.879464 progress 0 % (0 MB)
55 08:21:06.907893 progress 5 % (2 MB)
56 08:21:06.936983 progress 10 % (4 MB)
57 08:21:06.966102 progress 15 % (6 MB)
58 08:21:06.995208 progress 20 % (8 MB)
59 08:21:07.026572 progress 25 % (10 MB)
60 08:21:07.055167 progress 30 % (13 MB)
61 08:21:07.083917 progress 35 % (15 MB)
62 08:21:07.112881 progress 40 % (17 MB)
63 08:21:07.141341 progress 45 % (19 MB)
64 08:21:07.170446 progress 50 % (21 MB)
65 08:21:07.199164 progress 55 % (24 MB)
66 08:21:07.228260 progress 60 % (26 MB)
67 08:21:07.257246 progress 65 % (28 MB)
68 08:21:07.285563 progress 70 % (30 MB)
69 08:21:07.314672 progress 75 % (32 MB)
70 08:21:07.343338 progress 80 % (34 MB)
71 08:21:07.372622 progress 85 % (37 MB)
72 08:21:07.401518 progress 90 % (39 MB)
73 08:21:07.430450 progress 95 % (41 MB)
74 08:21:07.459179 progress 100 % (43 MB)
75 08:21:07.459702 43 MB downloaded in 0.62 s (70.77 MB/s)
76 08:21:07.460207 end: 1.2.1 http-download (duration 00:00:01) [common]
78 08:21:07.461016 end: 1.2 download-retry (duration 00:00:01) [common]
79 08:21:07.461293 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:21:07.461556 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:21:07.462033 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 08:21:07.462284 saving as /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/dtb/meson-g12b-a311d-libretech-cc.dtb
83 08:21:07.462490 total size: 54703 (0 MB)
84 08:21:07.462696 No compression specified
85 08:21:07.498047 progress 59 % (0 MB)
86 08:21:07.498890 progress 100 % (0 MB)
87 08:21:07.499439 0 MB downloaded in 0.04 s (1.41 MB/s)
88 08:21:07.499897 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:21:07.500740 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:21:07.501003 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:21:07.501268 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:21:07.501719 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 08:21:07.501966 saving as /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/nfsrootfs/full.rootfs.tar
95 08:21:07.502171 total size: 474398908 (452 MB)
96 08:21:07.502380 Using unxz to decompress xz
97 08:21:07.538533 progress 0 % (0 MB)
98 08:21:08.645918 progress 5 % (22 MB)
99 08:21:10.099648 progress 10 % (45 MB)
100 08:21:10.531750 progress 15 % (67 MB)
101 08:21:11.368293 progress 20 % (90 MB)
102 08:21:11.917537 progress 25 % (113 MB)
103 08:21:12.276171 progress 30 % (135 MB)
104 08:21:12.882511 progress 35 % (158 MB)
105 08:21:13.816515 progress 40 % (181 MB)
106 08:21:14.684031 progress 45 % (203 MB)
107 08:21:15.438415 progress 50 % (226 MB)
108 08:21:16.204390 progress 55 % (248 MB)
109 08:21:17.409914 progress 60 % (271 MB)
110 08:21:18.885191 progress 65 % (294 MB)
111 08:21:20.524104 progress 70 % (316 MB)
112 08:21:23.614506 progress 75 % (339 MB)
113 08:21:26.054021 progress 80 % (361 MB)
114 08:21:28.943942 progress 85 % (384 MB)
115 08:21:32.106369 progress 90 % (407 MB)
116 08:21:35.287866 progress 95 % (429 MB)
117 08:21:38.576749 progress 100 % (452 MB)
118 08:21:38.590093 452 MB downloaded in 31.09 s (14.55 MB/s)
119 08:21:38.591058 end: 1.4.1 http-download (duration 00:00:31) [common]
121 08:21:38.592895 end: 1.4 download-retry (duration 00:00:31) [common]
122 08:21:38.593483 start: 1.5 download-retry (timeout 00:09:28) [common]
123 08:21:38.594065 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 08:21:38.594949 downloading http://storage.kernelci.org/next/master/next-20241001/arm64/defconfig/gcc-12/modules.tar.xz
125 08:21:38.595457 saving as /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/modules/modules.tar
126 08:21:38.595915 total size: 11621212 (11 MB)
127 08:21:38.596416 Using unxz to decompress xz
128 08:21:38.641100 progress 0 % (0 MB)
129 08:21:38.710248 progress 5 % (0 MB)
130 08:21:38.789575 progress 10 % (1 MB)
131 08:21:38.877758 progress 15 % (1 MB)
132 08:21:38.953531 progress 20 % (2 MB)
133 08:21:39.035695 progress 25 % (2 MB)
134 08:21:39.114825 progress 30 % (3 MB)
135 08:21:39.194218 progress 35 % (3 MB)
136 08:21:39.267065 progress 40 % (4 MB)
137 08:21:39.342636 progress 45 % (5 MB)
138 08:21:39.419169 progress 50 % (5 MB)
139 08:21:39.493946 progress 55 % (6 MB)
140 08:21:39.573487 progress 60 % (6 MB)
141 08:21:39.658680 progress 65 % (7 MB)
142 08:21:39.739212 progress 70 % (7 MB)
143 08:21:39.830563 progress 75 % (8 MB)
144 08:21:39.924972 progress 80 % (8 MB)
145 08:21:40.005473 progress 85 % (9 MB)
146 08:21:40.079747 progress 90 % (10 MB)
147 08:21:40.151357 progress 95 % (10 MB)
148 08:21:40.226672 progress 100 % (11 MB)
149 08:21:40.239842 11 MB downloaded in 1.64 s (6.74 MB/s)
150 08:21:40.240839 end: 1.5.1 http-download (duration 00:00:02) [common]
152 08:21:40.242546 end: 1.5 download-retry (duration 00:00:02) [common]
153 08:21:40.243092 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 08:21:40.243623 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 08:21:55.706813 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/784956/extract-nfsrootfs-02gnh_w1
156 08:21:55.707418 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 08:21:55.707705 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 08:21:55.708575 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8
159 08:21:55.709051 makedir: /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin
160 08:21:55.709374 makedir: /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/tests
161 08:21:55.709682 makedir: /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/results
162 08:21:55.710009 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-add-keys
163 08:21:55.710530 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-add-sources
164 08:21:55.711031 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-background-process-start
165 08:21:55.711539 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-background-process-stop
166 08:21:55.712115 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-common-functions
167 08:21:55.712657 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-echo-ipv4
168 08:21:55.713149 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-install-packages
169 08:21:55.713706 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-installed-packages
170 08:21:55.714187 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-os-build
171 08:21:55.714661 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-probe-channel
172 08:21:55.715129 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-probe-ip
173 08:21:55.715597 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-target-ip
174 08:21:55.716083 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-target-mac
175 08:21:55.716575 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-target-storage
176 08:21:55.717070 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-test-case
177 08:21:55.717553 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-test-event
178 08:21:55.718020 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-test-feedback
179 08:21:55.718488 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-test-raise
180 08:21:55.718953 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-test-reference
181 08:21:55.719422 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-test-runner
182 08:21:55.719898 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-test-set
183 08:21:55.720447 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-test-shell
184 08:21:55.720951 Updating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-install-packages (oe)
185 08:21:55.721475 Updating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/bin/lava-installed-packages (oe)
186 08:21:55.721912 Creating /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/environment
187 08:21:55.722273 LAVA metadata
188 08:21:55.722527 - LAVA_JOB_ID=784956
189 08:21:55.722739 - LAVA_DISPATCHER_IP=192.168.6.2
190 08:21:55.723088 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 08:21:55.724055 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 08:21:55.724367 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 08:21:55.724574 skipped lava-vland-overlay
194 08:21:55.724813 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 08:21:55.725065 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 08:21:55.725280 skipped lava-multinode-overlay
197 08:21:55.725518 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 08:21:55.725768 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 08:21:55.726018 Loading test definitions
200 08:21:55.726292 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 08:21:55.726509 Using /lava-784956 at stage 0
202 08:21:55.727619 uuid=784956_1.6.2.4.1 testdef=None
203 08:21:55.727915 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 08:21:55.728202 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 08:21:55.729946 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 08:21:55.730719 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 08:21:55.732840 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 08:21:55.733656 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 08:21:55.735673 runner path: /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 784956_1.6.2.4.1
212 08:21:55.736274 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 08:21:55.737022 Creating lava-test-runner.conf files
215 08:21:55.737220 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/784956/lava-overlay-ntphr8g8/lava-784956/0 for stage 0
216 08:21:55.737545 - 0_v4l2-decoder-conformance-vp9
217 08:21:55.737877 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 08:21:55.738145 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 08:21:55.759471 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 08:21:55.759817 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 08:21:55.760098 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 08:21:55.760361 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 08:21:55.760620 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 08:21:56.372610 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 08:21:56.373071 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 08:21:56.373317 extracting modules file /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/modules/modules.tar to /var/lib/lava/dispatcher/tmp/784956/extract-nfsrootfs-02gnh_w1
227 08:21:57.729084 extracting modules file /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/modules/modules.tar to /var/lib/lava/dispatcher/tmp/784956/extract-overlay-ramdisk-ateglckz/ramdisk
228 08:21:59.117895 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 08:21:59.118371 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 08:21:59.118647 [common] Applying overlay to NFS
231 08:21:59.118858 [common] Applying overlay /var/lib/lava/dispatcher/tmp/784956/compress-overlay-txypxwd_/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/784956/extract-nfsrootfs-02gnh_w1
232 08:21:59.147675 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 08:21:59.148056 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 08:21:59.148330 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 08:21:59.148554 Converting downloaded kernel to a uImage
236 08:21:59.148864 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/kernel/Image /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/kernel/uImage
237 08:21:59.622350 output: Image Name:
238 08:21:59.622777 output: Created: Tue Oct 1 08:21:59 2024
239 08:21:59.622985 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 08:21:59.623189 output: Data Size: 45779456 Bytes = 44706.50 KiB = 43.66 MiB
241 08:21:59.623389 output: Load Address: 01080000
242 08:21:59.623586 output: Entry Point: 01080000
243 08:21:59.623782 output:
244 08:21:59.624150 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 08:21:59.624429 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 08:21:59.624699 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 08:21:59.624951 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 08:21:59.625207 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 08:21:59.625461 Building ramdisk /var/lib/lava/dispatcher/tmp/784956/extract-overlay-ramdisk-ateglckz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/784956/extract-overlay-ramdisk-ateglckz/ramdisk
250 08:22:01.760735 >> 166898 blocks
251 08:22:09.439605 Adding RAMdisk u-boot header.
252 08:22:09.440333 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/784956/extract-overlay-ramdisk-ateglckz/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/784956/extract-overlay-ramdisk-ateglckz/ramdisk.cpio.gz.uboot
253 08:22:09.686994 output: Image Name:
254 08:22:09.687444 output: Created: Tue Oct 1 08:22:09 2024
255 08:22:09.687947 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 08:22:09.688481 output: Data Size: 23437633 Bytes = 22888.31 KiB = 22.35 MiB
257 08:22:09.688937 output: Load Address: 00000000
258 08:22:09.689380 output: Entry Point: 00000000
259 08:22:09.689816 output:
260 08:22:09.690847 rename /var/lib/lava/dispatcher/tmp/784956/extract-overlay-ramdisk-ateglckz/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/ramdisk/ramdisk.cpio.gz.uboot
261 08:22:09.691631 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 08:22:09.692285 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 08:22:09.692887 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 08:22:09.693414 No LXC device requested
265 08:22:09.693983 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 08:22:09.694552 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 08:22:09.695106 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 08:22:09.695570 Checking files for TFTP limit of 4294967296 bytes.
269 08:22:09.698519 end: 1 tftp-deploy (duration 00:01:03) [common]
270 08:22:09.699157 start: 2 uboot-action (timeout 00:05:00) [common]
271 08:22:09.699752 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 08:22:09.700362 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 08:22:09.700932 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 08:22:09.701516 Using kernel file from prepare-kernel: 784956/tftp-deploy-mlirw_rs/kernel/uImage
275 08:22:09.702210 substitutions:
276 08:22:09.702665 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 08:22:09.703110 - {DTB_ADDR}: 0x01070000
278 08:22:09.703549 - {DTB}: 784956/tftp-deploy-mlirw_rs/dtb/meson-g12b-a311d-libretech-cc.dtb
279 08:22:09.704050 - {INITRD}: 784956/tftp-deploy-mlirw_rs/ramdisk/ramdisk.cpio.gz.uboot
280 08:22:09.704511 - {KERNEL_ADDR}: 0x01080000
281 08:22:09.704954 - {KERNEL}: 784956/tftp-deploy-mlirw_rs/kernel/uImage
282 08:22:09.705394 - {LAVA_MAC}: None
283 08:22:09.705874 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/784956/extract-nfsrootfs-02gnh_w1
284 08:22:09.706318 - {NFS_SERVER_IP}: 192.168.6.2
285 08:22:09.706751 - {PRESEED_CONFIG}: None
286 08:22:09.707185 - {PRESEED_LOCAL}: None
287 08:22:09.707618 - {RAMDISK_ADDR}: 0x08000000
288 08:22:09.708073 - {RAMDISK}: 784956/tftp-deploy-mlirw_rs/ramdisk/ramdisk.cpio.gz.uboot
289 08:22:09.708510 - {ROOT_PART}: None
290 08:22:09.708945 - {ROOT}: None
291 08:22:09.709372 - {SERVER_IP}: 192.168.6.2
292 08:22:09.709803 - {TEE_ADDR}: 0x83000000
293 08:22:09.710234 - {TEE}: None
294 08:22:09.710663 Parsed boot commands:
295 08:22:09.711084 - setenv autoload no
296 08:22:09.711513 - setenv initrd_high 0xffffffff
297 08:22:09.711939 - setenv fdt_high 0xffffffff
298 08:22:09.712396 - dhcp
299 08:22:09.712827 - setenv serverip 192.168.6.2
300 08:22:09.713251 - tftpboot 0x01080000 784956/tftp-deploy-mlirw_rs/kernel/uImage
301 08:22:09.713681 - tftpboot 0x08000000 784956/tftp-deploy-mlirw_rs/ramdisk/ramdisk.cpio.gz.uboot
302 08:22:09.714108 - tftpboot 0x01070000 784956/tftp-deploy-mlirw_rs/dtb/meson-g12b-a311d-libretech-cc.dtb
303 08:22:09.714534 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/784956/extract-nfsrootfs-02gnh_w1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 08:22:09.714977 - bootm 0x01080000 0x08000000 0x01070000
305 08:22:09.715529 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 08:22:09.717241 start: 2.3 connect-device (timeout 00:05:00) [common]
308 08:22:09.717711 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 08:22:09.732993 Setting prompt string to ['lava-test: # ']
310 08:22:09.734574 end: 2.3 connect-device (duration 00:00:00) [common]
311 08:22:09.735232 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 08:22:09.735836 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 08:22:09.736497 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 08:22:09.737749 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 08:22:09.783910 >> OK - accepted request
316 08:22:09.786039 Returned 0 in 0 seconds
317 08:22:09.887194 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 08:22:09.888998 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 08:22:09.889678 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 08:22:09.890267 Setting prompt string to ['Hit any key to stop autoboot']
322 08:22:09.890796 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 08:22:09.892549 Trying 192.168.56.21...
324 08:22:09.893084 Connected to conserv1.
325 08:22:09.893565 Escape character is '^]'.
326 08:22:09.894033
327 08:22:09.894515 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 08:22:09.894986
329 08:22:20.610701 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 08:22:20.611336 bl2_stage_init 0x01
331 08:22:20.611792 bl2_stage_init 0x81
332 08:22:20.616252 hw id: 0x0000 - pwm id 0x01
333 08:22:20.616744 bl2_stage_init 0xc1
334 08:22:20.617179 bl2_stage_init 0x02
335 08:22:20.617610
336 08:22:20.621687 L0:00000000
337 08:22:20.622153 L1:20000703
338 08:22:20.622600 L2:00008067
339 08:22:20.623027 L3:14000000
340 08:22:20.624614 B2:00402000
341 08:22:20.625073 B1:e0f83180
342 08:22:20.625517
343 08:22:20.625949 TE: 58159
344 08:22:20.626381
345 08:22:20.635834 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 08:22:20.636332
347 08:22:20.636763 Board ID = 1
348 08:22:20.637189 Set A53 clk to 24M
349 08:22:20.637610 Set A73 clk to 24M
350 08:22:20.641333 Set clk81 to 24M
351 08:22:20.641792 A53 clk: 1200 MHz
352 08:22:20.642221 A73 clk: 1200 MHz
353 08:22:20.644923 CLK81: 166.6M
354 08:22:20.645377 smccc: 00012ab5
355 08:22:20.650595 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 08:22:20.656166 board id: 1
357 08:22:20.661355 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 08:22:20.671726 fw parse done
359 08:22:20.677710 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 08:22:20.720354 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 08:22:20.731359 PIEI prepare done
362 08:22:20.731808 fastboot data load
363 08:22:20.732293 fastboot data verify
364 08:22:20.736860 verify result: 266
365 08:22:20.742598 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 08:22:20.743065 LPDDR4 probe
367 08:22:20.743517 ddr clk to 1584MHz
368 08:22:20.750533 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 08:22:20.787718
370 08:22:20.788229 dmc_version 0001
371 08:22:20.794499 Check phy result
372 08:22:20.800393 INFO : End of CA training
373 08:22:20.800860 INFO : End of initialization
374 08:22:20.805933 INFO : Training has run successfully!
375 08:22:20.806403 Check phy result
376 08:22:20.811526 INFO : End of initialization
377 08:22:20.812030 INFO : End of read enable training
378 08:22:20.814780 INFO : End of fine write leveling
379 08:22:20.820426 INFO : End of Write leveling coarse delay
380 08:22:20.825911 INFO : Training has run successfully!
381 08:22:20.826376 Check phy result
382 08:22:20.826816 INFO : End of initialization
383 08:22:20.831484 INFO : End of read dq deskew training
384 08:22:20.837168 INFO : End of MPR read delay center optimization
385 08:22:20.837644 INFO : End of write delay center optimization
386 08:22:20.842755 INFO : End of read delay center optimization
387 08:22:20.848392 INFO : End of max read latency training
388 08:22:20.848856 INFO : Training has run successfully!
389 08:22:20.853989 1D training succeed
390 08:22:20.859963 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 08:22:20.907487 Check phy result
392 08:22:20.907964 INFO : End of initialization
393 08:22:20.929926 INFO : End of 2D read delay Voltage center optimization
394 08:22:20.950038 INFO : End of 2D read delay Voltage center optimization
395 08:22:21.001976 INFO : End of 2D write delay Voltage center optimization
396 08:22:21.051229 INFO : End of 2D write delay Voltage center optimization
397 08:22:21.056810 INFO : Training has run successfully!
398 08:22:21.057274
399 08:22:21.057740 channel==0
400 08:22:21.062511 RxClkDly_Margin_A0==98 ps 10
401 08:22:21.062976 TxDqDly_Margin_A0==98 ps 10
402 08:22:21.068057 RxClkDly_Margin_A1==88 ps 9
403 08:22:21.068540 TxDqDly_Margin_A1==88 ps 9
404 08:22:21.068985 TrainedVREFDQ_A0==74
405 08:22:21.073615 TrainedVREFDQ_A1==74
406 08:22:21.074082 VrefDac_Margin_A0==25
407 08:22:21.074525 DeviceVref_Margin_A0==40
408 08:22:21.079219 VrefDac_Margin_A1==24
409 08:22:21.079679 DeviceVref_Margin_A1==40
410 08:22:21.080153
411 08:22:21.080604
412 08:22:21.084804 channel==1
413 08:22:21.085273 RxClkDly_Margin_A0==98 ps 10
414 08:22:21.085716 TxDqDly_Margin_A0==98 ps 10
415 08:22:21.090505 RxClkDly_Margin_A1==98 ps 10
416 08:22:21.090968 TxDqDly_Margin_A1==88 ps 9
417 08:22:21.095954 TrainedVREFDQ_A0==77
418 08:22:21.096449 TrainedVREFDQ_A1==77
419 08:22:21.096897 VrefDac_Margin_A0==22
420 08:22:21.101630 DeviceVref_Margin_A0==37
421 08:22:21.102095 VrefDac_Margin_A1==22
422 08:22:21.107175 DeviceVref_Margin_A1==37
423 08:22:21.107636
424 08:22:21.108115 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 08:22:21.112787
426 08:22:21.140760 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 08:22:21.141300 2D training succeed
428 08:22:21.146400 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 08:22:21.151921 auto size-- 65535DDR cs0 size: 2048MB
430 08:22:21.152414 DDR cs1 size: 2048MB
431 08:22:21.157521 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 08:22:21.157985 cs0 DataBus test pass
433 08:22:21.163153 cs1 DataBus test pass
434 08:22:21.163617 cs0 AddrBus test pass
435 08:22:21.164097 cs1 AddrBus test pass
436 08:22:21.164543
437 08:22:21.168740 100bdlr_step_size ps== 420
438 08:22:21.169224 result report
439 08:22:21.174397 boot times 0Enable ddr reg access
440 08:22:21.179775 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 08:22:21.193229 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 08:22:21.765108 0.0;M3 CHK:0;cm4_sp_mode 0
443 08:22:21.765602 MVN_1=0x00000000
444 08:22:21.770624 MVN_2=0x00000000
445 08:22:21.776417 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 08:22:21.776882 OPS=0x10
447 08:22:21.777326 ring efuse init
448 08:22:21.777764 chipver efuse init
449 08:22:21.782001 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 08:22:21.787584 [0.018961 Inits done]
451 08:22:21.788089 secure task start!
452 08:22:21.788537 high task start!
453 08:22:21.792193 low task start!
454 08:22:21.792660 run into bl31
455 08:22:21.798839 NOTICE: BL31: v1.3(release):4fc40b1
456 08:22:21.806634 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 08:22:21.807106 NOTICE: BL31: G12A normal boot!
458 08:22:21.832010 NOTICE: BL31: BL33 decompress pass
459 08:22:21.837692 ERROR: Error initializing runtime service opteed_fast
460 08:22:23.070726
461 08:22:23.071238
462 08:22:23.079012 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 08:22:23.079495
464 08:22:23.079943 Model: Libre Computer AML-A311D-CC Alta
465 08:22:23.287498 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 08:22:23.310802 DRAM: 2 GiB (effective 3.8 GiB)
467 08:22:23.453851 Core: 408 devices, 31 uclasses, devicetree: separate
468 08:22:23.459693 WDT: Not starting watchdog@f0d0
469 08:22:23.491935 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 08:22:23.504434 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 08:22:23.509423 ** Bad device specification mmc 0 **
472 08:22:23.519736 Card did not respond to voltage select! : -110
473 08:22:23.527446 ** Bad device specification mmc 0 **
474 08:22:23.527951 Couldn't find partition mmc 0
475 08:22:23.535744 Card did not respond to voltage select! : -110
476 08:22:23.541270 ** Bad device specification mmc 0 **
477 08:22:23.541776 Couldn't find partition mmc 0
478 08:22:23.546324 Error: could not access storage.
479 08:22:24.810835 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 08:22:24.811541 bl2_stage_init 0x01
481 08:22:24.812092 bl2_stage_init 0x81
482 08:22:24.816248 hw id: 0x0000 - pwm id 0x01
483 08:22:24.816792 bl2_stage_init 0xc1
484 08:22:24.817261 bl2_stage_init 0x02
485 08:22:24.817723
486 08:22:24.822019 L0:00000000
487 08:22:24.822702 L1:20000703
488 08:22:24.823219 L2:00008067
489 08:22:24.823733 L3:14000000
490 08:22:24.824892 B2:00402000
491 08:22:24.825402 B1:e0f83180
492 08:22:24.825881
493 08:22:24.826142 TE: 58124
494 08:22:24.826359
495 08:22:24.836059 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 08:22:24.836710
497 08:22:24.837227 Board ID = 1
498 08:22:24.837722 Set A53 clk to 24M
499 08:22:24.838184 Set A73 clk to 24M
500 08:22:24.841684 Set clk81 to 24M
501 08:22:24.842286 A53 clk: 1200 MHz
502 08:22:24.842762 A73 clk: 1200 MHz
503 08:22:24.847235 CLK81: 166.6M
504 08:22:24.847758 smccc: 00012a91
505 08:22:24.852825 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 08:22:24.853345 board id: 1
507 08:22:24.861355 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 08:22:24.872011 fw parse done
509 08:22:24.877992 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 08:22:24.920676 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 08:22:24.931496 PIEI prepare done
512 08:22:24.932018 fastboot data load
513 08:22:24.932486 fastboot data verify
514 08:22:24.937113 verify result: 266
515 08:22:24.942706 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 08:22:24.943180 LPDDR4 probe
517 08:22:24.943628 ddr clk to 1584MHz
518 08:22:24.950681 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 08:22:24.987950
520 08:22:24.988452 dmc_version 0001
521 08:22:24.994591 Check phy result
522 08:22:25.000494 INFO : End of CA training
523 08:22:25.000960 INFO : End of initialization
524 08:22:25.006075 INFO : Training has run successfully!
525 08:22:25.006544 Check phy result
526 08:22:25.011666 INFO : End of initialization
527 08:22:25.012180 INFO : End of read enable training
528 08:22:25.017306 INFO : End of fine write leveling
529 08:22:25.022921 INFO : End of Write leveling coarse delay
530 08:22:25.023391 INFO : Training has run successfully!
531 08:22:25.023837 Check phy result
532 08:22:25.028486 INFO : End of initialization
533 08:22:25.028955 INFO : End of read dq deskew training
534 08:22:25.034066 INFO : End of MPR read delay center optimization
535 08:22:25.039656 INFO : End of write delay center optimization
536 08:22:25.045288 INFO : End of read delay center optimization
537 08:22:25.045762 INFO : End of max read latency training
538 08:22:25.050918 INFO : Training has run successfully!
539 08:22:25.051390 1D training succeed
540 08:22:25.060070 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 08:22:25.107647 Check phy result
542 08:22:25.108148 INFO : End of initialization
543 08:22:25.129381 INFO : End of 2D read delay Voltage center optimization
544 08:22:25.149712 INFO : End of 2D read delay Voltage center optimization
545 08:22:25.201743 INFO : End of 2D write delay Voltage center optimization
546 08:22:25.251035 INFO : End of 2D write delay Voltage center optimization
547 08:22:25.256650 INFO : Training has run successfully!
548 08:22:25.257130
549 08:22:25.257583 channel==0
550 08:22:25.262234 RxClkDly_Margin_A0==88 ps 9
551 08:22:25.262720 TxDqDly_Margin_A0==98 ps 10
552 08:22:25.267896 RxClkDly_Margin_A1==88 ps 9
553 08:22:25.268467 TxDqDly_Margin_A1==98 ps 10
554 08:22:25.268926 TrainedVREFDQ_A0==74
555 08:22:25.273423 TrainedVREFDQ_A1==74
556 08:22:25.273908 VrefDac_Margin_A0==25
557 08:22:25.274353 DeviceVref_Margin_A0==40
558 08:22:25.279052 VrefDac_Margin_A1==25
559 08:22:25.279520 DeviceVref_Margin_A1==40
560 08:22:25.279962
561 08:22:25.280440
562 08:22:25.284698 channel==1
563 08:22:25.285195 RxClkDly_Margin_A0==98 ps 10
564 08:22:25.285649 TxDqDly_Margin_A0==98 ps 10
565 08:22:25.290208 RxClkDly_Margin_A1==88 ps 9
566 08:22:25.290680 TxDqDly_Margin_A1==108 ps 11
567 08:22:25.295880 TrainedVREFDQ_A0==77
568 08:22:25.296402 TrainedVREFDQ_A1==78
569 08:22:25.296853 VrefDac_Margin_A0==22
570 08:22:25.301415 DeviceVref_Margin_A0==37
571 08:22:25.301884 VrefDac_Margin_A1==24
572 08:22:25.307032 DeviceVref_Margin_A1==36
573 08:22:25.307499
574 08:22:25.307942 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 08:22:25.312679
576 08:22:25.340696 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 08:22:25.341223 2D training succeed
578 08:22:25.346221 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 08:22:25.351905 auto size-- 65535DDR cs0 size: 2048MB
580 08:22:25.352413 DDR cs1 size: 2048MB
581 08:22:25.357428 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 08:22:25.357899 cs0 DataBus test pass
583 08:22:25.363031 cs1 DataBus test pass
584 08:22:25.363498 cs0 AddrBus test pass
585 08:22:25.363940 cs1 AddrBus test pass
586 08:22:25.364423
587 08:22:25.368663 100bdlr_step_size ps== 420
588 08:22:25.369154 result report
589 08:22:25.374224 boot times 0Enable ddr reg access
590 08:22:25.379807 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 08:22:25.393239 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 08:22:25.966376 0.0;M3 CHK:0;cm4_sp_mode 0
593 08:22:25.966988 MVN_1=0x00000000
594 08:22:25.971810 MVN_2=0x00000000
595 08:22:25.977573 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 08:22:25.978114 OPS=0x10
597 08:22:25.978587 ring efuse init
598 08:22:25.979073 chipver efuse init
599 08:22:25.983231 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 08:22:25.988805 [0.018961 Inits done]
601 08:22:25.989288 secure task start!
602 08:22:25.989723 high task start!
603 08:22:25.993325 low task start!
604 08:22:25.993791 run into bl31
605 08:22:26.000048 NOTICE: BL31: v1.3(release):4fc40b1
606 08:22:26.007810 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 08:22:26.008314 NOTICE: BL31: G12A normal boot!
608 08:22:26.033219 NOTICE: BL31: BL33 decompress pass
609 08:22:26.038884 ERROR: Error initializing runtime service opteed_fast
610 08:22:27.271958
611 08:22:27.272679
612 08:22:27.280454 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 08:22:27.280969
614 08:22:27.281435 Model: Libre Computer AML-A311D-CC Alta
615 08:22:27.488779 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 08:22:27.512182 DRAM: 2 GiB (effective 3.8 GiB)
617 08:22:27.655213 Core: 408 devices, 31 uclasses, devicetree: separate
618 08:22:27.660958 WDT: Not starting watchdog@f0d0
619 08:22:27.693123 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 08:22:27.705653 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 08:22:27.710667 ** Bad device specification mmc 0 **
622 08:22:27.720930 Card did not respond to voltage select! : -110
623 08:22:27.728579 ** Bad device specification mmc 0 **
624 08:22:27.729064 Couldn't find partition mmc 0
625 08:22:27.737188 Card did not respond to voltage select! : -110
626 08:22:27.742513 ** Bad device specification mmc 0 **
627 08:22:27.742999 Couldn't find partition mmc 0
628 08:22:27.747516 Error: could not access storage.
629 08:22:28.090038 Net: eth0: ethernet@ff3f0000
630 08:22:28.090683 starting USB...
631 08:22:28.341763 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 08:22:28.342335 Starting the controller
633 08:22:28.348809 USB XHCI 1.10
634 08:22:30.061037 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 08:22:30.061674 bl2_stage_init 0x01
636 08:22:30.062150 bl2_stage_init 0x81
637 08:22:30.066603 hw id: 0x0000 - pwm id 0x01
638 08:22:30.067095 bl2_stage_init 0xc1
639 08:22:30.067550 bl2_stage_init 0x02
640 08:22:30.068085
641 08:22:30.072268 L0:00000000
642 08:22:30.072767 L1:20000703
643 08:22:30.073240 L2:00008067
644 08:22:30.073688 L3:14000000
645 08:22:30.078173 B2:00402000
646 08:22:30.078672 B1:e0f83180
647 08:22:30.079126
648 08:22:30.079613 TE: 58124
649 08:22:30.080170
650 08:22:30.083402 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 08:22:30.083925
652 08:22:30.084430 Board ID = 1
653 08:22:30.088995 Set A53 clk to 24M
654 08:22:30.089484 Set A73 clk to 24M
655 08:22:30.089938 Set clk81 to 24M
656 08:22:30.094677 A53 clk: 1200 MHz
657 08:22:30.095170 A73 clk: 1200 MHz
658 08:22:30.095621 CLK81: 166.6M
659 08:22:30.096104 smccc: 00012a92
660 08:22:30.100244 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 08:22:30.105806 board id: 1
662 08:22:30.111705 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 08:22:30.122475 fw parse done
664 08:22:30.128369 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 08:22:30.170944 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 08:22:30.181901 PIEI prepare done
667 08:22:30.182578 fastboot data load
668 08:22:30.183069 fastboot data verify
669 08:22:30.187466 verify result: 266
670 08:22:30.193020 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 08:22:30.193574 LPDDR4 probe
672 08:22:30.194052 ddr clk to 1584MHz
673 08:22:30.201074 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 08:22:30.238356
675 08:22:30.238940 dmc_version 0001
676 08:22:30.245296 Check phy result
677 08:22:30.250992 INFO : End of CA training
678 08:22:30.251532 INFO : End of initialization
679 08:22:30.256653 INFO : Training has run successfully!
680 08:22:30.257245 Check phy result
681 08:22:30.262799 INFO : End of initialization
682 08:22:30.263396 INFO : End of read enable training
683 08:22:30.267750 INFO : End of fine write leveling
684 08:22:30.273263 INFO : End of Write leveling coarse delay
685 08:22:30.273794 INFO : Training has run successfully!
686 08:22:30.274214 Check phy result
687 08:22:30.278823 INFO : End of initialization
688 08:22:30.279316 INFO : End of read dq deskew training
689 08:22:30.284608 INFO : End of MPR read delay center optimization
690 08:22:30.290088 INFO : End of write delay center optimization
691 08:22:30.295683 INFO : End of read delay center optimization
692 08:22:30.296285 INFO : End of max read latency training
693 08:22:30.301297 INFO : Training has run successfully!
694 08:22:30.301834 1D training succeed
695 08:22:30.310443 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 08:22:30.358155 Check phy result
697 08:22:30.358781 INFO : End of initialization
698 08:22:30.380526 INFO : End of 2D read delay Voltage center optimization
699 08:22:30.399834 INFO : End of 2D read delay Voltage center optimization
700 08:22:30.451773 INFO : End of 2D write delay Voltage center optimization
701 08:22:30.500900 INFO : End of 2D write delay Voltage center optimization
702 08:22:30.506414 INFO : Training has run successfully!
703 08:22:30.506893
704 08:22:30.507320 channel==0
705 08:22:30.512014 RxClkDly_Margin_A0==88 ps 9
706 08:22:30.512478 TxDqDly_Margin_A0==98 ps 10
707 08:22:30.517625 RxClkDly_Margin_A1==88 ps 9
708 08:22:30.518081 TxDqDly_Margin_A1==98 ps 10
709 08:22:30.518501 TrainedVREFDQ_A0==74
710 08:22:30.523214 TrainedVREFDQ_A1==74
711 08:22:30.523682 VrefDac_Margin_A0==24
712 08:22:30.524130 DeviceVref_Margin_A0==40
713 08:22:30.528810 VrefDac_Margin_A1==24
714 08:22:30.529279 DeviceVref_Margin_A1==40
715 08:22:30.529694
716 08:22:30.530105
717 08:22:30.534394 channel==1
718 08:22:30.534848 RxClkDly_Margin_A0==88 ps 9
719 08:22:30.535263 TxDqDly_Margin_A0==98 ps 10
720 08:22:30.540011 RxClkDly_Margin_A1==88 ps 9
721 08:22:30.540474 TxDqDly_Margin_A1==108 ps 11
722 08:22:30.545637 TrainedVREFDQ_A0==77
723 08:22:30.546098 TrainedVREFDQ_A1==78
724 08:22:30.546518 VrefDac_Margin_A0==23
725 08:22:30.551197 DeviceVref_Margin_A0==37
726 08:22:30.551652 VrefDac_Margin_A1==24
727 08:22:30.556812 DeviceVref_Margin_A1==36
728 08:22:30.557264
729 08:22:30.557680 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 08:22:30.562434
731 08:22:30.590449 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 08:22:30.591027 2D training succeed
733 08:22:30.596039 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 08:22:30.601654 auto size-- 65535DDR cs0 size: 2048MB
735 08:22:30.602117 DDR cs1 size: 2048MB
736 08:22:30.607225 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 08:22:30.607685 cs0 DataBus test pass
738 08:22:30.612784 cs1 DataBus test pass
739 08:22:30.613235 cs0 AddrBus test pass
740 08:22:30.613649 cs1 AddrBus test pass
741 08:22:30.614055
742 08:22:30.618405 100bdlr_step_size ps== 420
743 08:22:30.618871 result report
744 08:22:30.624017 boot times 0Enable ddr reg access
745 08:22:30.629472 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 08:22:30.642898 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 08:22:31.214967 0.0;M3 CHK:0;cm4_sp_mode 0
748 08:22:31.215594 MVN_1=0x00000000
749 08:22:31.220423 MVN_2=0x00000000
750 08:22:31.226161 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 08:22:31.226690 OPS=0x10
752 08:22:31.227091 ring efuse init
753 08:22:31.227481 chipver efuse init
754 08:22:31.231718 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 08:22:31.237357 [0.018961 Inits done]
756 08:22:31.237903 secure task start!
757 08:22:31.238353 high task start!
758 08:22:31.241936 low task start!
759 08:22:31.242433 run into bl31
760 08:22:31.248689 NOTICE: BL31: v1.3(release):4fc40b1
761 08:22:31.256408 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 08:22:31.256908 NOTICE: BL31: G12A normal boot!
763 08:22:31.281775 NOTICE: BL31: BL33 decompress pass
764 08:22:31.287522 ERROR: Error initializing runtime service opteed_fast
765 08:22:32.520351
766 08:22:32.520925
767 08:22:32.528683 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 08:22:32.529094
769 08:22:32.529480 Model: Libre Computer AML-A311D-CC Alta
770 08:22:32.737137 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 08:22:32.760514 DRAM: 2 GiB (effective 3.8 GiB)
772 08:22:32.903594 Core: 408 devices, 31 uclasses, devicetree: separate
773 08:22:32.909319 WDT: Not starting watchdog@f0d0
774 08:22:32.941684 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 08:22:32.954047 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 08:22:32.959054 ** Bad device specification mmc 0 **
777 08:22:32.969402 Card did not respond to voltage select! : -110
778 08:22:32.977039 ** Bad device specification mmc 0 **
779 08:22:32.977438 Couldn't find partition mmc 0
780 08:22:32.985392 Card did not respond to voltage select! : -110
781 08:22:32.990862 ** Bad device specification mmc 0 **
782 08:22:32.991267 Couldn't find partition mmc 0
783 08:22:32.995974 Error: could not access storage.
784 08:22:33.338502 Net: eth0: ethernet@ff3f0000
785 08:22:33.338910 starting USB...
786 08:22:33.590302 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 08:22:33.590708 Starting the controller
788 08:22:33.597236 USB XHCI 1.10
789 08:22:35.762789 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 08:22:35.763221 bl2_stage_init 0x01
791 08:22:35.763471 bl2_stage_init 0x81
792 08:22:35.768406 hw id: 0x0000 - pwm id 0x01
793 08:22:35.768700 bl2_stage_init 0xc1
794 08:22:35.768942 bl2_stage_init 0x02
795 08:22:35.769181
796 08:22:35.773905 L0:00000000
797 08:22:35.774189 L1:20000703
798 08:22:35.774427 L2:00008067
799 08:22:35.774658 L3:14000000
800 08:22:35.779478 B2:00402000
801 08:22:35.779745 B1:e0f83180
802 08:22:35.780004
803 08:22:35.780239 TE: 58124
804 08:22:35.780457
805 08:22:35.785183 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 08:22:35.785565
807 08:22:35.785893 Board ID = 1
808 08:22:35.790718 Set A53 clk to 24M
809 08:22:35.791085 Set A73 clk to 24M
810 08:22:35.791406 Set clk81 to 24M
811 08:22:35.796406 A53 clk: 1200 MHz
812 08:22:35.796790 A73 clk: 1200 MHz
813 08:22:35.797109 CLK81: 166.6M
814 08:22:35.797457 smccc: 00012a92
815 08:22:35.801895 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 08:22:35.807390 board id: 1
817 08:22:35.813668 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 08:22:35.824107 fw parse done
819 08:22:35.830148 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 08:22:35.872530 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 08:22:35.883438 PIEI prepare done
822 08:22:35.883961 fastboot data load
823 08:22:35.884427 fastboot data verify
824 08:22:35.889109 verify result: 266
825 08:22:35.894620 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 08:22:35.895130 LPDDR4 probe
827 08:22:35.895549 ddr clk to 1584MHz
828 08:22:35.902648 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 08:22:35.939888
830 08:22:35.940485 dmc_version 0001
831 08:22:35.946524 Check phy result
832 08:22:35.952384 INFO : End of CA training
833 08:22:35.952909 INFO : End of initialization
834 08:22:35.957995 INFO : Training has run successfully!
835 08:22:35.958515 Check phy result
836 08:22:35.963568 INFO : End of initialization
837 08:22:35.964113 INFO : End of read enable training
838 08:22:35.969362 INFO : End of fine write leveling
839 08:22:35.974803 INFO : End of Write leveling coarse delay
840 08:22:35.975356 INFO : Training has run successfully!
841 08:22:35.975786 Check phy result
842 08:22:35.980423 INFO : End of initialization
843 08:22:35.980943 INFO : End of read dq deskew training
844 08:22:35.986009 INFO : End of MPR read delay center optimization
845 08:22:35.991607 INFO : End of write delay center optimization
846 08:22:35.997349 INFO : End of read delay center optimization
847 08:22:35.997800 INFO : End of max read latency training
848 08:22:36.002789 INFO : Training has run successfully!
849 08:22:36.003225 1D training succeed
850 08:22:36.011958 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 08:22:36.059600 Check phy result
852 08:22:36.060101 INFO : End of initialization
853 08:22:36.081319 INFO : End of 2D read delay Voltage center optimization
854 08:22:36.101554 INFO : End of 2D read delay Voltage center optimization
855 08:22:36.153612 INFO : End of 2D write delay Voltage center optimization
856 08:22:36.202927 INFO : End of 2D write delay Voltage center optimization
857 08:22:36.208461 INFO : Training has run successfully!
858 08:22:36.208898
859 08:22:36.209296 channel==0
860 08:22:36.214074 RxClkDly_Margin_A0==88 ps 9
861 08:22:36.214508 TxDqDly_Margin_A0==98 ps 10
862 08:22:36.219636 RxClkDly_Margin_A1==78 ps 8
863 08:22:36.220107 TxDqDly_Margin_A1==98 ps 10
864 08:22:36.220509 TrainedVREFDQ_A0==74
865 08:22:36.225324 TrainedVREFDQ_A1==74
866 08:22:36.225758 VrefDac_Margin_A0==25
867 08:22:36.226149 DeviceVref_Margin_A0==40
868 08:22:36.230839 VrefDac_Margin_A1==25
869 08:22:36.231266 DeviceVref_Margin_A1==40
870 08:22:36.231652
871 08:22:36.232069
872 08:22:36.236443 channel==1
873 08:22:36.236871 RxClkDly_Margin_A0==98 ps 10
874 08:22:36.237262 TxDqDly_Margin_A0==98 ps 10
875 08:22:36.242056 RxClkDly_Margin_A1==98 ps 10
876 08:22:36.242484 TxDqDly_Margin_A1==108 ps 11
877 08:22:36.247637 TrainedVREFDQ_A0==77
878 08:22:36.248087 TrainedVREFDQ_A1==77
879 08:22:36.248483 VrefDac_Margin_A0==22
880 08:22:36.253326 DeviceVref_Margin_A0==37
881 08:22:36.253751 VrefDac_Margin_A1==24
882 08:22:36.258829 DeviceVref_Margin_A1==37
883 08:22:36.259254
884 08:22:36.264466 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 08:22:36.264889
886 08:22:36.292494 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 08:22:36.292949 2D training succeed
888 08:22:36.298092 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 08:22:36.303654 auto size-- 65535DDR cs0 size: 2048MB
890 08:22:36.304107 DDR cs1 size: 2048MB
891 08:22:36.309347 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 08:22:36.309779 cs0 DataBus test pass
893 08:22:36.314872 cs1 DataBus test pass
894 08:22:36.315297 cs0 AddrBus test pass
895 08:22:36.315687 cs1 AddrBus test pass
896 08:22:36.316106
897 08:22:36.320459 100bdlr_step_size ps== 420
898 08:22:36.320893 result report
899 08:22:36.326086 boot times 0Enable ddr reg access
900 08:22:36.331679 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 08:22:36.345182 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 08:22:36.919032 0.0;M3 CHK:0;cm4_sp_mode 0
903 08:22:36.919635 MVN_1=0x00000000
904 08:22:36.924465 MVN_2=0x00000000
905 08:22:36.930200 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 08:22:36.930637 OPS=0x10
907 08:22:36.931038 ring efuse init
908 08:22:36.931430 chipver efuse init
909 08:22:36.935734 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 08:22:36.941423 [0.018960 Inits done]
911 08:22:36.941853 secure task start!
912 08:22:36.942247 high task start!
913 08:22:36.945923 low task start!
914 08:22:36.946348 run into bl31
915 08:22:36.952562 NOTICE: BL31: v1.3(release):4fc40b1
916 08:22:36.960359 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 08:22:36.960792 NOTICE: BL31: G12A normal boot!
918 08:22:36.985808 NOTICE: BL31: BL33 decompress pass
919 08:22:36.991548 ERROR: Error initializing runtime service opteed_fast
920 08:22:38.224441
921 08:22:38.225056
922 08:22:38.232760 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 08:22:38.233207
924 08:22:38.233612 Model: Libre Computer AML-A311D-CC Alta
925 08:22:38.441231 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 08:22:38.464573 DRAM: 2 GiB (effective 3.8 GiB)
927 08:22:38.607605 Core: 408 devices, 31 uclasses, devicetree: separate
928 08:22:38.613455 WDT: Not starting watchdog@f0d0
929 08:22:38.645809 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 08:22:38.658114 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 08:22:38.663094 ** Bad device specification mmc 0 **
932 08:22:38.673450 Card did not respond to voltage select! : -110
933 08:22:38.681050 ** Bad device specification mmc 0 **
934 08:22:38.681512 Couldn't find partition mmc 0
935 08:22:38.689450 Card did not respond to voltage select! : -110
936 08:22:38.694929 ** Bad device specification mmc 0 **
937 08:22:38.695397 Couldn't find partition mmc 0
938 08:22:38.699952 Error: could not access storage.
939 08:22:39.042525 Net: eth0: ethernet@ff3f0000
940 08:22:39.043131 starting USB...
941 08:22:39.294389 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 08:22:39.294983 Starting the controller
943 08:22:39.301279 USB XHCI 1.10
944 08:22:41.162850 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 08:22:41.163461 bl2_stage_init 0x01
946 08:22:41.163885 bl2_stage_init 0x81
947 08:22:41.168311 hw id: 0x0000 - pwm id 0x01
948 08:22:41.168761 bl2_stage_init 0xc1
949 08:22:41.169170 bl2_stage_init 0x02
950 08:22:41.169574
951 08:22:41.173865 L0:00000000
952 08:22:41.174304 L1:20000703
953 08:22:41.174714 L2:00008067
954 08:22:41.175117 L3:14000000
955 08:22:41.179487 B2:00402000
956 08:22:41.179917 B1:e0f83180
957 08:22:41.180358
958 08:22:41.180764 TE: 58124
959 08:22:41.181166
960 08:22:41.185108 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 08:22:41.185559
962 08:22:41.185973 Board ID = 1
963 08:22:41.190637 Set A53 clk to 24M
964 08:22:41.191077 Set A73 clk to 24M
965 08:22:41.191482 Set clk81 to 24M
966 08:22:41.196206 A53 clk: 1200 MHz
967 08:22:41.196644 A73 clk: 1200 MHz
968 08:22:41.197046 CLK81: 166.6M
969 08:22:41.197445 smccc: 00012a92
970 08:22:41.204726 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 08:22:41.205168 board id: 1
972 08:22:41.213336 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 08:22:41.223883 fw parse done
974 08:22:41.230010 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 08:22:41.272605 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 08:22:41.283475 PIEI prepare done
977 08:22:41.283905 fastboot data load
978 08:22:41.284352 fastboot data verify
979 08:22:41.289114 verify result: 266
980 08:22:41.294631 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 08:22:41.295051 LPDDR4 probe
982 08:22:41.295441 ddr clk to 1584MHz
983 08:22:41.302631 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 08:22:41.339907
985 08:22:41.340400 dmc_version 0001
986 08:22:41.346537 Check phy result
987 08:22:41.352387 INFO : End of CA training
988 08:22:41.352806 INFO : End of initialization
989 08:22:41.358123 INFO : Training has run successfully!
990 08:22:41.358537 Check phy result
991 08:22:41.363651 INFO : End of initialization
992 08:22:41.364180 INFO : End of read enable training
993 08:22:41.366895 INFO : End of fine write leveling
994 08:22:41.372471 INFO : End of Write leveling coarse delay
995 08:22:41.378207 INFO : Training has run successfully!
996 08:22:41.378684 Check phy result
997 08:22:41.379092 INFO : End of initialization
998 08:22:41.383730 INFO : End of read dq deskew training
999 08:22:41.389250 INFO : End of MPR read delay center optimization
1000 08:22:41.389735 INFO : End of write delay center optimization
1001 08:22:41.394920 INFO : End of read delay center optimization
1002 08:22:41.400455 INFO : End of max read latency training
1003 08:22:41.400918 INFO : Training has run successfully!
1004 08:22:41.406199 1D training succeed
1005 08:22:41.412088 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 08:22:41.459614 Check phy result
1007 08:22:41.460116 INFO : End of initialization
1008 08:22:41.481266 INFO : End of 2D read delay Voltage center optimization
1009 08:22:41.501337 INFO : End of 2D read delay Voltage center optimization
1010 08:22:41.553346 INFO : End of 2D write delay Voltage center optimization
1011 08:22:41.602496 INFO : End of 2D write delay Voltage center optimization
1012 08:22:41.607965 INFO : Training has run successfully!
1013 08:22:41.608462
1014 08:22:41.608878 channel==0
1015 08:22:41.613682 RxClkDly_Margin_A0==88 ps 9
1016 08:22:41.614127 TxDqDly_Margin_A0==98 ps 10
1017 08:22:41.619251 RxClkDly_Margin_A1==88 ps 9
1018 08:22:41.619687 TxDqDly_Margin_A1==88 ps 9
1019 08:22:41.620133 TrainedVREFDQ_A0==74
1020 08:22:41.624793 TrainedVREFDQ_A1==74
1021 08:22:41.625242 VrefDac_Margin_A0==25
1022 08:22:41.625651 DeviceVref_Margin_A0==40
1023 08:22:41.630441 VrefDac_Margin_A1==25
1024 08:22:41.630882 DeviceVref_Margin_A1==40
1025 08:22:41.631288
1026 08:22:41.631691
1027 08:22:41.632122 channel==1
1028 08:22:41.635960 RxClkDly_Margin_A0==98 ps 10
1029 08:22:41.636427 TxDqDly_Margin_A0==98 ps 10
1030 08:22:41.641545 RxClkDly_Margin_A1==98 ps 10
1031 08:22:41.641983 TxDqDly_Margin_A1==88 ps 9
1032 08:22:41.647231 TrainedVREFDQ_A0==77
1033 08:22:41.647676 TrainedVREFDQ_A1==77
1034 08:22:41.648121 VrefDac_Margin_A0==22
1035 08:22:41.652825 DeviceVref_Margin_A0==37
1036 08:22:41.653259 VrefDac_Margin_A1==22
1037 08:22:41.658390 DeviceVref_Margin_A1==37
1038 08:22:41.658824
1039 08:22:41.659231 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 08:22:41.659630
1041 08:22:41.692066 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
1042 08:22:41.692553 2D training succeed
1043 08:22:41.697623 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 08:22:41.703120 auto size-- 65535DDR cs0 size: 2048MB
1045 08:22:41.703569 DDR cs1 size: 2048MB
1046 08:22:41.708695 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 08:22:41.709140 cs0 DataBus test pass
1048 08:22:41.714295 cs1 DataBus test pass
1049 08:22:41.714733 cs0 AddrBus test pass
1050 08:22:41.715140 cs1 AddrBus test pass
1051 08:22:41.715541
1052 08:22:41.719880 100bdlr_step_size ps== 420
1053 08:22:41.720361 result report
1054 08:22:41.725467 boot times 0Enable ddr reg access
1055 08:22:41.730823 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 08:22:41.744318 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 08:22:42.316436 0.0;M3 CHK:0;cm4_sp_mode 0
1058 08:22:42.316998 MVN_1=0x00000000
1059 08:22:42.321871 MVN_2=0x00000000
1060 08:22:42.327621 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 08:22:42.328119 OPS=0x10
1062 08:22:42.328541 ring efuse init
1063 08:22:42.328949 chipver efuse init
1064 08:22:42.333209 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 08:22:42.338798 [0.018961 Inits done]
1066 08:22:42.339233 secure task start!
1067 08:22:42.339643 high task start!
1068 08:22:42.343397 low task start!
1069 08:22:42.343831 run into bl31
1070 08:22:42.350226 NOTICE: BL31: v1.3(release):4fc40b1
1071 08:22:42.357864 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 08:22:42.358306 NOTICE: BL31: G12A normal boot!
1073 08:22:42.383251 NOTICE: BL31: BL33 decompress pass
1074 08:22:42.388922 ERROR: Error initializing runtime service opteed_fast
1075 08:22:43.621924
1076 08:22:43.622521
1077 08:22:43.630266 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 08:22:43.630735
1079 08:22:43.631174 Model: Libre Computer AML-A311D-CC Alta
1080 08:22:43.839304 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 08:22:43.862099 DRAM: 2 GiB (effective 3.8 GiB)
1082 08:22:44.005184 Core: 408 devices, 31 uclasses, devicetree: separate
1083 08:22:44.010890 WDT: Not starting watchdog@f0d0
1084 08:22:44.043206 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 08:22:44.055615 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 08:22:44.060578 ** Bad device specification mmc 0 **
1087 08:22:44.070901 Card did not respond to voltage select! : -110
1088 08:22:44.078600 ** Bad device specification mmc 0 **
1089 08:22:44.079050 Couldn't find partition mmc 0
1090 08:22:44.086883 Card did not respond to voltage select! : -110
1091 08:22:44.092454 ** Bad device specification mmc 0 **
1092 08:22:44.092902 Couldn't find partition mmc 0
1093 08:22:44.097531 Error: could not access storage.
1094 08:22:44.439951 Net: eth0: ethernet@ff3f0000
1095 08:22:44.440538 starting USB...
1096 08:22:44.691813 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 08:22:44.692400 Starting the controller
1098 08:22:44.698738 USB XHCI 1.10
1099 08:22:46.253055 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 08:22:46.261243 scanning usb for storage devices... 0 Storage Device(s) found
1102 08:22:46.312747 Hit any key to stop autoboot: 1
1103 08:22:46.313491 end: 2.4.2 bootloader-interrupt (duration 00:00:36) [common]
1104 08:22:46.314052 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 08:22:46.314498 Setting prompt string to ['=>']
1106 08:22:46.314960 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 08:22:46.328685 0
1108 08:22:46.329522 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 08:22:46.329993 Sending with 10 millisecond of delay
1111 08:22:47.464364 => setenv autoload no
1112 08:22:47.475132 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 08:22:47.479961 setenv autoload no
1114 08:22:47.480713 Sending with 10 millisecond of delay
1116 08:22:49.277236 => setenv initrd_high 0xffffffff
1117 08:22:49.288041 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 08:22:49.288848 setenv initrd_high 0xffffffff
1119 08:22:49.289554 Sending with 10 millisecond of delay
1121 08:22:50.905511 => setenv fdt_high 0xffffffff
1122 08:22:50.916243 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1123 08:22:50.917013 setenv fdt_high 0xffffffff
1124 08:22:50.917711 Sending with 10 millisecond of delay
1126 08:22:51.209438 => dhcp
1127 08:22:51.220125 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 08:22:51.220893 dhcp
1129 08:22:51.221327 Speed: 1000, full duplex
1130 08:22:51.221739 BOOTP broadcast 1
1131 08:22:51.468635 BOOTP broadcast 2
1132 08:22:51.480805 DHCP client bound to address 192.168.6.33 (261 ms)
1133 08:22:51.481572 Sending with 10 millisecond of delay
1135 08:22:53.157728 => setenv serverip 192.168.6.2
1136 08:22:53.168513 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1137 08:22:53.169316 setenv serverip 192.168.6.2
1138 08:22:53.170019 Sending with 10 millisecond of delay
1140 08:22:56.893254 => tftpboot 0x01080000 784956/tftp-deploy-mlirw_rs/kernel/uImage
1141 08:22:56.904090 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1142 08:22:56.904991 tftpboot 0x01080000 784956/tftp-deploy-mlirw_rs/kernel/uImage
1143 08:22:56.905439 Speed: 1000, full duplex
1144 08:22:56.905842 Using ethernet@ff3f0000 device
1145 08:22:56.906852 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1146 08:22:56.912527 Filename '784956/tftp-deploy-mlirw_rs/kernel/uImage'.
1147 08:22:56.916359 Load address: 0x1080000
1148 08:23:00.244862 Loading: *################################################## 43.7 MiB
1149 08:23:00.245509 13.1 MiB/s
1150 08:23:00.245939 done
1151 08:23:00.249263 Bytes transferred = 45779520 (2ba8a40 hex)
1152 08:23:00.250022 Sending with 10 millisecond of delay
1154 08:23:04.938562 => tftpboot 0x08000000 784956/tftp-deploy-mlirw_rs/ramdisk/ramdisk.cpio.gz.uboot
1155 08:23:04.949367 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1156 08:23:04.950218 tftpboot 0x08000000 784956/tftp-deploy-mlirw_rs/ramdisk/ramdisk.cpio.gz.uboot
1157 08:23:04.950645 Speed: 1000, full duplex
1158 08:23:04.951047 Using ethernet@ff3f0000 device
1159 08:23:04.952235 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1160 08:23:04.960753 Filename '784956/tftp-deploy-mlirw_rs/ramdisk/ramdisk.cpio.gz.uboot'.
1161 08:23:04.961234 Load address: 0x8000000
1162 08:23:12.370225 Loading: *#####T ############################################ UDP wrong checksum 00000005 0000db9b
1163 08:23:17.372083 T UDP wrong checksum 00000005 0000db9b
1164 08:23:27.374184 T T UDP wrong checksum 00000005 0000db9b
1165 08:23:47.378096 T T T T UDP wrong checksum 00000005 0000db9b
1166 08:24:02.382273 T T
1167 08:24:02.382897 Retry count exceeded; starting again
1169 08:24:02.384395 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1172 08:24:02.386296 end: 2.4 uboot-commands (duration 00:01:53) [common]
1174 08:24:02.387680 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1176 08:24:02.388753 end: 2 uboot-action (duration 00:01:53) [common]
1178 08:24:02.390241 Cleaning after the job
1179 08:24:02.390777 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/ramdisk
1180 08:24:02.391945 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/kernel
1181 08:24:02.433300 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/dtb
1182 08:24:02.434143 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/nfsrootfs
1183 08:24:02.724574 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/784956/tftp-deploy-mlirw_rs/modules
1184 08:24:02.745635 start: 4.1 power-off (timeout 00:00:30) [common]
1185 08:24:02.746273 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1186 08:24:02.779477 >> OK - accepted request
1187 08:24:02.781535 Returned 0 in 0 seconds
1188 08:24:02.882203 end: 4.1 power-off (duration 00:00:00) [common]
1190 08:24:02.883078 start: 4.2 read-feedback (timeout 00:10:00) [common]
1191 08:24:02.883708 Listened to connection for namespace 'common' for up to 1s
1192 08:24:03.883666 Finalising connection for namespace 'common'
1193 08:24:03.884094 Disconnecting from shell: Finalise
1194 08:24:03.884384 =>
1195 08:24:03.985080 end: 4.2 read-feedback (duration 00:00:01) [common]
1196 08:24:03.985651 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/784956
1197 08:24:06.584912 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/784956
1198 08:24:06.585509 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.