Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:07:57.534875 lava-dispatcher, installed at version: 2024.01
2 06:07:57.535794 start: 0 validate
3 06:07:57.536391 Start time: 2024-10-02 06:07:57.536356+00:00 (UTC)
4 06:07:57.536996 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:07:57.537586 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 06:07:57.576520 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:07:57.577088 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 06:07:57.608145 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:07:57.608785 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:08:00.676812 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:08:00.677326 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 06:08:00.718653 validate duration: 3.18
14 06:08:00.719859 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:08:00.720516 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:08:00.721020 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:08:00.721782 Not decompressing ramdisk as can be used compressed.
18 06:08:00.722426 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 06:08:00.722794 saving as /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/ramdisk/rootfs.cpio.gz
20 06:08:00.723180 total size: 8181887 (7 MB)
21 06:08:00.762003 progress 0 % (0 MB)
22 06:08:00.773279 progress 5 % (0 MB)
23 06:08:00.783860 progress 10 % (0 MB)
24 06:08:00.791802 progress 15 % (1 MB)
25 06:08:00.797252 progress 20 % (1 MB)
26 06:08:00.803059 progress 25 % (1 MB)
27 06:08:00.808584 progress 30 % (2 MB)
28 06:08:00.814398 progress 35 % (2 MB)
29 06:08:00.819756 progress 40 % (3 MB)
30 06:08:00.825544 progress 45 % (3 MB)
31 06:08:00.830944 progress 50 % (3 MB)
32 06:08:00.836799 progress 55 % (4 MB)
33 06:08:00.842139 progress 60 % (4 MB)
34 06:08:00.847830 progress 65 % (5 MB)
35 06:08:00.853233 progress 70 % (5 MB)
36 06:08:00.858882 progress 75 % (5 MB)
37 06:08:00.864600 progress 80 % (6 MB)
38 06:08:00.870324 progress 85 % (6 MB)
39 06:08:00.875552 progress 90 % (7 MB)
40 06:08:00.881334 progress 95 % (7 MB)
41 06:08:00.886256 progress 100 % (7 MB)
42 06:08:00.886908 7 MB downloaded in 0.16 s (47.66 MB/s)
43 06:08:00.887460 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:08:00.888384 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:08:00.888676 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:08:00.888950 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:08:00.889428 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
49 06:08:00.889672 saving as /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/kernel/Image
50 06:08:00.889881 total size: 45713920 (43 MB)
51 06:08:00.890091 No compression specified
52 06:08:00.932807 progress 0 % (0 MB)
53 06:08:00.962574 progress 5 % (2 MB)
54 06:08:00.991807 progress 10 % (4 MB)
55 06:08:01.021279 progress 15 % (6 MB)
56 06:08:01.050616 progress 20 % (8 MB)
57 06:08:01.079393 progress 25 % (10 MB)
58 06:08:01.108670 progress 30 % (13 MB)
59 06:08:01.139564 progress 35 % (15 MB)
60 06:08:01.170378 progress 40 % (17 MB)
61 06:08:01.199903 progress 45 % (19 MB)
62 06:08:01.229991 progress 50 % (21 MB)
63 06:08:01.261850 progress 55 % (24 MB)
64 06:08:01.292301 progress 60 % (26 MB)
65 06:08:01.322779 progress 65 % (28 MB)
66 06:08:01.353428 progress 70 % (30 MB)
67 06:08:01.384116 progress 75 % (32 MB)
68 06:08:01.414607 progress 80 % (34 MB)
69 06:08:01.443959 progress 85 % (37 MB)
70 06:08:01.474643 progress 90 % (39 MB)
71 06:08:01.505564 progress 95 % (41 MB)
72 06:08:01.535647 progress 100 % (43 MB)
73 06:08:01.536212 43 MB downloaded in 0.65 s (67.45 MB/s)
74 06:08:01.536711 end: 1.2.1 http-download (duration 00:00:01) [common]
76 06:08:01.537533 end: 1.2 download-retry (duration 00:00:01) [common]
77 06:08:01.537811 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:08:01.538076 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:08:01.538554 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 06:08:01.538838 saving as /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/dtb/meson-g12b-a311d-libretech-cc.dtb
81 06:08:01.539047 total size: 54703 (0 MB)
82 06:08:01.539257 No compression specified
83 06:08:01.583575 progress 59 % (0 MB)
84 06:08:01.584740 progress 100 % (0 MB)
85 06:08:01.585345 0 MB downloaded in 0.05 s (1.13 MB/s)
86 06:08:01.585844 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:08:01.586702 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:08:01.586984 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:08:01.587261 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:08:01.587747 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
92 06:08:01.588042 saving as /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/modules/modules.tar
93 06:08:01.588269 total size: 11621068 (11 MB)
94 06:08:01.588490 Using unxz to decompress xz
95 06:08:01.625144 progress 0 % (0 MB)
96 06:08:01.698561 progress 5 % (0 MB)
97 06:08:01.777833 progress 10 % (1 MB)
98 06:08:01.865343 progress 15 % (1 MB)
99 06:08:01.942804 progress 20 % (2 MB)
100 06:08:02.027305 progress 25 % (2 MB)
101 06:08:02.110067 progress 30 % (3 MB)
102 06:08:02.190910 progress 35 % (3 MB)
103 06:08:02.265515 progress 40 % (4 MB)
104 06:08:02.343157 progress 45 % (5 MB)
105 06:08:02.420849 progress 50 % (5 MB)
106 06:08:02.497348 progress 55 % (6 MB)
107 06:08:02.577060 progress 60 % (6 MB)
108 06:08:02.662929 progress 65 % (7 MB)
109 06:08:02.745432 progress 70 % (7 MB)
110 06:08:02.837517 progress 75 % (8 MB)
111 06:08:02.932951 progress 80 % (8 MB)
112 06:08:03.014422 progress 85 % (9 MB)
113 06:08:03.089805 progress 90 % (10 MB)
114 06:08:03.162736 progress 95 % (10 MB)
115 06:08:03.239303 progress 100 % (11 MB)
116 06:08:03.251655 11 MB downloaded in 1.66 s (6.66 MB/s)
117 06:08:03.252713 end: 1.4.1 http-download (duration 00:00:02) [common]
119 06:08:03.254511 end: 1.4 download-retry (duration 00:00:02) [common]
120 06:08:03.255112 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 06:08:03.255700 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 06:08:03.256345 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:08:03.256933 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 06:08:03.257999 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1
125 06:08:03.258976 makedir: /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin
126 06:08:03.259732 makedir: /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/tests
127 06:08:03.260469 makedir: /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/results
128 06:08:03.261186 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-add-keys
129 06:08:03.262301 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-add-sources
130 06:08:03.263372 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-background-process-start
131 06:08:03.264477 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-background-process-stop
132 06:08:03.265570 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-common-functions
133 06:08:03.266567 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-echo-ipv4
134 06:08:03.267567 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-install-packages
135 06:08:03.268631 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-installed-packages
136 06:08:03.269617 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-os-build
137 06:08:03.270609 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-probe-channel
138 06:08:03.271584 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-probe-ip
139 06:08:03.272603 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-target-ip
140 06:08:03.273592 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-target-mac
141 06:08:03.274563 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-target-storage
142 06:08:03.275590 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-test-case
143 06:08:03.276632 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-test-event
144 06:08:03.277652 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-test-feedback
145 06:08:03.278650 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-test-raise
146 06:08:03.279638 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-test-reference
147 06:08:03.280672 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-test-runner
148 06:08:03.281651 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-test-set
149 06:08:03.282644 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-test-shell
150 06:08:03.283629 Updating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-install-packages (oe)
151 06:08:03.284833 Updating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/bin/lava-installed-packages (oe)
152 06:08:03.285773 Creating /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/environment
153 06:08:03.286561 LAVA metadata
154 06:08:03.287102 - LAVA_JOB_ID=790069
155 06:08:03.287582 - LAVA_DISPATCHER_IP=192.168.6.2
156 06:08:03.288439 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 06:08:03.290293 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 06:08:03.290894 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 06:08:03.291308 skipped lava-vland-overlay
160 06:08:03.291799 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 06:08:03.292354 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 06:08:03.292792 skipped lava-multinode-overlay
163 06:08:03.293276 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 06:08:03.293782 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 06:08:03.294261 Loading test definitions
166 06:08:03.294805 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 06:08:03.295245 Using /lava-790069 at stage 0
168 06:08:03.296887 uuid=790069_1.5.2.4.1 testdef=None
169 06:08:03.297238 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 06:08:03.297511 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 06:08:03.299335 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 06:08:03.300186 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 06:08:03.302495 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 06:08:03.303357 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 06:08:03.305617 runner path: /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/0/tests/0_dmesg test_uuid 790069_1.5.2.4.1
178 06:08:03.306211 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 06:08:03.307006 Creating lava-test-runner.conf files
181 06:08:03.307214 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/790069/lava-overlay-_680fvv1/lava-790069/0 for stage 0
182 06:08:03.307563 - 0_dmesg
183 06:08:03.307920 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 06:08:03.308254 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 06:08:03.332368 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 06:08:03.332819 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 06:08:03.333090 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 06:08:03.333361 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 06:08:03.333625 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 06:08:04.241781 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 06:08:04.242247 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 06:08:04.242514 extracting modules file /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/790069/extract-overlay-ramdisk-fsw5t08a/ramdisk
193 06:08:05.597425 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 06:08:05.597919 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 06:08:05.598218 [common] Applying overlay /var/lib/lava/dispatcher/tmp/790069/compress-overlay-ty4x1xdw/overlay-1.5.2.5.tar.gz to ramdisk
196 06:08:05.598447 [common] Applying overlay /var/lib/lava/dispatcher/tmp/790069/compress-overlay-ty4x1xdw/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/790069/extract-overlay-ramdisk-fsw5t08a/ramdisk
197 06:08:05.628463 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 06:08:05.628897 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 06:08:05.629196 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 06:08:05.629441 Converting downloaded kernel to a uImage
201 06:08:05.629765 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/kernel/Image /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/kernel/uImage
202 06:08:06.087440 output: Image Name:
203 06:08:06.087861 output: Created: Wed Oct 2 06:08:05 2024
204 06:08:06.088115 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 06:08:06.088324 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 06:08:06.088527 output: Load Address: 01080000
207 06:08:06.088726 output: Entry Point: 01080000
208 06:08:06.088924 output:
209 06:08:06.089256 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 06:08:06.089521 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 06:08:06.089788 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 06:08:06.090043 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 06:08:06.090296 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 06:08:06.090552 Building ramdisk /var/lib/lava/dispatcher/tmp/790069/extract-overlay-ramdisk-fsw5t08a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/790069/extract-overlay-ramdisk-fsw5t08a/ramdisk
215 06:08:08.555509 >> 181702 blocks
216 06:08:17.032636 Adding RAMdisk u-boot header.
217 06:08:17.033304 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/790069/extract-overlay-ramdisk-fsw5t08a/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/790069/extract-overlay-ramdisk-fsw5t08a/ramdisk.cpio.gz.uboot
218 06:08:17.362822 output: Image Name:
219 06:08:17.363244 output: Created: Wed Oct 2 06:08:17 2024
220 06:08:17.363471 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 06:08:17.363683 output: Data Size: 26060451 Bytes = 25449.66 KiB = 24.85 MiB
222 06:08:17.363888 output: Load Address: 00000000
223 06:08:17.364258 output: Entry Point: 00000000
224 06:08:17.364723 output:
225 06:08:17.365859 rename /var/lib/lava/dispatcher/tmp/790069/extract-overlay-ramdisk-fsw5t08a/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/ramdisk/ramdisk.cpio.gz.uboot
226 06:08:17.366651 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 06:08:17.367320 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 06:08:17.367959 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 06:08:17.368527 No LXC device requested
230 06:08:17.369095 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 06:08:17.369662 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 06:08:17.370223 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 06:08:17.370722 Checking files for TFTP limit of 4294967296 bytes.
234 06:08:17.373976 end: 1 tftp-deploy (duration 00:00:17) [common]
235 06:08:17.374662 start: 2 uboot-action (timeout 00:05:00) [common]
236 06:08:17.375324 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 06:08:17.375903 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 06:08:17.376554 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 06:08:17.377204 Using kernel file from prepare-kernel: 790069/tftp-deploy-g9ax95hw/kernel/uImage
240 06:08:17.377967 substitutions:
241 06:08:17.378485 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 06:08:17.378975 - {DTB_ADDR}: 0x01070000
243 06:08:17.379457 - {DTB}: 790069/tftp-deploy-g9ax95hw/dtb/meson-g12b-a311d-libretech-cc.dtb
244 06:08:17.379947 - {INITRD}: 790069/tftp-deploy-g9ax95hw/ramdisk/ramdisk.cpio.gz.uboot
245 06:08:17.380479 - {KERNEL_ADDR}: 0x01080000
246 06:08:17.380927 - {KERNEL}: 790069/tftp-deploy-g9ax95hw/kernel/uImage
247 06:08:17.381371 - {LAVA_MAC}: None
248 06:08:17.381899 - {PRESEED_CONFIG}: None
249 06:08:17.382398 - {PRESEED_LOCAL}: None
250 06:08:17.382877 - {RAMDISK_ADDR}: 0x08000000
251 06:08:17.383353 - {RAMDISK}: 790069/tftp-deploy-g9ax95hw/ramdisk/ramdisk.cpio.gz.uboot
252 06:08:17.383841 - {ROOT_PART}: None
253 06:08:17.384334 - {ROOT}: None
254 06:08:17.384777 - {SERVER_IP}: 192.168.6.2
255 06:08:17.385225 - {TEE_ADDR}: 0x83000000
256 06:08:17.385666 - {TEE}: None
257 06:08:17.386105 Parsed boot commands:
258 06:08:17.386538 - setenv autoload no
259 06:08:17.387016 - setenv initrd_high 0xffffffff
260 06:08:17.387497 - setenv fdt_high 0xffffffff
261 06:08:17.387977 - dhcp
262 06:08:17.388499 - setenv serverip 192.168.6.2
263 06:08:17.388982 - tftpboot 0x01080000 790069/tftp-deploy-g9ax95hw/kernel/uImage
264 06:08:17.389469 - tftpboot 0x08000000 790069/tftp-deploy-g9ax95hw/ramdisk/ramdisk.cpio.gz.uboot
265 06:08:17.389943 - tftpboot 0x01070000 790069/tftp-deploy-g9ax95hw/dtb/meson-g12b-a311d-libretech-cc.dtb
266 06:08:17.390520 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 06:08:17.391001 - bootm 0x01080000 0x08000000 0x01070000
268 06:08:17.391622 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 06:08:17.393457 start: 2.3 connect-device (timeout 00:05:00) [common]
271 06:08:17.394013 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 06:08:17.409679 Setting prompt string to ['lava-test: # ']
273 06:08:17.411304 end: 2.3 connect-device (duration 00:00:00) [common]
274 06:08:17.412025 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 06:08:17.412677 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 06:08:17.413274 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 06:08:17.414549 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 06:08:17.453222 >> OK - accepted request
279 06:08:17.455417 Returned 0 in 0 seconds
280 06:08:17.556697 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 06:08:17.558474 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 06:08:17.559107 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 06:08:17.559674 Setting prompt string to ['Hit any key to stop autoboot']
285 06:08:17.560249 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 06:08:17.562012 Trying 192.168.56.21...
287 06:08:17.562548 Connected to conserv1.
288 06:08:17.563018 Escape character is '^]'.
289 06:08:17.563492
290 06:08:17.563963 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 06:08:17.564496
292 06:08:29.004404 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 06:08:29.004845 bl2_stage_init 0x01
294 06:08:29.005065 bl2_stage_init 0x81
295 06:08:29.009927 hw id: 0x0000 - pwm id 0x01
296 06:08:29.010253 bl2_stage_init 0xc1
297 06:08:29.010461 bl2_stage_init 0x02
298 06:08:29.010669
299 06:08:29.015539 L0:00000000
300 06:08:29.015814 L1:20000703
301 06:08:29.016061 L2:00008067
302 06:08:29.016266 L3:14000000
303 06:08:29.018422 B2:00402000
304 06:08:29.018697 B1:e0f83180
305 06:08:29.018904
306 06:08:29.019102 TE: 58124
307 06:08:29.019298
308 06:08:29.029629 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 06:08:29.029951
310 06:08:29.030169 Board ID = 1
311 06:08:29.030378 Set A53 clk to 24M
312 06:08:29.030587 Set A73 clk to 24M
313 06:08:29.035300 Set clk81 to 24M
314 06:08:29.035607 A53 clk: 1200 MHz
315 06:08:29.035820 A73 clk: 1200 MHz
316 06:08:29.038855 CLK81: 166.6M
317 06:08:29.039148 smccc: 00012a92
318 06:08:29.044458 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 06:08:29.049838 board id: 1
320 06:08:29.054286 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 06:08:29.065569 fw parse done
322 06:08:29.070525 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 06:08:29.113184 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 06:08:29.125135 PIEI prepare done
325 06:08:29.125495 fastboot data load
326 06:08:29.125710 fastboot data verify
327 06:08:29.130705 verify result: 266
328 06:08:29.136377 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 06:08:29.136672 LPDDR4 probe
330 06:08:29.136877 ddr clk to 1584MHz
331 06:08:29.143330 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 06:08:29.180545
333 06:08:29.180908 dmc_version 0001
334 06:08:29.187185 Check phy result
335 06:08:29.194138 INFO : End of CA training
336 06:08:29.194436 INFO : End of initialization
337 06:08:29.199676 INFO : Training has run successfully!
338 06:08:29.199959 Check phy result
339 06:08:29.205280 INFO : End of initialization
340 06:08:29.205571 INFO : End of read enable training
341 06:08:29.208544 INFO : End of fine write leveling
342 06:08:29.214113 INFO : End of Write leveling coarse delay
343 06:08:29.219731 INFO : Training has run successfully!
344 06:08:29.220139 Check phy result
345 06:08:29.220373 INFO : End of initialization
346 06:08:29.225261 INFO : End of read dq deskew training
347 06:08:29.228652 INFO : End of MPR read delay center optimization
348 06:08:29.234297 INFO : End of write delay center optimization
349 06:08:29.239809 INFO : End of read delay center optimization
350 06:08:29.240110 INFO : End of max read latency training
351 06:08:29.245473 INFO : Training has run successfully!
352 06:08:29.245752 1D training succeed
353 06:08:29.252674 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 06:08:29.300649 Check phy result
355 06:08:29.301044 INFO : End of initialization
356 06:08:29.323909 INFO : End of 2D read delay Voltage center optimization
357 06:08:29.344275 INFO : End of 2D read delay Voltage center optimization
358 06:08:29.396368 INFO : End of 2D write delay Voltage center optimization
359 06:08:29.445527 INFO : End of 2D write delay Voltage center optimization
360 06:08:29.451146 INFO : Training has run successfully!
361 06:08:29.451463
362 06:08:29.451680 channel==0
363 06:08:29.456602 RxClkDly_Margin_A0==88 ps 9
364 06:08:29.456912 TxDqDly_Margin_A0==98 ps 10
365 06:08:29.462187 RxClkDly_Margin_A1==78 ps 8
366 06:08:29.462480 TxDqDly_Margin_A1==98 ps 10
367 06:08:29.462697 TrainedVREFDQ_A0==74
368 06:08:29.467814 TrainedVREFDQ_A1==74
369 06:08:29.468147 VrefDac_Margin_A0==25
370 06:08:29.468365 DeviceVref_Margin_A0==40
371 06:08:29.473354 VrefDac_Margin_A1==26
372 06:08:29.473649 DeviceVref_Margin_A1==40
373 06:08:29.473868
374 06:08:29.474080
375 06:08:29.479101 channel==1
376 06:08:29.479384 RxClkDly_Margin_A0==88 ps 9
377 06:08:29.479593 TxDqDly_Margin_A0==88 ps 9
378 06:08:29.484607 RxClkDly_Margin_A1==98 ps 10
379 06:08:29.484887 TxDqDly_Margin_A1==98 ps 10
380 06:08:29.490476 TrainedVREFDQ_A0==76
381 06:08:29.490763 TrainedVREFDQ_A1==78
382 06:08:29.490971 VrefDac_Margin_A0==22
383 06:08:29.496020 DeviceVref_Margin_A0==38
384 06:08:29.496307 VrefDac_Margin_A1==24
385 06:08:29.501579 DeviceVref_Margin_A1==36
386 06:08:29.501861
387 06:08:29.502072 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 06:08:29.502277
389 06:08:29.535187 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 06:08:29.535603 2D training succeed
391 06:08:29.540655 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 06:08:29.546190 auto size-- 65535DDR cs0 size: 2048MB
393 06:08:29.546503 DDR cs1 size: 2048MB
394 06:08:29.551840 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 06:08:29.552141 cs0 DataBus test pass
396 06:08:29.557435 cs1 DataBus test pass
397 06:08:29.557726 cs0 AddrBus test pass
398 06:08:29.557936 cs1 AddrBus test pass
399 06:08:29.558138
400 06:08:29.563115 100bdlr_step_size ps== 420
401 06:08:29.563397 result report
402 06:08:29.568670 boot times 0Enable ddr reg access
403 06:08:29.573063 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 06:08:29.587425 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 06:08:30.161066 0.0;M3 CHK:0;cm4_sp_mode 0
406 06:08:30.161494 MVN_1=0x00000000
407 06:08:30.166532 MVN_2=0x00000000
408 06:08:30.172268 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 06:08:30.172747 OPS=0x10
410 06:08:30.173001 ring efuse init
411 06:08:30.173212 chipver efuse init
412 06:08:30.177845 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 06:08:30.183487 [0.018961 Inits done]
414 06:08:30.183837 secure task start!
415 06:08:30.184103 high task start!
416 06:08:30.188212 low task start!
417 06:08:30.188545 run into bl31
418 06:08:30.194732 NOTICE: BL31: v1.3(release):4fc40b1
419 06:08:30.202625 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 06:08:30.203155 NOTICE: BL31: G12A normal boot!
421 06:08:30.227954 NOTICE: BL31: BL33 decompress pass
422 06:08:30.233544 ERROR: Error initializing runtime service opteed_fast
423 06:08:31.466538
424 06:08:31.467189
425 06:08:31.474297 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 06:08:31.474848
427 06:08:31.475330 Model: Libre Computer AML-A311D-CC Alta
428 06:08:31.683441 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 06:08:31.706853 DRAM: 2 GiB (effective 3.8 GiB)
430 06:08:31.849927 Core: 408 devices, 31 uclasses, devicetree: separate
431 06:08:31.855738 WDT: Not starting watchdog@f0d0
432 06:08:31.888360 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 06:08:31.900470 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 06:08:31.905419 ** Bad device specification mmc 0 **
435 06:08:31.915745 Card did not respond to voltage select! : -110
436 06:08:31.923420 ** Bad device specification mmc 0 **
437 06:08:31.924394 Couldn't find partition mmc 0
438 06:08:31.931750 Card did not respond to voltage select! : -110
439 06:08:31.937272 ** Bad device specification mmc 0 **
440 06:08:31.938213 Couldn't find partition mmc 0
441 06:08:31.942400 Error: could not access storage.
442 06:08:33.205489 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 06:08:33.206173 bl2_stage_init 0x81
444 06:08:33.210548 hw id: 0x0000 - pwm id 0x01
445 06:08:33.211062 bl2_stage_init 0xc1
446 06:08:33.211480 bl2_stage_init 0x02
447 06:08:33.211891
448 06:08:33.216026 L0:00000000
449 06:08:33.216549 L1:20000703
450 06:08:33.216966 L2:00008067
451 06:08:33.217382 L3:14000000
452 06:08:33.217812 B2:00402000
453 06:08:33.221551 B1:e0f83180
454 06:08:33.222055
455 06:08:33.222474 TE: 58150
456 06:08:33.222899
457 06:08:33.227188 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 06:08:33.227693
459 06:08:33.228165 Board ID = 1
460 06:08:33.232831 Set A53 clk to 24M
461 06:08:33.233306 Set A73 clk to 24M
462 06:08:33.233720 Set clk81 to 24M
463 06:08:33.238543 A53 clk: 1200 MHz
464 06:08:33.239025 A73 clk: 1200 MHz
465 06:08:33.239435 CLK81: 166.6M
466 06:08:33.239866 smccc: 00012aac
467 06:08:33.244012 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 06:08:33.249626 board id: 1
469 06:08:33.255377 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 06:08:33.266028 fw parse done
471 06:08:33.271033 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 06:08:33.313775 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 06:08:33.325576 PIEI prepare done
474 06:08:33.326147 fastboot data load
475 06:08:33.326571 fastboot data verify
476 06:08:33.331315 verify result: 266
477 06:08:33.336923 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 06:08:33.337410 LPDDR4 probe
479 06:08:33.337823 ddr clk to 1584MHz
480 06:08:33.343966 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 06:08:33.381149
482 06:08:33.381630 dmc_version 0001
483 06:08:33.387741 Check phy result
484 06:08:33.394609 INFO : End of CA training
485 06:08:33.395066 INFO : End of initialization
486 06:08:33.400191 INFO : Training has run successfully!
487 06:08:33.400637 Check phy result
488 06:08:33.405732 INFO : End of initialization
489 06:08:33.406170 INFO : End of read enable training
490 06:08:33.409081 INFO : End of fine write leveling
491 06:08:33.414593 INFO : End of Write leveling coarse delay
492 06:08:33.420228 INFO : Training has run successfully!
493 06:08:33.420713 Check phy result
494 06:08:33.421127 INFO : End of initialization
495 06:08:33.425845 INFO : End of read dq deskew training
496 06:08:33.429243 INFO : End of MPR read delay center optimization
497 06:08:33.434752 INFO : End of write delay center optimization
498 06:08:33.440362 INFO : End of read delay center optimization
499 06:08:33.440824 INFO : End of max read latency training
500 06:08:33.445961 INFO : Training has run successfully!
501 06:08:33.446401 1D training succeed
502 06:08:33.454211 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 06:08:33.501815 Check phy result
504 06:08:33.502303 INFO : End of initialization
505 06:08:33.523536 INFO : End of 2D read delay Voltage center optimization
506 06:08:33.543739 INFO : End of 2D read delay Voltage center optimization
507 06:08:33.595806 INFO : End of 2D write delay Voltage center optimization
508 06:08:33.645254 INFO : End of 2D write delay Voltage center optimization
509 06:08:33.650731 INFO : Training has run successfully!
510 06:08:33.651272
511 06:08:33.651700 channel==0
512 06:08:33.656297 RxClkDly_Margin_A0==88 ps 9
513 06:08:33.656777 TxDqDly_Margin_A0==98 ps 10
514 06:08:33.659630 RxClkDly_Margin_A1==88 ps 9
515 06:08:33.660129 TxDqDly_Margin_A1==98 ps 10
516 06:08:33.665230 TrainedVREFDQ_A0==74
517 06:08:33.665707 TrainedVREFDQ_A1==74
518 06:08:33.666120 VrefDac_Margin_A0==25
519 06:08:33.670844 DeviceVref_Margin_A0==40
520 06:08:33.671320 VrefDac_Margin_A1==25
521 06:08:33.676442 DeviceVref_Margin_A1==40
522 06:08:33.676896
523 06:08:33.677303
524 06:08:33.677700 channel==1
525 06:08:33.678095 RxClkDly_Margin_A0==98 ps 10
526 06:08:33.682034 TxDqDly_Margin_A0==98 ps 10
527 06:08:33.682494 RxClkDly_Margin_A1==88 ps 9
528 06:08:33.687656 TxDqDly_Margin_A1==88 ps 9
529 06:08:33.688134 TrainedVREFDQ_A0==77
530 06:08:33.688552 TrainedVREFDQ_A1==77
531 06:08:33.693221 VrefDac_Margin_A0==22
532 06:08:33.693664 DeviceVref_Margin_A0==37
533 06:08:33.698816 VrefDac_Margin_A1==24
534 06:08:33.699282 DeviceVref_Margin_A1==37
535 06:08:33.699692
536 06:08:33.704422 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 06:08:33.704864
538 06:08:33.732459 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 06:08:33.738014 2D training succeed
540 06:08:33.743623 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 06:08:33.744124 auto size-- 65535DDR cs0 size: 2048MB
542 06:08:33.749215 DDR cs1 size: 2048MB
543 06:08:33.749702 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 06:08:33.754831 cs0 DataBus test pass
545 06:08:33.755332 cs1 DataBus test pass
546 06:08:33.755785 cs0 AddrBus test pass
547 06:08:33.760503 cs1 AddrBus test pass
548 06:08:33.761029
549 06:08:33.761452 100bdlr_step_size ps== 420
550 06:08:33.761869 result report
551 06:08:33.766109 boot times 0Enable ddr reg access
552 06:08:33.773803 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 06:08:33.787132 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 06:08:34.361294 0.0;M3 CHK:0;cm4_sp_mode 0
555 06:08:34.361919 MVN_1=0x00000000
556 06:08:34.367480 MVN_2=0x00000000
557 06:08:34.372645 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 06:08:34.373100 OPS=0x10
559 06:08:34.373498 ring efuse init
560 06:08:34.373886 chipver efuse init
561 06:08:34.378134 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 06:08:34.384067 [0.018961 Inits done]
563 06:08:34.384495 secure task start!
564 06:08:34.384889 high task start!
565 06:08:34.388779 low task start!
566 06:08:34.389197 run into bl31
567 06:08:34.394819 NOTICE: BL31: v1.3(release):4fc40b1
568 06:08:34.402407 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 06:08:34.402840 NOTICE: BL31: G12A normal boot!
570 06:08:34.428097 NOTICE: BL31: BL33 decompress pass
571 06:08:34.433570 ERROR: Error initializing runtime service opteed_fast
572 06:08:35.665753
573 06:08:35.666270
574 06:08:35.674182 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 06:08:35.674687
576 06:08:35.675079 Model: Libre Computer AML-A311D-CC Alta
577 06:08:35.882646 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 06:08:35.906029 DRAM: 2 GiB (effective 3.8 GiB)
579 06:08:36.048922 Core: 408 devices, 31 uclasses, devicetree: separate
580 06:08:36.054753 WDT: Not starting watchdog@f0d0
581 06:08:36.087140 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 06:08:36.099483 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 06:08:36.103682 ** Bad device specification mmc 0 **
584 06:08:36.114842 Card did not respond to voltage select! : -110
585 06:08:36.122486 ** Bad device specification mmc 0 **
586 06:08:36.122834 Couldn't find partition mmc 0
587 06:08:36.130825 Card did not respond to voltage select! : -110
588 06:08:36.136224 ** Bad device specification mmc 0 **
589 06:08:36.136737 Couldn't find partition mmc 0
590 06:08:36.141399 Error: could not access storage.
591 06:08:36.484088 Net: eth0: ethernet@ff3f0000
592 06:08:36.484618 starting USB...
593 06:08:36.735516 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 06:08:36.736043 Starting the controller
595 06:08:36.741512 USB XHCI 1.10
596 06:08:38.455031 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 06:08:38.455852 bl2_stage_init 0x01
598 06:08:38.456484 bl2_stage_init 0x81
599 06:08:38.460645 hw id: 0x0000 - pwm id 0x01
600 06:08:38.461292 bl2_stage_init 0xc1
601 06:08:38.461843 bl2_stage_init 0x02
602 06:08:38.462520
603 06:08:38.466182 L0:00000000
604 06:08:38.466878 L1:20000703
605 06:08:38.467458 L2:00008067
606 06:08:38.468026 L3:14000000
607 06:08:38.469195 B2:00402000
608 06:08:38.469680 B1:e0f83180
609 06:08:38.470101
610 06:08:38.470518 TE: 58124
611 06:08:38.470928
612 06:08:38.480340 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 06:08:38.480865
614 06:08:38.481288 Board ID = 1
615 06:08:38.481697 Set A53 clk to 24M
616 06:08:38.482098 Set A73 clk to 24M
617 06:08:38.485902 Set clk81 to 24M
618 06:08:38.486385 A53 clk: 1200 MHz
619 06:08:38.486801 A73 clk: 1200 MHz
620 06:08:38.491540 CLK81: 166.6M
621 06:08:38.492094 smccc: 00012a92
622 06:08:38.497142 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 06:08:38.497630 board id: 1
624 06:08:38.504948 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 06:08:38.516475 fw parse done
626 06:08:38.522337 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 06:08:38.564955 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 06:08:38.575880 PIEI prepare done
629 06:08:38.576446 fastboot data load
630 06:08:38.576869 fastboot data verify
631 06:08:38.581521 verify result: 266
632 06:08:38.587076 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 06:08:38.587572 LPDDR4 probe
634 06:08:38.588013 ddr clk to 1584MHz
635 06:08:38.595113 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 06:08:38.632452
637 06:08:38.633067 dmc_version 0001
638 06:08:38.639026 Check phy result
639 06:08:38.644870 INFO : End of CA training
640 06:08:38.645415 INFO : End of initialization
641 06:08:38.650499 INFO : Training has run successfully!
642 06:08:38.651020 Check phy result
643 06:08:38.656079 INFO : End of initialization
644 06:08:38.656593 INFO : End of read enable training
645 06:08:38.661704 INFO : End of fine write leveling
646 06:08:38.667272 INFO : End of Write leveling coarse delay
647 06:08:38.667786 INFO : Training has run successfully!
648 06:08:38.668249 Check phy result
649 06:08:38.672898 INFO : End of initialization
650 06:08:38.673433 INFO : End of read dq deskew training
651 06:08:38.678491 INFO : End of MPR read delay center optimization
652 06:08:38.684104 INFO : End of write delay center optimization
653 06:08:38.689694 INFO : End of read delay center optimization
654 06:08:38.690214 INFO : End of max read latency training
655 06:08:38.695253 INFO : Training has run successfully!
656 06:08:38.695753 1D training succeed
657 06:08:38.704586 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 06:08:38.752193 Check phy result
659 06:08:38.752974 INFO : End of initialization
660 06:08:38.773551 INFO : End of 2D read delay Voltage center optimization
661 06:08:38.794136 INFO : End of 2D read delay Voltage center optimization
662 06:08:38.846250 INFO : End of 2D write delay Voltage center optimization
663 06:08:38.895615 INFO : End of 2D write delay Voltage center optimization
664 06:08:38.901083 INFO : Training has run successfully!
665 06:08:38.901600
666 06:08:38.902020 channel==0
667 06:08:38.906648 RxClkDly_Margin_A0==88 ps 9
668 06:08:38.907165 TxDqDly_Margin_A0==98 ps 10
669 06:08:38.912310 RxClkDly_Margin_A1==88 ps 9
670 06:08:38.912833 TxDqDly_Margin_A1==98 ps 10
671 06:08:38.913252 TrainedVREFDQ_A0==74
672 06:08:38.917843 TrainedVREFDQ_A1==74
673 06:08:38.918380 VrefDac_Margin_A0==25
674 06:08:38.918800 DeviceVref_Margin_A0==40
675 06:08:38.923504 VrefDac_Margin_A1==25
676 06:08:38.924074 DeviceVref_Margin_A1==40
677 06:08:38.924509
678 06:08:38.924935
679 06:08:38.929022 channel==1
680 06:08:38.929558 RxClkDly_Margin_A0==98 ps 10
681 06:08:38.929992 TxDqDly_Margin_A0==88 ps 9
682 06:08:38.934632 RxClkDly_Margin_A1==98 ps 10
683 06:08:38.935145 TxDqDly_Margin_A1==88 ps 9
684 06:08:38.940269 TrainedVREFDQ_A0==76
685 06:08:38.940816 TrainedVREFDQ_A1==77
686 06:08:38.941259 VrefDac_Margin_A0==22
687 06:08:38.945845 DeviceVref_Margin_A0==38
688 06:08:38.946395 VrefDac_Margin_A1==22
689 06:08:38.951530 DeviceVref_Margin_A1==37
690 06:08:38.952111
691 06:08:38.952560 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 06:08:38.952999
693 06:08:38.985018 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
694 06:08:38.985621 2D training succeed
695 06:08:38.990674 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 06:08:38.996424 auto size-- 65535DDR cs0 size: 2048MB
697 06:08:38.996965 DDR cs1 size: 2048MB
698 06:08:39.001956 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 06:08:39.002656 cs0 DataBus test pass
700 06:08:39.007583 cs1 DataBus test pass
701 06:08:39.008313 cs0 AddrBus test pass
702 06:08:39.008837 cs1 AddrBus test pass
703 06:08:39.009363
704 06:08:39.013058 100bdlr_step_size ps== 420
705 06:08:39.013576 result report
706 06:08:39.018680 boot times 0Enable ddr reg access
707 06:08:39.024008 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 06:08:39.037606 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 06:08:39.611027 0.0;M3 CHK:0;cm4_sp_mode 0
710 06:08:39.611669 MVN_1=0x00000000
711 06:08:39.616670 MVN_2=0x00000000
712 06:08:39.623006 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 06:08:39.623561 OPS=0x10
714 06:08:39.624044 ring efuse init
715 06:08:39.624459 chipver efuse init
716 06:08:39.627926 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 06:08:39.633561 [0.018960 Inits done]
718 06:08:39.634240 secure task start!
719 06:08:39.634778 high task start!
720 06:08:39.638088 low task start!
721 06:08:39.638723 run into bl31
722 06:08:39.644781 NOTICE: BL31: v1.3(release):4fc40b1
723 06:08:39.652771 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 06:08:39.653319 NOTICE: BL31: G12A normal boot!
725 06:08:39.678036 NOTICE: BL31: BL33 decompress pass
726 06:08:39.683704 ERROR: Error initializing runtime service opteed_fast
727 06:08:40.916522
728 06:08:40.916937
729 06:08:40.924998 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 06:08:40.925397
731 06:08:40.925631 Model: Libre Computer AML-A311D-CC Alta
732 06:08:41.133544 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 06:08:41.156905 DRAM: 2 GiB (effective 3.8 GiB)
734 06:08:41.300167 Core: 408 devices, 31 uclasses, devicetree: separate
735 06:08:41.305634 WDT: Not starting watchdog@f0d0
736 06:08:41.337900 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 06:08:41.350378 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 06:08:41.355654 ** Bad device specification mmc 0 **
739 06:08:41.366106 Card did not respond to voltage select! : -110
740 06:08:41.373870 ** Bad device specification mmc 0 **
741 06:08:41.374308 Couldn't find partition mmc 0
742 06:08:41.381760 Card did not respond to voltage select! : -110
743 06:08:41.387189 ** Bad device specification mmc 0 **
744 06:08:41.387791 Couldn't find partition mmc 0
745 06:08:41.392587 Error: could not access storage.
746 06:08:41.736144 Net: eth0: ethernet@ff3f0000
747 06:08:41.736615 starting USB...
748 06:08:41.987711 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 06:08:41.988390 Starting the controller
750 06:08:41.994689 USB XHCI 1.10
751 06:08:44.155142 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 06:08:44.155586 bl2_stage_init 0x01
753 06:08:44.155810 bl2_stage_init 0x81
754 06:08:44.160586 hw id: 0x0000 - pwm id 0x01
755 06:08:44.160965 bl2_stage_init 0xc1
756 06:08:44.161187 bl2_stage_init 0x02
757 06:08:44.161398
758 06:08:44.166288 L0:00000000
759 06:08:44.166767 L1:20000703
760 06:08:44.167086 L2:00008067
761 06:08:44.167397 L3:14000000
762 06:08:44.169320 B2:00402000
763 06:08:44.169833 B1:e0f83180
764 06:08:44.170166
765 06:08:44.170481 TE: 58124
766 06:08:44.170781
767 06:08:44.180483 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 06:08:44.180987
769 06:08:44.181317 Board ID = 1
770 06:08:44.181637 Set A53 clk to 24M
771 06:08:44.181947 Set A73 clk to 24M
772 06:08:44.185996 Set clk81 to 24M
773 06:08:44.186441 A53 clk: 1200 MHz
774 06:08:44.186769 A73 clk: 1200 MHz
775 06:08:44.189607 CLK81: 166.6M
776 06:08:44.190021 smccc: 00012a92
777 06:08:44.195240 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 06:08:44.200737 board id: 1
779 06:08:44.205923 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 06:08:44.216308 fw parse done
781 06:08:44.222287 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 06:08:44.265026 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 06:08:44.275940 PIEI prepare done
784 06:08:44.276486 fastboot data load
785 06:08:44.276821 fastboot data verify
786 06:08:44.281520 verify result: 266
787 06:08:44.287139 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 06:08:44.287627 LPDDR4 probe
789 06:08:44.287956 ddr clk to 1584MHz
790 06:08:44.295214 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 06:08:44.332426
792 06:08:44.332947 dmc_version 0001
793 06:08:44.339221 Check phy result
794 06:08:44.344959 INFO : End of CA training
795 06:08:44.345453 INFO : End of initialization
796 06:08:44.350524 INFO : Training has run successfully!
797 06:08:44.350992 Check phy result
798 06:08:44.356184 INFO : End of initialization
799 06:08:44.356641 INFO : End of read enable training
800 06:08:44.359422 INFO : End of fine write leveling
801 06:08:44.364958 INFO : End of Write leveling coarse delay
802 06:08:44.370592 INFO : Training has run successfully!
803 06:08:44.371060 Check phy result
804 06:08:44.371406 INFO : End of initialization
805 06:08:44.376213 INFO : End of read dq deskew training
806 06:08:44.381703 INFO : End of MPR read delay center optimization
807 06:08:44.382139 INFO : End of write delay center optimization
808 06:08:44.387374 INFO : End of read delay center optimization
809 06:08:44.393000 INFO : End of max read latency training
810 06:08:44.393482 INFO : Training has run successfully!
811 06:08:44.398587 1D training succeed
812 06:08:44.404581 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 06:08:44.452236 Check phy result
814 06:08:44.452764 INFO : End of initialization
815 06:08:44.473967 INFO : End of 2D read delay Voltage center optimization
816 06:08:44.494200 INFO : End of 2D read delay Voltage center optimization
817 06:08:44.546265 INFO : End of 2D write delay Voltage center optimization
818 06:08:44.595587 INFO : End of 2D write delay Voltage center optimization
819 06:08:44.601168 INFO : Training has run successfully!
820 06:08:44.601653
821 06:08:44.601978 channel==0
822 06:08:44.606779 RxClkDly_Margin_A0==88 ps 9
823 06:08:44.607243 TxDqDly_Margin_A0==98 ps 10
824 06:08:44.612394 RxClkDly_Margin_A1==88 ps 9
825 06:08:44.612862 TxDqDly_Margin_A1==98 ps 10
826 06:08:44.613187 TrainedVREFDQ_A0==74
827 06:08:44.617947 TrainedVREFDQ_A1==75
828 06:08:44.618413 VrefDac_Margin_A0==25
829 06:08:44.618730 DeviceVref_Margin_A0==40
830 06:08:44.623494 VrefDac_Margin_A1==25
831 06:08:44.623949 DeviceVref_Margin_A1==39
832 06:08:44.624305
833 06:08:44.624763
834 06:08:44.629091 channel==1
835 06:08:44.629539 RxClkDly_Margin_A0==98 ps 10
836 06:08:44.629852 TxDqDly_Margin_A0==98 ps 10
837 06:08:44.634743 RxClkDly_Margin_A1==98 ps 10
838 06:08:44.635174 TxDqDly_Margin_A1==88 ps 9
839 06:08:44.640366 TrainedVREFDQ_A0==77
840 06:08:44.640796 TrainedVREFDQ_A1==77
841 06:08:44.641101 VrefDac_Margin_A0==22
842 06:08:44.645959 DeviceVref_Margin_A0==37
843 06:08:44.646412 VrefDac_Margin_A1==22
844 06:08:44.651480 DeviceVref_Margin_A1==37
845 06:08:44.651935
846 06:08:44.652278 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 06:08:44.657118
848 06:08:44.685078 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
849 06:08:44.685591 2D training succeed
850 06:08:44.690706 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 06:08:44.696317 auto size-- 65535DDR cs0 size: 2048MB
852 06:08:44.696763 DDR cs1 size: 2048MB
853 06:08:44.701961 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 06:08:44.702583 cs0 DataBus test pass
855 06:08:44.707457 cs1 DataBus test pass
856 06:08:44.708066 cs0 AddrBus test pass
857 06:08:44.708522 cs1 AddrBus test pass
858 06:08:44.708959
859 06:08:44.713092 100bdlr_step_size ps== 420
860 06:08:44.713717 result report
861 06:08:44.718639 boot times 0Enable ddr reg access
862 06:08:44.724146 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 06:08:44.737562 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 06:08:45.310648 0.0;M3 CHK:0;cm4_sp_mode 0
865 06:08:45.311099 MVN_1=0x00000000
866 06:08:45.316198 MVN_2=0x00000000
867 06:08:45.321886 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 06:08:45.322562 OPS=0x10
869 06:08:45.323139 ring efuse init
870 06:08:45.323686 chipver efuse init
871 06:08:45.327454 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 06:08:45.333143 [0.018961 Inits done]
873 06:08:45.333823 secure task start!
874 06:08:45.334377 high task start!
875 06:08:45.337702 low task start!
876 06:08:45.338374 run into bl31
877 06:08:45.344438 NOTICE: BL31: v1.3(release):4fc40b1
878 06:08:45.352238 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 06:08:45.352806 NOTICE: BL31: G12A normal boot!
880 06:08:45.377598 NOTICE: BL31: BL33 decompress pass
881 06:08:45.383311 ERROR: Error initializing runtime service opteed_fast
882 06:08:46.616116
883 06:08:46.616906
884 06:08:46.624554 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 06:08:46.625237
886 06:08:46.625787 Model: Libre Computer AML-A311D-CC Alta
887 06:08:46.833402 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 06:08:46.856387 DRAM: 2 GiB (effective 3.8 GiB)
889 06:08:46.999821 Core: 408 devices, 31 uclasses, devicetree: separate
890 06:08:47.005811 WDT: Not starting watchdog@f0d0
891 06:08:47.037482 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 06:08:47.049832 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 06:08:47.054803 ** Bad device specification mmc 0 **
894 06:08:47.065161 Card did not respond to voltage select! : -110
895 06:08:47.072846 ** Bad device specification mmc 0 **
896 06:08:47.073155 Couldn't find partition mmc 0
897 06:08:47.081131 Card did not respond to voltage select! : -110
898 06:08:47.086561 ** Bad device specification mmc 0 **
899 06:08:47.086867 Couldn't find partition mmc 0
900 06:08:47.091618 Error: could not access storage.
901 06:08:47.435268 Net: eth0: ethernet@ff3f0000
902 06:08:47.435687 starting USB...
903 06:08:47.687118 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 06:08:47.687569 Starting the controller
905 06:08:47.694071 USB XHCI 1.10
906 06:08:49.248111 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 06:08:49.256312 scanning usb for storage devices... 0 Storage Device(s) found
909 06:08:49.307461 Hit any key to stop autoboot: 1
910 06:08:49.308356 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 06:08:49.308759 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 06:08:49.309044 Setting prompt string to ['=>']
913 06:08:49.309316 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 06:08:49.323867 0
915 06:08:49.324614 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 06:08:49.324913 Sending with 10 millisecond of delay
918 06:08:50.462004 => setenv autoload no
919 06:08:50.472944 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 06:08:50.478874 setenv autoload no
921 06:08:50.479760 Sending with 10 millisecond of delay
923 06:08:52.283691 => setenv initrd_high 0xffffffff
924 06:08:52.294324 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 06:08:52.295184 setenv initrd_high 0xffffffff
926 06:08:52.295887 Sending with 10 millisecond of delay
928 06:08:53.913486 => setenv fdt_high 0xffffffff
929 06:08:53.924244 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 06:08:53.924808 setenv fdt_high 0xffffffff
931 06:08:53.925274 Sending with 10 millisecond of delay
933 06:08:54.216693 => dhcp
934 06:08:54.227252 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 06:08:54.227783 dhcp
936 06:08:54.228083 Speed: 1000, full duplex
937 06:08:54.228307 BOOTP broadcast 1
938 06:08:54.475664 BOOTP broadcast 2
939 06:08:54.487832 DHCP client bound to address 192.168.6.33 (261 ms)
940 06:08:54.488657 Sending with 10 millisecond of delay
942 06:08:56.167328 => setenv serverip 192.168.6.2
943 06:08:56.178169 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 06:08:56.179068 setenv serverip 192.168.6.2
945 06:08:56.179752 Sending with 10 millisecond of delay
947 06:08:59.906901 => tftpboot 0x01080000 790069/tftp-deploy-g9ax95hw/kernel/uImage
948 06:08:59.917684 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
949 06:08:59.918320 tftpboot 0x01080000 790069/tftp-deploy-g9ax95hw/kernel/uImage
950 06:08:59.918602 Speed: 1000, full duplex
951 06:08:59.918840 Using ethernet@ff3f0000 device
952 06:08:59.920551 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
953 06:08:59.926113 Filename '790069/tftp-deploy-g9ax95hw/kernel/uImage'.
954 06:08:59.929751 Load address: 0x1080000
955 06:09:04.262042 Loading: *################################################## 43.6 MiB
956 06:09:04.262472 10.1 MiB/s
957 06:09:04.262683 done
958 06:09:04.265349 Bytes transferred = 45713984 (2b98a40 hex)
959 06:09:04.265836 Sending with 10 millisecond of delay
961 06:09:08.955616 => tftpboot 0x08000000 790069/tftp-deploy-g9ax95hw/ramdisk/ramdisk.cpio.gz.uboot
962 06:09:08.966487 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:08)
963 06:09:08.967365 tftpboot 0x08000000 790069/tftp-deploy-g9ax95hw/ramdisk/ramdisk.cpio.gz.uboot
964 06:09:08.967857 Speed: 1000, full duplex
965 06:09:08.968361 Using ethernet@ff3f0000 device
966 06:09:08.969224 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
967 06:09:08.977784 Filename '790069/tftp-deploy-g9ax95hw/ramdisk/ramdisk.cpio.gz.uboot'.
968 06:09:08.978330 Load address: 0x8000000
969 06:09:11.333473 Loading: *################################################# UDP wrong checksum 00000005 0000dc72
970 06:09:16.335069 T UDP wrong checksum 00000005 0000dc72
971 06:09:26.336722 T T UDP wrong checksum 00000005 0000dc72
972 06:09:33.590306 T UDP wrong checksum 000000ff 00000a02
973 06:09:33.621082 UDP wrong checksum 000000ff 0000a6f4
974 06:09:46.341037 T T T UDP wrong checksum 00000005 0000dc72
975 06:10:02.312744 T T T UDP wrong checksum 000000ff 000053fe
976 06:10:02.349800 UDP wrong checksum 000000ff 0000e9f0
977 06:10:06.346309
978 06:10:06.347026 Retry count exceeded; starting again
980 06:10:06.348465 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
983 06:10:06.350266 end: 2.4 uboot-commands (duration 00:01:49) [common]
985 06:10:06.351573 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
987 06:10:06.352608 end: 2 uboot-action (duration 00:01:49) [common]
989 06:10:06.354317 Cleaning after the job
990 06:10:06.354924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/ramdisk
991 06:10:06.356620 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/kernel
992 06:10:06.373268 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/dtb
993 06:10:06.376491 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790069/tftp-deploy-g9ax95hw/modules
994 06:10:06.384514 start: 4.1 power-off (timeout 00:00:30) [common]
995 06:10:06.385844 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
996 06:10:06.422092 >> OK - accepted request
997 06:10:06.424213 Returned 0 in 0 seconds
998 06:10:06.525669 end: 4.1 power-off (duration 00:00:00) [common]
1000 06:10:06.527848 start: 4.2 read-feedback (timeout 00:10:00) [common]
1001 06:10:06.529342 Listened to connection for namespace 'common' for up to 1s
1002 06:10:07.529310 Finalising connection for namespace 'common'
1003 06:10:07.530035 Disconnecting from shell: Finalise
1004 06:10:07.530533 =>
1005 06:10:07.631522 end: 4.2 read-feedback (duration 00:00:01) [common]
1006 06:10:07.632275 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/790069
1007 06:10:07.925068 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/790069
1008 06:10:07.925672 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.