Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:07:17.130612 lava-dispatcher, installed at version: 2024.01
2 06:07:17.131395 start: 0 validate
3 06:07:17.131857 Start time: 2024-10-02 06:07:17.131827+00:00 (UTC)
4 06:07:17.132421 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:07:17.132962 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 06:07:17.179683 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:07:17.180335 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 06:07:17.215213 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:07:17.216192 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 06:07:18.270179 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:07:18.270698 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 06:07:18.312450 validate duration: 1.18
14 06:07:18.313353 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:07:18.313713 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:07:18.314054 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:07:18.314627 Not decompressing ramdisk as can be used compressed.
18 06:07:18.315052 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 06:07:18.315335 saving as /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/ramdisk/rootfs.cpio.gz
20 06:07:18.315630 total size: 8181887 (7 MB)
21 06:07:18.353408 progress 0 % (0 MB)
22 06:07:18.368068 progress 5 % (0 MB)
23 06:07:18.380384 progress 10 % (0 MB)
24 06:07:18.386871 progress 15 % (1 MB)
25 06:07:18.392723 progress 20 % (1 MB)
26 06:07:18.398955 progress 25 % (1 MB)
27 06:07:18.404988 progress 30 % (2 MB)
28 06:07:18.411117 progress 35 % (2 MB)
29 06:07:18.417107 progress 40 % (3 MB)
30 06:07:18.423325 progress 45 % (3 MB)
31 06:07:18.429156 progress 50 % (3 MB)
32 06:07:18.435577 progress 55 % (4 MB)
33 06:07:18.441435 progress 60 % (4 MB)
34 06:07:18.447537 progress 65 % (5 MB)
35 06:07:18.453378 progress 70 % (5 MB)
36 06:07:18.459646 progress 75 % (5 MB)
37 06:07:18.465506 progress 80 % (6 MB)
38 06:07:18.471845 progress 85 % (6 MB)
39 06:07:18.477366 progress 90 % (7 MB)
40 06:07:18.483241 progress 95 % (7 MB)
41 06:07:18.489058 progress 100 % (7 MB)
42 06:07:18.489844 7 MB downloaded in 0.17 s (44.79 MB/s)
43 06:07:18.490568 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:07:18.491682 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:07:18.492045 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:07:18.492385 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:07:18.492968 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
49 06:07:18.493253 saving as /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/kernel/Image
50 06:07:18.493509 total size: 45713920 (43 MB)
51 06:07:18.493760 No compression specified
52 06:07:18.534075 progress 0 % (0 MB)
53 06:07:18.561686 progress 5 % (2 MB)
54 06:07:18.589485 progress 10 % (4 MB)
55 06:07:18.617194 progress 15 % (6 MB)
56 06:07:18.645140 progress 20 % (8 MB)
57 06:07:18.672162 progress 25 % (10 MB)
58 06:07:18.699718 progress 30 % (13 MB)
59 06:07:18.727264 progress 35 % (15 MB)
60 06:07:18.756908 progress 40 % (17 MB)
61 06:07:18.783882 progress 45 % (19 MB)
62 06:07:18.811390 progress 50 % (21 MB)
63 06:07:18.839229 progress 55 % (24 MB)
64 06:07:18.866479 progress 60 % (26 MB)
65 06:07:18.893638 progress 65 % (28 MB)
66 06:07:18.921237 progress 70 % (30 MB)
67 06:07:18.948934 progress 75 % (32 MB)
68 06:07:18.976258 progress 80 % (34 MB)
69 06:07:19.003441 progress 85 % (37 MB)
70 06:07:19.031030 progress 90 % (39 MB)
71 06:07:19.061112 progress 95 % (41 MB)
72 06:07:19.087640 progress 100 % (43 MB)
73 06:07:19.088178 43 MB downloaded in 0.59 s (73.31 MB/s)
74 06:07:19.088670 end: 1.2.1 http-download (duration 00:00:01) [common]
76 06:07:19.089482 end: 1.2 download-retry (duration 00:00:01) [common]
77 06:07:19.089757 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:07:19.090021 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:07:19.090491 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 06:07:19.090765 saving as /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 06:07:19.090974 total size: 53209 (0 MB)
82 06:07:19.091185 No compression specified
83 06:07:19.134158 progress 61 % (0 MB)
84 06:07:19.135005 progress 100 % (0 MB)
85 06:07:19.135545 0 MB downloaded in 0.04 s (1.14 MB/s)
86 06:07:19.136032 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:07:19.136854 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:07:19.137116 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:07:19.137379 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:07:19.137840 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
92 06:07:19.138081 saving as /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/modules/modules.tar
93 06:07:19.138285 total size: 11621068 (11 MB)
94 06:07:19.138495 Using unxz to decompress xz
95 06:07:19.179590 progress 0 % (0 MB)
96 06:07:19.251315 progress 5 % (0 MB)
97 06:07:19.336160 progress 10 % (1 MB)
98 06:07:19.422172 progress 15 % (1 MB)
99 06:07:19.498187 progress 20 % (2 MB)
100 06:07:19.581113 progress 25 % (2 MB)
101 06:07:19.660173 progress 30 % (3 MB)
102 06:07:19.738983 progress 35 % (3 MB)
103 06:07:19.811922 progress 40 % (4 MB)
104 06:07:19.887471 progress 45 % (5 MB)
105 06:07:19.964225 progress 50 % (5 MB)
106 06:07:20.039927 progress 55 % (6 MB)
107 06:07:20.119199 progress 60 % (6 MB)
108 06:07:20.204470 progress 65 % (7 MB)
109 06:07:20.285614 progress 70 % (7 MB)
110 06:07:20.377402 progress 75 % (8 MB)
111 06:07:20.472298 progress 80 % (8 MB)
112 06:07:20.553610 progress 85 % (9 MB)
113 06:07:20.627964 progress 90 % (10 MB)
114 06:07:20.699148 progress 95 % (10 MB)
115 06:07:20.774121 progress 100 % (11 MB)
116 06:07:20.786453 11 MB downloaded in 1.65 s (6.72 MB/s)
117 06:07:20.787454 end: 1.4.1 http-download (duration 00:00:02) [common]
119 06:07:20.789370 end: 1.4 download-retry (duration 00:00:02) [common]
120 06:07:20.789964 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 06:07:20.790534 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 06:07:20.791095 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:07:20.791675 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 06:07:20.792787 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net
125 06:07:20.793667 makedir: /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin
126 06:07:20.794393 makedir: /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/tests
127 06:07:20.795067 makedir: /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/results
128 06:07:20.795740 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-add-keys
129 06:07:20.796847 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-add-sources
130 06:07:20.797863 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-background-process-start
131 06:07:20.798895 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-background-process-stop
132 06:07:20.799963 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-common-functions
133 06:07:20.801062 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-echo-ipv4
134 06:07:20.802226 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-install-packages
135 06:07:20.803229 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-installed-packages
136 06:07:20.804236 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-os-build
137 06:07:20.805261 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-probe-channel
138 06:07:20.806242 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-probe-ip
139 06:07:20.807212 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-target-ip
140 06:07:20.808224 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-target-mac
141 06:07:20.809207 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-target-storage
142 06:07:20.810196 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-test-case
143 06:07:20.811227 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-test-event
144 06:07:20.812291 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-test-feedback
145 06:07:20.813361 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-test-raise
146 06:07:20.814404 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-test-reference
147 06:07:20.815453 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-test-runner
148 06:07:20.816753 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-test-set
149 06:07:20.817827 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-test-shell
150 06:07:20.818831 Updating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-install-packages (oe)
151 06:07:20.819877 Updating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/bin/lava-installed-packages (oe)
152 06:07:20.820857 Creating /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/environment
153 06:07:20.821645 LAVA metadata
154 06:07:20.822185 - LAVA_JOB_ID=790065
155 06:07:20.822655 - LAVA_DISPATCHER_IP=192.168.6.2
156 06:07:20.823358 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 06:07:20.825333 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 06:07:20.825987 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 06:07:20.826442 skipped lava-vland-overlay
160 06:07:20.826978 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 06:07:20.827532 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 06:07:20.828104 skipped lava-multinode-overlay
163 06:07:20.828628 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 06:07:20.829151 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 06:07:20.829635 Loading test definitions
166 06:07:20.830176 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 06:07:20.830617 Using /lava-790065 at stage 0
168 06:07:20.832546 uuid=790065_1.5.2.4.1 testdef=None
169 06:07:20.832888 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 06:07:20.833178 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 06:07:20.835029 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 06:07:20.835846 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 06:07:20.838111 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 06:07:20.838978 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 06:07:20.841182 runner path: /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/0/tests/0_dmesg test_uuid 790065_1.5.2.4.1
178 06:07:20.841748 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 06:07:20.842551 Creating lava-test-runner.conf files
181 06:07:20.842786 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/790065/lava-overlay-ux5x2net/lava-790065/0 for stage 0
182 06:07:20.843165 - 0_dmesg
183 06:07:20.843595 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 06:07:20.843889 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 06:07:20.867562 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 06:07:20.867948 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 06:07:20.868242 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 06:07:20.868510 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 06:07:20.868773 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 06:07:21.795371 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 06:07:21.795921 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 06:07:21.796608 extracting modules file /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/790065/extract-overlay-ramdisk-n5az9pos/ramdisk
193 06:07:23.164472 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 06:07:23.164920 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 06:07:23.165199 [common] Applying overlay /var/lib/lava/dispatcher/tmp/790065/compress-overlay-fh0i2f_0/overlay-1.5.2.5.tar.gz to ramdisk
196 06:07:23.165415 [common] Applying overlay /var/lib/lava/dispatcher/tmp/790065/compress-overlay-fh0i2f_0/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/790065/extract-overlay-ramdisk-n5az9pos/ramdisk
197 06:07:23.195671 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 06:07:23.196098 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 06:07:23.196381 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 06:07:23.196608 Converting downloaded kernel to a uImage
201 06:07:23.196910 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/kernel/Image /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/kernel/uImage
202 06:07:23.662293 output: Image Name:
203 06:07:23.662713 output: Created: Wed Oct 2 06:07:23 2024
204 06:07:23.662928 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 06:07:23.663135 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 06:07:23.663337 output: Load Address: 01080000
207 06:07:23.663536 output: Entry Point: 01080000
208 06:07:23.663733 output:
209 06:07:23.664093 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 06:07:23.664377 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 06:07:23.664649 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 06:07:23.664897 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 06:07:23.665149 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 06:07:23.665410 Building ramdisk /var/lib/lava/dispatcher/tmp/790065/extract-overlay-ramdisk-n5az9pos/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/790065/extract-overlay-ramdisk-n5az9pos/ramdisk
215 06:07:26.038783 >> 181702 blocks
216 06:07:34.501456 Adding RAMdisk u-boot header.
217 06:07:34.502094 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/790065/extract-overlay-ramdisk-n5az9pos/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/790065/extract-overlay-ramdisk-n5az9pos/ramdisk.cpio.gz.uboot
218 06:07:34.772925 output: Image Name:
219 06:07:34.773495 output: Created: Wed Oct 2 06:07:34 2024
220 06:07:34.773896 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 06:07:34.774292 output: Data Size: 26061519 Bytes = 25450.70 KiB = 24.85 MiB
222 06:07:34.774685 output: Load Address: 00000000
223 06:07:34.775070 output: Entry Point: 00000000
224 06:07:34.775454 output:
225 06:07:34.776429 rename /var/lib/lava/dispatcher/tmp/790065/extract-overlay-ramdisk-n5az9pos/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/ramdisk/ramdisk.cpio.gz.uboot
226 06:07:34.777129 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 06:07:34.777658 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 06:07:34.778169 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 06:07:34.778611 No LXC device requested
230 06:07:34.779093 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 06:07:34.779581 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 06:07:34.780088 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 06:07:34.780495 Checking files for TFTP limit of 4294967296 bytes.
234 06:07:34.783111 end: 1 tftp-deploy (duration 00:00:16) [common]
235 06:07:34.783668 start: 2 uboot-action (timeout 00:05:00) [common]
236 06:07:34.784214 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 06:07:34.784702 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 06:07:34.785196 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 06:07:34.785716 Using kernel file from prepare-kernel: 790065/tftp-deploy-sttw11oz/kernel/uImage
240 06:07:34.786326 substitutions:
241 06:07:34.786731 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 06:07:34.787127 - {DTB_ADDR}: 0x01070000
243 06:07:34.787517 - {DTB}: 790065/tftp-deploy-sttw11oz/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 06:07:34.787910 - {INITRD}: 790065/tftp-deploy-sttw11oz/ramdisk/ramdisk.cpio.gz.uboot
245 06:07:34.788335 - {KERNEL_ADDR}: 0x01080000
246 06:07:34.788724 - {KERNEL}: 790065/tftp-deploy-sttw11oz/kernel/uImage
247 06:07:34.789113 - {LAVA_MAC}: None
248 06:07:34.789552 - {PRESEED_CONFIG}: None
249 06:07:34.789940 - {PRESEED_LOCAL}: None
250 06:07:34.790324 - {RAMDISK_ADDR}: 0x08000000
251 06:07:34.790708 - {RAMDISK}: 790065/tftp-deploy-sttw11oz/ramdisk/ramdisk.cpio.gz.uboot
252 06:07:34.791095 - {ROOT_PART}: None
253 06:07:34.791479 - {ROOT}: None
254 06:07:34.791862 - {SERVER_IP}: 192.168.6.2
255 06:07:34.792294 - {TEE_ADDR}: 0x83000000
256 06:07:34.792681 - {TEE}: None
257 06:07:34.793065 Parsed boot commands:
258 06:07:34.793435 - setenv autoload no
259 06:07:34.793818 - setenv initrd_high 0xffffffff
260 06:07:34.794200 - setenv fdt_high 0xffffffff
261 06:07:34.794580 - dhcp
262 06:07:34.794963 - setenv serverip 192.168.6.2
263 06:07:34.795344 - tftpboot 0x01080000 790065/tftp-deploy-sttw11oz/kernel/uImage
264 06:07:34.795729 - tftpboot 0x08000000 790065/tftp-deploy-sttw11oz/ramdisk/ramdisk.cpio.gz.uboot
265 06:07:34.796136 - tftpboot 0x01070000 790065/tftp-deploy-sttw11oz/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 06:07:34.796520 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 06:07:34.796909 - bootm 0x01080000 0x08000000 0x01070000
268 06:07:34.797390 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 06:07:34.798841 start: 2.3 connect-device (timeout 00:05:00) [common]
271 06:07:34.799275 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 06:07:34.814005 Setting prompt string to ['lava-test: # ']
273 06:07:34.815437 end: 2.3 connect-device (duration 00:00:00) [common]
274 06:07:34.816060 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 06:07:34.816597 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 06:07:34.817108 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 06:07:34.818220 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 06:07:34.854496 >> OK - accepted request
279 06:07:34.857357 Returned 0 in 0 seconds
280 06:07:34.958430 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 06:07:34.959950 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 06:07:34.960556 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 06:07:34.961048 Setting prompt string to ['Hit any key to stop autoboot']
285 06:07:34.961503 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 06:07:34.963080 Trying 192.168.56.21...
287 06:07:34.963553 Connected to conserv1.
288 06:07:34.963974 Escape character is '^]'.
289 06:07:34.964432
290 06:07:34.964863 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 06:07:34.965289
292 06:07:41.741726 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 06:07:41.742358 bl2_stage_init 0x01
294 06:07:41.742799 bl2_stage_init 0x81
295 06:07:41.747109 hw id: 0x0000 - pwm id 0x01
296 06:07:41.747625 bl2_stage_init 0xc1
297 06:07:41.752734 bl2_stage_init 0x02
298 06:07:41.753205
299 06:07:41.753625 L0:00000000
300 06:07:41.754031 L1:00000703
301 06:07:41.754445 L2:00008067
302 06:07:41.754862 L3:15000000
303 06:07:41.758329 S1:00000000
304 06:07:41.758822 B2:20282000
305 06:07:41.759240 B1:a0f83180
306 06:07:41.759646
307 06:07:41.760084 TE: 71353
308 06:07:41.760498
309 06:07:41.763864 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 06:07:41.764385
311 06:07:41.769488 Board ID = 1
312 06:07:41.769937 Set cpu clk to 24M
313 06:07:41.770333 Set clk81 to 24M
314 06:07:41.775094 Use GP1_pll as DSU clk.
315 06:07:41.775565 DSU clk: 1200 Mhz
316 06:07:41.775964 CPU clk: 1200 MHz
317 06:07:41.780674 Set clk81 to 166.6M
318 06:07:41.786332 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 06:07:41.786837 board id: 1
320 06:07:41.793570 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 06:07:41.804436 fw parse done
322 06:07:41.809458 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 06:07:41.853542 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 06:07:41.864711 PIEI prepare done
325 06:07:41.865201 fastboot data load
326 06:07:41.865625 fastboot data verify
327 06:07:41.870307 verify result: 266
328 06:07:41.875837 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 06:07:41.876357 LPDDR4 probe
330 06:07:41.876774 ddr clk to 1584MHz
331 06:07:41.883797 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 06:07:41.921657
333 06:07:41.922161 dmc_version 0001
334 06:07:41.928639 Check phy result
335 06:07:41.934595 INFO : End of CA training
336 06:07:41.935028 INFO : End of initialization
337 06:07:41.940210 INFO : Training has run successfully!
338 06:07:41.940641 Check phy result
339 06:07:41.945771 INFO : End of initialization
340 06:07:41.946199 INFO : End of read enable training
341 06:07:41.951375 INFO : End of fine write leveling
342 06:07:41.956981 INFO : End of Write leveling coarse delay
343 06:07:41.957409 INFO : Training has run successfully!
344 06:07:41.957804 Check phy result
345 06:07:41.962581 INFO : End of initialization
346 06:07:41.963003 INFO : End of read dq deskew training
347 06:07:41.968212 INFO : End of MPR read delay center optimization
348 06:07:41.973829 INFO : End of write delay center optimization
349 06:07:41.979385 INFO : End of read delay center optimization
350 06:07:41.979820 INFO : End of max read latency training
351 06:07:41.984987 INFO : Training has run successfully!
352 06:07:41.985418 1D training succeed
353 06:07:41.994167 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 06:07:42.042443 Check phy result
355 06:07:42.042876 INFO : End of initialization
356 06:07:42.069875 INFO : End of 2D read delay Voltage center optimization
357 06:07:42.093943 INFO : End of 2D read delay Voltage center optimization
358 06:07:42.150988 INFO : End of 2D write delay Voltage center optimization
359 06:07:42.204594 INFO : End of 2D write delay Voltage center optimization
360 06:07:42.210093 INFO : Training has run successfully!
361 06:07:42.210517
362 06:07:42.210916 channel==0
363 06:07:42.215716 RxClkDly_Margin_A0==88 ps 9
364 06:07:42.216187 TxDqDly_Margin_A0==98 ps 10
365 06:07:42.221329 RxClkDly_Margin_A1==88 ps 9
366 06:07:42.221758 TxDqDly_Margin_A1==88 ps 9
367 06:07:42.222161 TrainedVREFDQ_A0==74
368 06:07:42.227083 TrainedVREFDQ_A1==74
369 06:07:42.227501 VrefDac_Margin_A0==23
370 06:07:42.227891 DeviceVref_Margin_A0==40
371 06:07:42.232576 VrefDac_Margin_A1==23
372 06:07:42.232994 DeviceVref_Margin_A1==40
373 06:07:42.233392
374 06:07:42.233781
375 06:07:42.234171 channel==1
376 06:07:42.238108 RxClkDly_Margin_A0==78 ps 8
377 06:07:42.238529 TxDqDly_Margin_A0==98 ps 10
378 06:07:42.243711 RxClkDly_Margin_A1==69 ps 7
379 06:07:42.244244 TxDqDly_Margin_A1==88 ps 9
380 06:07:42.249318 TrainedVREFDQ_A0==78
381 06:07:42.249744 TrainedVREFDQ_A1==75
382 06:07:42.250139 VrefDac_Margin_A0==22
383 06:07:42.254904 DeviceVref_Margin_A0==36
384 06:07:42.255326 VrefDac_Margin_A1==22
385 06:07:42.260580 DeviceVref_Margin_A1==39
386 06:07:42.260998
387 06:07:42.261397 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 06:07:42.261788
389 06:07:42.294104 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000018 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
390 06:07:42.294617 2D training succeed
391 06:07:42.299692 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 06:07:42.305328 auto size-- 65535DDR cs0 size: 2048MB
393 06:07:42.305746 DDR cs1 size: 2048MB
394 06:07:42.310904 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 06:07:42.311318 cs0 DataBus test pass
396 06:07:42.316935 cs1 DataBus test pass
397 06:07:42.317360 cs0 AddrBus test pass
398 06:07:42.317751 cs1 AddrBus test pass
399 06:07:42.318140
400 06:07:42.322104 100bdlr_step_size ps== 471
401 06:07:42.322534 result report
402 06:07:42.327717 boot times 0Enable ddr reg access
403 06:07:42.332920 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 06:07:42.346731 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 06:07:43.005171 bl2z: ptr: 05129330, size: 00001e40
406 06:07:43.013767 0.0;M3 CHK:0;cm4_sp_mode 0
407 06:07:43.014220 MVN_1=0x00000000
408 06:07:43.014620 MVN_2=0x00000000
409 06:07:43.025859 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 06:07:43.026309 OPS=0x04
411 06:07:43.026708 ring efuse init
412 06:07:43.030875 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 06:07:43.031314 [0.017354 Inits done]
414 06:07:43.031707 secure task start!
415 06:07:43.038286 high task start!
416 06:07:43.038714 low task start!
417 06:07:43.039109 run into bl31
418 06:07:43.046896 NOTICE: BL31: v1.3(release):4fc40b1
419 06:07:43.053783 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 06:07:43.054251 NOTICE: BL31: G12A normal boot!
421 06:07:43.070200 NOTICE: BL31: BL33 decompress pass
422 06:07:43.075899 ERROR: Error initializing runtime service opteed_fast
423 06:07:45.788659 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 06:07:45.789275 bl2_stage_init 0x01
425 06:07:45.789688 bl2_stage_init 0x81
426 06:07:45.794149 hw id: 0x0000 - pwm id 0x01
427 06:07:45.794657 bl2_stage_init 0xc1
428 06:07:45.799799 bl2_stage_init 0x02
429 06:07:45.800344
430 06:07:45.800759 L0:00000000
431 06:07:45.801154 L1:00000703
432 06:07:45.801545 L2:00008067
433 06:07:45.801936 L3:15000000
434 06:07:45.805378 S1:00000000
435 06:07:45.805836 B2:20282000
436 06:07:45.806228 B1:a0f83180
437 06:07:45.806616
438 06:07:45.807006 TE: 68633
439 06:07:45.807391
440 06:07:45.811024 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 06:07:45.811489
442 06:07:45.816590 Board ID = 1
443 06:07:45.817051 Set cpu clk to 24M
444 06:07:45.817445 Set clk81 to 24M
445 06:07:45.822176 Use GP1_pll as DSU clk.
446 06:07:45.822631 DSU clk: 1200 Mhz
447 06:07:45.823024 CPU clk: 1200 MHz
448 06:07:45.827763 Set clk81 to 166.6M
449 06:07:45.833350 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 06:07:45.833812 board id: 1
451 06:07:45.840549 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 06:07:45.851468 fw parse done
453 06:07:45.857409 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 06:07:45.900567 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 06:07:45.911660 PIEI prepare done
456 06:07:45.912177 fastboot data load
457 06:07:45.912583 fastboot data verify
458 06:07:45.917576 verify result: 266
459 06:07:45.922917 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 06:07:45.923398 LPDDR4 probe
461 06:07:45.923821 ddr clk to 1584MHz
462 06:07:45.930929 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 06:07:45.968675
464 06:07:45.969241 dmc_version 0001
465 06:07:45.975680 Check phy result
466 06:07:45.981651 INFO : End of CA training
467 06:07:45.982144 INFO : End of initialization
468 06:07:45.987253 INFO : Training has run successfully!
469 06:07:45.987714 Check phy result
470 06:07:45.992863 INFO : End of initialization
471 06:07:45.993332 INFO : End of read enable training
472 06:07:45.998446 INFO : End of fine write leveling
473 06:07:46.004141 INFO : End of Write leveling coarse delay
474 06:07:46.004602 INFO : Training has run successfully!
475 06:07:46.005002 Check phy result
476 06:07:46.010570 INFO : End of initialization
477 06:07:46.011029 INFO : End of read dq deskew training
478 06:07:46.015247 INFO : End of MPR read delay center optimization
479 06:07:46.020859 INFO : End of write delay center optimization
480 06:07:46.026448 INFO : End of read delay center optimization
481 06:07:46.026910 INFO : End of max read latency training
482 06:07:46.032350 INFO : Training has run successfully!
483 06:07:46.032813 1D training succeed
484 06:07:46.041281 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 06:07:46.089711 Check phy result
486 06:07:46.090258 INFO : End of initialization
487 06:07:46.116970 INFO : End of 2D read delay Voltage center optimization
488 06:07:46.141096 INFO : End of 2D read delay Voltage center optimization
489 06:07:46.197733 INFO : End of 2D write delay Voltage center optimization
490 06:07:46.251731 INFO : End of 2D write delay Voltage center optimization
491 06:07:46.257235 INFO : Training has run successfully!
492 06:07:46.257726
493 06:07:46.258138 channel==0
494 06:07:46.262764 RxClkDly_Margin_A0==78 ps 8
495 06:07:46.263198 TxDqDly_Margin_A0==98 ps 10
496 06:07:46.266143 RxClkDly_Margin_A1==88 ps 9
497 06:07:46.266574 TxDqDly_Margin_A1==98 ps 10
498 06:07:46.271670 TrainedVREFDQ_A0==74
499 06:07:46.272131 TrainedVREFDQ_A1==74
500 06:07:46.272534 VrefDac_Margin_A0==23
501 06:07:46.277261 DeviceVref_Margin_A0==40
502 06:07:46.277686 VrefDac_Margin_A1==22
503 06:07:46.283163 DeviceVref_Margin_A1==40
504 06:07:46.283591
505 06:07:46.284012
506 06:07:46.284411 channel==1
507 06:07:46.284801 RxClkDly_Margin_A0==78 ps 8
508 06:07:46.288504 TxDqDly_Margin_A0==98 ps 10
509 06:07:46.288947 RxClkDly_Margin_A1==78 ps 8
510 06:07:46.294144 TxDqDly_Margin_A1==98 ps 10
511 06:07:46.294578 TrainedVREFDQ_A0==78
512 06:07:46.294977 TrainedVREFDQ_A1==75
513 06:07:46.299665 VrefDac_Margin_A0==22
514 06:07:46.300116 DeviceVref_Margin_A0==36
515 06:07:46.305250 VrefDac_Margin_A1==22
516 06:07:46.305674 DeviceVref_Margin_A1==39
517 06:07:46.306067
518 06:07:46.310887 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 06:07:46.311311
520 06:07:46.338911 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 06:07:46.344528 2D training succeed
522 06:07:46.350114 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 06:07:46.350551 auto size-- 65535DDR cs0 size: 2048MB
524 06:07:46.355662 DDR cs1 size: 2048MB
525 06:07:46.356141 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 06:07:46.361260 cs0 DataBus test pass
527 06:07:46.361695 cs1 DataBus test pass
528 06:07:46.362093 cs0 AddrBus test pass
529 06:07:46.366867 cs1 AddrBus test pass
530 06:07:46.367292
531 06:07:46.367688 100bdlr_step_size ps== 471
532 06:07:46.368120 result report
533 06:07:46.372482 boot times 0Enable ddr reg access
534 06:07:46.380228 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 06:07:46.393972 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 06:07:47.051849 bl2z: ptr: 05129330, size: 00001e40
537 06:07:47.062039 0.0;M3 CHK:0;cm4_sp_mode 0
538 06:07:47.062517 MVN_1=0x00000000
539 06:07:47.062933 MVN_2=0x00000000
540 06:07:47.073477 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 06:07:47.073929 OPS=0x04
542 06:07:47.074343 ring efuse init
543 06:07:47.079166 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 06:07:47.079623 [0.017354 Inits done]
545 06:07:47.080064 secure task start!
546 06:07:47.085489 high task start!
547 06:07:47.085934 low task start!
548 06:07:47.086345 run into bl31
549 06:07:47.095219 NOTICE: BL31: v1.3(release):4fc40b1
550 06:07:47.101920 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 06:07:47.102372 NOTICE: BL31: G12A normal boot!
552 06:07:47.118409 NOTICE: BL31: BL33 decompress pass
553 06:07:47.124098 ERROR: Error initializing runtime service opteed_fast
554 06:07:48.490714 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 06:07:48.491322 bl2_stage_init 0x01
556 06:07:48.491760 bl2_stage_init 0x81
557 06:07:48.496272 hw id: 0x0000 - pwm id 0x01
558 06:07:48.496717 bl2_stage_init 0xc1
559 06:07:48.501864 bl2_stage_init 0x02
560 06:07:48.502298
561 06:07:48.502709 L0:00000000
562 06:07:48.503110 L1:00000703
563 06:07:48.503509 L2:00008067
564 06:07:48.503907 L3:15000000
565 06:07:48.507437 S1:00000000
566 06:07:48.507869 B2:20282000
567 06:07:48.508309 B1:a0f83180
568 06:07:48.508715
569 06:07:48.509118 TE: 70264
570 06:07:48.509521
571 06:07:48.513024 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 06:07:48.513465
573 06:07:48.518688 Board ID = 1
574 06:07:48.519123 Set cpu clk to 24M
575 06:07:48.519531 Set clk81 to 24M
576 06:07:48.524359 Use GP1_pll as DSU clk.
577 06:07:48.524793 DSU clk: 1200 Mhz
578 06:07:48.525198 CPU clk: 1200 MHz
579 06:07:48.529866 Set clk81 to 166.6M
580 06:07:48.535439 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 06:07:48.535876 board id: 1
582 06:07:48.542634 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 06:07:48.553436 fw parse done
584 06:07:48.559266 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 06:07:48.601880 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 06:07:48.612893 PIEI prepare done
587 06:07:48.613333 fastboot data load
588 06:07:48.613749 fastboot data verify
589 06:07:48.618740 verify result: 266
590 06:07:48.624051 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 06:07:48.624495 LPDDR4 probe
592 06:07:48.624904 ddr clk to 1584MHz
593 06:07:48.631461 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 06:07:48.669418
595 06:07:48.669883 dmc_version 0001
596 06:07:48.676013 Check phy result
597 06:07:48.682197 INFO : End of CA training
598 06:07:48.682636 INFO : End of initialization
599 06:07:48.687468 INFO : Training has run successfully!
600 06:07:48.687905 Check phy result
601 06:07:48.693112 INFO : End of initialization
602 06:07:48.693549 INFO : End of read enable training
603 06:07:48.699024 INFO : End of fine write leveling
604 06:07:48.704270 INFO : End of Write leveling coarse delay
605 06:07:48.704706 INFO : Training has run successfully!
606 06:07:48.705114 Check phy result
607 06:07:48.709883 INFO : End of initialization
608 06:07:48.710312 INFO : End of read dq deskew training
609 06:07:48.715563 INFO : End of MPR read delay center optimization
610 06:07:48.721071 INFO : End of write delay center optimization
611 06:07:48.726643 INFO : End of read delay center optimization
612 06:07:48.727075 INFO : End of max read latency training
613 06:07:48.732266 INFO : Training has run successfully!
614 06:07:48.732698 1D training succeed
615 06:07:48.741532 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 06:07:48.789191 Check phy result
617 06:07:48.789715 INFO : End of initialization
618 06:07:48.811154 INFO : End of 2D read delay Voltage center optimization
619 06:07:48.830585 INFO : End of 2D read delay Voltage center optimization
620 06:07:48.882508 INFO : End of 2D write delay Voltage center optimization
621 06:07:48.931578 INFO : End of 2D write delay Voltage center optimization
622 06:07:48.937142 INFO : Training has run successfully!
623 06:07:48.937581
624 06:07:48.937992 channel==0
625 06:07:48.942754 RxClkDly_Margin_A0==78 ps 8
626 06:07:48.943189 TxDqDly_Margin_A0==98 ps 10
627 06:07:48.948347 RxClkDly_Margin_A1==78 ps 8
628 06:07:48.948785 TxDqDly_Margin_A1==88 ps 9
629 06:07:48.949194 TrainedVREFDQ_A0==74
630 06:07:48.953936 TrainedVREFDQ_A1==74
631 06:07:48.954378 VrefDac_Margin_A0==22
632 06:07:48.954785 DeviceVref_Margin_A0==40
633 06:07:48.959566 VrefDac_Margin_A1==23
634 06:07:48.960033 DeviceVref_Margin_A1==40
635 06:07:48.960446
636 06:07:48.960854
637 06:07:48.961251 channel==1
638 06:07:48.965147 RxClkDly_Margin_A0==78 ps 8
639 06:07:48.965588 TxDqDly_Margin_A0==98 ps 10
640 06:07:48.970762 RxClkDly_Margin_A1==78 ps 8
641 06:07:48.971202 TxDqDly_Margin_A1==88 ps 9
642 06:07:48.976455 TrainedVREFDQ_A0==78
643 06:07:48.976896 TrainedVREFDQ_A1==78
644 06:07:48.977302 VrefDac_Margin_A0==22
645 06:07:48.981932 DeviceVref_Margin_A0==36
646 06:07:48.982363 VrefDac_Margin_A1==22
647 06:07:48.987583 DeviceVref_Margin_A1==36
648 06:07:48.988042
649 06:07:48.988455 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 06:07:48.988859
651 06:07:49.021152 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 06:07:49.021629 2D training succeed
653 06:07:49.026746 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 06:07:49.032328 auto size-- 65535DDR cs0 size: 2048MB
655 06:07:49.032765 DDR cs1 size: 2048MB
656 06:07:49.037932 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 06:07:49.038361 cs0 DataBus test pass
658 06:07:49.043553 cs1 DataBus test pass
659 06:07:49.044032 cs0 AddrBus test pass
660 06:07:49.044448 cs1 AddrBus test pass
661 06:07:49.044873
662 06:07:49.049226 100bdlr_step_size ps== 464
663 06:07:49.049715 result report
664 06:07:49.054992 boot times 0Enable ddr reg access
665 06:07:49.059941 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 06:07:49.072759 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 06:07:49.726876 bl2z: ptr: 05129330, size: 00001e40
668 06:07:49.734348 0.0;M3 CHK:0;cm4_sp_mode 0
669 06:07:49.734826 MVN_1=0x00000000
670 06:07:49.735244 MVN_2=0x00000000
671 06:07:49.745858 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 06:07:49.746321 OPS=0x04
673 06:07:49.746739 ring efuse init
674 06:07:49.751637 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 06:07:49.752141 [0.017320 Inits done]
676 06:07:49.752557 secure task start!
677 06:07:49.758054 high task start!
678 06:07:49.758496 low task start!
679 06:07:49.758911 run into bl31
680 06:07:49.767610 NOTICE: BL31: v1.3(release):4fc40b1
681 06:07:49.774360 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 06:07:49.774808 NOTICE: BL31: G12A normal boot!
683 06:07:49.790784 NOTICE: BL31: BL33 decompress pass
684 06:07:49.795515 ERROR: Error initializing runtime service opteed_fast
685 06:07:50.590762
686 06:07:50.591399
687 06:07:50.596230 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 06:07:50.596767
689 06:07:50.599658 Model: Libre Computer AML-S905D3-CC Solitude
690 06:07:50.745641 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 06:07:50.761878 DRAM: 2 GiB (effective 3.8 GiB)
692 06:07:50.862890 Core: 406 devices, 33 uclasses, devicetree: separate
693 06:07:50.868693 WDT: Not starting watchdog@f0d0
694 06:07:50.893845 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 06:07:50.905934 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 06:07:50.910962 ** Bad device specification mmc 0 **
697 06:07:50.921022 Card did not respond to voltage select! : -110
698 06:07:50.928689 ** Bad device specification mmc 0 **
699 06:07:50.929247 Couldn't find partition mmc 0
700 06:07:50.937032 Card did not respond to voltage select! : -110
701 06:07:50.942515 ** Bad device specification mmc 0 **
702 06:07:50.943011 Couldn't find partition mmc 0
703 06:07:50.947625 Error: could not access storage.
704 06:07:51.244612 Net: eth0: ethernet@ff3f0000
705 06:07:51.245232 starting USB...
706 06:07:51.489744 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 06:07:51.490363 Starting the controller
708 06:07:51.496727 USB XHCI 1.10
709 06:07:53.050251 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 06:07:53.057683 scanning usb for storage devices... 0 Storage Device(s) found
712 06:07:53.109339 Hit any key to stop autoboot: 1
713 06:07:53.110570 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
714 06:07:53.111268 start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
715 06:07:53.111811 Setting prompt string to ['=>']
716 06:07:53.112391 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:42)
717 06:07:53.123764 0
718 06:07:53.124789 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 06:07:53.226134 => setenv autoload no
721 06:07:53.226938 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
722 06:07:53.232334 setenv autoload no
724 06:07:53.334022 => setenv initrd_high 0xffffffff
725 06:07:53.334990 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 06:07:53.338700 setenv initrd_high 0xffffffff
728 06:07:53.440446 => setenv fdt_high 0xffffffff
729 06:07:53.441479 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 06:07:53.444841 setenv fdt_high 0xffffffff
732 06:07:53.546510 => dhcp
733 06:07:53.547321 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 06:07:53.550581 dhcp
735 06:07:54.557258 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 06:07:54.557916 Speed: 1000, full duplex
737 06:07:54.558367 BOOTP broadcast 1
738 06:07:54.805152 BOOTP broadcast 2
739 06:07:55.307072 BOOTP broadcast 3
740 06:07:56.308094 BOOTP broadcast 4
741 06:07:58.309061 BOOTP broadcast 5
742 06:07:58.325189 DHCP client bound to address 192.168.6.12 (3767 ms)
744 06:07:58.426376 => setenv serverip 192.168.6.2
745 06:07:58.427305 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
746 06:07:58.431759 setenv serverip 192.168.6.2
748 06:07:58.533150 => tftpboot 0x01080000 790065/tftp-deploy-sttw11oz/kernel/uImage
749 06:07:58.534076 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
750 06:07:58.540657 tftpboot 0x01080000 790065/tftp-deploy-sttw11oz/kernel/uImage
751 06:07:58.540997 Speed: 1000, full duplex
752 06:07:58.541210 Using ethernet@ff3f0000 device
753 06:07:58.546186 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 06:07:58.551663 Filename '790065/tftp-deploy-sttw11oz/kernel/uImage'.
755 06:07:58.555557 Load address: 0x1080000
756 06:08:03.231530 Loading: *################################################## 43.6 MiB
757 06:08:03.232575 9.3 MiB/s
758 06:08:03.233228 done
759 06:08:03.235054 Bytes transferred = 45713984 (2b98a40 hex)
761 06:08:03.336257 => tftpboot 0x08000000 790065/tftp-deploy-sttw11oz/ramdisk/ramdisk.cpio.gz.uboot
762 06:08:03.336950 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
763 06:08:03.343584 tftpboot 0x08000000 790065/tftp-deploy-sttw11oz/ramdisk/ramdisk.cpio.gz.uboot
764 06:08:03.343955 Speed: 1000, full duplex
765 06:08:03.344238 Using ethernet@ff3f0000 device
766 06:08:03.349049 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
767 06:08:03.358249 Filename '790065/tftp-deploy-sttw11oz/ramdisk/ramdisk.cpio.gz.uboot'.
768 06:08:03.358637 Load address: 0x8000000
769 06:08:11.035687 Loading: *#######T ########################################## UDP wrong checksum 00000005 0000fd0a
770 06:08:16.036019 T UDP wrong checksum 00000005 0000fd0a
771 06:08:21.970619 T UDP wrong checksum 000000ff 00003e7c
772 06:08:22.020342 UDP wrong checksum 000000ff 0000c56e
773 06:08:26.037920 T UDP wrong checksum 00000005 0000fd0a
774 06:08:34.190809 T UDP wrong checksum 000000ff 000048a4
775 06:08:34.200822 UDP wrong checksum 000000ff 0000cc96
776 06:08:37.020602 T UDP wrong checksum 000000ff 0000b292
777 06:08:37.030177 UDP wrong checksum 000000ff 00003585
778 06:08:46.040385 T UDP wrong checksum 00000005 0000fd0a
779 06:09:01.045884 T T T
780 06:09:01.046572 Retry count exceeded; starting again
782 06:09:01.048227 end: 2.4.3 bootloader-commands (duration 00:01:08) [common]
785 06:09:01.050349 end: 2.4 uboot-commands (duration 00:01:26) [common]
787 06:09:01.052105 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
789 06:09:01.053285 end: 2 uboot-action (duration 00:01:26) [common]
791 06:09:01.054963 Cleaning after the job
792 06:09:01.055568 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/ramdisk
793 06:09:01.056982 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/kernel
794 06:09:01.066581 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/dtb
795 06:09:01.068238 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790065/tftp-deploy-sttw11oz/modules
796 06:09:01.075082 start: 4.1 power-off (timeout 00:00:30) [common]
797 06:09:01.076242 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
798 06:09:01.115241 >> OK - accepted request
799 06:09:01.117596 Returned 0 in 0 seconds
800 06:09:01.218987 end: 4.1 power-off (duration 00:00:00) [common]
802 06:09:01.220953 start: 4.2 read-feedback (timeout 00:10:00) [common]
803 06:09:01.222191 Listened to connection for namespace 'common' for up to 1s
804 06:09:02.222983 Finalising connection for namespace 'common'
805 06:09:02.223807 Disconnecting from shell: Finalise
806 06:09:02.224453 =>
807 06:09:02.325606 end: 4.2 read-feedback (duration 00:00:01) [common]
808 06:09:02.326446 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/790065
809 06:09:02.810837 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/790065
810 06:09:02.811449 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.