Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:10:37.097635 lava-dispatcher, installed at version: 2024.01
2 06:10:37.098471 start: 0 validate
3 06:10:37.098971 Start time: 2024-10-02 06:10:37.098939+00:00 (UTC)
4 06:10:37.099597 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:10:37.100319 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 06:10:37.143318 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:10:37.143918 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 06:10:37.184413 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:10:37.185061 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:10:37.218601 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:10:37.219105 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:10:37.254158 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 06:10:37.254706 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
14 06:10:37.295021 validate duration: 0.20
16 06:10:37.296568 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:10:37.297178 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:10:37.297779 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:10:37.298737 Not decompressing ramdisk as can be used compressed.
20 06:10:37.299507 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 06:10:37.300061 saving as /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/ramdisk/initrd.cpio.gz
22 06:10:37.300585 total size: 5628182 (5 MB)
23 06:10:37.344246 progress 0 % (0 MB)
24 06:10:37.352767 progress 5 % (0 MB)
25 06:10:37.361456 progress 10 % (0 MB)
26 06:10:37.369127 progress 15 % (0 MB)
27 06:10:37.377733 progress 20 % (1 MB)
28 06:10:37.382483 progress 25 % (1 MB)
29 06:10:37.386410 progress 30 % (1 MB)
30 06:10:37.390412 progress 35 % (1 MB)
31 06:10:37.394015 progress 40 % (2 MB)
32 06:10:37.397867 progress 45 % (2 MB)
33 06:10:37.401350 progress 50 % (2 MB)
34 06:10:37.405346 progress 55 % (2 MB)
35 06:10:37.409253 progress 60 % (3 MB)
36 06:10:37.412735 progress 65 % (3 MB)
37 06:10:37.416727 progress 70 % (3 MB)
38 06:10:37.420442 progress 75 % (4 MB)
39 06:10:37.424397 progress 80 % (4 MB)
40 06:10:37.427911 progress 85 % (4 MB)
41 06:10:37.431642 progress 90 % (4 MB)
42 06:10:37.435164 progress 95 % (5 MB)
43 06:10:37.438350 progress 100 % (5 MB)
44 06:10:37.438990 5 MB downloaded in 0.14 s (38.78 MB/s)
45 06:10:37.439533 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:10:37.440456 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:10:37.440751 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:10:37.441024 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:10:37.441497 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
51 06:10:37.441738 saving as /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/kernel/Image
52 06:10:37.441949 total size: 45713920 (43 MB)
53 06:10:37.442160 No compression specified
54 06:10:37.484358 progress 0 % (0 MB)
55 06:10:37.512363 progress 5 % (2 MB)
56 06:10:37.540820 progress 10 % (4 MB)
57 06:10:37.568697 progress 15 % (6 MB)
58 06:10:37.596525 progress 20 % (8 MB)
59 06:10:37.624012 progress 25 % (10 MB)
60 06:10:37.651639 progress 30 % (13 MB)
61 06:10:37.679573 progress 35 % (15 MB)
62 06:10:37.707273 progress 40 % (17 MB)
63 06:10:37.734913 progress 45 % (19 MB)
64 06:10:37.762616 progress 50 % (21 MB)
65 06:10:37.790355 progress 55 % (24 MB)
66 06:10:37.818292 progress 60 % (26 MB)
67 06:10:37.845635 progress 65 % (28 MB)
68 06:10:37.873461 progress 70 % (30 MB)
69 06:10:37.900945 progress 75 % (32 MB)
70 06:10:37.928869 progress 80 % (34 MB)
71 06:10:37.956398 progress 85 % (37 MB)
72 06:10:37.984272 progress 90 % (39 MB)
73 06:10:38.012106 progress 95 % (41 MB)
74 06:10:38.039528 progress 100 % (43 MB)
75 06:10:38.040062 43 MB downloaded in 0.60 s (72.89 MB/s)
76 06:10:38.040533 end: 1.2.1 http-download (duration 00:00:01) [common]
78 06:10:38.041350 end: 1.2 download-retry (duration 00:00:01) [common]
79 06:10:38.041624 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:10:38.041887 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:10:38.042361 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 06:10:38.042660 saving as /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/dtb/meson-g12b-a311d-libretech-cc.dtb
83 06:10:38.042879 total size: 54703 (0 MB)
84 06:10:38.043089 No compression specified
85 06:10:38.079998 progress 59 % (0 MB)
86 06:10:38.080859 progress 100 % (0 MB)
87 06:10:38.081394 0 MB downloaded in 0.04 s (1.35 MB/s)
88 06:10:38.081853 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:10:38.082663 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:10:38.082924 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:10:38.083186 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:10:38.083639 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 06:10:38.083876 saving as /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/nfsrootfs/full.rootfs.tar
95 06:10:38.084104 total size: 107552908 (102 MB)
96 06:10:38.084318 Using unxz to decompress xz
97 06:10:38.123619 progress 0 % (0 MB)
98 06:10:38.761329 progress 5 % (5 MB)
99 06:10:39.477227 progress 10 % (10 MB)
100 06:10:40.193975 progress 15 % (15 MB)
101 06:10:40.942972 progress 20 % (20 MB)
102 06:10:41.508329 progress 25 % (25 MB)
103 06:10:42.125675 progress 30 % (30 MB)
104 06:10:42.858513 progress 35 % (35 MB)
105 06:10:43.204767 progress 40 % (41 MB)
106 06:10:43.631280 progress 45 % (46 MB)
107 06:10:44.320331 progress 50 % (51 MB)
108 06:10:45.016949 progress 55 % (56 MB)
109 06:10:45.784506 progress 60 % (61 MB)
110 06:10:46.541135 progress 65 % (66 MB)
111 06:10:47.279421 progress 70 % (71 MB)
112 06:10:48.052871 progress 75 % (76 MB)
113 06:10:48.734651 progress 80 % (82 MB)
114 06:10:49.441319 progress 85 % (87 MB)
115 06:10:50.177453 progress 90 % (92 MB)
116 06:10:50.892916 progress 95 % (97 MB)
117 06:10:51.632587 progress 100 % (102 MB)
118 06:10:51.644445 102 MB downloaded in 13.56 s (7.56 MB/s)
119 06:10:51.645465 end: 1.4.1 http-download (duration 00:00:14) [common]
121 06:10:51.647351 end: 1.4 download-retry (duration 00:00:14) [common]
122 06:10:51.647934 start: 1.5 download-retry (timeout 00:09:46) [common]
123 06:10:51.648586 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 06:10:51.649456 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
125 06:10:51.649983 saving as /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/modules/modules.tar
126 06:10:51.650452 total size: 11621068 (11 MB)
127 06:10:51.650943 Using unxz to decompress xz
128 06:10:51.696781 progress 0 % (0 MB)
129 06:10:51.771131 progress 5 % (0 MB)
130 06:10:51.848877 progress 10 % (1 MB)
131 06:10:51.935842 progress 15 % (1 MB)
132 06:10:52.013768 progress 20 % (2 MB)
133 06:10:52.097591 progress 25 % (2 MB)
134 06:10:52.179271 progress 30 % (3 MB)
135 06:10:52.259884 progress 35 % (3 MB)
136 06:10:52.335847 progress 40 % (4 MB)
137 06:10:52.414118 progress 45 % (5 MB)
138 06:10:52.493259 progress 50 % (5 MB)
139 06:10:52.571168 progress 55 % (6 MB)
140 06:10:52.651769 progress 60 % (6 MB)
141 06:10:52.738533 progress 65 % (7 MB)
142 06:10:52.822140 progress 70 % (7 MB)
143 06:10:52.916331 progress 75 % (8 MB)
144 06:10:53.013210 progress 80 % (8 MB)
145 06:10:53.095174 progress 85 % (9 MB)
146 06:10:53.173429 progress 90 % (10 MB)
147 06:10:53.246810 progress 95 % (10 MB)
148 06:10:53.323923 progress 100 % (11 MB)
149 06:10:53.336600 11 MB downloaded in 1.69 s (6.57 MB/s)
150 06:10:53.337395 end: 1.5.1 http-download (duration 00:00:02) [common]
152 06:10:53.339050 end: 1.5 download-retry (duration 00:00:02) [common]
153 06:10:53.339587 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 06:10:53.340159 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 06:11:03.246520 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/790068/extract-nfsrootfs-neft9m4w
156 06:11:03.247116 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 06:11:03.247406 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 06:11:03.248169 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g
159 06:11:03.248664 makedir: /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin
160 06:11:03.249027 makedir: /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/tests
161 06:11:03.249354 makedir: /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/results
162 06:11:03.249700 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-add-keys
163 06:11:03.250244 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-add-sources
164 06:11:03.250773 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-background-process-start
165 06:11:03.251289 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-background-process-stop
166 06:11:03.251819 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-common-functions
167 06:11:03.252377 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-echo-ipv4
168 06:11:03.252888 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-install-packages
169 06:11:03.253400 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-installed-packages
170 06:11:03.253955 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-os-build
171 06:11:03.254484 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-probe-channel
172 06:11:03.254988 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-probe-ip
173 06:11:03.255503 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-target-ip
174 06:11:03.256126 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-target-mac
175 06:11:03.256660 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-target-storage
176 06:11:03.257189 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-test-case
177 06:11:03.257726 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-test-event
178 06:11:03.258223 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-test-feedback
179 06:11:03.258738 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-test-raise
180 06:11:03.259239 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-test-reference
181 06:11:03.259735 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-test-runner
182 06:11:03.260294 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-test-set
183 06:11:03.260816 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-test-shell
184 06:11:03.261359 Updating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-install-packages (oe)
185 06:11:03.261935 Updating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/bin/lava-installed-packages (oe)
186 06:11:03.262392 Creating /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/environment
187 06:11:03.262796 LAVA metadata
188 06:11:03.263072 - LAVA_JOB_ID=790068
189 06:11:03.263294 - LAVA_DISPATCHER_IP=192.168.6.2
190 06:11:03.263692 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 06:11:03.264781 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 06:11:03.265148 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 06:11:03.265362 skipped lava-vland-overlay
194 06:11:03.265610 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 06:11:03.265871 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 06:11:03.266096 skipped lava-multinode-overlay
197 06:11:03.266344 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 06:11:03.266599 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 06:11:03.266855 Loading test definitions
200 06:11:03.267143 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 06:11:03.267368 Using /lava-790068 at stage 0
202 06:11:03.268662 uuid=790068_1.6.2.4.1 testdef=None
203 06:11:03.268998 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 06:11:03.269265 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 06:11:03.271083 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 06:11:03.271892 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 06:11:03.274226 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 06:11:03.275075 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 06:11:03.277354 runner path: /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/0/tests/0_dmesg test_uuid 790068_1.6.2.4.1
212 06:11:03.277993 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 06:11:03.278776 Creating lava-test-runner.conf files
215 06:11:03.278984 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/790068/lava-overlay-aizqaz8g/lava-790068/0 for stage 0
216 06:11:03.279347 - 0_dmesg
217 06:11:03.279710 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 06:11:03.280018 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 06:11:03.301851 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 06:11:03.302283 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 06:11:03.302553 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 06:11:03.302826 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 06:11:03.303097 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 06:11:03.934036 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 06:11:03.934626 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 06:11:03.935011 extracting modules file /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/790068/extract-nfsrootfs-neft9m4w
227 06:11:05.371219 extracting modules file /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/790068/extract-overlay-ramdisk-33hmzbpv/ramdisk
228 06:11:06.838607 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 06:11:06.839126 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 06:11:06.839459 [common] Applying overlay to NFS
231 06:11:06.839714 [common] Applying overlay /var/lib/lava/dispatcher/tmp/790068/compress-overlay-si2823qv/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/790068/extract-nfsrootfs-neft9m4w
232 06:11:06.874429 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 06:11:06.874938 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 06:11:06.875257 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 06:11:06.875527 Converting downloaded kernel to a uImage
236 06:11:06.875908 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/kernel/Image /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/kernel/uImage
237 06:11:07.343235 output: Image Name:
238 06:11:07.343664 output: Created: Wed Oct 2 06:11:06 2024
239 06:11:07.343881 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 06:11:07.344195 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 06:11:07.344409 output: Load Address: 01080000
242 06:11:07.344615 output: Entry Point: 01080000
243 06:11:07.344818 output:
244 06:11:07.345156 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 06:11:07.345433 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 06:11:07.345712 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 06:11:07.345978 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 06:11:07.346248 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 06:11:07.346516 Building ramdisk /var/lib/lava/dispatcher/tmp/790068/extract-overlay-ramdisk-33hmzbpv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/790068/extract-overlay-ramdisk-33hmzbpv/ramdisk
250 06:11:09.814979 >> 166918 blocks
251 06:11:17.999562 Adding RAMdisk u-boot header.
252 06:11:18.000322 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/790068/extract-overlay-ramdisk-33hmzbpv/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/790068/extract-overlay-ramdisk-33hmzbpv/ramdisk.cpio.gz.uboot
253 06:11:18.249239 output: Image Name:
254 06:11:18.249629 output: Created: Wed Oct 2 06:11:18 2024
255 06:11:18.249846 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 06:11:18.250054 output: Data Size: 23436579 Bytes = 22887.28 KiB = 22.35 MiB
257 06:11:18.250261 output: Load Address: 00000000
258 06:11:18.250463 output: Entry Point: 00000000
259 06:11:18.250661 output:
260 06:11:18.251275 rename /var/lib/lava/dispatcher/tmp/790068/extract-overlay-ramdisk-33hmzbpv/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/ramdisk/ramdisk.cpio.gz.uboot
261 06:11:18.251688 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 06:11:18.251974 end: 1.6 prepare-tftp-overlay (duration 00:00:25) [common]
263 06:11:18.252630 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
264 06:11:18.253171 No LXC device requested
265 06:11:18.253479 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 06:11:18.253759 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
267 06:11:18.254034 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 06:11:18.254263 Checking files for TFTP limit of 4294967296 bytes.
269 06:11:18.255697 end: 1 tftp-deploy (duration 00:00:41) [common]
270 06:11:18.256050 start: 2 uboot-action (timeout 00:05:00) [common]
271 06:11:18.256358 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 06:11:18.256639 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 06:11:18.256925 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 06:11:18.257229 Using kernel file from prepare-kernel: 790068/tftp-deploy-h58onhk9/kernel/uImage
275 06:11:18.257581 substitutions:
276 06:11:18.257802 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 06:11:18.258019 - {DTB_ADDR}: 0x01070000
278 06:11:18.258230 - {DTB}: 790068/tftp-deploy-h58onhk9/dtb/meson-g12b-a311d-libretech-cc.dtb
279 06:11:18.258442 - {INITRD}: 790068/tftp-deploy-h58onhk9/ramdisk/ramdisk.cpio.gz.uboot
280 06:11:18.258680 - {KERNEL_ADDR}: 0x01080000
281 06:11:18.258906 - {KERNEL}: 790068/tftp-deploy-h58onhk9/kernel/uImage
282 06:11:18.259112 - {LAVA_MAC}: None
283 06:11:18.259344 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/790068/extract-nfsrootfs-neft9m4w
284 06:11:18.259549 - {NFS_SERVER_IP}: 192.168.6.2
285 06:11:18.259759 - {PRESEED_CONFIG}: None
286 06:11:18.259976 - {PRESEED_LOCAL}: None
287 06:11:18.260278 - {RAMDISK_ADDR}: 0x08000000
288 06:11:18.260486 - {RAMDISK}: 790068/tftp-deploy-h58onhk9/ramdisk/ramdisk.cpio.gz.uboot
289 06:11:18.260696 - {ROOT_PART}: None
290 06:11:18.260901 - {ROOT}: None
291 06:11:18.261102 - {SERVER_IP}: 192.168.6.2
292 06:11:18.261317 - {TEE_ADDR}: 0x83000000
293 06:11:18.261521 - {TEE}: None
294 06:11:18.261722 Parsed boot commands:
295 06:11:18.261918 - setenv autoload no
296 06:11:18.262122 - setenv initrd_high 0xffffffff
297 06:11:18.262322 - setenv fdt_high 0xffffffff
298 06:11:18.262522 - dhcp
299 06:11:18.262735 - setenv serverip 192.168.6.2
300 06:11:18.262939 - tftpboot 0x01080000 790068/tftp-deploy-h58onhk9/kernel/uImage
301 06:11:18.263141 - tftpboot 0x08000000 790068/tftp-deploy-h58onhk9/ramdisk/ramdisk.cpio.gz.uboot
302 06:11:18.263377 - tftpboot 0x01070000 790068/tftp-deploy-h58onhk9/dtb/meson-g12b-a311d-libretech-cc.dtb
303 06:11:18.263600 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/790068/extract-nfsrootfs-neft9m4w,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 06:11:18.263814 - bootm 0x01080000 0x08000000 0x01070000
305 06:11:18.264178 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 06:11:18.265027 start: 2.3 connect-device (timeout 00:05:00) [common]
308 06:11:18.265260 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 06:11:18.277659 Setting prompt string to ['lava-test: # ']
310 06:11:18.278666 end: 2.3 connect-device (duration 00:00:00) [common]
311 06:11:18.279091 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 06:11:18.279442 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 06:11:18.279750 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 06:11:18.280440 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 06:11:18.319795 >> OK - accepted request
316 06:11:18.321997 Returned 0 in 0 seconds
317 06:11:18.422837 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 06:11:18.423903 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 06:11:18.424315 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 06:11:18.424651 Setting prompt string to ['Hit any key to stop autoboot']
322 06:11:18.424944 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 06:11:18.425938 Trying 192.168.56.21...
324 06:11:18.426258 Connected to conserv1.
325 06:11:18.426517 Escape character is '^]'.
326 06:11:18.426771
327 06:11:18.427036 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 06:11:18.427291
329 06:11:29.937147 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 06:11:29.937679 bl2_stage_init 0x01
331 06:11:29.937978 bl2_stage_init 0x81
332 06:11:29.942789 hw id: 0x0000 - pwm id 0x01
333 06:11:29.943187 bl2_stage_init 0xc1
334 06:11:29.943478 bl2_stage_init 0x02
335 06:11:29.943734
336 06:11:29.948110 L0:00000000
337 06:11:29.948509 L1:20000703
338 06:11:29.948774 L2:00008067
339 06:11:29.949028 L3:14000000
340 06:11:29.953736 B2:00402000
341 06:11:29.954110 B1:e0f83180
342 06:11:29.954391
343 06:11:29.954655 TE: 58159
344 06:11:29.954919
345 06:11:29.959342 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 06:11:29.959710
347 06:11:29.960005 Board ID = 1
348 06:11:29.965110 Set A53 clk to 24M
349 06:11:29.965488 Set A73 clk to 24M
350 06:11:29.965761 Set clk81 to 24M
351 06:11:29.970782 A53 clk: 1200 MHz
352 06:11:29.971202 A73 clk: 1200 MHz
353 06:11:29.971482 CLK81: 166.6M
354 06:11:29.971744 smccc: 00012ab5
355 06:11:29.976298 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 06:11:29.981744 board id: 1
357 06:11:29.987686 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 06:11:29.998325 fw parse done
359 06:11:30.004253 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 06:11:30.046671 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 06:11:30.057597 PIEI prepare done
362 06:11:30.057998 fastboot data load
363 06:11:30.058279 fastboot data verify
364 06:11:30.063145 verify result: 266
365 06:11:30.068758 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 06:11:30.069192 LPDDR4 probe
367 06:11:30.069483 ddr clk to 1584MHz
368 06:11:30.076690 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 06:11:30.114146
370 06:11:30.114827 dmc_version 0001
371 06:11:30.120694 Check phy result
372 06:11:30.126563 INFO : End of CA training
373 06:11:30.127112 INFO : End of initialization
374 06:11:30.132168 INFO : Training has run successfully!
375 06:11:30.132531 Check phy result
376 06:11:30.137743 INFO : End of initialization
377 06:11:30.138112 INFO : End of read enable training
378 06:11:30.143449 INFO : End of fine write leveling
379 06:11:30.148969 INFO : End of Write leveling coarse delay
380 06:11:30.149533 INFO : Training has run successfully!
381 06:11:30.149848 Check phy result
382 06:11:30.154516 INFO : End of initialization
383 06:11:30.154872 INFO : End of read dq deskew training
384 06:11:30.160156 INFO : End of MPR read delay center optimization
385 06:11:30.165684 INFO : End of write delay center optimization
386 06:11:30.171456 INFO : End of read delay center optimization
387 06:11:30.171810 INFO : End of max read latency training
388 06:11:30.176979 INFO : Training has run successfully!
389 06:11:30.177369 1D training succeed
390 06:11:30.186128 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 06:11:30.233787 Check phy result
392 06:11:30.234300 INFO : End of initialization
393 06:11:30.255639 INFO : End of 2D read delay Voltage center optimization
394 06:11:30.275758 INFO : End of 2D read delay Voltage center optimization
395 06:11:30.327857 INFO : End of 2D write delay Voltage center optimization
396 06:11:30.377131 INFO : End of 2D write delay Voltage center optimization
397 06:11:30.382666 INFO : Training has run successfully!
398 06:11:30.383189
399 06:11:30.383504 channel==0
400 06:11:30.388312 RxClkDly_Margin_A0==88 ps 9
401 06:11:30.388708 TxDqDly_Margin_A0==98 ps 10
402 06:11:30.393842 RxClkDly_Margin_A1==88 ps 9
403 06:11:30.394188 TxDqDly_Margin_A1==88 ps 9
404 06:11:30.394455 TrainedVREFDQ_A0==74
405 06:11:30.399530 TrainedVREFDQ_A1==75
406 06:11:30.399907 VrefDac_Margin_A0==25
407 06:11:30.400217 DeviceVref_Margin_A0==40
408 06:11:30.405011 VrefDac_Margin_A1==25
409 06:11:30.405360 DeviceVref_Margin_A1==39
410 06:11:30.405637
411 06:11:30.405907
412 06:11:30.406177 channel==1
413 06:11:30.410587 RxClkDly_Margin_A0==98 ps 10
414 06:11:30.410919 TxDqDly_Margin_A0==98 ps 10
415 06:11:30.416295 RxClkDly_Margin_A1==98 ps 10
416 06:11:30.416654 TxDqDly_Margin_A1==88 ps 9
417 06:11:30.421785 TrainedVREFDQ_A0==77
418 06:11:30.422136 TrainedVREFDQ_A1==77
419 06:11:30.422411 VrefDac_Margin_A0==22
420 06:11:30.427436 DeviceVref_Margin_A0==37
421 06:11:30.427773 VrefDac_Margin_A1==24
422 06:11:30.433093 DeviceVref_Margin_A1==37
423 06:11:30.433556
424 06:11:30.433896 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 06:11:30.434246
426 06:11:30.466622 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 06:11:30.467190 2D training succeed
428 06:11:30.472277 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 06:11:30.477812 auto size-- 65535DDR cs0 size: 2048MB
430 06:11:30.478279 DDR cs1 size: 2048MB
431 06:11:30.483575 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 06:11:30.484102 cs0 DataBus test pass
433 06:11:30.489098 cs1 DataBus test pass
434 06:11:30.489571 cs0 AddrBus test pass
435 06:11:30.490212 cs1 AddrBus test pass
436 06:11:30.490894
437 06:11:30.494688 100bdlr_step_size ps== 420
438 06:11:30.495201 result report
439 06:11:30.500433 boot times 0Enable ddr reg access
440 06:11:30.505681 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 06:11:30.519251 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 06:11:31.092863 0.0;M3 CHK:0;cm4_sp_mode 0
443 06:11:31.093566 MVN_1=0x00000000
444 06:11:31.098617 MVN_2=0x00000000
445 06:11:31.104142 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 06:11:31.104760 OPS=0x10
447 06:11:31.105230 ring efuse init
448 06:11:31.105680 chipver efuse init
449 06:11:31.109673 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 06:11:31.115320 [0.018961 Inits done]
451 06:11:31.115965 secure task start!
452 06:11:31.116470 high task start!
453 06:11:31.119862 low task start!
454 06:11:31.120531 run into bl31
455 06:11:31.126704 NOTICE: BL31: v1.3(release):4fc40b1
456 06:11:31.134300 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 06:11:31.134993 NOTICE: BL31: G12A normal boot!
458 06:11:31.160316 NOTICE: BL31: BL33 decompress pass
459 06:11:31.166158 ERROR: Error initializing runtime service opteed_fast
460 06:11:32.398114
461 06:11:32.398772
462 06:11:32.405790 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 06:11:32.406331
464 06:11:32.406822 Model: Libre Computer AML-A311D-CC Alta
465 06:11:32.614114 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 06:11:32.637517 DRAM: 2 GiB (effective 3.8 GiB)
467 06:11:32.781350 Core: 408 devices, 31 uclasses, devicetree: separate
468 06:11:32.786278 WDT: Not starting watchdog@f0d0
469 06:11:32.819542 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 06:11:32.831910 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 06:11:32.835969 ** Bad device specification mmc 0 **
472 06:11:32.847413 Card did not respond to voltage select! : -110
473 06:11:32.853947 ** Bad device specification mmc 0 **
474 06:11:32.854507 Couldn't find partition mmc 0
475 06:11:32.863289 Card did not respond to voltage select! : -110
476 06:11:32.868857 ** Bad device specification mmc 0 **
477 06:11:32.869399 Couldn't find partition mmc 0
478 06:11:32.872947 Error: could not access storage.
479 06:11:34.136414 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 06:11:34.137081 bl2_stage_init 0x01
481 06:11:34.137652 bl2_stage_init 0x81
482 06:11:34.141788 hw id: 0x0000 - pwm id 0x01
483 06:11:34.142316 bl2_stage_init 0xc1
484 06:11:34.142780 bl2_stage_init 0x02
485 06:11:34.143233
486 06:11:34.147346 L0:00000000
487 06:11:34.147878 L1:20000703
488 06:11:34.148384 L2:00008067
489 06:11:34.148831 L3:14000000
490 06:11:34.153020 B2:00402000
491 06:11:34.153539 B1:e0f83180
492 06:11:34.153997
493 06:11:34.154444 TE: 58124
494 06:11:34.154889
495 06:11:34.158570 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 06:11:34.159090
497 06:11:34.159550 Board ID = 1
498 06:11:34.164124 Set A53 clk to 24M
499 06:11:34.164644 Set A73 clk to 24M
500 06:11:34.165199 Set clk81 to 24M
501 06:11:34.169843 A53 clk: 1200 MHz
502 06:11:34.170381 A73 clk: 1200 MHz
503 06:11:34.170847 CLK81: 166.6M
504 06:11:34.171304 smccc: 00012a92
505 06:11:34.175365 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 06:11:34.181025 board id: 1
507 06:11:34.186857 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 06:11:34.197649 fw parse done
509 06:11:34.202583 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 06:11:34.246118 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 06:11:34.257065 PIEI prepare done
512 06:11:34.257598 fastboot data load
513 06:11:34.258057 fastboot data verify
514 06:11:34.262669 verify result: 266
515 06:11:34.268206 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 06:11:34.268725 LPDDR4 probe
517 06:11:34.269185 ddr clk to 1584MHz
518 06:11:34.276204 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 06:11:34.313589
520 06:11:34.314182 dmc_version 0001
521 06:11:34.320198 Check phy result
522 06:11:34.326030 INFO : End of CA training
523 06:11:34.326533 INFO : End of initialization
524 06:11:34.331599 INFO : Training has run successfully!
525 06:11:34.332160 Check phy result
526 06:11:34.337208 INFO : End of initialization
527 06:11:34.337714 INFO : End of read enable training
528 06:11:34.342796 INFO : End of fine write leveling
529 06:11:34.348397 INFO : End of Write leveling coarse delay
530 06:11:34.348901 INFO : Training has run successfully!
531 06:11:34.349354 Check phy result
532 06:11:34.354057 INFO : End of initialization
533 06:11:34.354568 INFO : End of read dq deskew training
534 06:11:34.359633 INFO : End of MPR read delay center optimization
535 06:11:34.365226 INFO : End of write delay center optimization
536 06:11:34.370755 INFO : End of read delay center optimization
537 06:11:34.371251 INFO : End of max read latency training
538 06:11:34.376370 INFO : Training has run successfully!
539 06:11:34.376855 1D training succeed
540 06:11:34.384631 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 06:11:34.433349 Check phy result
542 06:11:34.434024 INFO : End of initialization
543 06:11:34.455722 INFO : End of 2D read delay Voltage center optimization
544 06:11:34.475738 INFO : End of 2D read delay Voltage center optimization
545 06:11:34.527701 INFO : End of 2D write delay Voltage center optimization
546 06:11:34.576857 INFO : End of 2D write delay Voltage center optimization
547 06:11:34.582420 INFO : Training has run successfully!
548 06:11:34.582951
549 06:11:34.583422 channel==0
550 06:11:34.588059 RxClkDly_Margin_A0==88 ps 9
551 06:11:34.588601 TxDqDly_Margin_A0==98 ps 10
552 06:11:34.593619 RxClkDly_Margin_A1==88 ps 9
553 06:11:34.594213 TxDqDly_Margin_A1==98 ps 10
554 06:11:34.594691 TrainedVREFDQ_A0==74
555 06:11:34.599293 TrainedVREFDQ_A1==74
556 06:11:34.599839 VrefDac_Margin_A0==25
557 06:11:34.600354 DeviceVref_Margin_A0==40
558 06:11:34.604920 VrefDac_Margin_A1==24
559 06:11:34.605449 DeviceVref_Margin_A1==40
560 06:11:34.605916
561 06:11:34.606366
562 06:11:34.610485 channel==1
563 06:11:34.611009 RxClkDly_Margin_A0==88 ps 9
564 06:11:34.611464 TxDqDly_Margin_A0==98 ps 10
565 06:11:34.616201 RxClkDly_Margin_A1==98 ps 10
566 06:11:34.616751 TxDqDly_Margin_A1==98 ps 10
567 06:11:34.621730 TrainedVREFDQ_A0==77
568 06:11:34.622280 TrainedVREFDQ_A1==78
569 06:11:34.622745 VrefDac_Margin_A0==22
570 06:11:34.627315 DeviceVref_Margin_A0==37
571 06:11:34.627871 VrefDac_Margin_A1==22
572 06:11:34.632950 DeviceVref_Margin_A1==36
573 06:11:34.633507
574 06:11:34.633977 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 06:11:34.638477
576 06:11:34.666454 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 06:11:34.667101 2D training succeed
578 06:11:34.672218 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 06:11:34.677763 auto size-- 65535DDR cs0 size: 2048MB
580 06:11:34.678349 DDR cs1 size: 2048MB
581 06:11:34.683323 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 06:11:34.683895 cs0 DataBus test pass
583 06:11:34.688921 cs1 DataBus test pass
584 06:11:34.689486 cs0 AddrBus test pass
585 06:11:34.689958 cs1 AddrBus test pass
586 06:11:34.690416
587 06:11:34.694518 100bdlr_step_size ps== 420
588 06:11:34.695109 result report
589 06:11:34.700232 boot times 0Enable ddr reg access
590 06:11:34.705564 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 06:11:34.718988 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 06:11:35.290899 0.0;M3 CHK:0;cm4_sp_mode 0
593 06:11:35.291599 MVN_1=0x00000000
594 06:11:35.296555 MVN_2=0x00000000
595 06:11:35.302372 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 06:11:35.302945 OPS=0x10
597 06:11:35.303458 ring efuse init
598 06:11:35.303973 chipver efuse init
599 06:11:35.310496 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 06:11:35.311094 [0.018961 Inits done]
601 06:11:35.317161 secure task start!
602 06:11:35.317694 high task start!
603 06:11:35.318136 low task start!
604 06:11:35.318570 run into bl31
605 06:11:35.324789 NOTICE: BL31: v1.3(release):4fc40b1
606 06:11:35.331899 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 06:11:35.332482 NOTICE: BL31: G12A normal boot!
608 06:11:35.357924 NOTICE: BL31: BL33 decompress pass
609 06:11:35.362788 ERROR: Error initializing runtime service opteed_fast
610 06:11:36.596527
611 06:11:36.597209
612 06:11:36.604926 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 06:11:36.605515
614 06:11:36.605992 Model: Libre Computer AML-A311D-CC Alta
615 06:11:36.813261 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 06:11:36.836759 DRAM: 2 GiB (effective 3.8 GiB)
617 06:11:36.979615 Core: 408 devices, 31 uclasses, devicetree: separate
618 06:11:36.985490 WDT: Not starting watchdog@f0d0
619 06:11:37.017873 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 06:11:37.030178 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 06:11:37.035244 ** Bad device specification mmc 0 **
622 06:11:37.045497 Card did not respond to voltage select! : -110
623 06:11:37.053209 ** Bad device specification mmc 0 **
624 06:11:37.053807 Couldn't find partition mmc 0
625 06:11:37.061534 Card did not respond to voltage select! : -110
626 06:11:37.067032 ** Bad device specification mmc 0 **
627 06:11:37.067572 Couldn't find partition mmc 0
628 06:11:37.072103 Error: could not access storage.
629 06:11:37.414677 Net: eth0: ethernet@ff3f0000
630 06:11:37.415368 starting USB...
631 06:11:37.666271 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 06:11:37.666703 Starting the controller
633 06:11:37.673155 USB XHCI 1.10
634 06:11:39.387899 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 06:11:39.388372 bl2_stage_init 0x01
636 06:11:39.388594 bl2_stage_init 0x81
637 06:11:39.393424 hw id: 0x0000 - pwm id 0x01
638 06:11:39.393732 bl2_stage_init 0xc1
639 06:11:39.393944 bl2_stage_init 0x02
640 06:11:39.394157
641 06:11:39.399104 L0:00000000
642 06:11:39.399417 L1:20000703
643 06:11:39.399637 L2:00008067
644 06:11:39.399856 L3:14000000
645 06:11:39.404620 B2:00402000
646 06:11:39.404939 B1:e0f83180
647 06:11:39.405153
648 06:11:39.405363 TE: 58124
649 06:11:39.405585
650 06:11:39.410257 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 06:11:39.410570
652 06:11:39.410786 Board ID = 1
653 06:11:39.415827 Set A53 clk to 24M
654 06:11:39.416129 Set A73 clk to 24M
655 06:11:39.416340 Set clk81 to 24M
656 06:11:39.421434 A53 clk: 1200 MHz
657 06:11:39.421719 A73 clk: 1200 MHz
658 06:11:39.421922 CLK81: 166.6M
659 06:11:39.422120 smccc: 00012a92
660 06:11:39.426989 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 06:11:39.432588 board id: 1
662 06:11:39.438485 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 06:11:39.449241 fw parse done
664 06:11:39.455146 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 06:11:39.497773 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 06:11:39.508752 PIEI prepare done
667 06:11:39.509374 fastboot data load
668 06:11:39.509917 fastboot data verify
669 06:11:39.514392 verify result: 266
670 06:11:39.519946 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 06:11:39.520596 LPDDR4 probe
672 06:11:39.521120 ddr clk to 1584MHz
673 06:11:39.528053 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 06:11:39.565246
675 06:11:39.565882 dmc_version 0001
676 06:11:39.571865 Check phy result
677 06:11:39.577686 INFO : End of CA training
678 06:11:39.578224 INFO : End of initialization
679 06:11:39.583335 INFO : Training has run successfully!
680 06:11:39.583878 Check phy result
681 06:11:39.588900 INFO : End of initialization
682 06:11:39.589429 INFO : End of read enable training
683 06:11:39.592342 INFO : End of fine write leveling
684 06:11:39.597821 INFO : End of Write leveling coarse delay
685 06:11:39.603390 INFO : Training has run successfully!
686 06:11:39.603916 Check phy result
687 06:11:39.604429 INFO : End of initialization
688 06:11:39.610901 INFO : End of read dq deskew training
689 06:11:39.614758 INFO : End of MPR read delay center optimization
690 06:11:39.615318 INFO : End of write delay center optimization
691 06:11:39.620342 INFO : End of read delay center optimization
692 06:11:39.625865 INFO : End of max read latency training
693 06:11:39.626418 INFO : Training has run successfully!
694 06:11:39.631434 1D training succeed
695 06:11:39.637508 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 06:11:39.685085 Check phy result
697 06:11:39.685707 INFO : End of initialization
698 06:11:39.706577 INFO : End of 2D read delay Voltage center optimization
699 06:11:39.726723 INFO : End of 2D read delay Voltage center optimization
700 06:11:39.778644 INFO : End of 2D write delay Voltage center optimization
701 06:11:39.827897 INFO : End of 2D write delay Voltage center optimization
702 06:11:39.833417 INFO : Training has run successfully!
703 06:11:39.833979
704 06:11:39.834463 channel==0
705 06:11:39.838953 RxClkDly_Margin_A0==88 ps 9
706 06:11:39.839483 TxDqDly_Margin_A0==98 ps 10
707 06:11:39.844604 RxClkDly_Margin_A1==88 ps 9
708 06:11:39.845139 TxDqDly_Margin_A1==98 ps 10
709 06:11:39.845612 TrainedVREFDQ_A0==74
710 06:11:39.850198 TrainedVREFDQ_A1==74
711 06:11:39.850713 VrefDac_Margin_A0==25
712 06:11:39.851177 DeviceVref_Margin_A0==40
713 06:11:39.855824 VrefDac_Margin_A1==25
714 06:11:39.856371 DeviceVref_Margin_A1==40
715 06:11:39.856837
716 06:11:39.857296
717 06:11:39.861366 channel==1
718 06:11:39.861870 RxClkDly_Margin_A0==98 ps 10
719 06:11:39.862333 TxDqDly_Margin_A0==98 ps 10
720 06:11:39.866958 RxClkDly_Margin_A1==98 ps 10
721 06:11:39.867471 TxDqDly_Margin_A1==88 ps 9
722 06:11:39.872577 TrainedVREFDQ_A0==77
723 06:11:39.873142 TrainedVREFDQ_A1==77
724 06:11:39.873624 VrefDac_Margin_A0==22
725 06:11:39.878200 DeviceVref_Margin_A0==37
726 06:11:39.878721 VrefDac_Margin_A1==22
727 06:11:39.883800 DeviceVref_Margin_A1==37
728 06:11:39.884349
729 06:11:39.884817 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 06:11:39.889370
731 06:11:39.917402 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 06:11:39.918012 2D training succeed
733 06:11:39.923066 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 06:11:39.928613 auto size-- 65535DDR cs0 size: 2048MB
735 06:11:39.929145 DDR cs1 size: 2048MB
736 06:11:39.934131 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 06:11:39.934655 cs0 DataBus test pass
738 06:11:39.939860 cs1 DataBus test pass
739 06:11:39.940432 cs0 AddrBus test pass
740 06:11:39.940895 cs1 AddrBus test pass
741 06:11:39.941342
742 06:11:39.945352 100bdlr_step_size ps== 420
743 06:11:39.945875 result report
744 06:11:39.950925 boot times 0Enable ddr reg access
745 06:11:39.956428 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 06:11:39.969905 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 06:11:40.542143 0.0;M3 CHK:0;cm4_sp_mode 0
748 06:11:40.542871 MVN_1=0x00000000
749 06:11:40.547641 MVN_2=0x00000000
750 06:11:40.553360 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 06:11:40.553953 OPS=0x10
752 06:11:40.554413 ring efuse init
753 06:11:40.554857 chipver efuse init
754 06:11:40.559094 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 06:11:40.564513 [0.018961 Inits done]
756 06:11:40.565014 secure task start!
757 06:11:40.565455 high task start!
758 06:11:40.569070 low task start!
759 06:11:40.569557 run into bl31
760 06:11:40.575707 NOTICE: BL31: v1.3(release):4fc40b1
761 06:11:40.583529 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 06:11:40.584208 NOTICE: BL31: G12A normal boot!
763 06:11:40.609079 NOTICE: BL31: BL33 decompress pass
764 06:11:40.614594 ERROR: Error initializing runtime service opteed_fast
765 06:11:41.847440
766 06:11:41.848165
767 06:11:41.855966 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 06:11:41.856527
769 06:11:41.857008 Model: Libre Computer AML-A311D-CC Alta
770 06:11:42.064398 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 06:11:42.087793 DRAM: 2 GiB (effective 3.8 GiB)
772 06:11:42.230589 Core: 408 devices, 31 uclasses, devicetree: separate
773 06:11:42.236549 WDT: Not starting watchdog@f0d0
774 06:11:42.268726 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 06:11:42.281192 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 06:11:42.286288 ** Bad device specification mmc 0 **
777 06:11:42.296530 Card did not respond to voltage select! : -110
778 06:11:42.304321 ** Bad device specification mmc 0 **
779 06:11:42.304839 Couldn't find partition mmc 0
780 06:11:42.312468 Card did not respond to voltage select! : -110
781 06:11:42.318061 ** Bad device specification mmc 0 **
782 06:11:42.318563 Couldn't find partition mmc 0
783 06:11:42.323049 Error: could not access storage.
784 06:11:42.665589 Net: eth0: ethernet@ff3f0000
785 06:11:42.666288 starting USB...
786 06:11:42.917427 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 06:11:42.918099 Starting the controller
788 06:11:42.924492 USB XHCI 1.10
789 06:11:45.086617 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
790 06:11:45.087061 bl2_stage_init 0x81
791 06:11:45.092281 hw id: 0x0000 - pwm id 0x01
792 06:11:45.092637 bl2_stage_init 0xc1
793 06:11:45.092865 bl2_stage_init 0x02
794 06:11:45.093075
795 06:11:45.097843 L0:00000000
796 06:11:45.098148 L1:20000703
797 06:11:45.098353 L2:00008067
798 06:11:45.098558 L3:14000000
799 06:11:45.098769 B2:00402000
800 06:11:45.100758 B1:e0f83180
801 06:11:45.101046
802 06:11:45.101259 TE: 58150
803 06:11:45.101479
804 06:11:45.111818 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 06:11:45.112182
806 06:11:45.112395 Board ID = 1
807 06:11:45.112606 Set A53 clk to 24M
808 06:11:45.112820 Set A73 clk to 24M
809 06:11:45.117486 Set clk81 to 24M
810 06:11:45.117781 A53 clk: 1200 MHz
811 06:11:45.117990 A73 clk: 1200 MHz
812 06:11:45.121115 CLK81: 166.6M
813 06:11:45.121455 smccc: 00012aac
814 06:11:45.126688 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 06:11:45.132186 board id: 1
816 06:11:45.137208 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 06:11:45.147895 fw parse done
818 06:11:45.153838 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 06:11:45.196403 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 06:11:45.207306 PIEI prepare done
821 06:11:45.207659 fastboot data load
822 06:11:45.207872 fastboot data verify
823 06:11:45.212838 verify result: 266
824 06:11:45.218499 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 06:11:45.218803 LPDDR4 probe
826 06:11:45.219018 ddr clk to 1584MHz
827 06:11:45.226583 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 06:11:45.263772
829 06:11:45.264193 dmc_version 0001
830 06:11:45.270515 Check phy result
831 06:11:45.276205 INFO : End of CA training
832 06:11:45.276515 INFO : End of initialization
833 06:11:45.281790 INFO : Training has run successfully!
834 06:11:45.282090 Check phy result
835 06:11:45.287465 INFO : End of initialization
836 06:11:45.287763 INFO : End of read enable training
837 06:11:45.293075 INFO : End of fine write leveling
838 06:11:45.298625 INFO : End of Write leveling coarse delay
839 06:11:45.298977 INFO : Training has run successfully!
840 06:11:45.299189 Check phy result
841 06:11:45.304203 INFO : End of initialization
842 06:11:45.304525 INFO : End of read dq deskew training
843 06:11:45.309792 INFO : End of MPR read delay center optimization
844 06:11:45.315376 INFO : End of write delay center optimization
845 06:11:45.321031 INFO : End of read delay center optimization
846 06:11:45.321334 INFO : End of max read latency training
847 06:11:45.326611 INFO : Training has run successfully!
848 06:11:45.326915 1D training succeed
849 06:11:45.335747 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 06:11:45.383558 Check phy result
851 06:11:45.383973 INFO : End of initialization
852 06:11:45.405176 INFO : End of 2D read delay Voltage center optimization
853 06:11:45.425346 INFO : End of 2D read delay Voltage center optimization
854 06:11:45.477457 INFO : End of 2D write delay Voltage center optimization
855 06:11:45.526780 INFO : End of 2D write delay Voltage center optimization
856 06:11:45.532522 INFO : Training has run successfully!
857 06:11:45.532900
858 06:11:45.533128 channel==0
859 06:11:45.538012 RxClkDly_Margin_A0==88 ps 9
860 06:11:45.538455 TxDqDly_Margin_A0==98 ps 10
861 06:11:45.543562 RxClkDly_Margin_A1==88 ps 9
862 06:11:45.544026 TxDqDly_Margin_A1==88 ps 9
863 06:11:45.544263 TrainedVREFDQ_A0==74
864 06:11:45.549146 TrainedVREFDQ_A1==74
865 06:11:45.549546 VrefDac_Margin_A0==25
866 06:11:45.549851 DeviceVref_Margin_A0==40
867 06:11:45.554989 VrefDac_Margin_A1==25
868 06:11:45.555426 DeviceVref_Margin_A1==40
869 06:11:45.555640
870 06:11:45.555851
871 06:11:45.556158 channel==1
872 06:11:45.560325 RxClkDly_Margin_A0==98 ps 10
873 06:11:45.560670 TxDqDly_Margin_A0==88 ps 9
874 06:11:45.565921 RxClkDly_Margin_A1==98 ps 10
875 06:11:45.566265 TxDqDly_Margin_A1==88 ps 9
876 06:11:45.571585 TrainedVREFDQ_A0==76
877 06:11:45.572017 TrainedVREFDQ_A1==77
878 06:11:45.572290 VrefDac_Margin_A0==22
879 06:11:45.577036 DeviceVref_Margin_A0==38
880 06:11:45.577358 VrefDac_Margin_A1==24
881 06:11:45.582651 DeviceVref_Margin_A1==37
882 06:11:45.582890
883 06:11:45.583091 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 06:11:45.583291
885 06:11:45.616295 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
886 06:11:45.616910 2D training succeed
887 06:11:45.621876 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 06:11:45.627507 auto size-- 65535DDR cs0 size: 2048MB
889 06:11:45.628166 DDR cs1 size: 2048MB
890 06:11:45.633070 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 06:11:45.633591 cs0 DataBus test pass
892 06:11:45.638652 cs1 DataBus test pass
893 06:11:45.639159 cs0 AddrBus test pass
894 06:11:45.639625 cs1 AddrBus test pass
895 06:11:45.640096
896 06:11:45.644487 100bdlr_step_size ps== 420
897 06:11:45.644992 result report
898 06:11:45.649866 boot times 0Enable ddr reg access
899 06:11:45.655161 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 06:11:45.668600 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 06:11:46.241685 0.0;M3 CHK:0;cm4_sp_mode 0
902 06:11:46.242404 MVN_1=0x00000000
903 06:11:46.247116 MVN_2=0x00000000
904 06:11:46.252859 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 06:11:46.253209 OPS=0x10
906 06:11:46.253470 ring efuse init
907 06:11:46.253700 chipver efuse init
908 06:11:46.261234 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 06:11:46.261597 [0.018961 Inits done]
910 06:11:46.261819 secure task start!
911 06:11:46.268663 high task start!
912 06:11:46.268984 low task start!
913 06:11:46.269197 run into bl31
914 06:11:46.275344 NOTICE: BL31: v1.3(release):4fc40b1
915 06:11:46.283176 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 06:11:46.283521 NOTICE: BL31: G12A normal boot!
917 06:11:46.308635 NOTICE: BL31: BL33 decompress pass
918 06:11:46.314326 ERROR: Error initializing runtime service opteed_fast
919 06:11:47.547321
920 06:11:47.548072
921 06:11:47.555690 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 06:11:47.556270
923 06:11:47.556745 Model: Libre Computer AML-A311D-CC Alta
924 06:11:47.764147 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 06:11:47.787656 DRAM: 2 GiB (effective 3.8 GiB)
926 06:11:47.930619 Core: 408 devices, 31 uclasses, devicetree: separate
927 06:11:47.936417 WDT: Not starting watchdog@f0d0
928 06:11:47.968710 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 06:11:47.981136 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 06:11:47.986096 ** Bad device specification mmc 0 **
931 06:11:47.996579 Card did not respond to voltage select! : -110
932 06:11:48.004138 ** Bad device specification mmc 0 **
933 06:11:48.004745 Couldn't find partition mmc 0
934 06:11:48.012403 Card did not respond to voltage select! : -110
935 06:11:48.017935 ** Bad device specification mmc 0 **
936 06:11:48.018496 Couldn't find partition mmc 0
937 06:11:48.023013 Error: could not access storage.
938 06:11:48.365459 Net: eth0: ethernet@ff3f0000
939 06:11:48.366164 starting USB...
940 06:11:48.617284 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 06:11:48.617948 Starting the controller
942 06:11:48.624160 USB XHCI 1.10
943 06:11:50.486506 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
944 06:11:50.487177 bl2_stage_init 0x01
945 06:11:50.487655 bl2_stage_init 0x81
946 06:11:50.492138 hw id: 0x0000 - pwm id 0x01
947 06:11:50.492653 bl2_stage_init 0xc1
948 06:11:50.493112 bl2_stage_init 0x02
949 06:11:50.493559
950 06:11:50.497583 L0:00000000
951 06:11:50.498074 L1:20000703
952 06:11:50.498530 L2:00008067
953 06:11:50.498975 L3:14000000
954 06:11:50.500632 B2:00402000
955 06:11:50.501117 B1:e0f83180
956 06:11:50.501573
957 06:11:50.502020 TE: 58159
958 06:11:50.502467
959 06:11:50.511822 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 06:11:50.512364
961 06:11:50.512824 Board ID = 1
962 06:11:50.513276 Set A53 clk to 24M
963 06:11:50.513716 Set A73 clk to 24M
964 06:11:50.517814 Set clk81 to 24M
965 06:11:50.518297 A53 clk: 1200 MHz
966 06:11:50.518741 A73 clk: 1200 MHz
967 06:11:50.520948 CLK81: 166.6M
968 06:11:50.521433 smccc: 00012ab5
969 06:11:50.526559 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 06:11:50.532284 board id: 1
971 06:11:50.537193 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 06:11:50.547664 fw parse done
973 06:11:50.553598 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 06:11:50.596239 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 06:11:50.607330 PIEI prepare done
976 06:11:50.607890 fastboot data load
977 06:11:50.608212 fastboot data verify
978 06:11:50.612880 verify result: 266
979 06:11:50.618423 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 06:11:50.618828 LPDDR4 probe
981 06:11:50.619086 ddr clk to 1584MHz
982 06:11:50.626449 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 06:11:50.663784
984 06:11:50.664302 dmc_version 0001
985 06:11:50.670377 Check phy result
986 06:11:50.676936 INFO : End of CA training
987 06:11:50.677580 INFO : End of initialization
988 06:11:50.682094 INFO : Training has run successfully!
989 06:11:50.682550 Check phy result
990 06:11:50.688101 INFO : End of initialization
991 06:11:50.688491 INFO : End of read enable training
992 06:11:50.690804 INFO : End of fine write leveling
993 06:11:50.696677 INFO : End of Write leveling coarse delay
994 06:11:50.704161 INFO : Training has run successfully!
995 06:11:50.704905 Check phy result
996 06:11:50.705451 INFO : End of initialization
997 06:11:50.707710 INFO : End of read dq deskew training
998 06:11:50.713332 INFO : End of MPR read delay center optimization
999 06:11:50.713779 INFO : End of write delay center optimization
1000 06:11:50.719175 INFO : End of read delay center optimization
1001 06:11:50.730207 INFO : End of max read latency training
1002 06:11:50.730858 INFO : Training has run successfully!
1003 06:11:50.731183 1D training succeed
1004 06:11:50.736064 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 06:11:50.784422 Check phy result
1006 06:11:50.785030 INFO : End of initialization
1007 06:11:50.805329 INFO : End of 2D read delay Voltage center optimization
1008 06:11:50.825641 INFO : End of 2D read delay Voltage center optimization
1009 06:11:50.877544 INFO : End of 2D write delay Voltage center optimization
1010 06:11:50.926815 INFO : End of 2D write delay Voltage center optimization
1011 06:11:50.932398 INFO : Training has run successfully!
1012 06:11:50.932803
1013 06:11:50.933034 channel==0
1014 06:11:50.937985 RxClkDly_Margin_A0==88 ps 9
1015 06:11:50.938415 TxDqDly_Margin_A0==98 ps 10
1016 06:11:50.941558 RxClkDly_Margin_A1==88 ps 9
1017 06:11:50.941914 TxDqDly_Margin_A1==98 ps 10
1018 06:11:50.948457 TrainedVREFDQ_A0==74
1019 06:11:50.948871 TrainedVREFDQ_A1==74
1020 06:11:50.949096 VrefDac_Margin_A0==25
1021 06:11:50.952850 DeviceVref_Margin_A0==40
1022 06:11:50.953265 VrefDac_Margin_A1==25
1023 06:11:50.958233 DeviceVref_Margin_A1==40
1024 06:11:50.958816
1025 06:11:50.959234
1026 06:11:50.959508 channel==1
1027 06:11:50.959747 RxClkDly_Margin_A0==98 ps 10
1028 06:11:50.963918 TxDqDly_Margin_A0==88 ps 9
1029 06:11:50.964371 RxClkDly_Margin_A1==88 ps 9
1030 06:11:50.969362 TxDqDly_Margin_A1==98 ps 10
1031 06:11:50.969781 TrainedVREFDQ_A0==77
1032 06:11:50.970007 TrainedVREFDQ_A1==77
1033 06:11:50.975612 VrefDac_Margin_A0==22
1034 06:11:50.976055 DeviceVref_Margin_A0==37
1035 06:11:50.980551 VrefDac_Margin_A1==24
1036 06:11:50.981118 DeviceVref_Margin_A1==37
1037 06:11:50.981399
1038 06:11:50.986147 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 06:11:50.986733
1040 06:11:51.014110 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1041 06:11:51.019706 2D training succeed
1042 06:11:51.025291 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 06:11:51.025670 auto size-- 65535DDR cs0 size: 2048MB
1044 06:11:51.030877 DDR cs1 size: 2048MB
1045 06:11:51.031268 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 06:11:51.036553 cs0 DataBus test pass
1047 06:11:51.036956 cs1 DataBus test pass
1048 06:11:51.037189 cs0 AddrBus test pass
1049 06:11:51.042152 cs1 AddrBus test pass
1050 06:11:51.042583
1051 06:11:51.042818 100bdlr_step_size ps== 420
1052 06:11:51.043066 result report
1053 06:11:51.047749 boot times 0Enable ddr reg access
1054 06:11:51.055433 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 06:11:51.069035 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 06:11:51.642403 0.0;M3 CHK:0;cm4_sp_mode 0
1057 06:11:51.642846 MVN_1=0x00000000
1058 06:11:51.647818 MVN_2=0x00000000
1059 06:11:51.653549 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 06:11:51.653860 OPS=0x10
1061 06:11:51.654091 ring efuse init
1062 06:11:51.654323 chipver efuse init
1063 06:11:51.659300 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 06:11:51.664863 [0.018961 Inits done]
1065 06:11:51.665176 secure task start!
1066 06:11:51.665391 high task start!
1067 06:11:51.669349 low task start!
1068 06:11:51.669643 run into bl31
1069 06:11:51.676029 NOTICE: BL31: v1.3(release):4fc40b1
1070 06:11:51.683846 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 06:11:51.684178 NOTICE: BL31: G12A normal boot!
1072 06:11:51.709404 NOTICE: BL31: BL33 decompress pass
1073 06:11:51.714969 ERROR: Error initializing runtime service opteed_fast
1074 06:11:52.947857
1075 06:11:52.948579
1076 06:11:52.956186 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 06:11:52.956723
1078 06:11:52.957201 Model: Libre Computer AML-A311D-CC Alta
1079 06:11:53.164663 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 06:11:53.188120 DRAM: 2 GiB (effective 3.8 GiB)
1081 06:11:53.331066 Core: 408 devices, 31 uclasses, devicetree: separate
1082 06:11:53.336849 WDT: Not starting watchdog@f0d0
1083 06:11:53.369149 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 06:11:53.381681 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 06:11:53.386595 ** Bad device specification mmc 0 **
1086 06:11:53.396897 Card did not respond to voltage select! : -110
1087 06:11:53.404526 ** Bad device specification mmc 0 **
1088 06:11:53.405143 Couldn't find partition mmc 0
1089 06:11:53.412865 Card did not respond to voltage select! : -110
1090 06:11:53.418445 ** Bad device specification mmc 0 **
1091 06:11:53.418960 Couldn't find partition mmc 0
1092 06:11:53.423494 Error: could not access storage.
1093 06:11:53.767037 Net: eth0: ethernet@ff3f0000
1094 06:11:53.767738 starting USB...
1095 06:11:54.018831 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 06:11:54.019491 Starting the controller
1097 06:11:54.025711 USB XHCI 1.10
1098 06:11:55.579806 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 06:11:55.588093 scanning usb for storage devices... 0 Storage Device(s) found
1101 06:11:55.639959 Hit any key to stop autoboot: 1
1102 06:11:55.640983 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1103 06:11:55.641726 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1104 06:11:55.642316 Setting prompt string to ['=>']
1105 06:11:55.642944 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1106 06:11:55.655526 0
1107 06:11:55.656510 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 06:11:55.657065 Sending with 10 millisecond of delay
1110 06:11:56.792661 => setenv autoload no
1111 06:11:56.803537 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1112 06:11:56.808884 setenv autoload no
1113 06:11:56.809687 Sending with 10 millisecond of delay
1115 06:11:58.607962 => setenv initrd_high 0xffffffff
1116 06:11:58.618840 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1117 06:11:58.619750 setenv initrd_high 0xffffffff
1118 06:11:58.620569 Sending with 10 millisecond of delay
1120 06:12:00.237980 => setenv fdt_high 0xffffffff
1121 06:12:00.248764 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 06:12:00.249550 setenv fdt_high 0xffffffff
1123 06:12:00.250254 Sending with 10 millisecond of delay
1125 06:12:00.541997 => dhcp
1126 06:12:00.552705 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1127 06:12:00.553528 dhcp
1128 06:12:00.553973 Speed: 1000, full duplex
1129 06:12:00.554389 BOOTP broadcast 1
1130 06:12:00.800599 BOOTP broadcast 2
1131 06:12:00.812399 DHCP client bound to address 192.168.6.33 (259 ms)
1132 06:12:00.813200 Sending with 10 millisecond of delay
1134 06:12:02.489113 => setenv serverip 192.168.6.2
1135 06:12:02.499819 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 06:12:02.500387 setenv serverip 192.168.6.2
1137 06:12:02.500849 Sending with 10 millisecond of delay
1139 06:12:06.226217 => tftpboot 0x01080000 790068/tftp-deploy-h58onhk9/kernel/uImage
1140 06:12:06.237040 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 06:12:06.237935 tftpboot 0x01080000 790068/tftp-deploy-h58onhk9/kernel/uImage
1142 06:12:06.238409 Speed: 1000, full duplex
1143 06:12:06.238839 Using ethernet@ff3f0000 device
1144 06:12:06.239863 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1145 06:12:06.245258 Filename '790068/tftp-deploy-h58onhk9/kernel/uImage'.
1146 06:12:06.249213 Load address: 0x1080000
1147 06:12:11.174426 Loading: *################################################## 43.6 MiB
1148 06:12:11.175029 8.8 MiB/s
1149 06:12:11.175463 done
1150 06:12:11.178672 Bytes transferred = 45713984 (2b98a40 hex)
1151 06:12:11.179384 Sending with 10 millisecond of delay
1153 06:12:15.868140 => tftpboot 0x08000000 790068/tftp-deploy-h58onhk9/ramdisk/ramdisk.cpio.gz.uboot
1154 06:12:15.882181 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
1155 06:12:15.883073 tftpboot 0x08000000 790068/tftp-deploy-h58onhk9/ramdisk/ramdisk.cpio.gz.uboot
1156 06:12:15.883505 Speed: 1000, full duplex
1157 06:12:15.883903 Using ethernet@ff3f0000 device
1158 06:12:15.884387 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1159 06:12:15.890344 Filename '790068/tftp-deploy-h58onhk9/ramdisk/ramdisk.cpio.gz.uboot'.
1160 06:12:15.890809 Load address: 0x8000000
1161 06:12:18.223266 Loading: *################################################# UDP wrong checksum 00000005 00009de5
1162 06:12:19.748246 UDP wrong checksum 000000ff 00002f00
1163 06:12:19.787833 UDP wrong checksum 000000ff 0000b5f2
1164 06:12:23.226386 T UDP wrong checksum 00000005 00009de5
1165 06:12:33.227657 T T UDP wrong checksum 00000005 00009de5
1166 06:12:35.927762 UDP wrong checksum 000000ff 000043ec
1167 06:12:35.964037 UDP wrong checksum 000000ff 0000dcde
1168 06:12:53.232192 T T T T UDP wrong checksum 00000005 00009de5
1169 06:13:02.560610 T UDP wrong checksum 000000ff 0000cc2e
1170 06:13:02.591743 UDP wrong checksum 000000ff 00006421
1171 06:13:06.104802 T UDP wrong checksum 000000ff 00001229
1172 06:13:06.130554 UDP wrong checksum 000000ff 0000ac1b
1173 06:13:13.236953 T
1174 06:13:13.237551 Retry count exceeded; starting again
1176 06:13:13.238957 end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
1179 06:13:13.240849 end: 2.4 uboot-commands (duration 00:01:55) [common]
1181 06:13:13.242236 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1183 06:13:13.243276 end: 2 uboot-action (duration 00:01:55) [common]
1185 06:13:13.244854 Cleaning after the job
1186 06:13:13.245425 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/ramdisk
1187 06:13:13.246729 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/kernel
1188 06:13:13.255776 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/dtb
1189 06:13:13.257040 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/nfsrootfs
1190 06:13:13.299077 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790068/tftp-deploy-h58onhk9/modules
1191 06:13:13.306064 start: 4.1 power-off (timeout 00:00:30) [common]
1192 06:13:13.306662 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1193 06:13:13.343112 >> OK - accepted request
1194 06:13:13.345056 Returned 0 in 0 seconds
1195 06:13:13.446183 end: 4.1 power-off (duration 00:00:00) [common]
1197 06:13:13.447889 start: 4.2 read-feedback (timeout 00:10:00) [common]
1198 06:13:13.449055 Listened to connection for namespace 'common' for up to 1s
1199 06:13:14.449893 Finalising connection for namespace 'common'
1200 06:13:14.450612 Disconnecting from shell: Finalise
1201 06:13:14.451133 =>
1202 06:13:14.552170 end: 4.2 read-feedback (duration 00:00:01) [common]
1203 06:13:14.552868 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/790068
1204 06:13:16.313007 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/790068
1205 06:13:16.313771 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.