Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:17:37.376843 lava-dispatcher, installed at version: 2024.01
2 06:17:37.377687 start: 0 validate
3 06:17:37.378172 Start time: 2024-10-02 06:17:37.378141+00:00 (UTC)
4 06:17:37.378726 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:17:37.379273 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 06:17:37.424102 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:17:37.424686 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fkernel%2FImage exists
8 06:17:37.457743 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:17:37.458382 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:17:38.510304 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:17:38.510827 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241002%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-17%2Fmodules.tar.xz exists
12 06:17:38.556489 validate duration: 1.18
14 06:17:38.557978 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:17:38.558615 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:17:38.559191 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:17:38.560164 Not decompressing ramdisk as can be used compressed.
18 06:17:38.560915 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 06:17:38.561373 saving as /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/ramdisk/rootfs.cpio.gz
20 06:17:38.561850 total size: 8181887 (7 MB)
21 06:17:38.605519 progress 0 % (0 MB)
22 06:17:38.617208 progress 5 % (0 MB)
23 06:17:38.628456 progress 10 % (0 MB)
24 06:17:38.640524 progress 15 % (1 MB)
25 06:17:38.647521 progress 20 % (1 MB)
26 06:17:38.653227 progress 25 % (1 MB)
27 06:17:38.658313 progress 30 % (2 MB)
28 06:17:38.663924 progress 35 % (2 MB)
29 06:17:38.669039 progress 40 % (3 MB)
30 06:17:38.674584 progress 45 % (3 MB)
31 06:17:38.679765 progress 50 % (3 MB)
32 06:17:38.685316 progress 55 % (4 MB)
33 06:17:38.690593 progress 60 % (4 MB)
34 06:17:38.696225 progress 65 % (5 MB)
35 06:17:38.701386 progress 70 % (5 MB)
36 06:17:38.706867 progress 75 % (5 MB)
37 06:17:38.711949 progress 80 % (6 MB)
38 06:17:38.717576 progress 85 % (6 MB)
39 06:17:38.722674 progress 90 % (7 MB)
40 06:17:38.728138 progress 95 % (7 MB)
41 06:17:38.732988 progress 100 % (7 MB)
42 06:17:38.733635 7 MB downloaded in 0.17 s (45.42 MB/s)
43 06:17:38.734183 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:17:38.735085 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:17:38.735378 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:17:38.735650 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:17:38.736157 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/kernel/Image
49 06:17:38.736426 saving as /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/kernel/Image
50 06:17:38.736639 total size: 39424512 (37 MB)
51 06:17:38.736852 No compression specified
52 06:17:38.783366 progress 0 % (0 MB)
53 06:17:38.808342 progress 5 % (1 MB)
54 06:17:38.834458 progress 10 % (3 MB)
55 06:17:38.858817 progress 15 % (5 MB)
56 06:17:38.883049 progress 20 % (7 MB)
57 06:17:38.907084 progress 25 % (9 MB)
58 06:17:38.931172 progress 30 % (11 MB)
59 06:17:38.955451 progress 35 % (13 MB)
60 06:17:38.979761 progress 40 % (15 MB)
61 06:17:39.004117 progress 45 % (16 MB)
62 06:17:39.028192 progress 50 % (18 MB)
63 06:17:39.052231 progress 55 % (20 MB)
64 06:17:39.076307 progress 60 % (22 MB)
65 06:17:39.100903 progress 65 % (24 MB)
66 06:17:39.125448 progress 70 % (26 MB)
67 06:17:39.149558 progress 75 % (28 MB)
68 06:17:39.173478 progress 80 % (30 MB)
69 06:17:39.197569 progress 85 % (31 MB)
70 06:17:39.221560 progress 90 % (33 MB)
71 06:17:39.245383 progress 95 % (35 MB)
72 06:17:39.269853 progress 100 % (37 MB)
73 06:17:39.270407 37 MB downloaded in 0.53 s (70.44 MB/s)
74 06:17:39.270885 end: 1.2.1 http-download (duration 00:00:01) [common]
76 06:17:39.271702 end: 1.2 download-retry (duration 00:00:01) [common]
77 06:17:39.271976 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:17:39.272276 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:17:39.272750 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 06:17:39.273025 saving as /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/dtb/meson-g12b-a311d-libretech-cc.dtb
81 06:17:39.273236 total size: 54703 (0 MB)
82 06:17:39.273444 No compression specified
83 06:17:39.320915 progress 59 % (0 MB)
84 06:17:39.321753 progress 100 % (0 MB)
85 06:17:39.322302 0 MB downloaded in 0.05 s (1.06 MB/s)
86 06:17:39.322762 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:17:39.323574 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:17:39.323833 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:17:39.324145 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:17:39.324617 downloading http://storage.kernelci.org/next/master/next-20241002/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-17/modules.tar.xz
92 06:17:39.324866 saving as /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/modules/modules.tar
93 06:17:39.325073 total size: 11764284 (11 MB)
94 06:17:39.325284 Using unxz to decompress xz
95 06:17:39.365416 progress 0 % (0 MB)
96 06:17:39.434407 progress 5 % (0 MB)
97 06:17:39.513006 progress 10 % (1 MB)
98 06:17:39.600640 progress 15 % (1 MB)
99 06:17:39.682873 progress 20 % (2 MB)
100 06:17:39.766607 progress 25 % (2 MB)
101 06:17:39.848352 progress 30 % (3 MB)
102 06:17:39.928817 progress 35 % (3 MB)
103 06:17:40.007462 progress 40 % (4 MB)
104 06:17:40.085204 progress 45 % (5 MB)
105 06:17:40.164226 progress 50 % (5 MB)
106 06:17:40.241355 progress 55 % (6 MB)
107 06:17:40.327200 progress 60 % (6 MB)
108 06:17:40.415769 progress 65 % (7 MB)
109 06:17:40.499306 progress 70 % (7 MB)
110 06:17:40.594211 progress 75 % (8 MB)
111 06:17:40.691900 progress 80 % (9 MB)
112 06:17:40.774581 progress 85 % (9 MB)
113 06:17:40.852719 progress 90 % (10 MB)
114 06:17:40.931926 progress 95 % (10 MB)
115 06:17:41.009648 progress 100 % (11 MB)
116 06:17:41.019512 11 MB downloaded in 1.69 s (6.62 MB/s)
117 06:17:41.020248 end: 1.4.1 http-download (duration 00:00:02) [common]
119 06:17:41.022122 end: 1.4 download-retry (duration 00:00:02) [common]
120 06:17:41.022721 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 06:17:41.023298 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 06:17:41.023849 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:17:41.024489 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 06:17:41.025642 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss
125 06:17:41.026617 makedir: /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin
126 06:17:41.027395 makedir: /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/tests
127 06:17:41.028179 makedir: /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/results
128 06:17:41.028867 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-add-keys
129 06:17:41.030010 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-add-sources
130 06:17:41.031066 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-background-process-start
131 06:17:41.032248 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-background-process-stop
132 06:17:41.033416 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-common-functions
133 06:17:41.034496 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-echo-ipv4
134 06:17:41.035625 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-install-packages
135 06:17:41.036768 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-installed-packages
136 06:17:41.037858 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-os-build
137 06:17:41.038889 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-probe-channel
138 06:17:41.039925 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-probe-ip
139 06:17:41.041062 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-target-ip
140 06:17:41.042112 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-target-mac
141 06:17:41.043163 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-target-storage
142 06:17:41.044379 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-test-case
143 06:17:41.045558 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-test-event
144 06:17:41.046765 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-test-feedback
145 06:17:41.047867 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-test-raise
146 06:17:41.049128 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-test-reference
147 06:17:41.050366 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-test-runner
148 06:17:41.051535 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-test-set
149 06:17:41.052571 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-test-shell
150 06:17:41.053247 Updating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-install-packages (oe)
151 06:17:41.054291 Updating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/bin/lava-installed-packages (oe)
152 06:17:41.055375 Creating /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/environment
153 06:17:41.056324 LAVA metadata
154 06:17:41.056926 - LAVA_JOB_ID=790179
155 06:17:41.057481 - LAVA_DISPATCHER_IP=192.168.6.2
156 06:17:41.058239 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 06:17:41.060565 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 06:17:41.061340 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 06:17:41.061833 skipped lava-vland-overlay
160 06:17:41.062397 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 06:17:41.063016 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 06:17:41.063471 skipped lava-multinode-overlay
163 06:17:41.064107 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 06:17:41.064694 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 06:17:41.065260 Loading test definitions
166 06:17:41.065946 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 06:17:41.066465 Using /lava-790179 at stage 0
168 06:17:41.069176 uuid=790179_1.5.2.4.1 testdef=None
169 06:17:41.069915 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 06:17:41.070510 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 06:17:41.073620 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 06:17:41.074578 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 06:17:41.077461 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 06:17:41.078446 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 06:17:41.081265 runner path: /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/0/tests/0_dmesg test_uuid 790179_1.5.2.4.1
178 06:17:41.082067 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 06:17:41.082958 Creating lava-test-runner.conf files
181 06:17:41.083172 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/790179/lava-overlay-98ns7lss/lava-790179/0 for stage 0
182 06:17:41.083634 - 0_dmesg
183 06:17:41.084117 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 06:17:41.084476 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 06:17:41.113310 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 06:17:41.113829 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 06:17:41.114121 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 06:17:41.114444 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 06:17:41.114761 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 06:17:42.048786 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 06:17:42.049237 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 06:17:42.049504 extracting modules file /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/790179/extract-overlay-ramdisk-6u7qyl_h/ramdisk
193 06:17:43.388058 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 06:17:43.388539 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 06:17:43.388808 [common] Applying overlay /var/lib/lava/dispatcher/tmp/790179/compress-overlay-cfiefc8b/overlay-1.5.2.5.tar.gz to ramdisk
196 06:17:43.389021 [common] Applying overlay /var/lib/lava/dispatcher/tmp/790179/compress-overlay-cfiefc8b/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/790179/extract-overlay-ramdisk-6u7qyl_h/ramdisk
197 06:17:43.418722 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 06:17:43.419144 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 06:17:43.419413 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 06:17:43.419641 Converting downloaded kernel to a uImage
201 06:17:43.419946 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/kernel/Image /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/kernel/uImage
202 06:17:43.845375 output: Image Name:
203 06:17:43.845778 output: Created: Wed Oct 2 06:17:43 2024
204 06:17:43.845990 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 06:17:43.846196 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
206 06:17:43.846399 output: Load Address: 01080000
207 06:17:43.846600 output: Entry Point: 01080000
208 06:17:43.846797 output:
209 06:17:43.847123 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 06:17:43.847391 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 06:17:43.847658 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 06:17:43.847911 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 06:17:43.848208 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 06:17:43.848464 Building ramdisk /var/lib/lava/dispatcher/tmp/790179/extract-overlay-ramdisk-6u7qyl_h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/790179/extract-overlay-ramdisk-6u7qyl_h/ramdisk
215 06:17:46.417907 >> 188425 blocks
216 06:17:55.179226 Adding RAMdisk u-boot header.
217 06:17:55.179957 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/790179/extract-overlay-ramdisk-6u7qyl_h/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/790179/extract-overlay-ramdisk-6u7qyl_h/ramdisk.cpio.gz.uboot
218 06:17:55.469293 output: Image Name:
219 06:17:55.469715 output: Created: Wed Oct 2 06:17:55 2024
220 06:17:55.469926 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 06:17:55.470129 output: Data Size: 26780389 Bytes = 26152.72 KiB = 25.54 MiB
222 06:17:55.470328 output: Load Address: 00000000
223 06:17:55.470526 output: Entry Point: 00000000
224 06:17:55.470721 output:
225 06:17:55.471368 rename /var/lib/lava/dispatcher/tmp/790179/extract-overlay-ramdisk-6u7qyl_h/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/ramdisk/ramdisk.cpio.gz.uboot
226 06:17:55.471791 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 06:17:55.472236 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 06:17:55.472817 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 06:17:55.473292 No LXC device requested
230 06:17:55.473788 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 06:17:55.474287 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 06:17:55.474768 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 06:17:55.475172 Checking files for TFTP limit of 4294967296 bytes.
234 06:17:55.477825 end: 1 tftp-deploy (duration 00:00:17) [common]
235 06:17:55.478395 start: 2 uboot-action (timeout 00:05:00) [common]
236 06:17:55.478915 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 06:17:55.479404 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 06:17:55.479900 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 06:17:55.480459 Using kernel file from prepare-kernel: 790179/tftp-deploy-thu7g5dj/kernel/uImage
240 06:17:55.481057 substitutions:
241 06:17:55.481460 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 06:17:55.481857 - {DTB_ADDR}: 0x01070000
243 06:17:55.482252 - {DTB}: 790179/tftp-deploy-thu7g5dj/dtb/meson-g12b-a311d-libretech-cc.dtb
244 06:17:55.482646 - {INITRD}: 790179/tftp-deploy-thu7g5dj/ramdisk/ramdisk.cpio.gz.uboot
245 06:17:55.483039 - {KERNEL_ADDR}: 0x01080000
246 06:17:55.483431 - {KERNEL}: 790179/tftp-deploy-thu7g5dj/kernel/uImage
247 06:17:55.483823 - {LAVA_MAC}: None
248 06:17:55.484279 - {PRESEED_CONFIG}: None
249 06:17:55.484674 - {PRESEED_LOCAL}: None
250 06:17:55.485065 - {RAMDISK_ADDR}: 0x08000000
251 06:17:55.485449 - {RAMDISK}: 790179/tftp-deploy-thu7g5dj/ramdisk/ramdisk.cpio.gz.uboot
252 06:17:55.485842 - {ROOT_PART}: None
253 06:17:55.486232 - {ROOT}: None
254 06:17:55.486617 - {SERVER_IP}: 192.168.6.2
255 06:17:55.487008 - {TEE_ADDR}: 0x83000000
256 06:17:55.487395 - {TEE}: None
257 06:17:55.487782 Parsed boot commands:
258 06:17:55.488187 - setenv autoload no
259 06:17:55.488576 - setenv initrd_high 0xffffffff
260 06:17:55.488961 - setenv fdt_high 0xffffffff
261 06:17:55.489347 - dhcp
262 06:17:55.489733 - setenv serverip 192.168.6.2
263 06:17:55.490119 - tftpboot 0x01080000 790179/tftp-deploy-thu7g5dj/kernel/uImage
264 06:17:55.490504 - tftpboot 0x08000000 790179/tftp-deploy-thu7g5dj/ramdisk/ramdisk.cpio.gz.uboot
265 06:17:55.490888 - tftpboot 0x01070000 790179/tftp-deploy-thu7g5dj/dtb/meson-g12b-a311d-libretech-cc.dtb
266 06:17:55.491273 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 06:17:55.491665 - bootm 0x01080000 0x08000000 0x01070000
268 06:17:55.492181 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 06:17:55.493653 start: 2.3 connect-device (timeout 00:05:00) [common]
271 06:17:55.494089 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 06:17:55.508437 Setting prompt string to ['lava-test: # ']
273 06:17:55.509921 end: 2.3 connect-device (duration 00:00:00) [common]
274 06:17:55.510504 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 06:17:55.511089 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 06:17:55.511706 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 06:17:55.512912 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 06:17:55.549312 >> OK - accepted request
279 06:17:55.551501 Returned 0 in 0 seconds
280 06:17:55.652689 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 06:17:55.654323 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 06:17:55.654866 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 06:17:55.655384 Setting prompt string to ['Hit any key to stop autoboot']
285 06:17:55.655835 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 06:17:55.657426 Trying 192.168.56.21...
287 06:17:55.657892 Connected to conserv1.
288 06:17:55.658295 Escape character is '^]'.
289 06:17:55.658710
290 06:17:55.659125 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 06:17:55.659549
292 06:18:07.079573 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 06:18:07.080763 bl2_stage_init 0x01
294 06:18:07.081611 bl2_stage_init 0x81
295 06:18:07.085025 hw id: 0x0000 - pwm id 0x01
296 06:18:07.085610 bl2_stage_init 0xc1
297 06:18:07.086079 bl2_stage_init 0x02
298 06:18:07.086535
299 06:18:07.091108 L0:00000000
300 06:18:07.091618 L1:20000703
301 06:18:07.092098 L2:00008067
302 06:18:07.092535 L3:14000000
303 06:18:07.093528 B2:00402000
304 06:18:07.094045 B1:e0f83180
305 06:18:07.094494
306 06:18:07.094936 TE: 58167
307 06:18:07.095375
308 06:18:07.104792 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 06:18:07.105314
310 06:18:07.105752 Board ID = 1
311 06:18:07.106184 Set A53 clk to 24M
312 06:18:07.106616 Set A73 clk to 24M
313 06:18:07.110370 Set clk81 to 24M
314 06:18:07.110874 A53 clk: 1200 MHz
315 06:18:07.111310 A73 clk: 1200 MHz
316 06:18:07.116080 CLK81: 166.6M
317 06:18:07.116588 smccc: 00012abe
318 06:18:07.121676 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 06:18:07.122184 board id: 1
320 06:18:07.129598 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 06:18:07.140739 fw parse done
322 06:18:07.145793 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 06:18:07.189201 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 06:18:07.200203 PIEI prepare done
325 06:18:07.200731 fastboot data load
326 06:18:07.201168 fastboot data verify
327 06:18:07.205689 verify result: 266
328 06:18:07.211339 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 06:18:07.211875 LPDDR4 probe
330 06:18:07.212385 ddr clk to 1584MHz
331 06:18:07.219295 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 06:18:07.256566
333 06:18:07.257119 dmc_version 0001
334 06:18:07.263290 Check phy result
335 06:18:07.269222 INFO : End of CA training
336 06:18:07.269752 INFO : End of initialization
337 06:18:07.274698 INFO : Training has run successfully!
338 06:18:07.275223 Check phy result
339 06:18:07.280305 INFO : End of initialization
340 06:18:07.280835 INFO : End of read enable training
341 06:18:07.285977 INFO : End of fine write leveling
342 06:18:07.291473 INFO : End of Write leveling coarse delay
343 06:18:07.292044 INFO : Training has run successfully!
344 06:18:07.292496 Check phy result
345 06:18:07.297093 INFO : End of initialization
346 06:18:07.297616 INFO : End of read dq deskew training
347 06:18:07.302693 INFO : End of MPR read delay center optimization
348 06:18:07.308306 INFO : End of write delay center optimization
349 06:18:07.313877 INFO : End of read delay center optimization
350 06:18:07.314406 INFO : End of max read latency training
351 06:18:07.319453 INFO : Training has run successfully!
352 06:18:07.320034 1D training succeed
353 06:18:07.328621 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 06:18:07.376353 Check phy result
355 06:18:07.376910 INFO : End of initialization
356 06:18:07.397872 INFO : End of 2D read delay Voltage center optimization
357 06:18:07.417991 INFO : End of 2D read delay Voltage center optimization
358 06:18:07.469895 INFO : End of 2D write delay Voltage center optimization
359 06:18:07.519149 INFO : End of 2D write delay Voltage center optimization
360 06:18:07.524705 INFO : Training has run successfully!
361 06:18:07.525230
362 06:18:07.525693 channel==0
363 06:18:07.530302 RxClkDly_Margin_A0==88 ps 9
364 06:18:07.530821 TxDqDly_Margin_A0==98 ps 10
365 06:18:07.535913 RxClkDly_Margin_A1==88 ps 9
366 06:18:07.536475 TxDqDly_Margin_A1==98 ps 10
367 06:18:07.536939 TrainedVREFDQ_A0==74
368 06:18:07.541510 TrainedVREFDQ_A1==74
369 06:18:07.542035 VrefDac_Margin_A0==25
370 06:18:07.542489 DeviceVref_Margin_A0==40
371 06:18:07.547082 VrefDac_Margin_A1==25
372 06:18:07.547599 DeviceVref_Margin_A1==40
373 06:18:07.548090
374 06:18:07.548540
375 06:18:07.552703 channel==1
376 06:18:07.553211 RxClkDly_Margin_A0==98 ps 10
377 06:18:07.553662 TxDqDly_Margin_A0==88 ps 9
378 06:18:07.558323 RxClkDly_Margin_A1==88 ps 9
379 06:18:07.558836 TxDqDly_Margin_A1==88 ps 9
380 06:18:07.563920 TrainedVREFDQ_A0==77
381 06:18:07.564469 TrainedVREFDQ_A1==77
382 06:18:07.564929 VrefDac_Margin_A0==22
383 06:18:07.569527 DeviceVref_Margin_A0==37
384 06:18:07.570042 VrefDac_Margin_A1==24
385 06:18:07.575075 DeviceVref_Margin_A1==37
386 06:18:07.575583
387 06:18:07.576079 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 06:18:07.576536
389 06:18:07.608705 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 06:18:07.609323 2D training succeed
391 06:18:07.614407 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 06:18:07.621924 auto size-- 65535DDR cs0 size: 2048MB
393 06:18:07.622438 DDR cs1 size: 2048MB
394 06:18:07.625555 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 06:18:07.626064 cs0 DataBus test pass
396 06:18:07.631101 cs1 DataBus test pass
397 06:18:07.631609 cs0 AddrBus test pass
398 06:18:07.632102 cs1 AddrBus test pass
399 06:18:07.632551
400 06:18:07.636676 100bdlr_step_size ps== 420
401 06:18:07.637200 result report
402 06:18:07.642338 boot times 0Enable ddr reg access
403 06:18:07.647562 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 06:18:07.661003 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 06:18:08.233039 0.0;M3 CHK:0;cm4_sp_mode 0
406 06:18:08.233681 MVN_1=0x00000000
407 06:18:08.238557 MVN_2=0x00000000
408 06:18:08.244358 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 06:18:08.244873 OPS=0x10
410 06:18:08.245330 ring efuse init
411 06:18:08.245774 chipver efuse init
412 06:18:08.249881 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 06:18:08.255480 [0.018961 Inits done]
414 06:18:08.255976 secure task start!
415 06:18:08.256476 high task start!
416 06:18:08.260084 low task start!
417 06:18:08.260587 run into bl31
418 06:18:08.266712 NOTICE: BL31: v1.3(release):4fc40b1
419 06:18:08.274503 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 06:18:08.275016 NOTICE: BL31: G12A normal boot!
421 06:18:08.299883 NOTICE: BL31: BL33 decompress pass
422 06:18:08.305547 ERROR: Error initializing runtime service opteed_fast
423 06:18:09.538418
424 06:18:09.539048
425 06:18:09.546864 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 06:18:09.547383
427 06:18:09.547838 Model: Libre Computer AML-A311D-CC Alta
428 06:18:09.755292 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 06:18:09.778653 DRAM: 2 GiB (effective 3.8 GiB)
430 06:18:09.921692 Core: 408 devices, 31 uclasses, devicetree: separate
431 06:18:09.927658 WDT: Not starting watchdog@f0d0
432 06:18:09.959765 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 06:18:09.972321 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 06:18:09.977226 ** Bad device specification mmc 0 **
435 06:18:09.987576 Card did not respond to voltage select! : -110
436 06:18:09.995197 ** Bad device specification mmc 0 **
437 06:18:09.995713 Couldn't find partition mmc 0
438 06:18:10.003577 Card did not respond to voltage select! : -110
439 06:18:10.009084 ** Bad device specification mmc 0 **
440 06:18:10.009586 Couldn't find partition mmc 0
441 06:18:10.014127 Error: could not access storage.
442 06:18:11.259552 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 06:18:11.260235 bl2_stage_init 0x01
444 06:18:11.260704 bl2_stage_init 0x81
445 06:18:11.265211 hw id: 0x0000 - pwm id 0x01
446 06:18:11.265715 bl2_stage_init 0xc1
447 06:18:11.266168 bl2_stage_init 0x02
448 06:18:11.266608
449 06:18:11.270817 L0:00000000
450 06:18:11.271316 L1:20000703
451 06:18:11.271764 L2:00008067
452 06:18:11.272249 L3:14000000
453 06:18:11.276412 B2:00402000
454 06:18:11.276909 B1:e0f83180
455 06:18:11.277354
456 06:18:11.277794 TE: 58159
457 06:18:11.278239
458 06:18:11.281997 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 06:18:11.282500
460 06:18:11.282949 Board ID = 1
461 06:18:11.287582 Set A53 clk to 24M
462 06:18:11.288127 Set A73 clk to 24M
463 06:18:11.288584 Set clk81 to 24M
464 06:18:11.293182 A53 clk: 1200 MHz
465 06:18:11.293687 A73 clk: 1200 MHz
466 06:18:11.294138 CLK81: 166.6M
467 06:18:11.294572 smccc: 00012ab4
468 06:18:11.298800 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 06:18:11.304347 board id: 1
470 06:18:11.310243 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 06:18:11.320941 fw parse done
472 06:18:11.326892 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 06:18:11.369533 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 06:18:11.380417 PIEI prepare done
475 06:18:11.380914 fastboot data load
476 06:18:11.381365 fastboot data verify
477 06:18:11.386042 verify result: 266
478 06:18:11.391611 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 06:18:11.392152 LPDDR4 probe
480 06:18:11.392604 ddr clk to 1584MHz
481 06:18:11.399618 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 06:18:11.436867
483 06:18:11.437378 dmc_version 0001
484 06:18:11.443531 Check phy result
485 06:18:11.449517 INFO : End of CA training
486 06:18:11.450050 INFO : End of initialization
487 06:18:11.455025 INFO : Training has run successfully!
488 06:18:11.455523 Check phy result
489 06:18:11.460609 INFO : End of initialization
490 06:18:11.461106 INFO : End of read enable training
491 06:18:11.466194 INFO : End of fine write leveling
492 06:18:11.471788 INFO : End of Write leveling coarse delay
493 06:18:11.472334 INFO : Training has run successfully!
494 06:18:11.472789 Check phy result
495 06:18:11.477419 INFO : End of initialization
496 06:18:11.477916 INFO : End of read dq deskew training
497 06:18:11.483008 INFO : End of MPR read delay center optimization
498 06:18:11.488613 INFO : End of write delay center optimization
499 06:18:11.494196 INFO : End of read delay center optimization
500 06:18:11.494691 INFO : End of max read latency training
501 06:18:11.499802 INFO : Training has run successfully!
502 06:18:11.500337 1D training succeed
503 06:18:11.508963 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 06:18:11.556582 Check phy result
505 06:18:11.557098 INFO : End of initialization
506 06:18:11.579157 INFO : End of 2D read delay Voltage center optimization
507 06:18:11.599389 INFO : End of 2D read delay Voltage center optimization
508 06:18:11.651433 INFO : End of 2D write delay Voltage center optimization
509 06:18:11.700850 INFO : End of 2D write delay Voltage center optimization
510 06:18:11.706346 INFO : Training has run successfully!
511 06:18:11.706846
512 06:18:11.707299 channel==0
513 06:18:11.711965 RxClkDly_Margin_A0==88 ps 9
514 06:18:11.712501 TxDqDly_Margin_A0==98 ps 10
515 06:18:11.717579 RxClkDly_Margin_A1==88 ps 9
516 06:18:11.718074 TxDqDly_Margin_A1==98 ps 10
517 06:18:11.718521 TrainedVREFDQ_A0==74
518 06:18:11.723113 TrainedVREFDQ_A1==74
519 06:18:11.723631 VrefDac_Margin_A0==24
520 06:18:11.724118 DeviceVref_Margin_A0==40
521 06:18:11.728824 VrefDac_Margin_A1==24
522 06:18:11.729320 DeviceVref_Margin_A1==40
523 06:18:11.729767
524 06:18:11.730207
525 06:18:11.734334 channel==1
526 06:18:11.734829 RxClkDly_Margin_A0==98 ps 10
527 06:18:11.735276 TxDqDly_Margin_A0==88 ps 9
528 06:18:11.739908 RxClkDly_Margin_A1==88 ps 9
529 06:18:11.740437 TxDqDly_Margin_A1==88 ps 9
530 06:18:11.745558 TrainedVREFDQ_A0==77
531 06:18:11.746053 TrainedVREFDQ_A1==77
532 06:18:11.746502 VrefDac_Margin_A0==22
533 06:18:11.751117 DeviceVref_Margin_A0==37
534 06:18:11.751619 VrefDac_Margin_A1==24
535 06:18:11.756803 DeviceVref_Margin_A1==37
536 06:18:11.757299
537 06:18:11.757744 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 06:18:11.758185
539 06:18:11.790299 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 06:18:11.790848 2D training succeed
541 06:18:11.795937 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 06:18:11.801631 auto size-- 65535DDR cs0 size: 2048MB
543 06:18:11.802135 DDR cs1 size: 2048MB
544 06:18:11.807133 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 06:18:11.807632 cs0 DataBus test pass
546 06:18:11.812871 cs1 DataBus test pass
547 06:18:11.813376 cs0 AddrBus test pass
548 06:18:11.813825 cs1 AddrBus test pass
549 06:18:11.814266
550 06:18:11.818312 100bdlr_step_size ps== 420
551 06:18:11.818820 result report
552 06:18:11.823907 boot times 0Enable ddr reg access
553 06:18:11.829169 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 06:18:11.842656 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 06:18:12.416453 0.0;M3 CHK:0;cm4_sp_mode 0
556 06:18:12.417065 MVN_1=0x00000000
557 06:18:12.422079 MVN_2=0x00000000
558 06:18:12.427823 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 06:18:12.428398 OPS=0x10
560 06:18:12.428877 ring efuse init
561 06:18:12.429340 chipver efuse init
562 06:18:12.433447 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 06:18:12.439023 [0.018960 Inits done]
564 06:18:12.439512 secure task start!
565 06:18:12.439943 high task start!
566 06:18:12.442736 low task start!
567 06:18:12.443215 run into bl31
568 06:18:12.450213 NOTICE: BL31: v1.3(release):4fc40b1
569 06:18:12.457705 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 06:18:12.458202 NOTICE: BL31: G12A normal boot!
571 06:18:12.483435 NOTICE: BL31: BL33 decompress pass
572 06:18:12.488147 ERROR: Error initializing runtime service opteed_fast
573 06:18:13.721728
574 06:18:13.722344
575 06:18:13.729253 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 06:18:13.729761
577 06:18:13.730215 Model: Libre Computer AML-A311D-CC Alta
578 06:18:13.938529 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 06:18:13.961136 DRAM: 2 GiB (effective 3.8 GiB)
580 06:18:14.105092 Core: 408 devices, 31 uclasses, devicetree: separate
581 06:18:14.110416 WDT: Not starting watchdog@f0d0
582 06:18:14.143272 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 06:18:14.155545 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 06:18:14.160410 ** Bad device specification mmc 0 **
585 06:18:14.171010 Card did not respond to voltage select! : -110
586 06:18:14.178122 ** Bad device specification mmc 0 **
587 06:18:14.178711 Couldn't find partition mmc 0
588 06:18:14.187003 Card did not respond to voltage select! : -110
589 06:18:14.192461 ** Bad device specification mmc 0 **
590 06:18:14.193042 Couldn't find partition mmc 0
591 06:18:14.196540 Error: could not access storage.
592 06:18:14.591401 Net: eth0: ethernet@ff3f0000
593 06:18:14.592086 starting USB...
594 06:18:14.791705 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 06:18:14.792387 Starting the controller
596 06:18:14.798189 USB XHCI 1.10
597 06:18:16.511367 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
598 06:18:16.512106 bl2_stage_init 0x81
599 06:18:16.516892 hw id: 0x0000 - pwm id 0x01
600 06:18:16.517422 bl2_stage_init 0xc1
601 06:18:16.517879 bl2_stage_init 0x02
602 06:18:16.518330
603 06:18:16.522496 L0:00000000
604 06:18:16.523007 L1:20000703
605 06:18:16.523457 L2:00008067
606 06:18:16.523901 L3:14000000
607 06:18:16.524392 B2:00402000
608 06:18:16.525381 B1:e0f83180
609 06:18:16.525873
610 06:18:16.526326 TE: 58150
611 06:18:16.526774
612 06:18:16.536434 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 06:18:16.536982
614 06:18:16.537453 Board ID = 1
615 06:18:16.537910 Set A53 clk to 24M
616 06:18:16.538358 Set A73 clk to 24M
617 06:18:16.542069 Set clk81 to 24M
618 06:18:16.542581 A53 clk: 1200 MHz
619 06:18:16.543039 A73 clk: 1200 MHz
620 06:18:16.547681 CLK81: 166.6M
621 06:18:16.548221 smccc: 00012aac
622 06:18:16.553282 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 06:18:16.553790 board id: 1
624 06:18:16.561692 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 06:18:16.572421 fw parse done
626 06:18:16.577474 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 06:18:16.621074 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 06:18:16.631945 PIEI prepare done
629 06:18:16.632530 fastboot data load
630 06:18:16.632995 fastboot data verify
631 06:18:16.637652 verify result: 266
632 06:18:16.643269 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 06:18:16.643798 LPDDR4 probe
634 06:18:16.644294 ddr clk to 1584MHz
635 06:18:16.650304 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 06:18:16.687719
637 06:18:16.688308 dmc_version 0001
638 06:18:16.694193 Check phy result
639 06:18:16.700995 INFO : End of CA training
640 06:18:16.701515 INFO : End of initialization
641 06:18:16.706596 INFO : Training has run successfully!
642 06:18:16.707110 Check phy result
643 06:18:16.712313 INFO : End of initialization
644 06:18:16.712829 INFO : End of read enable training
645 06:18:16.717802 INFO : End of fine write leveling
646 06:18:16.723431 INFO : End of Write leveling coarse delay
647 06:18:16.723953 INFO : Training has run successfully!
648 06:18:16.724454 Check phy result
649 06:18:16.729050 INFO : End of initialization
650 06:18:16.729579 INFO : End of read dq deskew training
651 06:18:16.734607 INFO : End of MPR read delay center optimization
652 06:18:16.740291 INFO : End of write delay center optimization
653 06:18:16.745800 INFO : End of read delay center optimization
654 06:18:16.746324 INFO : End of max read latency training
655 06:18:16.751404 INFO : Training has run successfully!
656 06:18:16.751926 1D training succeed
657 06:18:16.759936 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 06:18:16.807297 Check phy result
659 06:18:16.807867 INFO : End of initialization
660 06:18:16.829939 INFO : End of 2D read delay Voltage center optimization
661 06:18:16.849260 INFO : End of 2D read delay Voltage center optimization
662 06:18:16.901314 INFO : End of 2D write delay Voltage center optimization
663 06:18:16.951576 INFO : End of 2D write delay Voltage center optimization
664 06:18:16.957146 INFO : Training has run successfully!
665 06:18:16.957686
666 06:18:16.958141 channel==0
667 06:18:16.962734 RxClkDly_Margin_A0==88 ps 9
668 06:18:16.963264 TxDqDly_Margin_A0==98 ps 10
669 06:18:16.968305 RxClkDly_Margin_A1==88 ps 9
670 06:18:16.968829 TxDqDly_Margin_A1==98 ps 10
671 06:18:16.969281 TrainedVREFDQ_A0==74
672 06:18:16.973967 TrainedVREFDQ_A1==74
673 06:18:16.974547 VrefDac_Margin_A0==25
674 06:18:16.975005 DeviceVref_Margin_A0==40
675 06:18:16.979541 VrefDac_Margin_A1==25
676 06:18:16.980103 DeviceVref_Margin_A1==40
677 06:18:16.980560
678 06:18:16.981010
679 06:18:16.985130 channel==1
680 06:18:16.985654 RxClkDly_Margin_A0==98 ps 10
681 06:18:16.986108 TxDqDly_Margin_A0==98 ps 10
682 06:18:16.990747 RxClkDly_Margin_A1==98 ps 10
683 06:18:16.991285 TxDqDly_Margin_A1==98 ps 10
684 06:18:16.996343 TrainedVREFDQ_A0==77
685 06:18:16.996874 TrainedVREFDQ_A1==77
686 06:18:16.997329 VrefDac_Margin_A0==22
687 06:18:17.001943 DeviceVref_Margin_A0==37
688 06:18:17.002476 VrefDac_Margin_A1==22
689 06:18:17.007518 DeviceVref_Margin_A1==37
690 06:18:17.008064
691 06:18:17.008525 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 06:18:17.013096
693 06:18:17.041073 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 06:18:17.041684 2D training succeed
695 06:18:17.046753 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 06:18:17.052344 auto size-- 65535DDR cs0 size: 2048MB
697 06:18:17.052880 DDR cs1 size: 2048MB
698 06:18:17.057921 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 06:18:17.058442 cs0 DataBus test pass
700 06:18:17.063509 cs1 DataBus test pass
701 06:18:17.064079 cs0 AddrBus test pass
702 06:18:17.064538 cs1 AddrBus test pass
703 06:18:17.064982
704 06:18:17.069132 100bdlr_step_size ps== 420
705 06:18:17.069659 result report
706 06:18:17.074734 boot times 0Enable ddr reg access
707 06:18:17.079314 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 06:18:17.092801 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 06:18:17.667401 0.0;M3 CHK:0;cm4_sp_mode 0
710 06:18:17.668108 MVN_1=0x00000000
711 06:18:17.672858 MVN_2=0x00000000
712 06:18:17.678625 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 06:18:17.679198 OPS=0x10
714 06:18:17.679654 ring efuse init
715 06:18:17.680179 chipver efuse init
716 06:18:17.686822 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 06:18:17.687357 [0.018961 Inits done]
718 06:18:17.687796 secure task start!
719 06:18:17.693623 high task start!
720 06:18:17.694138 low task start!
721 06:18:17.694572 run into bl31
722 06:18:17.701053 NOTICE: BL31: v1.3(release):4fc40b1
723 06:18:17.708894 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 06:18:17.709449 NOTICE: BL31: G12A normal boot!
725 06:18:17.734218 NOTICE: BL31: BL33 decompress pass
726 06:18:17.739008 ERROR: Error initializing runtime service opteed_fast
727 06:18:18.972718
728 06:18:18.973147
729 06:18:18.980791 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 06:18:18.981119
731 06:18:18.981342 Model: Libre Computer AML-A311D-CC Alta
732 06:18:19.188997 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 06:18:19.212603 DRAM: 2 GiB (effective 3.8 GiB)
734 06:18:19.356266 Core: 408 devices, 31 uclasses, devicetree: separate
735 06:18:19.361620 WDT: Not starting watchdog@f0d0
736 06:18:19.394292 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 06:18:19.406782 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 06:18:19.411610 ** Bad device specification mmc 0 **
739 06:18:19.421940 Card did not respond to voltage select! : -110
740 06:18:19.429355 ** Bad device specification mmc 0 **
741 06:18:19.430066 Couldn't find partition mmc 0
742 06:18:19.437846 Card did not respond to voltage select! : -110
743 06:18:19.443369 ** Bad device specification mmc 0 **
744 06:18:19.444179 Couldn't find partition mmc 0
745 06:18:19.447721 Error: could not access storage.
746 06:18:19.790627 Net: eth0: ethernet@ff3f0000
747 06:18:19.791470 starting USB...
748 06:18:20.042882 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 06:18:20.043661 Starting the controller
750 06:18:20.049272 USB XHCI 1.10
751 06:18:22.209895 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 06:18:22.210553 bl2_stage_init 0x01
753 06:18:22.210992 bl2_stage_init 0x81
754 06:18:22.215431 hw id: 0x0000 - pwm id 0x01
755 06:18:22.215906 bl2_stage_init 0xc1
756 06:18:22.216387 bl2_stage_init 0x02
757 06:18:22.216805
758 06:18:22.221116 L0:00000000
759 06:18:22.221596 L1:20000703
760 06:18:22.222020 L2:00008067
761 06:18:22.222439 L3:14000000
762 06:18:22.226661 B2:00402000
763 06:18:22.227133 B1:e0f83180
764 06:18:22.227550
765 06:18:22.227961 TE: 58167
766 06:18:22.228415
767 06:18:22.232223 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 06:18:22.232703
769 06:18:22.233135 Board ID = 1
770 06:18:22.237815 Set A53 clk to 24M
771 06:18:22.238284 Set A73 clk to 24M
772 06:18:22.238701 Set clk81 to 24M
773 06:18:22.243413 A53 clk: 1200 MHz
774 06:18:22.243869 A73 clk: 1200 MHz
775 06:18:22.244317 CLK81: 166.6M
776 06:18:22.244723 smccc: 00012abd
777 06:18:22.249058 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 06:18:22.254693 board id: 1
779 06:18:22.259453 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 06:18:22.271184 fw parse done
781 06:18:22.276281 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 06:18:22.318792 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 06:18:22.330654 PIEI prepare done
784 06:18:22.331158 fastboot data load
785 06:18:22.331580 fastboot data verify
786 06:18:22.336257 verify result: 266
787 06:18:22.341908 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 06:18:22.342388 LPDDR4 probe
789 06:18:22.342801 ddr clk to 1584MHz
790 06:18:22.348846 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 06:18:22.386253
792 06:18:22.386804 dmc_version 0001
793 06:18:22.392814 Check phy result
794 06:18:22.399639 INFO : End of CA training
795 06:18:22.400153 INFO : End of initialization
796 06:18:22.405151 INFO : Training has run successfully!
797 06:18:22.405636 Check phy result
798 06:18:22.410752 INFO : End of initialization
799 06:18:22.411226 INFO : End of read enable training
800 06:18:22.414064 INFO : End of fine write leveling
801 06:18:22.419726 INFO : End of Write leveling coarse delay
802 06:18:22.425260 INFO : Training has run successfully!
803 06:18:22.425743 Check phy result
804 06:18:22.426163 INFO : End of initialization
805 06:18:22.431412 INFO : End of read dq deskew training
806 06:18:22.434290 INFO : End of MPR read delay center optimization
807 06:18:22.439819 INFO : End of write delay center optimization
808 06:18:22.445454 INFO : End of read delay center optimization
809 06:18:22.445934 INFO : End of max read latency training
810 06:18:22.451022 INFO : Training has run successfully!
811 06:18:22.451485 1D training succeed
812 06:18:22.458316 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 06:18:22.505844 Check phy result
814 06:18:22.506370 INFO : End of initialization
815 06:18:22.527693 INFO : End of 2D read delay Voltage center optimization
816 06:18:22.547957 INFO : End of 2D read delay Voltage center optimization
817 06:18:22.599963 INFO : End of 2D write delay Voltage center optimization
818 06:18:22.650302 INFO : End of 2D write delay Voltage center optimization
819 06:18:22.655840 INFO : Training has run successfully!
820 06:18:22.656366
821 06:18:22.656798 channel==0
822 06:18:22.661413 RxClkDly_Margin_A0==88 ps 9
823 06:18:22.661876 TxDqDly_Margin_A0==98 ps 10
824 06:18:22.664676 RxClkDly_Margin_A1==88 ps 9
825 06:18:22.665128 TxDqDly_Margin_A1==88 ps 9
826 06:18:22.670181 TrainedVREFDQ_A0==74
827 06:18:22.670644 TrainedVREFDQ_A1==74
828 06:18:22.671068 VrefDac_Margin_A0==25
829 06:18:22.675916 DeviceVref_Margin_A0==40
830 06:18:22.676441 VrefDac_Margin_A1==25
831 06:18:22.681481 DeviceVref_Margin_A1==40
832 06:18:22.681962
833 06:18:22.682360
834 06:18:22.682749 channel==1
835 06:18:22.683138 RxClkDly_Margin_A0==98 ps 10
836 06:18:22.684931 TxDqDly_Margin_A0==88 ps 9
837 06:18:22.690923 RxClkDly_Margin_A1==88 ps 9
838 06:18:22.691386 TxDqDly_Margin_A1==88 ps 9
839 06:18:22.691785 TrainedVREFDQ_A0==77
840 06:18:22.696018 TrainedVREFDQ_A1==77
841 06:18:22.696478 VrefDac_Margin_A0==22
842 06:18:22.701539 DeviceVref_Margin_A0==37
843 06:18:22.701978 VrefDac_Margin_A1==24
844 06:18:22.702381 DeviceVref_Margin_A1==37
845 06:18:22.702777
846 06:18:22.710547 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 06:18:22.711020
848 06:18:22.736201 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
849 06:18:22.741742 2D training succeed
850 06:18:22.745174 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 06:18:22.750737 auto size-- 65535DDR cs0 size: 2048MB
852 06:18:22.751188 DDR cs1 size: 2048MB
853 06:18:22.756319 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 06:18:22.756770 cs0 DataBus test pass
855 06:18:22.761953 cs1 DataBus test pass
856 06:18:22.762390 cs0 AddrBus test pass
857 06:18:22.762779 cs1 AddrBus test pass
858 06:18:22.763165
859 06:18:22.767722 100bdlr_step_size ps== 420
860 06:18:22.768229 result report
861 06:18:22.773217 boot times 0Enable ddr reg access
862 06:18:22.777661 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 06:18:22.791141 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 06:18:23.365729 0.0;M3 CHK:0;cm4_sp_mode 0
865 06:18:23.366331 MVN_1=0x00000000
866 06:18:23.371225 MVN_2=0x00000000
867 06:18:23.376928 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 06:18:23.377411 OPS=0x10
869 06:18:23.377844 ring efuse init
870 06:18:23.378264 chipver efuse init
871 06:18:23.385291 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 06:18:23.385770 [0.018961 Inits done]
873 06:18:23.386181 secure task start!
874 06:18:23.391769 high task start!
875 06:18:23.392264 low task start!
876 06:18:23.392690 run into bl31
877 06:18:23.399453 NOTICE: BL31: v1.3(release):4fc40b1
878 06:18:23.406336 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 06:18:23.406808 NOTICE: BL31: G12A normal boot!
880 06:18:23.433125 NOTICE: BL31: BL33 decompress pass
881 06:18:23.438199 ERROR: Error initializing runtime service opteed_fast
882 06:18:24.671604
883 06:18:24.672238
884 06:18:24.679059 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 06:18:24.679547
886 06:18:24.679973 Model: Libre Computer AML-A311D-CC Alta
887 06:18:24.888204 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 06:18:24.911711 DRAM: 2 GiB (effective 3.8 GiB)
889 06:18:25.054842 Core: 408 devices, 31 uclasses, devicetree: separate
890 06:18:25.059760 WDT: Not starting watchdog@f0d0
891 06:18:25.092975 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 06:18:25.105432 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 06:18:25.109732 ** Bad device specification mmc 0 **
894 06:18:25.120757 Card did not respond to voltage select! : -110
895 06:18:25.127414 ** Bad device specification mmc 0 **
896 06:18:25.127934 Couldn't find partition mmc 0
897 06:18:25.136771 Card did not respond to voltage select! : -110
898 06:18:25.142285 ** Bad device specification mmc 0 **
899 06:18:25.142785 Couldn't find partition mmc 0
900 06:18:25.147021 Error: could not access storage.
901 06:18:25.490493 Net: eth0: ethernet@ff3f0000
902 06:18:25.491205 starting USB...
903 06:18:25.742648 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 06:18:25.743290 Starting the controller
905 06:18:25.749159 USB XHCI 1.10
906 06:18:27.609677 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 06:18:27.610672 bl2_stage_init 0x01
908 06:18:27.611337 bl2_stage_init 0x81
909 06:18:27.615140 hw id: 0x0000 - pwm id 0x01
910 06:18:27.615704 bl2_stage_init 0xc1
911 06:18:27.616232 bl2_stage_init 0x02
912 06:18:27.616712
913 06:18:27.620736 L0:00000000
914 06:18:27.621479 L1:20000703
915 06:18:27.622186 L2:00008067
916 06:18:27.622919 L3:14000000
917 06:18:27.623886 B2:00402000
918 06:18:27.624479 B1:e0f83180
919 06:18:27.624944
920 06:18:27.625428 TE: 58167
921 06:18:27.625922
922 06:18:27.634865 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 06:18:27.635627
924 06:18:27.636259 Board ID = 1
925 06:18:27.636771 Set A53 clk to 24M
926 06:18:27.637185 Set A73 clk to 24M
927 06:18:27.640415 Set clk81 to 24M
928 06:18:27.640977 A53 clk: 1200 MHz
929 06:18:27.641461 A73 clk: 1200 MHz
930 06:18:27.646109 CLK81: 166.6M
931 06:18:27.646836 smccc: 00012abe
932 06:18:27.651581 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 06:18:27.652178 board id: 1
934 06:18:27.660160 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 06:18:27.670922 fw parse done
936 06:18:27.676955 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 06:18:27.719418 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 06:18:27.730307 PIEI prepare done
939 06:18:27.730848 fastboot data load
940 06:18:27.731267 fastboot data verify
941 06:18:27.735926 verify result: 266
942 06:18:27.741564 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 06:18:27.742434 LPDDR4 probe
944 06:18:27.743064 ddr clk to 1584MHz
945 06:18:27.749488 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 06:18:27.786907
947 06:18:27.787486 dmc_version 0001
948 06:18:27.793550 Check phy result
949 06:18:27.799377 INFO : End of CA training
950 06:18:27.800147 INFO : End of initialization
951 06:18:27.804976 INFO : Training has run successfully!
952 06:18:27.805501 Check phy result
953 06:18:27.810495 INFO : End of initialization
954 06:18:27.810961 INFO : End of read enable training
955 06:18:27.816193 INFO : End of fine write leveling
956 06:18:27.821688 INFO : End of Write leveling coarse delay
957 06:18:27.822146 INFO : Training has run successfully!
958 06:18:27.822559 Check phy result
959 06:18:27.827284 INFO : End of initialization
960 06:18:27.827772 INFO : End of read dq deskew training
961 06:18:27.832895 INFO : End of MPR read delay center optimization
962 06:18:27.838557 INFO : End of write delay center optimization
963 06:18:27.844130 INFO : End of read delay center optimization
964 06:18:27.844614 INFO : End of max read latency training
965 06:18:27.849713 INFO : Training has run successfully!
966 06:18:27.850294 1D training succeed
967 06:18:27.858922 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 06:18:27.906498 Check phy result
969 06:18:27.907085 INFO : End of initialization
970 06:18:27.928235 INFO : End of 2D read delay Voltage center optimization
971 06:18:27.947033 INFO : End of 2D read delay Voltage center optimization
972 06:18:27.998848 INFO : End of 2D write delay Voltage center optimization
973 06:18:28.049116 INFO : End of 2D write delay Voltage center optimization
974 06:18:28.054585 INFO : Training has run successfully!
975 06:18:28.055087
976 06:18:28.055516 channel==0
977 06:18:28.060183 RxClkDly_Margin_A0==88 ps 9
978 06:18:28.060643 TxDqDly_Margin_A0==98 ps 10
979 06:18:28.065829 RxClkDly_Margin_A1==88 ps 9
980 06:18:28.066467 TxDqDly_Margin_A1==88 ps 9
981 06:18:28.066923 TrainedVREFDQ_A0==74
982 06:18:28.071381 TrainedVREFDQ_A1==74
983 06:18:28.071855 VrefDac_Margin_A0==25
984 06:18:28.072368 DeviceVref_Margin_A0==40
985 06:18:28.077021 VrefDac_Margin_A1==25
986 06:18:28.077595 DeviceVref_Margin_A1==40
987 06:18:28.078001
988 06:18:28.078528
989 06:18:28.078981 channel==1
990 06:18:28.082576 RxClkDly_Margin_A0==88 ps 9
991 06:18:28.083030 TxDqDly_Margin_A0==88 ps 9
992 06:18:28.088254 RxClkDly_Margin_A1==98 ps 10
993 06:18:28.088999 TxDqDly_Margin_A1==88 ps 9
994 06:18:28.093868 TrainedVREFDQ_A0==77
995 06:18:28.094398 TrainedVREFDQ_A1==77
996 06:18:28.094859 VrefDac_Margin_A0==23
997 06:18:28.099472 DeviceVref_Margin_A0==37
998 06:18:28.100268 VrefDac_Margin_A1==23
999 06:18:28.105013 DeviceVref_Margin_A1==37
1000 06:18:28.105523
1001 06:18:28.105978 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 06:18:28.106393
1003 06:18:28.138734 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000019 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1004 06:18:28.139393 2D training succeed
1005 06:18:28.144275 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 06:18:28.150025 auto size-- 65535DDR cs0 size: 2048MB
1007 06:18:28.150847 DDR cs1 size: 2048MB
1008 06:18:28.155415 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 06:18:28.156017 cs0 DataBus test pass
1010 06:18:28.161057 cs1 DataBus test pass
1011 06:18:28.161845 cs0 AddrBus test pass
1012 06:18:28.162708 cs1 AddrBus test pass
1013 06:18:28.163414
1014 06:18:28.166639 100bdlr_step_size ps== 420
1015 06:18:28.167163 result report
1016 06:18:28.172238 boot times 0Enable ddr reg access
1017 06:18:28.177450 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 06:18:28.190951 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 06:18:28.764540 0.0;M3 CHK:0;cm4_sp_mode 0
1020 06:18:28.765282 MVN_1=0x00000000
1021 06:18:28.769958 MVN_2=0x00000000
1022 06:18:28.775802 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 06:18:28.776340 OPS=0x10
1024 06:18:28.776850 ring efuse init
1025 06:18:28.777679 chipver efuse init
1026 06:18:28.781369 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 06:18:28.786973 [0.018961 Inits done]
1028 06:18:28.787482 secure task start!
1029 06:18:28.787903 high task start!
1030 06:18:28.791494 low task start!
1031 06:18:28.792009 run into bl31
1032 06:18:28.798170 NOTICE: BL31: v1.3(release):4fc40b1
1033 06:18:28.805097 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 06:18:28.805746 NOTICE: BL31: G12A normal boot!
1035 06:18:28.831391 NOTICE: BL31: BL33 decompress pass
1036 06:18:28.837037 ERROR: Error initializing runtime service opteed_fast
1037 06:18:30.069925
1038 06:18:30.070557
1039 06:18:30.078367 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 06:18:30.079007
1041 06:18:30.079479 Model: Libre Computer AML-A311D-CC Alta
1042 06:18:30.286817 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 06:18:30.309644 DRAM: 2 GiB (effective 3.8 GiB)
1044 06:18:30.453264 Core: 408 devices, 31 uclasses, devicetree: separate
1045 06:18:30.458122 WDT: Not starting watchdog@f0d0
1046 06:18:30.491383 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 06:18:30.503808 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 06:18:30.508722 ** Bad device specification mmc 0 **
1049 06:18:30.519104 Card did not respond to voltage select! : -110
1050 06:18:30.526755 ** Bad device specification mmc 0 **
1051 06:18:30.527348 Couldn't find partition mmc 0
1052 06:18:30.535124 Card did not respond to voltage select! : -110
1053 06:18:30.540550 ** Bad device specification mmc 0 **
1054 06:18:30.541112 Couldn't find partition mmc 0
1055 06:18:30.545627 Error: could not access storage.
1056 06:18:30.888158 Net: eth0: ethernet@ff3f0000
1057 06:18:30.888856 starting USB...
1058 06:18:31.139903 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 06:18:31.140667 Starting the controller
1060 06:18:31.146836 USB XHCI 1.10
1061 06:18:32.702922 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 06:18:32.710579 scanning usb for storage devices... 0 Storage Device(s) found
1064 06:18:32.762588 Hit any key to stop autoboot: 1
1065 06:18:32.763642 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 06:18:32.764394 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 06:18:32.764915 Setting prompt string to ['=>']
1068 06:18:32.765441 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 06:18:32.778870 0
1070 06:18:32.780006 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 06:18:32.780570 Sending with 10 millisecond of delay
1073 06:18:33.915477 => setenv autoload no
1074 06:18:33.926367 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 06:18:33.931718 setenv autoload no
1076 06:18:33.932553 Sending with 10 millisecond of delay
1078 06:18:35.729526 => setenv initrd_high 0xffffffff
1079 06:18:35.740350 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 06:18:35.741289 setenv initrd_high 0xffffffff
1081 06:18:35.742048 Sending with 10 millisecond of delay
1083 06:18:37.358556 => setenv fdt_high 0xffffffff
1084 06:18:37.369400 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 06:18:37.370349 setenv fdt_high 0xffffffff
1086 06:18:37.371112 Sending with 10 millisecond of delay
1088 06:18:37.663220 => dhcp
1089 06:18:37.674047 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 06:18:37.674980 dhcp
1091 06:18:37.675462 Speed: 1000, full duplex
1092 06:18:37.675926 BOOTP broadcast 1
1093 06:18:37.922797 BOOTP broadcast 2
1094 06:18:38.423807 BOOTP broadcast 3
1095 06:18:38.445223 DHCP client bound to address 192.168.6.33 (771 ms)
1096 06:18:38.446050 Sending with 10 millisecond of delay
1098 06:18:40.123495 => setenv serverip 192.168.6.2
1099 06:18:40.134413 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1100 06:18:40.135380 setenv serverip 192.168.6.2
1101 06:18:40.136153 Sending with 10 millisecond of delay
1103 06:18:43.862278 => tftpboot 0x01080000 790179/tftp-deploy-thu7g5dj/kernel/uImage
1104 06:18:43.872840 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1105 06:18:43.873397 tftpboot 0x01080000 790179/tftp-deploy-thu7g5dj/kernel/uImage
1106 06:18:43.873635 Speed: 1000, full duplex
1107 06:18:43.873851 Using ethernet@ff3f0000 device
1108 06:18:43.875546 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1109 06:18:43.881024 Filename '790179/tftp-deploy-thu7g5dj/kernel/uImage'.
1110 06:18:43.884608 Load address: 0x1080000
1111 06:18:47.802523 Loading: *################################################## 37.6 MiB
1112 06:18:47.802941 9.6 MiB/s
1113 06:18:47.803166 done
1114 06:18:47.806761 Bytes transferred = 39424576 (2599240 hex)
1115 06:18:47.807273 Sending with 10 millisecond of delay
1117 06:18:52.499540 => tftpboot 0x08000000 790179/tftp-deploy-thu7g5dj/ramdisk/ramdisk.cpio.gz.uboot
1118 06:18:52.510400 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
1119 06:18:52.511302 tftpboot 0x08000000 790179/tftp-deploy-thu7g5dj/ramdisk/ramdisk.cpio.gz.uboot
1120 06:18:52.511743 Speed: 1000, full duplex
1121 06:18:52.512191 Using ethernet@ff3f0000 device
1122 06:18:52.513463 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1123 06:18:52.524294 Filename '790179/tftp-deploy-thu7g5dj/ramdisk/ramdisk.cpio.gz.uboot'.
1124 06:18:52.524870 Load address: 0x8000000
1125 06:18:52.635205 Loading: *## UDP wrong checksum 000000ff 0000e198
1126 06:18:52.678710 # UDP wrong checksum 000000ff 0000768b
1127 06:18:55.243227 ############################################## UDP wrong checksum 00000005 0000ad8c
1128 06:18:57.089047 UDP wrong checksum 000000ff 00006ea2
1129 06:18:57.109917 UDP wrong checksum 000000ff 0000f194
1130 06:19:00.237072 T UDP wrong checksum 00000005 0000ad8c
1131 06:19:10.239171 T T UDP wrong checksum 00000005 0000ad8c
1132 06:19:12.159973 UDP wrong checksum 000000ff 0000d0a8
1133 06:19:12.171148 UDP wrong checksum 000000ff 0000549b
1134 06:19:30.240179 T T T UDP wrong checksum 00000005 0000ad8c
1135 06:19:50.246969 T T T T
1136 06:19:50.247408 Retry count exceeded; starting again
1138 06:19:50.248627 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1141 06:19:50.249565 end: 2.4 uboot-commands (duration 00:01:55) [common]
1143 06:19:50.250265 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1145 06:19:50.250818 end: 2 uboot-action (duration 00:01:55) [common]
1147 06:19:50.251628 Cleaning after the job
1148 06:19:50.251952 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/ramdisk
1149 06:19:50.252696 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/kernel
1150 06:19:50.256147 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/dtb
1151 06:19:50.256866 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/790179/tftp-deploy-thu7g5dj/modules
1152 06:19:50.260243 start: 4.1 power-off (timeout 00:00:30) [common]
1153 06:19:50.260815 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1154 06:19:50.292671 >> OK - accepted request
1155 06:19:50.294586 Returned 0 in 0 seconds
1156 06:19:50.395368 end: 4.1 power-off (duration 00:00:00) [common]
1158 06:19:50.396458 start: 4.2 read-feedback (timeout 00:10:00) [common]
1159 06:19:50.397125 Listened to connection for namespace 'common' for up to 1s
1160 06:19:51.398243 Finalising connection for namespace 'common'
1161 06:19:51.398859 Disconnecting from shell: Finalise
1162 06:19:51.399227 =>
1163 06:19:51.500627 end: 4.2 read-feedback (duration 00:00:01) [common]
1164 06:19:51.501522 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/790179
1165 06:19:51.773757 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/790179
1166 06:19:51.774368 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.