Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:27:13.999590 lava-dispatcher, installed at version: 2024.01
2 05:27:14.000415 start: 0 validate
3 05:27:14.000907 Start time: 2024-10-03 05:27:14.000876+00:00 (UTC)
4 05:27:14.001471 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:27:14.002021 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:27:14.039629 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:27:14.040246 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 05:27:15.092889 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:27:15.093526 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:27:21.164216 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:27:21.164745 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 05:27:23.215162 validate duration: 9.21
14 05:27:23.216093 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:27:23.216465 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:27:23.216780 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:27:23.217393 Not decompressing ramdisk as can be used compressed.
18 05:27:23.217840 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:27:23.218098 saving as /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/ramdisk/rootfs.cpio.gz
20 05:27:23.218375 total size: 8181887 (7 MB)
21 05:27:23.255689 progress 0 % (0 MB)
22 05:27:23.267009 progress 5 % (0 MB)
23 05:27:23.278817 progress 10 % (0 MB)
24 05:27:23.289127 progress 15 % (1 MB)
25 05:27:23.294639 progress 20 % (1 MB)
26 05:27:23.300482 progress 25 % (1 MB)
27 05:27:23.306096 progress 30 % (2 MB)
28 05:27:23.311841 progress 35 % (2 MB)
29 05:27:23.317357 progress 40 % (3 MB)
30 05:27:23.328393 progress 45 % (3 MB)
31 05:27:23.336750 progress 50 % (3 MB)
32 05:27:23.342669 progress 55 % (4 MB)
33 05:27:23.348110 progress 60 % (4 MB)
34 05:27:23.353932 progress 65 % (5 MB)
35 05:27:23.359318 progress 70 % (5 MB)
36 05:27:23.365174 progress 75 % (5 MB)
37 05:27:23.370556 progress 80 % (6 MB)
38 05:27:23.376282 progress 85 % (6 MB)
39 05:27:23.381671 progress 90 % (7 MB)
40 05:27:23.387140 progress 95 % (7 MB)
41 05:27:23.392126 progress 100 % (7 MB)
42 05:27:23.392824 7 MB downloaded in 0.17 s (44.73 MB/s)
43 05:27:23.393414 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:27:23.394352 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:27:23.394692 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:27:23.395073 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:27:23.395597 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/kernel/Image
49 05:27:23.395874 saving as /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/kernel/Image
50 05:27:23.396134 total size: 47391232 (45 MB)
51 05:27:23.396364 No compression specified
52 05:27:23.430814 progress 0 % (0 MB)
53 05:27:23.461054 progress 5 % (2 MB)
54 05:27:23.491401 progress 10 % (4 MB)
55 05:27:23.521205 progress 15 % (6 MB)
56 05:27:23.551865 progress 20 % (9 MB)
57 05:27:23.581838 progress 25 % (11 MB)
58 05:27:23.611528 progress 30 % (13 MB)
59 05:27:23.642004 progress 35 % (15 MB)
60 05:27:23.671944 progress 40 % (18 MB)
61 05:27:23.701816 progress 45 % (20 MB)
62 05:27:23.732037 progress 50 % (22 MB)
63 05:27:23.763120 progress 55 % (24 MB)
64 05:27:23.793045 progress 60 % (27 MB)
65 05:27:23.823196 progress 65 % (29 MB)
66 05:27:23.852987 progress 70 % (31 MB)
67 05:27:23.882284 progress 75 % (33 MB)
68 05:27:23.912196 progress 80 % (36 MB)
69 05:27:23.941641 progress 85 % (38 MB)
70 05:27:23.971581 progress 90 % (40 MB)
71 05:27:24.001091 progress 95 % (42 MB)
72 05:27:24.030099 progress 100 % (45 MB)
73 05:27:24.030672 45 MB downloaded in 0.63 s (71.23 MB/s)
74 05:27:24.031152 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:27:24.031963 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:27:24.032277 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:27:24.032546 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:27:24.033029 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 05:27:24.033309 saving as /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/dtb/meson-g12b-a311d-libretech-cc.dtb
81 05:27:24.033518 total size: 54703 (0 MB)
82 05:27:24.033727 No compression specified
83 05:27:24.067439 progress 59 % (0 MB)
84 05:27:24.068300 progress 100 % (0 MB)
85 05:27:24.068858 0 MB downloaded in 0.04 s (1.48 MB/s)
86 05:27:24.069319 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:27:24.070133 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:27:24.070396 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:27:24.070662 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:27:24.071139 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/modules.tar.xz
92 05:27:24.071389 saving as /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/modules/modules.tar
93 05:27:24.071594 total size: 11605712 (11 MB)
94 05:27:24.071805 Using unxz to decompress xz
95 05:27:24.108028 progress 0 % (0 MB)
96 05:27:24.176789 progress 5 % (0 MB)
97 05:27:24.255554 progress 10 % (1 MB)
98 05:27:24.342858 progress 15 % (1 MB)
99 05:27:24.420172 progress 20 % (2 MB)
100 05:27:24.503778 progress 25 % (2 MB)
101 05:27:24.583908 progress 30 % (3 MB)
102 05:27:24.659779 progress 35 % (3 MB)
103 05:27:24.738832 progress 40 % (4 MB)
104 05:27:24.816072 progress 45 % (5 MB)
105 05:27:24.893801 progress 50 % (5 MB)
106 05:27:24.964879 progress 55 % (6 MB)
107 05:27:25.049305 progress 60 % (6 MB)
108 05:27:25.134840 progress 65 % (7 MB)
109 05:27:25.212416 progress 70 % (7 MB)
110 05:27:25.309259 progress 75 % (8 MB)
111 05:27:25.405657 progress 80 % (8 MB)
112 05:27:25.488911 progress 85 % (9 MB)
113 05:27:25.560586 progress 90 % (9 MB)
114 05:27:25.638212 progress 95 % (10 MB)
115 05:27:25.715601 progress 100 % (11 MB)
116 05:27:25.726151 11 MB downloaded in 1.65 s (6.69 MB/s)
117 05:27:25.727222 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:27:25.729199 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:27:25.729847 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 05:27:25.730493 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 05:27:25.731098 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:27:25.731721 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 05:27:25.732937 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw
125 05:27:25.733945 makedir: /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin
126 05:27:25.734764 makedir: /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/tests
127 05:27:25.735574 makedir: /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/results
128 05:27:25.736375 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-add-keys
129 05:27:25.737734 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-add-sources
130 05:27:25.738980 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-background-process-start
131 05:27:25.740263 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-background-process-stop
132 05:27:25.741579 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-common-functions
133 05:27:25.742824 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-echo-ipv4
134 05:27:25.744035 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-install-packages
135 05:27:25.745269 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-installed-packages
136 05:27:25.746458 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-os-build
137 05:27:25.747692 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-probe-channel
138 05:27:25.748945 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-probe-ip
139 05:27:25.750159 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-target-ip
140 05:27:25.751337 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-target-mac
141 05:27:25.752542 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-target-storage
142 05:27:25.753786 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-test-case
143 05:27:25.754974 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-test-event
144 05:27:25.756201 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-test-feedback
145 05:27:25.757437 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-test-raise
146 05:27:25.758779 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-test-reference
147 05:27:25.760064 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-test-runner
148 05:27:25.761335 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-test-set
149 05:27:25.762522 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-test-shell
150 05:27:25.763706 Updating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-install-packages (oe)
151 05:27:25.765092 Updating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/bin/lava-installed-packages (oe)
152 05:27:25.766233 Creating /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/environment
153 05:27:25.767176 LAVA metadata
154 05:27:25.767789 - LAVA_JOB_ID=796581
155 05:27:25.768356 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:27:25.769188 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 05:27:25.771545 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:27:25.772337 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 05:27:25.772870 skipped lava-vland-overlay
160 05:27:25.773476 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:27:25.774114 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 05:27:25.774647 skipped lava-multinode-overlay
163 05:27:25.775255 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:27:25.775887 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 05:27:25.776526 Loading test definitions
166 05:27:25.777221 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 05:27:25.777765 Using /lava-796581 at stage 0
168 05:27:25.780470 uuid=796581_1.5.2.4.1 testdef=None
169 05:27:25.781225 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:27:25.781882 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 05:27:25.786385 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:27:25.788347 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 05:27:25.792817 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:27:25.793822 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 05:27:25.796675 runner path: /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/0/tests/0_dmesg test_uuid 796581_1.5.2.4.1
178 05:27:25.797432 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:27:25.798307 Creating lava-test-runner.conf files
181 05:27:25.798538 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796581/lava-overlay-cz719dcw/lava-796581/0 for stage 0
182 05:27:25.798960 - 0_dmesg
183 05:27:25.799375 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:27:25.799705 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 05:27:25.826565 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:27:25.826994 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:27:25.827308 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:27:25.827620 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:27:25.827927 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:27:26.782050 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:27:26.782493 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 05:27:26.782739 extracting modules file /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796581/extract-overlay-ramdisk-set_u836/ramdisk
193 05:27:28.144537 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 05:27:28.145012 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 05:27:28.145296 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796581/compress-overlay-q7xz5z12/overlay-1.5.2.5.tar.gz to ramdisk
196 05:27:28.145512 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796581/compress-overlay-q7xz5z12/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796581/extract-overlay-ramdisk-set_u836/ramdisk
197 05:27:28.175887 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:27:28.176360 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 05:27:28.176636 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 05:27:28.176870 Converting downloaded kernel to a uImage
201 05:27:28.177196 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/kernel/Image /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/kernel/uImage
202 05:27:28.695765 output: Image Name:
203 05:27:28.696219 output: Created: Thu Oct 3 05:27:28 2024
204 05:27:28.696434 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:27:28.696639 output: Data Size: 47391232 Bytes = 46280.50 KiB = 45.20 MiB
206 05:27:28.696839 output: Load Address: 01080000
207 05:27:28.697036 output: Entry Point: 01080000
208 05:27:28.697232 output:
209 05:27:28.697569 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 05:27:28.697833 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 05:27:28.698101 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 05:27:28.698353 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:27:28.698608 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 05:27:28.698864 Building ramdisk /var/lib/lava/dispatcher/tmp/796581/extract-overlay-ramdisk-set_u836/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796581/extract-overlay-ramdisk-set_u836/ramdisk
215 05:27:31.142979 >> 181738 blocks
216 05:27:39.574453 Adding RAMdisk u-boot header.
217 05:27:39.574919 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796581/extract-overlay-ramdisk-set_u836/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796581/extract-overlay-ramdisk-set_u836/ramdisk.cpio.gz.uboot
218 05:27:39.896661 output: Image Name:
219 05:27:39.897084 output: Created: Thu Oct 3 05:27:39 2024
220 05:27:39.897294 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:27:39.897499 output: Data Size: 26049621 Bytes = 25439.08 KiB = 24.84 MiB
222 05:27:39.897699 output: Load Address: 00000000
223 05:27:39.897898 output: Entry Point: 00000000
224 05:27:39.898094 output:
225 05:27:39.898789 rename /var/lib/lava/dispatcher/tmp/796581/extract-overlay-ramdisk-set_u836/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/ramdisk/ramdisk.cpio.gz.uboot
226 05:27:39.899211 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 05:27:39.899493 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 05:27:39.899763 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 05:27:39.900041 No LXC device requested
230 05:27:39.900556 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:27:39.901060 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 05:27:39.901548 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:27:39.901967 Checking files for TFTP limit of 4294967296 bytes.
234 05:27:39.904658 end: 1 tftp-deploy (duration 00:00:17) [common]
235 05:27:39.905241 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:27:39.905763 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:27:39.906257 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:27:39.906753 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:27:39.907276 Using kernel file from prepare-kernel: 796581/tftp-deploy-df2mtcuo/kernel/uImage
240 05:27:39.907876 substitutions:
241 05:27:39.908321 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:27:39.908723 - {DTB_ADDR}: 0x01070000
243 05:27:39.909122 - {DTB}: 796581/tftp-deploy-df2mtcuo/dtb/meson-g12b-a311d-libretech-cc.dtb
244 05:27:39.909519 - {INITRD}: 796581/tftp-deploy-df2mtcuo/ramdisk/ramdisk.cpio.gz.uboot
245 05:27:39.909913 - {KERNEL_ADDR}: 0x01080000
246 05:27:39.910305 - {KERNEL}: 796581/tftp-deploy-df2mtcuo/kernel/uImage
247 05:27:39.910698 - {LAVA_MAC}: None
248 05:27:39.911125 - {PRESEED_CONFIG}: None
249 05:27:39.911515 - {PRESEED_LOCAL}: None
250 05:27:39.911904 - {RAMDISK_ADDR}: 0x08000000
251 05:27:39.912320 - {RAMDISK}: 796581/tftp-deploy-df2mtcuo/ramdisk/ramdisk.cpio.gz.uboot
252 05:27:39.912715 - {ROOT_PART}: None
253 05:27:39.913102 - {ROOT}: None
254 05:27:39.913490 - {SERVER_IP}: 192.168.6.2
255 05:27:39.913880 - {TEE_ADDR}: 0x83000000
256 05:27:39.914268 - {TEE}: None
257 05:27:39.914654 Parsed boot commands:
258 05:27:39.915031 - setenv autoload no
259 05:27:39.915416 - setenv initrd_high 0xffffffff
260 05:27:39.915802 - setenv fdt_high 0xffffffff
261 05:27:39.916213 - dhcp
262 05:27:39.916599 - setenv serverip 192.168.6.2
263 05:27:39.916982 - tftpboot 0x01080000 796581/tftp-deploy-df2mtcuo/kernel/uImage
264 05:27:39.917368 - tftpboot 0x08000000 796581/tftp-deploy-df2mtcuo/ramdisk/ramdisk.cpio.gz.uboot
265 05:27:39.917752 - tftpboot 0x01070000 796581/tftp-deploy-df2mtcuo/dtb/meson-g12b-a311d-libretech-cc.dtb
266 05:27:39.918137 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:27:39.918528 - bootm 0x01080000 0x08000000 0x01070000
268 05:27:39.919025 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:27:39.920538 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:27:39.920980 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 05:27:39.935706 Setting prompt string to ['lava-test: # ']
273 05:27:39.937234 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:27:39.937826 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:27:39.938374 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:27:39.938902 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:27:39.940053 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 05:27:39.976306 >> OK - accepted request
279 05:27:39.978549 Returned 0 in 0 seconds
280 05:27:40.079642 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:27:40.081265 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:27:40.081813 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:27:40.082317 Setting prompt string to ['Hit any key to stop autoboot']
285 05:27:40.082763 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:27:40.084336 Trying 192.168.56.21...
287 05:27:40.084819 Connected to conserv1.
288 05:27:40.085221 Escape character is '^]'.
289 05:27:40.085631
290 05:27:40.086042 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 05:27:40.086473
292 05:27:51.311385 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 05:27:51.312067 bl2_stage_init 0x01
294 05:27:51.312499 bl2_stage_init 0x81
295 05:27:51.316905 hw id: 0x0000 - pwm id 0x01
296 05:27:51.317395 bl2_stage_init 0xc1
297 05:27:51.317816 bl2_stage_init 0x02
298 05:27:51.318222
299 05:27:51.322474 L0:00000000
300 05:27:51.322918 L1:20000703
301 05:27:51.323312 L2:00008067
302 05:27:51.323700 L3:14000000
303 05:27:51.328080 B2:00402000
304 05:27:51.328524 B1:e0f83180
305 05:27:51.328912
306 05:27:51.329304 TE: 58124
307 05:27:51.329693
308 05:27:51.333831 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 05:27:51.334294
310 05:27:51.334686 Board ID = 1
311 05:27:51.339276 Set A53 clk to 24M
312 05:27:51.339700 Set A73 clk to 24M
313 05:27:51.340118 Set clk81 to 24M
314 05:27:51.344852 A53 clk: 1200 MHz
315 05:27:51.345273 A73 clk: 1200 MHz
316 05:27:51.345661 CLK81: 166.6M
317 05:27:51.346044 smccc: 00012a92
318 05:27:51.350474 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 05:27:51.356064 board id: 1
320 05:27:51.361925 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:27:51.372657 fw parse done
322 05:27:51.378563 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:27:51.422096 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:27:51.432105 PIEI prepare done
325 05:27:51.432599 fastboot data load
326 05:27:51.432998 fastboot data verify
327 05:27:51.438189 verify result: 266
328 05:27:51.443328 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 05:27:51.443669 LPDDR4 probe
330 05:27:51.443953 ddr clk to 1584MHz
331 05:27:51.451332 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:27:51.488657
333 05:27:51.489133 dmc_version 0001
334 05:27:51.495278 Check phy result
335 05:27:51.501219 INFO : End of CA training
336 05:27:51.501612 INFO : End of initialization
337 05:27:51.506910 INFO : Training has run successfully!
338 05:27:51.507295 Check phy result
339 05:27:51.512433 INFO : End of initialization
340 05:27:51.512845 INFO : End of read enable training
341 05:27:51.518018 INFO : End of fine write leveling
342 05:27:51.523624 INFO : End of Write leveling coarse delay
343 05:27:51.524040 INFO : Training has run successfully!
344 05:27:51.524330 Check phy result
345 05:27:51.529371 INFO : End of initialization
346 05:27:51.529761 INFO : End of read dq deskew training
347 05:27:51.534969 INFO : End of MPR read delay center optimization
348 05:27:51.540451 INFO : End of write delay center optimization
349 05:27:51.546031 INFO : End of read delay center optimization
350 05:27:51.546517 INFO : End of max read latency training
351 05:27:51.551624 INFO : Training has run successfully!
352 05:27:51.552133 1D training succeed
353 05:27:51.560932 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:27:51.608449 Check phy result
355 05:27:51.608827 INFO : End of initialization
356 05:27:51.631115 INFO : End of 2D read delay Voltage center optimization
357 05:27:51.651372 INFO : End of 2D read delay Voltage center optimization
358 05:27:51.703351 INFO : End of 2D write delay Voltage center optimization
359 05:27:51.752710 INFO : End of 2D write delay Voltage center optimization
360 05:27:51.758281 INFO : Training has run successfully!
361 05:27:51.758773
362 05:27:51.759182 channel==0
363 05:27:51.763913 RxClkDly_Margin_A0==88 ps 9
364 05:27:51.764438 TxDqDly_Margin_A0==98 ps 10
365 05:27:51.769457 RxClkDly_Margin_A1==88 ps 9
366 05:27:51.769935 TxDqDly_Margin_A1==98 ps 10
367 05:27:51.770340 TrainedVREFDQ_A0==74
368 05:27:51.775045 TrainedVREFDQ_A1==74
369 05:27:51.775543 VrefDac_Margin_A0==25
370 05:27:51.775943 DeviceVref_Margin_A0==40
371 05:27:51.780676 VrefDac_Margin_A1==25
372 05:27:51.781174 DeviceVref_Margin_A1==40
373 05:27:51.781575
374 05:27:51.781972
375 05:27:51.786278 channel==1
376 05:27:51.786761 RxClkDly_Margin_A0==98 ps 10
377 05:27:51.787161 TxDqDly_Margin_A0==88 ps 9
378 05:27:51.791900 RxClkDly_Margin_A1==98 ps 10
379 05:27:51.792422 TxDqDly_Margin_A1==88 ps 9
380 05:27:51.797490 TrainedVREFDQ_A0==76
381 05:27:51.797980 TrainedVREFDQ_A1==77
382 05:27:51.798381 VrefDac_Margin_A0==23
383 05:27:51.803153 DeviceVref_Margin_A0==38
384 05:27:51.803632 VrefDac_Margin_A1==23
385 05:27:51.808673 DeviceVref_Margin_A1==37
386 05:27:51.809147
387 05:27:51.809551 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:27:51.809945
389 05:27:51.842243 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
390 05:27:51.842859 2D training succeed
391 05:27:51.847910 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:27:51.853492 auto size-- 65535DDR cs0 size: 2048MB
393 05:27:51.853998 DDR cs1 size: 2048MB
394 05:27:51.859105 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:27:51.859587 cs0 DataBus test pass
396 05:27:51.864546 cs1 DataBus test pass
397 05:27:51.864854 cs0 AddrBus test pass
398 05:27:51.865060 cs1 AddrBus test pass
399 05:27:51.865257
400 05:27:51.870107 100bdlr_step_size ps== 420
401 05:27:51.870382 result report
402 05:27:51.875732 boot times 0Enable ddr reg access
403 05:27:51.881047 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:27:51.894634 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 05:27:52.468352 0.0;M3 CHK:0;cm4_sp_mode 0
406 05:27:52.469000 MVN_1=0x00000000
407 05:27:52.473834 MVN_2=0x00000000
408 05:27:52.479635 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 05:27:52.480204 OPS=0x10
410 05:27:52.480678 ring efuse init
411 05:27:52.481173 chipver efuse init
412 05:27:52.485228 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 05:27:52.490784 [0.018961 Inits done]
414 05:27:52.491301 secure task start!
415 05:27:52.491745 high task start!
416 05:27:52.495347 low task start!
417 05:27:52.495834 run into bl31
418 05:27:52.502000 NOTICE: BL31: v1.3(release):4fc40b1
419 05:27:52.509848 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 05:27:52.510374 NOTICE: BL31: G12A normal boot!
421 05:27:52.535234 NOTICE: BL31: BL33 decompress pass
422 05:27:52.539977 ERROR: Error initializing runtime service opteed_fast
423 05:27:53.776228
424 05:27:53.776632
425 05:27:53.782215 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 05:27:53.782716
427 05:27:53.783182 Model: Libre Computer AML-A311D-CC Alta
428 05:27:53.990922 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 05:27:54.014230 DRAM: 2 GiB (effective 3.8 GiB)
430 05:27:54.157226 Core: 408 devices, 31 uclasses, devicetree: separate
431 05:27:54.162992 WDT: Not starting watchdog@f0d0
432 05:27:54.195204 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 05:27:54.207710 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 05:27:54.212644 ** Bad device specification mmc 0 **
435 05:27:54.222897 Card did not respond to voltage select! : -110
436 05:27:54.230691 ** Bad device specification mmc 0 **
437 05:27:54.231216 Couldn't find partition mmc 0
438 05:27:54.238969 Card did not respond to voltage select! : -110
439 05:27:54.244473 ** Bad device specification mmc 0 **
440 05:27:54.244956 Couldn't find partition mmc 0
441 05:27:54.249599 Error: could not access storage.
442 05:27:55.512469 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 05:27:55.513135 bl2_stage_init 0x81
444 05:27:55.518363 hw id: 0x0000 - pwm id 0x01
445 05:27:55.518877 bl2_stage_init 0xc1
446 05:27:55.519339 bl2_stage_init 0x02
447 05:27:55.519792
448 05:27:55.523573 L0:00000000
449 05:27:55.524103 L1:20000703
450 05:27:55.524560 L2:00008067
451 05:27:55.525004 L3:14000000
452 05:27:55.525447 B2:00402000
453 05:27:55.526349 B1:e0f83180
454 05:27:55.526835
455 05:27:55.527285 TE: 58150
456 05:27:55.527731
457 05:27:55.537745 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 05:27:55.538248
459 05:27:55.538706 Board ID = 1
460 05:27:55.539153 Set A53 clk to 24M
461 05:27:55.539598 Set A73 clk to 24M
462 05:27:55.543096 Set clk81 to 24M
463 05:27:55.543574 A53 clk: 1200 MHz
464 05:27:55.544058 A73 clk: 1200 MHz
465 05:27:55.546613 CLK81: 166.6M
466 05:27:55.547087 smccc: 00012aab
467 05:27:55.552382 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 05:27:55.557576 board id: 1
469 05:27:55.561841 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 05:27:55.573500 fw parse done
471 05:27:55.578317 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 05:27:55.621393 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 05:27:55.633016 PIEI prepare done
474 05:27:55.633494 fastboot data load
475 05:27:55.633945 fastboot data verify
476 05:27:55.638353 verify result: 266
477 05:27:55.643960 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 05:27:55.644483 LPDDR4 probe
479 05:27:55.644934 ddr clk to 1584MHz
480 05:27:55.652093 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 05:27:55.689462
482 05:27:55.689998 dmc_version 0001
483 05:27:55.695897 Check phy result
484 05:27:55.701815 INFO : End of CA training
485 05:27:55.702299 INFO : End of initialization
486 05:27:55.707476 INFO : Training has run successfully!
487 05:27:55.707960 Check phy result
488 05:27:55.712919 INFO : End of initialization
489 05:27:55.713413 INFO : End of read enable training
490 05:27:55.718520 INFO : End of fine write leveling
491 05:27:55.724296 INFO : End of Write leveling coarse delay
492 05:27:55.724773 INFO : Training has run successfully!
493 05:27:55.725217 Check phy result
494 05:27:55.729710 INFO : End of initialization
495 05:27:55.730190 INFO : End of read dq deskew training
496 05:27:55.735363 INFO : End of MPR read delay center optimization
497 05:27:55.741089 INFO : End of write delay center optimization
498 05:27:55.746538 INFO : End of read delay center optimization
499 05:27:55.747032 INFO : End of max read latency training
500 05:27:55.752136 INFO : Training has run successfully!
501 05:27:55.752614 1D training succeed
502 05:27:55.761308 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 05:27:55.809111 Check phy result
504 05:27:55.809604 INFO : End of initialization
505 05:27:55.830642 INFO : End of 2D read delay Voltage center optimization
506 05:27:55.851105 INFO : End of 2D read delay Voltage center optimization
507 05:27:55.903084 INFO : End of 2D write delay Voltage center optimization
508 05:27:55.952400 INFO : End of 2D write delay Voltage center optimization
509 05:27:55.957907 INFO : Training has run successfully!
510 05:27:55.958405
511 05:27:55.958870 channel==0
512 05:27:55.963521 RxClkDly_Margin_A0==88 ps 9
513 05:27:55.964053 TxDqDly_Margin_A0==98 ps 10
514 05:27:55.969120 RxClkDly_Margin_A1==88 ps 9
515 05:27:55.969617 TxDqDly_Margin_A1==98 ps 10
516 05:27:55.970073 TrainedVREFDQ_A0==74
517 05:27:55.974747 TrainedVREFDQ_A1==75
518 05:27:55.975244 VrefDac_Margin_A0==25
519 05:27:55.975691 DeviceVref_Margin_A0==40
520 05:27:55.980288 VrefDac_Margin_A1==24
521 05:27:55.980764 DeviceVref_Margin_A1==39
522 05:27:55.981209
523 05:27:55.981646
524 05:27:55.985874 channel==1
525 05:27:55.986344 RxClkDly_Margin_A0==98 ps 10
526 05:27:55.986785 TxDqDly_Margin_A0==88 ps 9
527 05:27:55.991529 RxClkDly_Margin_A1==98 ps 10
528 05:27:55.992036 TxDqDly_Margin_A1==88 ps 9
529 05:27:55.997069 TrainedVREFDQ_A0==76
530 05:27:55.997547 TrainedVREFDQ_A1==77
531 05:27:55.997999 VrefDac_Margin_A0==22
532 05:27:56.002716 DeviceVref_Margin_A0==38
533 05:27:56.003188 VrefDac_Margin_A1==24
534 05:27:56.008279 DeviceVref_Margin_A1==37
535 05:27:56.008765
536 05:27:56.009214 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 05:27:56.009654
538 05:27:56.041905 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
539 05:27:56.042439 2D training succeed
540 05:27:56.047509 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 05:27:56.053083 auto size-- 65535DDR cs0 size: 2048MB
542 05:27:56.053569 DDR cs1 size: 2048MB
543 05:27:56.058675 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 05:27:56.059159 cs0 DataBus test pass
545 05:27:56.064302 cs1 DataBus test pass
546 05:27:56.064778 cs0 AddrBus test pass
547 05:27:56.065225 cs1 AddrBus test pass
548 05:27:56.065665
549 05:27:56.069887 100bdlr_step_size ps== 420
550 05:27:56.070389 result report
551 05:27:56.075515 boot times 0Enable ddr reg access
552 05:27:56.080825 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 05:27:56.094310 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 05:27:56.668028 0.0;M3 CHK:0;cm4_sp_mode 0
555 05:27:56.668630 MVN_1=0x00000000
556 05:27:56.673509 MVN_2=0x00000000
557 05:27:56.679232 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 05:27:56.679753 OPS=0x10
559 05:27:56.680446 ring efuse init
560 05:27:56.680932 chipver efuse init
561 05:27:56.684817 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 05:27:56.690459 [0.018961 Inits done]
563 05:27:56.690943 secure task start!
564 05:27:56.691386 high task start!
565 05:27:56.695129 low task start!
566 05:27:56.695608 run into bl31
567 05:27:56.701651 NOTICE: BL31: v1.3(release):4fc40b1
568 05:27:56.709437 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 05:27:56.709927 NOTICE: BL31: G12A normal boot!
570 05:27:56.734835 NOTICE: BL31: BL33 decompress pass
571 05:27:56.740573 ERROR: Error initializing runtime service opteed_fast
572 05:27:57.973368
573 05:27:57.974029
574 05:27:57.981814 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 05:27:57.982331
576 05:27:57.982801 Model: Libre Computer AML-A311D-CC Alta
577 05:27:58.190206 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 05:27:58.213524 DRAM: 2 GiB (effective 3.8 GiB)
579 05:27:58.356525 Core: 408 devices, 31 uclasses, devicetree: separate
580 05:27:58.362375 WDT: Not starting watchdog@f0d0
581 05:27:58.394707 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 05:27:58.407092 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 05:27:58.412102 ** Bad device specification mmc 0 **
584 05:27:58.422415 Card did not respond to voltage select! : -110
585 05:27:58.430041 ** Bad device specification mmc 0 **
586 05:27:58.430543 Couldn't find partition mmc 0
587 05:27:58.438414 Card did not respond to voltage select! : -110
588 05:27:58.443899 ** Bad device specification mmc 0 **
589 05:27:58.444427 Couldn't find partition mmc 0
590 05:27:58.448956 Error: could not access storage.
591 05:27:58.791529 Net: eth0: ethernet@ff3f0000
592 05:27:58.792142 starting USB...
593 05:27:59.043265 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 05:27:59.043822 Starting the controller
595 05:27:59.050238 USB XHCI 1.10
596 05:28:00.762428 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 05:28:00.763130 bl2_stage_init 0x01
598 05:28:00.763626 bl2_stage_init 0x81
599 05:28:00.767803 hw id: 0x0000 - pwm id 0x01
600 05:28:00.768379 bl2_stage_init 0xc1
601 05:28:00.768850 bl2_stage_init 0x02
602 05:28:00.769307
603 05:28:00.773449 L0:00000000
604 05:28:00.773989 L1:20000703
605 05:28:00.774454 L2:00008067
606 05:28:00.774903 L3:14000000
607 05:28:00.779074 B2:00402000
608 05:28:00.779600 B1:e0f83180
609 05:28:00.780087
610 05:28:00.780546 TE: 58124
611 05:28:00.781003
612 05:28:00.784646 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 05:28:00.785185
614 05:28:00.785654 Board ID = 1
615 05:28:00.790310 Set A53 clk to 24M
616 05:28:00.790830 Set A73 clk to 24M
617 05:28:00.791293 Set clk81 to 24M
618 05:28:00.795777 A53 clk: 1200 MHz
619 05:28:00.796329 A73 clk: 1200 MHz
620 05:28:00.796786 CLK81: 166.6M
621 05:28:00.797235 smccc: 00012a92
622 05:28:00.801387 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 05:28:00.807032 board id: 1
624 05:28:00.813047 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 05:28:00.823549 fw parse done
626 05:28:00.829432 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 05:28:00.871917 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 05:28:00.882880 PIEI prepare done
629 05:28:00.883384 fastboot data load
630 05:28:00.883844 fastboot data verify
631 05:28:00.888480 verify result: 266
632 05:28:00.894119 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 05:28:00.894618 LPDDR4 probe
634 05:28:00.895071 ddr clk to 1584MHz
635 05:28:00.902117 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 05:28:00.939379
637 05:28:00.939880 dmc_version 0001
638 05:28:00.946082 Check phy result
639 05:28:00.951947 INFO : End of CA training
640 05:28:00.952461 INFO : End of initialization
641 05:28:00.957519 INFO : Training has run successfully!
642 05:28:00.958011 Check phy result
643 05:28:00.963128 INFO : End of initialization
644 05:28:00.963617 INFO : End of read enable training
645 05:28:00.966397 INFO : End of fine write leveling
646 05:28:00.972048 INFO : End of Write leveling coarse delay
647 05:28:00.977537 INFO : Training has run successfully!
648 05:28:00.978021 Check phy result
649 05:28:00.978472 INFO : End of initialization
650 05:28:00.983128 INFO : End of read dq deskew training
651 05:28:00.988762 INFO : End of MPR read delay center optimization
652 05:28:00.989247 INFO : End of write delay center optimization
653 05:28:00.994340 INFO : End of read delay center optimization
654 05:28:01.000020 INFO : End of max read latency training
655 05:28:01.000507 INFO : Training has run successfully!
656 05:28:01.005541 1D training succeed
657 05:28:01.011525 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 05:28:01.059036 Check phy result
659 05:28:01.059593 INFO : End of initialization
660 05:28:01.081664 INFO : End of 2D read delay Voltage center optimization
661 05:28:01.101931 INFO : End of 2D read delay Voltage center optimization
662 05:28:01.153965 INFO : End of 2D write delay Voltage center optimization
663 05:28:01.203311 INFO : End of 2D write delay Voltage center optimization
664 05:28:01.208903 INFO : Training has run successfully!
665 05:28:01.209407
666 05:28:01.209977 channel==0
667 05:28:01.214505 RxClkDly_Margin_A0==88 ps 9
668 05:28:01.215001 TxDqDly_Margin_A0==98 ps 10
669 05:28:01.220107 RxClkDly_Margin_A1==88 ps 9
670 05:28:01.220592 TxDqDly_Margin_A1==98 ps 10
671 05:28:01.221047 TrainedVREFDQ_A0==74
672 05:28:01.225683 TrainedVREFDQ_A1==74
673 05:28:01.226186 VrefDac_Margin_A0==25
674 05:28:01.226644 DeviceVref_Margin_A0==40
675 05:28:01.231288 VrefDac_Margin_A1==25
676 05:28:01.231779 DeviceVref_Margin_A1==40
677 05:28:01.232281
678 05:28:01.232733
679 05:28:01.237009 channel==1
680 05:28:01.237501 RxClkDly_Margin_A0==98 ps 10
681 05:28:01.237952 TxDqDly_Margin_A0==88 ps 9
682 05:28:01.242510 RxClkDly_Margin_A1==98 ps 10
683 05:28:01.242993 TxDqDly_Margin_A1==88 ps 9
684 05:28:01.248090 TrainedVREFDQ_A0==76
685 05:28:01.248588 TrainedVREFDQ_A1==77
686 05:28:01.249043 VrefDac_Margin_A0==22
687 05:28:01.253706 DeviceVref_Margin_A0==38
688 05:28:01.254197 VrefDac_Margin_A1==24
689 05:28:01.259318 DeviceVref_Margin_A1==37
690 05:28:01.259796
691 05:28:01.260284 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 05:28:01.260734
693 05:28:01.292920 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
694 05:28:01.293491 2D training succeed
695 05:28:01.298514 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 05:28:01.304113 auto size-- 65535DDR cs0 size: 2048MB
697 05:28:01.304605 DDR cs1 size: 2048MB
698 05:28:01.309700 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 05:28:01.310184 cs0 DataBus test pass
700 05:28:01.315300 cs1 DataBus test pass
701 05:28:01.315779 cs0 AddrBus test pass
702 05:28:01.316274 cs1 AddrBus test pass
703 05:28:01.316722
704 05:28:01.320890 100bdlr_step_size ps== 420
705 05:28:01.321383 result report
706 05:28:01.326491 boot times 0Enable ddr reg access
707 05:28:01.331838 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 05:28:01.345377 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 05:28:01.918949 0.0;M3 CHK:0;cm4_sp_mode 0
710 05:28:01.919573 MVN_1=0x00000000
711 05:28:01.924506 MVN_2=0x00000000
712 05:28:01.930374 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 05:28:01.930944 OPS=0x10
714 05:28:01.931387 ring efuse init
715 05:28:01.931822 chipver efuse init
716 05:28:01.935849 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 05:28:01.941453 [0.018961 Inits done]
718 05:28:01.941923 secure task start!
719 05:28:01.942352 high task start!
720 05:28:01.946016 low task start!
721 05:28:01.946479 run into bl31
722 05:28:01.952696 NOTICE: BL31: v1.3(release):4fc40b1
723 05:28:01.960474 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 05:28:01.960951 NOTICE: BL31: G12A normal boot!
725 05:28:01.985863 NOTICE: BL31: BL33 decompress pass
726 05:28:01.991546 ERROR: Error initializing runtime service opteed_fast
727 05:28:03.224469
728 05:28:03.225115
729 05:28:03.232760 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 05:28:03.233256
731 05:28:03.233715 Model: Libre Computer AML-A311D-CC Alta
732 05:28:03.441114 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 05:28:03.464606 DRAM: 2 GiB (effective 3.8 GiB)
734 05:28:03.607593 Core: 408 devices, 31 uclasses, devicetree: separate
735 05:28:03.613507 WDT: Not starting watchdog@f0d0
736 05:28:03.645675 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 05:28:03.658138 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 05:28:03.663114 ** Bad device specification mmc 0 **
739 05:28:03.673600 Card did not respond to voltage select! : -110
740 05:28:03.681143 ** Bad device specification mmc 0 **
741 05:28:03.681622 Couldn't find partition mmc 0
742 05:28:03.689698 Card did not respond to voltage select! : -110
743 05:28:03.695389 ** Bad device specification mmc 0 **
744 05:28:03.695888 Couldn't find partition mmc 0
745 05:28:03.700594 Error: could not access storage.
746 05:28:04.042468 Net: eth0: ethernet@ff3f0000
747 05:28:04.043044 starting USB...
748 05:28:04.294244 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 05:28:04.294804 Starting the controller
750 05:28:04.301239 USB XHCI 1.10
751 05:28:06.463736 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 05:28:06.464439 bl2_stage_init 0x01
753 05:28:06.464916 bl2_stage_init 0x81
754 05:28:06.469126 hw id: 0x0000 - pwm id 0x01
755 05:28:06.469619 bl2_stage_init 0xc1
756 05:28:06.470084 bl2_stage_init 0x02
757 05:28:06.470533
758 05:28:06.474772 L0:00000000
759 05:28:06.475264 L1:20000703
760 05:28:06.475718 L2:00008067
761 05:28:06.476199 L3:14000000
762 05:28:06.480369 B2:00402000
763 05:28:06.480848 B1:e0f83180
764 05:28:06.481295
765 05:28:06.481742 TE: 58124
766 05:28:06.482186
767 05:28:06.486013 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 05:28:06.486492
769 05:28:06.486946 Board ID = 1
770 05:28:06.491517 Set A53 clk to 24M
771 05:28:06.492028 Set A73 clk to 24M
772 05:28:06.492486 Set clk81 to 24M
773 05:28:06.497201 A53 clk: 1200 MHz
774 05:28:06.497710 A73 clk: 1200 MHz
775 05:28:06.498176 CLK81: 166.6M
776 05:28:06.498620 smccc: 00012a92
777 05:28:06.502722 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 05:28:06.508300 board id: 1
779 05:28:06.514347 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 05:28:06.525011 fw parse done
781 05:28:06.530970 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 05:28:06.573398 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 05:28:06.584282 PIEI prepare done
784 05:28:06.584758 fastboot data load
785 05:28:06.585215 fastboot data verify
786 05:28:06.589884 verify result: 266
787 05:28:06.595463 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 05:28:06.595958 LPDDR4 probe
789 05:28:06.596452 ddr clk to 1584MHz
790 05:28:06.603449 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 05:28:06.640745
792 05:28:06.641245 dmc_version 0001
793 05:28:06.647399 Check phy result
794 05:28:06.653267 INFO : End of CA training
795 05:28:06.653746 INFO : End of initialization
796 05:28:06.658892 INFO : Training has run successfully!
797 05:28:06.659363 Check phy result
798 05:28:06.664471 INFO : End of initialization
799 05:28:06.664967 INFO : End of read enable training
800 05:28:06.670060 INFO : End of fine write leveling
801 05:28:06.675642 INFO : End of Write leveling coarse delay
802 05:28:06.676147 INFO : Training has run successfully!
803 05:28:06.676597 Check phy result
804 05:28:06.681275 INFO : End of initialization
805 05:28:06.681797 INFO : End of read dq deskew training
806 05:28:06.686901 INFO : End of MPR read delay center optimization
807 05:28:06.692466 INFO : End of write delay center optimization
808 05:28:06.698057 INFO : End of read delay center optimization
809 05:28:06.698547 INFO : End of max read latency training
810 05:28:06.703658 INFO : Training has run successfully!
811 05:28:06.704169 1D training succeed
812 05:28:06.712969 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 05:28:06.760438 Check phy result
814 05:28:06.760941 INFO : End of initialization
815 05:28:06.782183 INFO : End of 2D read delay Voltage center optimization
816 05:28:06.802308 INFO : End of 2D read delay Voltage center optimization
817 05:28:06.854485 INFO : End of 2D write delay Voltage center optimization
818 05:28:06.903953 INFO : End of 2D write delay Voltage center optimization
819 05:28:06.909543 INFO : Training has run successfully!
820 05:28:06.910027
821 05:28:06.910483 channel==0
822 05:28:06.915053 RxClkDly_Margin_A0==88 ps 9
823 05:28:06.915532 TxDqDly_Margin_A0==98 ps 10
824 05:28:06.920610 RxClkDly_Margin_A1==88 ps 9
825 05:28:06.921092 TxDqDly_Margin_A1==98 ps 10
826 05:28:06.921564 TrainedVREFDQ_A0==74
827 05:28:06.926223 TrainedVREFDQ_A1==75
828 05:28:06.926772 VrefDac_Margin_A0==25
829 05:28:06.927230 DeviceVref_Margin_A0==40
830 05:28:06.931942 VrefDac_Margin_A1==25
831 05:28:06.932478 DeviceVref_Margin_A1==39
832 05:28:06.932912
833 05:28:06.933340
834 05:28:06.937417 channel==1
835 05:28:06.937884 RxClkDly_Margin_A0==88 ps 9
836 05:28:06.938315 TxDqDly_Margin_A0==98 ps 10
837 05:28:06.943022 RxClkDly_Margin_A1==98 ps 10
838 05:28:06.943502 TxDqDly_Margin_A1==88 ps 9
839 05:28:06.948625 TrainedVREFDQ_A0==77
840 05:28:06.949099 TrainedVREFDQ_A1==77
841 05:28:06.949532 VrefDac_Margin_A0==23
842 05:28:06.954222 DeviceVref_Margin_A0==37
843 05:28:06.954678 VrefDac_Margin_A1==23
844 05:28:06.959931 DeviceVref_Margin_A1==37
845 05:28:06.960423
846 05:28:06.960857 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 05:28:06.961282
848 05:28:06.993440 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
849 05:28:06.993981 2D training succeed
850 05:28:06.999033 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 05:28:07.004612 auto size-- 65535DDR cs0 size: 2048MB
852 05:28:07.005086 DDR cs1 size: 2048MB
853 05:28:07.010225 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 05:28:07.010708 cs0 DataBus test pass
855 05:28:07.015913 cs1 DataBus test pass
856 05:28:07.016410 cs0 AddrBus test pass
857 05:28:07.016843 cs1 AddrBus test pass
858 05:28:07.017273
859 05:28:07.021444 100bdlr_step_size ps== 420
860 05:28:07.021944 result report
861 05:28:07.027014 boot times 0Enable ddr reg access
862 05:28:07.032408 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 05:28:07.045872 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 05:28:07.619581 0.0;M3 CHK:0;cm4_sp_mode 0
865 05:28:07.620276 MVN_1=0x00000000
866 05:28:07.625083 MVN_2=0x00000000
867 05:28:07.630787 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 05:28:07.631275 OPS=0x10
869 05:28:07.631734 ring efuse init
870 05:28:07.632213 chipver efuse init
871 05:28:07.636321 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 05:28:07.642069 [0.018961 Inits done]
873 05:28:07.642563 secure task start!
874 05:28:07.643013 high task start!
875 05:28:07.646509 low task start!
876 05:28:07.646984 run into bl31
877 05:28:07.653193 NOTICE: BL31: v1.3(release):4fc40b1
878 05:28:07.661105 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 05:28:07.661593 NOTICE: BL31: G12A normal boot!
880 05:28:07.686418 NOTICE: BL31: BL33 decompress pass
881 05:28:07.692149 ERROR: Error initializing runtime service opteed_fast
882 05:28:08.924901
883 05:28:08.925553
884 05:28:08.933299 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 05:28:08.933799
886 05:28:08.934259 Model: Libre Computer AML-A311D-CC Alta
887 05:28:09.141813 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 05:28:09.165241 DRAM: 2 GiB (effective 3.8 GiB)
889 05:28:09.308159 Core: 408 devices, 31 uclasses, devicetree: separate
890 05:28:09.314048 WDT: Not starting watchdog@f0d0
891 05:28:09.346311 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 05:28:09.358714 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 05:28:09.363678 ** Bad device specification mmc 0 **
894 05:28:09.374111 Card did not respond to voltage select! : -110
895 05:28:09.381684 ** Bad device specification mmc 0 **
896 05:28:09.382178 Couldn't find partition mmc 0
897 05:28:09.390100 Card did not respond to voltage select! : -110
898 05:28:09.395548 ** Bad device specification mmc 0 **
899 05:28:09.396065 Couldn't find partition mmc 0
900 05:28:09.400600 Error: could not access storage.
901 05:28:09.744204 Net: eth0: ethernet@ff3f0000
902 05:28:09.744832 starting USB...
903 05:28:09.995912 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 05:28:09.996523 Starting the controller
905 05:28:10.002904 USB XHCI 1.10
906 05:28:11.863663 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 05:28:11.864361 bl2_stage_init 0x01
908 05:28:11.864842 bl2_stage_init 0x81
909 05:28:11.869132 hw id: 0x0000 - pwm id 0x01
910 05:28:11.869619 bl2_stage_init 0xc1
911 05:28:11.870075 bl2_stage_init 0x02
912 05:28:11.870525
913 05:28:11.874849 L0:00000000
914 05:28:11.875329 L1:20000703
915 05:28:11.875780 L2:00008067
916 05:28:11.876267 L3:14000000
917 05:28:11.877716 B2:00402000
918 05:28:11.878191 B1:e0f83180
919 05:28:11.878640
920 05:28:11.879085 TE: 58159
921 05:28:11.879529
922 05:28:11.888815 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 05:28:11.889320
924 05:28:11.889780 Board ID = 1
925 05:28:11.890220 Set A53 clk to 24M
926 05:28:11.890660 Set A73 clk to 24M
927 05:28:11.894352 Set clk81 to 24M
928 05:28:11.894885 A53 clk: 1200 MHz
929 05:28:11.895344 A73 clk: 1200 MHz
930 05:28:11.900127 CLK81: 166.6M
931 05:28:11.900602 smccc: 00012ab5
932 05:28:11.905790 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 05:28:11.906280 board id: 1
934 05:28:11.914385 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 05:28:11.925040 fw parse done
936 05:28:11.930964 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 05:28:11.973407 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 05:28:11.984256 PIEI prepare done
939 05:28:11.984748 fastboot data load
940 05:28:11.985189 fastboot data verify
941 05:28:11.989862 verify result: 266
942 05:28:11.995476 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 05:28:11.995939 LPDDR4 probe
944 05:28:11.996417 ddr clk to 1584MHz
945 05:28:12.003434 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 05:28:12.040851
947 05:28:12.041352 dmc_version 0001
948 05:28:12.047475 Check phy result
949 05:28:12.053262 INFO : End of CA training
950 05:28:12.053724 INFO : End of initialization
951 05:28:12.058842 INFO : Training has run successfully!
952 05:28:12.059300 Check phy result
953 05:28:12.064426 INFO : End of initialization
954 05:28:12.064935 INFO : End of read enable training
955 05:28:12.067777 INFO : End of fine write leveling
956 05:28:12.073320 INFO : End of Write leveling coarse delay
957 05:28:12.078950 INFO : Training has run successfully!
958 05:28:12.079419 Check phy result
959 05:28:12.079860 INFO : End of initialization
960 05:28:12.084509 INFO : End of read dq deskew training
961 05:28:12.087935 INFO : End of MPR read delay center optimization
962 05:28:12.093510 INFO : End of write delay center optimization
963 05:28:12.099046 INFO : End of read delay center optimization
964 05:28:12.099515 INFO : End of max read latency training
965 05:28:12.104673 INFO : Training has run successfully!
966 05:28:12.105143 1D training succeed
967 05:28:12.112856 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 05:28:12.160539 Check phy result
969 05:28:12.161022 INFO : End of initialization
970 05:28:12.183063 INFO : End of 2D read delay Voltage center optimization
971 05:28:12.203267 INFO : End of 2D read delay Voltage center optimization
972 05:28:12.255394 INFO : End of 2D write delay Voltage center optimization
973 05:28:12.304848 INFO : End of 2D write delay Voltage center optimization
974 05:28:12.310234 INFO : Training has run successfully!
975 05:28:12.310721
976 05:28:12.311175 channel==0
977 05:28:12.315889 RxClkDly_Margin_A0==88 ps 9
978 05:28:12.316402 TxDqDly_Margin_A0==98 ps 10
979 05:28:12.319278 RxClkDly_Margin_A1==88 ps 9
980 05:28:12.319743 TxDqDly_Margin_A1==98 ps 10
981 05:28:12.324814 TrainedVREFDQ_A0==74
982 05:28:12.325294 TrainedVREFDQ_A1==74
983 05:28:12.325743 VrefDac_Margin_A0==26
984 05:28:12.332032 DeviceVref_Margin_A0==40
985 05:28:12.332512 VrefDac_Margin_A1==25
986 05:28:12.336049 DeviceVref_Margin_A1==40
987 05:28:12.336522
988 05:28:12.336968
989 05:28:12.337410 channel==1
990 05:28:12.337844 RxClkDly_Margin_A0==98 ps 10
991 05:28:12.341725 TxDqDly_Margin_A0==98 ps 10
992 05:28:12.342204 RxClkDly_Margin_A1==98 ps 10
993 05:28:12.347113 TxDqDly_Margin_A1==88 ps 9
994 05:28:12.347598 TrainedVREFDQ_A0==77
995 05:28:12.348074 TrainedVREFDQ_A1==77
996 05:28:12.352839 VrefDac_Margin_A0==22
997 05:28:12.353306 DeviceVref_Margin_A0==37
998 05:28:12.358428 VrefDac_Margin_A1==22
999 05:28:12.358898 DeviceVref_Margin_A1==37
1000 05:28:12.359338
1001 05:28:12.364035 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 05:28:12.364507
1003 05:28:12.391878 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1004 05:28:12.397535 2D training succeed
1005 05:28:12.403072 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 05:28:12.403545 auto size-- 65535DDR cs0 size: 2048MB
1007 05:28:12.408710 DDR cs1 size: 2048MB
1008 05:28:12.409184 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 05:28:12.414301 cs0 DataBus test pass
1010 05:28:12.414771 cs1 DataBus test pass
1011 05:28:12.415215 cs0 AddrBus test pass
1012 05:28:12.419872 cs1 AddrBus test pass
1013 05:28:12.420368
1014 05:28:12.420817 100bdlr_step_size ps== 420
1015 05:28:12.421270 result report
1016 05:28:12.425603 boot times 0Enable ddr reg access
1017 05:28:12.433220 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 05:28:12.446738 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 05:28:13.020588 0.0;M3 CHK:0;cm4_sp_mode 0
1020 05:28:13.021250 MVN_1=0x00000000
1021 05:28:13.025973 MVN_2=0x00000000
1022 05:28:13.031763 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 05:28:13.032286 OPS=0x10
1024 05:28:13.032743 ring efuse init
1025 05:28:13.033184 chipver efuse init
1026 05:28:13.040044 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 05:28:13.040563 [0.018960 Inits done]
1028 05:28:13.041013 secure task start!
1029 05:28:13.047472 high task start!
1030 05:28:13.047945 low task start!
1031 05:28:13.048429 run into bl31
1032 05:28:13.054134 NOTICE: BL31: v1.3(release):4fc40b1
1033 05:28:13.061946 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 05:28:13.062439 NOTICE: BL31: G12A normal boot!
1035 05:28:13.087438 NOTICE: BL31: BL33 decompress pass
1036 05:28:13.093096 ERROR: Error initializing runtime service opteed_fast
1037 05:28:14.326032
1038 05:28:14.326690
1039 05:28:14.334948 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 05:28:14.335444
1041 05:28:14.335907 Model: Libre Computer AML-A311D-CC Alta
1042 05:28:14.542786 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 05:28:14.566142 DRAM: 2 GiB (effective 3.8 GiB)
1044 05:28:14.709168 Core: 408 devices, 31 uclasses, devicetree: separate
1045 05:28:14.714926 WDT: Not starting watchdog@f0d0
1046 05:28:14.747221 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 05:28:14.759662 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 05:28:14.764644 ** Bad device specification mmc 0 **
1049 05:28:14.775005 Card did not respond to voltage select! : -110
1050 05:28:14.782613 ** Bad device specification mmc 0 **
1051 05:28:14.783092 Couldn't find partition mmc 0
1052 05:28:14.790979 Card did not respond to voltage select! : -110
1053 05:28:14.796482 ** Bad device specification mmc 0 **
1054 05:28:14.796961 Couldn't find partition mmc 0
1055 05:28:14.801514 Error: could not access storage.
1056 05:28:15.145289 Net: eth0: ethernet@ff3f0000
1057 05:28:15.145925 starting USB...
1058 05:28:15.396917 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 05:28:15.397565 Starting the controller
1060 05:28:15.403810 USB XHCI 1.10
1061 05:28:16.957733 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 05:28:16.965106 scanning usb for storage devices... 0 Storage Device(s) found
1064 05:28:17.016917 Hit any key to stop autoboot: 1
1065 05:28:17.017801 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 05:28:17.018425 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 05:28:17.018928 Setting prompt string to ['=>']
1068 05:28:17.019436 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 05:28:17.022416 0
1070 05:28:17.023325 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 05:28:17.023853 Sending with 10 millisecond of delay
1073 05:28:18.159026 => setenv autoload no
1074 05:28:18.169844 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 05:28:18.175180 setenv autoload no
1076 05:28:18.176022 Sending with 10 millisecond of delay
1078 05:28:19.972874 => setenv initrd_high 0xffffffff
1079 05:28:19.983572 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 05:28:19.984148 setenv initrd_high 0xffffffff
1081 05:28:19.984643 Sending with 10 millisecond of delay
1083 05:28:21.600823 => setenv fdt_high 0xffffffff
1084 05:28:21.611638 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 05:28:21.612568 setenv fdt_high 0xffffffff
1086 05:28:21.613338 Sending with 10 millisecond of delay
1088 05:28:21.905221 => dhcp
1089 05:28:21.915952 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 05:28:21.916844 dhcp
1091 05:28:21.917323 Speed: 1000, full duplex
1092 05:28:21.917782 BOOTP broadcast 1
1093 05:28:22.164322 BOOTP broadcast 2
1094 05:28:22.306840 DHCP client bound to address 192.168.6.33 (391 ms)
1095 05:28:22.307765 Sending with 10 millisecond of delay
1097 05:28:23.984281 => setenv serverip 192.168.6.2
1098 05:28:23.995082 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 05:28:23.995953 setenv serverip 192.168.6.2
1100 05:28:23.996744 Sending with 10 millisecond of delay
1102 05:28:27.720865 => tftpboot 0x01080000 796581/tftp-deploy-df2mtcuo/kernel/uImage
1103 05:28:27.731668 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 05:28:27.732619 tftpboot 0x01080000 796581/tftp-deploy-df2mtcuo/kernel/uImage
1105 05:28:27.733089 Speed: 1000, full duplex
1106 05:28:27.733527 Using ethernet@ff3f0000 device
1107 05:28:27.734284 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1108 05:28:27.739962 Filename '796581/tftp-deploy-df2mtcuo/kernel/uImage'.
1109 05:28:27.744025 Load address: 0x1080000
1110 05:28:31.312105 Loading: *################################################## 45.2 MiB
1111 05:28:31.312547 12.7 MiB/s
1112 05:28:31.312771 done
1113 05:28:31.316423 Bytes transferred = 47391296 (2d32240 hex)
1114 05:28:31.317045 Sending with 10 millisecond of delay
1116 05:28:36.002713 => tftpboot 0x08000000 796581/tftp-deploy-df2mtcuo/ramdisk/ramdisk.cpio.gz.uboot
1117 05:28:36.013847 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1118 05:28:36.014589 tftpboot 0x08000000 796581/tftp-deploy-df2mtcuo/ramdisk/ramdisk.cpio.gz.uboot
1119 05:28:36.014961 Speed: 1000, full duplex
1120 05:28:36.015287 Using ethernet@ff3f0000 device
1121 05:28:36.016479 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1122 05:28:36.024969 Filename '796581/tftp-deploy-df2mtcuo/ramdisk/ramdisk.cpio.gz.uboot'.
1123 05:28:36.025374 Load address: 0x8000000
1124 05:28:43.104750 Loading: *T ################################################# UDP wrong checksum 00000005 0000243d
1125 05:28:48.106671 T UDP wrong checksum 00000005 0000243d
1126 05:28:58.108932 T T UDP wrong checksum 00000005 0000243d
1127 05:29:18.112667 T T T T UDP wrong checksum 00000005 0000243d
1128 05:29:33.116178 T T
1129 05:29:33.116599 Retry count exceeded; starting again
1131 05:29:33.119562 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1134 05:29:33.120662 end: 2.4 uboot-commands (duration 00:01:53) [common]
1136 05:29:33.121421 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1138 05:29:33.122060 end: 2 uboot-action (duration 00:01:53) [common]
1140 05:29:33.122939 Cleaning after the job
1141 05:29:33.123264 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/ramdisk
1142 05:29:33.124265 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/kernel
1143 05:29:33.152635 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/dtb
1144 05:29:33.153500 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796581/tftp-deploy-df2mtcuo/modules
1145 05:29:33.173604 start: 4.1 power-off (timeout 00:00:30) [common]
1146 05:29:33.174259 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1147 05:29:33.207003 >> OK - accepted request
1148 05:29:33.209097 Returned 0 in 0 seconds
1149 05:29:33.309792 end: 4.1 power-off (duration 00:00:00) [common]
1151 05:29:33.310729 start: 4.2 read-feedback (timeout 00:10:00) [common]
1152 05:29:33.311381 Listened to connection for namespace 'common' for up to 1s
1153 05:29:34.312203 Finalising connection for namespace 'common'
1154 05:29:34.312699 Disconnecting from shell: Finalise
1155 05:29:34.312985 =>
1156 05:29:34.413663 end: 4.2 read-feedback (duration 00:00:01) [common]
1157 05:29:34.414101 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796581
1158 05:29:34.722052 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796581
1159 05:29:34.722645 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.