Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:43:54.539304 lava-dispatcher, installed at version: 2024.01
2 05:43:54.540144 start: 0 validate
3 05:43:54.540636 Start time: 2024-10-03 05:43:54.540605+00:00 (UTC)
4 05:43:54.541172 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:43:54.541724 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:43:54.590651 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:43:54.591227 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 05:43:54.620734 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:43:54.621366 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:43:55.663862 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:43:55.664435 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 05:43:55.706284 validate duration: 1.17
14 05:43:55.707776 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:43:55.708442 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:43:55.709021 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:43:55.710037 Not decompressing ramdisk as can be used compressed.
18 05:43:55.710858 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:43:55.711373 saving as /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/ramdisk/rootfs.cpio.gz
20 05:43:55.711911 total size: 8181887 (7 MB)
21 05:43:55.750670 progress 0 % (0 MB)
22 05:43:55.760963 progress 5 % (0 MB)
23 05:43:55.771566 progress 10 % (0 MB)
24 05:43:55.783368 progress 15 % (1 MB)
25 05:43:55.789633 progress 20 % (1 MB)
26 05:43:55.795598 progress 25 % (1 MB)
27 05:43:55.800962 progress 30 % (2 MB)
28 05:43:55.806797 progress 35 % (2 MB)
29 05:43:55.812248 progress 40 % (3 MB)
30 05:43:55.818004 progress 45 % (3 MB)
31 05:43:55.823581 progress 50 % (3 MB)
32 05:43:55.829342 progress 55 % (4 MB)
33 05:43:55.834751 progress 60 % (4 MB)
34 05:43:55.840592 progress 65 % (5 MB)
35 05:43:55.845977 progress 70 % (5 MB)
36 05:43:55.851999 progress 75 % (5 MB)
37 05:43:55.857379 progress 80 % (6 MB)
38 05:43:55.863147 progress 85 % (6 MB)
39 05:43:55.868565 progress 90 % (7 MB)
40 05:43:55.874307 progress 95 % (7 MB)
41 05:43:55.879347 progress 100 % (7 MB)
42 05:43:55.880027 7 MB downloaded in 0.17 s (46.42 MB/s)
43 05:43:55.880611 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:43:55.881535 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:43:55.881846 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:43:55.882136 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:43:55.882642 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
49 05:43:55.882901 saving as /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/kernel/Image
50 05:43:55.883119 total size: 45713920 (43 MB)
51 05:43:55.883338 No compression specified
52 05:43:55.922893 progress 0 % (0 MB)
53 05:43:55.953160 progress 5 % (2 MB)
54 05:43:55.983407 progress 10 % (4 MB)
55 05:43:56.013295 progress 15 % (6 MB)
56 05:43:56.043258 progress 20 % (8 MB)
57 05:43:56.072667 progress 25 % (10 MB)
58 05:43:56.102064 progress 30 % (13 MB)
59 05:43:56.131409 progress 35 % (15 MB)
60 05:43:56.161379 progress 40 % (17 MB)
61 05:43:56.190233 progress 45 % (19 MB)
62 05:43:56.219418 progress 50 % (21 MB)
63 05:43:56.248712 progress 55 % (24 MB)
64 05:43:56.278064 progress 60 % (26 MB)
65 05:43:56.306914 progress 65 % (28 MB)
66 05:43:56.336367 progress 70 % (30 MB)
67 05:43:56.365606 progress 75 % (32 MB)
68 05:43:56.395000 progress 80 % (34 MB)
69 05:43:56.423896 progress 85 % (37 MB)
70 05:43:56.453036 progress 90 % (39 MB)
71 05:43:56.482199 progress 95 % (41 MB)
72 05:43:56.510979 progress 100 % (43 MB)
73 05:43:56.511523 43 MB downloaded in 0.63 s (69.38 MB/s)
74 05:43:56.512058 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:43:56.512919 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:43:56.513207 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:43:56.513484 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:43:56.513974 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 05:43:56.514252 saving as /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/dtb/meson-g12b-a311d-libretech-cc.dtb
81 05:43:56.514471 total size: 54703 (0 MB)
82 05:43:56.514687 No compression specified
83 05:43:56.558249 progress 59 % (0 MB)
84 05:43:56.559120 progress 100 % (0 MB)
85 05:43:56.559684 0 MB downloaded in 0.05 s (1.15 MB/s)
86 05:43:56.560198 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:43:56.561063 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:43:56.561342 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:43:56.561617 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:43:56.562099 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
92 05:43:56.562351 saving as /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/modules/modules.tar
93 05:43:56.562567 total size: 11621592 (11 MB)
94 05:43:56.562789 Using unxz to decompress xz
95 05:43:56.594184 progress 0 % (0 MB)
96 05:43:56.662990 progress 5 % (0 MB)
97 05:43:56.741045 progress 10 % (1 MB)
98 05:43:56.828920 progress 15 % (1 MB)
99 05:43:56.905969 progress 20 % (2 MB)
100 05:43:56.989030 progress 25 % (2 MB)
101 05:43:57.070653 progress 30 % (3 MB)
102 05:43:57.158868 progress 35 % (3 MB)
103 05:43:57.233207 progress 40 % (4 MB)
104 05:43:57.309864 progress 45 % (5 MB)
105 05:43:57.387774 progress 50 % (5 MB)
106 05:43:57.464497 progress 55 % (6 MB)
107 05:43:57.544715 progress 60 % (6 MB)
108 05:43:57.630971 progress 65 % (7 MB)
109 05:43:57.714060 progress 70 % (7 MB)
110 05:43:57.807498 progress 75 % (8 MB)
111 05:43:57.903461 progress 80 % (8 MB)
112 05:43:57.985629 progress 85 % (9 MB)
113 05:43:58.062102 progress 90 % (10 MB)
114 05:43:58.135201 progress 95 % (10 MB)
115 05:43:58.212295 progress 100 % (11 MB)
116 05:43:58.225185 11 MB downloaded in 1.66 s (6.67 MB/s)
117 05:43:58.225818 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:43:58.226647 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:43:58.226922 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 05:43:58.227192 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 05:43:58.227442 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:43:58.227696 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 05:43:58.228537 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0
125 05:43:58.229506 makedir: /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin
126 05:43:58.230171 makedir: /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/tests
127 05:43:58.230790 makedir: /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/results
128 05:43:58.231406 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-add-keys
129 05:43:58.232416 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-add-sources
130 05:43:58.233372 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-background-process-start
131 05:43:58.234320 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-background-process-stop
132 05:43:58.235315 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-common-functions
133 05:43:58.236279 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-echo-ipv4
134 05:43:58.237235 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-install-packages
135 05:43:58.238150 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-installed-packages
136 05:43:58.239090 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-os-build
137 05:43:58.240050 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-probe-channel
138 05:43:58.240989 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-probe-ip
139 05:43:58.241895 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-target-ip
140 05:43:58.242792 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-target-mac
141 05:43:58.243801 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-target-storage
142 05:43:58.244796 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-test-case
143 05:43:58.245714 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-test-event
144 05:43:58.246617 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-test-feedback
145 05:43:58.247513 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-test-raise
146 05:43:58.248448 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-test-reference
147 05:43:58.249370 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-test-runner
148 05:43:58.250278 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-test-set
149 05:43:58.251214 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-test-shell
150 05:43:58.252221 Updating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-install-packages (oe)
151 05:43:58.253242 Updating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/bin/lava-installed-packages (oe)
152 05:43:58.254083 Creating /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/environment
153 05:43:58.254811 LAVA metadata
154 05:43:58.255303 - LAVA_JOB_ID=796781
155 05:43:58.255732 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:43:58.256446 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 05:43:58.258295 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:43:58.258910 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 05:43:58.259319 skipped lava-vland-overlay
160 05:43:58.259807 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:43:58.260412 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 05:43:58.260846 skipped lava-multinode-overlay
163 05:43:58.261328 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:43:58.261828 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 05:43:58.262306 Loading test definitions
166 05:43:58.262850 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 05:43:58.263288 Using /lava-796781 at stage 0
168 05:43:58.264944 uuid=796781_1.5.2.4.1 testdef=None
169 05:43:58.265308 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:43:58.265585 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 05:43:58.267431 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:43:58.268308 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 05:43:58.270637 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:43:58.271501 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 05:43:58.273793 runner path: /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/0/tests/0_dmesg test_uuid 796781_1.5.2.4.1
178 05:43:58.274403 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:43:58.275202 Creating lava-test-runner.conf files
181 05:43:58.275407 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796781/lava-overlay-smrk9xd0/lava-796781/0 for stage 0
182 05:43:58.275754 - 0_dmesg
183 05:43:58.276163 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:43:58.276482 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 05:43:58.300996 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:43:58.301443 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:43:58.301715 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:43:58.301987 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:43:58.302253 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:43:59.231101 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:43:59.231628 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 05:43:59.232214 extracting modules file /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796781/extract-overlay-ramdisk-mdmuvj65/ramdisk
193 05:44:00.622760 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 05:44:00.623254 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 05:44:00.623545 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796781/compress-overlay-xhno00qk/overlay-1.5.2.5.tar.gz to ramdisk
196 05:44:00.623776 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796781/compress-overlay-xhno00qk/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796781/extract-overlay-ramdisk-mdmuvj65/ramdisk
197 05:44:00.654617 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:44:00.655028 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 05:44:00.655293 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 05:44:00.655522 Converting downloaded kernel to a uImage
201 05:44:00.655823 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/kernel/Image /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/kernel/uImage
202 05:44:01.106039 output: Image Name:
203 05:44:01.106462 output: Created: Thu Oct 3 05:44:00 2024
204 05:44:01.106678 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:44:01.106883 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 05:44:01.107085 output: Load Address: 01080000
207 05:44:01.107285 output: Entry Point: 01080000
208 05:44:01.107483 output:
209 05:44:01.107813 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 05:44:01.108124 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 05:44:01.108398 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 05:44:01.108650 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:44:01.108902 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 05:44:01.109155 Building ramdisk /var/lib/lava/dispatcher/tmp/796781/extract-overlay-ramdisk-mdmuvj65/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796781/extract-overlay-ramdisk-mdmuvj65/ramdisk
215 05:44:03.539167 >> 181716 blocks
216 05:44:12.046720 Adding RAMdisk u-boot header.
217 05:44:12.047204 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796781/extract-overlay-ramdisk-mdmuvj65/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796781/extract-overlay-ramdisk-mdmuvj65/ramdisk.cpio.gz.uboot
218 05:44:12.333395 output: Image Name:
219 05:44:12.333834 output: Created: Thu Oct 3 05:44:12 2024
220 05:44:12.334044 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:44:12.334251 output: Data Size: 26069143 Bytes = 25458.15 KiB = 24.86 MiB
222 05:44:12.334450 output: Load Address: 00000000
223 05:44:12.334648 output: Entry Point: 00000000
224 05:44:12.334843 output:
225 05:44:12.335569 rename /var/lib/lava/dispatcher/tmp/796781/extract-overlay-ramdisk-mdmuvj65/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/ramdisk/ramdisk.cpio.gz.uboot
226 05:44:12.336149 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 05:44:12.336801 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 05:44:12.337458 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 05:44:12.337990 No LXC device requested
230 05:44:12.338569 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:44:12.339135 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 05:44:12.339678 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:44:12.340171 Checking files for TFTP limit of 4294967296 bytes.
234 05:44:12.343151 end: 1 tftp-deploy (duration 00:00:17) [common]
235 05:44:12.343814 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:44:12.344444 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:44:12.345003 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:44:12.345552 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:44:12.346136 Using kernel file from prepare-kernel: 796781/tftp-deploy-lr2clkzu/kernel/uImage
240 05:44:12.346803 substitutions:
241 05:44:12.347254 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:44:12.347697 - {DTB_ADDR}: 0x01070000
243 05:44:12.348172 - {DTB}: 796781/tftp-deploy-lr2clkzu/dtb/meson-g12b-a311d-libretech-cc.dtb
244 05:44:12.348615 - {INITRD}: 796781/tftp-deploy-lr2clkzu/ramdisk/ramdisk.cpio.gz.uboot
245 05:44:12.349051 - {KERNEL_ADDR}: 0x01080000
246 05:44:12.349482 - {KERNEL}: 796781/tftp-deploy-lr2clkzu/kernel/uImage
247 05:44:12.349916 - {LAVA_MAC}: None
248 05:44:12.350394 - {PRESEED_CONFIG}: None
249 05:44:12.350830 - {PRESEED_LOCAL}: None
250 05:44:12.351264 - {RAMDISK_ADDR}: 0x08000000
251 05:44:12.351694 - {RAMDISK}: 796781/tftp-deploy-lr2clkzu/ramdisk/ramdisk.cpio.gz.uboot
252 05:44:12.352161 - {ROOT_PART}: None
253 05:44:12.352597 - {ROOT}: None
254 05:44:12.353031 - {SERVER_IP}: 192.168.6.2
255 05:44:12.353467 - {TEE_ADDR}: 0x83000000
256 05:44:12.353900 - {TEE}: None
257 05:44:12.354333 Parsed boot commands:
258 05:44:12.354752 - setenv autoload no
259 05:44:12.355181 - setenv initrd_high 0xffffffff
260 05:44:12.355608 - setenv fdt_high 0xffffffff
261 05:44:12.356063 - dhcp
262 05:44:12.356495 - setenv serverip 192.168.6.2
263 05:44:12.356921 - tftpboot 0x01080000 796781/tftp-deploy-lr2clkzu/kernel/uImage
264 05:44:12.357350 - tftpboot 0x08000000 796781/tftp-deploy-lr2clkzu/ramdisk/ramdisk.cpio.gz.uboot
265 05:44:12.357778 - tftpboot 0x01070000 796781/tftp-deploy-lr2clkzu/dtb/meson-g12b-a311d-libretech-cc.dtb
266 05:44:12.358207 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:44:12.358644 - bootm 0x01080000 0x08000000 0x01070000
268 05:44:12.359201 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:44:12.360885 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:44:12.361420 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 05:44:12.378087 Setting prompt string to ['lava-test: # ']
273 05:44:12.379776 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:44:12.380494 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:44:12.381101 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:44:12.381696 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:44:12.382975 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 05:44:12.417854 >> OK - accepted request
279 05:44:12.420186 Returned 0 in 0 seconds
280 05:44:12.521618 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:44:12.523571 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:44:12.524332 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:44:12.524786 Setting prompt string to ['Hit any key to stop autoboot']
285 05:44:12.525064 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:44:12.526029 Trying 192.168.56.21...
287 05:44:12.526318 Connected to conserv1.
288 05:44:12.526541 Escape character is '^]'.
289 05:44:12.526776
290 05:44:12.527002 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 05:44:12.527224
292 05:44:23.828811 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 05:44:23.829507 bl2_stage_init 0x01
294 05:44:23.829972 bl2_stage_init 0x81
295 05:44:23.834347 hw id: 0x0000 - pwm id 0x01
296 05:44:23.834925 bl2_stage_init 0xc1
297 05:44:23.835386 bl2_stage_init 0x02
298 05:44:23.835831
299 05:44:23.839886 L0:00000000
300 05:44:23.840392 L1:20000703
301 05:44:23.840826 L2:00008067
302 05:44:23.841253 L3:14000000
303 05:44:23.845318 B2:00402000
304 05:44:23.845785 B1:e0f83180
305 05:44:23.846215
306 05:44:23.846646 TE: 58159
307 05:44:23.847071
308 05:44:23.851067 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 05:44:23.851535
310 05:44:23.851964 Board ID = 1
311 05:44:23.856615 Set A53 clk to 24M
312 05:44:23.857080 Set A73 clk to 24M
313 05:44:23.857507 Set clk81 to 24M
314 05:44:23.862171 A53 clk: 1200 MHz
315 05:44:23.862628 A73 clk: 1200 MHz
316 05:44:23.863058 CLK81: 166.6M
317 05:44:23.863486 smccc: 00012ab4
318 05:44:23.868064 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 05:44:23.873580 board id: 1
320 05:44:23.879269 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:44:23.890053 fw parse done
322 05:44:23.896081 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:44:23.938612 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:44:23.949437 PIEI prepare done
325 05:44:23.949895 fastboot data load
326 05:44:23.950332 fastboot data verify
327 05:44:23.955016 verify result: 266
328 05:44:23.960603 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 05:44:23.961122 LPDDR4 probe
330 05:44:23.961586 ddr clk to 1584MHz
331 05:44:23.967642 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:44:24.005894
333 05:44:24.006390 dmc_version 0001
334 05:44:24.012546 Check phy result
335 05:44:24.018439 INFO : End of CA training
336 05:44:24.018919 INFO : End of initialization
337 05:44:24.024071 INFO : Training has run successfully!
338 05:44:24.024544 Check phy result
339 05:44:24.029675 INFO : End of initialization
340 05:44:24.030199 INFO : End of read enable training
341 05:44:24.035261 INFO : End of fine write leveling
342 05:44:24.041043 INFO : End of Write leveling coarse delay
343 05:44:24.041514 INFO : Training has run successfully!
344 05:44:24.041960 Check phy result
345 05:44:24.046333 INFO : End of initialization
346 05:44:24.046799 INFO : End of read dq deskew training
347 05:44:24.052082 INFO : End of MPR read delay center optimization
348 05:44:24.057616 INFO : End of write delay center optimization
349 05:44:24.063333 INFO : End of read delay center optimization
350 05:44:24.063808 INFO : End of max read latency training
351 05:44:24.069027 INFO : Training has run successfully!
352 05:44:24.069545 1D training succeed
353 05:44:24.078061 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:44:24.125633 Check phy result
355 05:44:24.126214 INFO : End of initialization
356 05:44:24.147217 INFO : End of 2D read delay Voltage center optimization
357 05:44:24.167645 INFO : End of 2D read delay Voltage center optimization
358 05:44:24.219656 INFO : End of 2D write delay Voltage center optimization
359 05:44:24.269168 INFO : End of 2D write delay Voltage center optimization
360 05:44:24.274721 INFO : Training has run successfully!
361 05:44:24.275200
362 05:44:24.275651 channel==0
363 05:44:24.280223 RxClkDly_Margin_A0==88 ps 9
364 05:44:24.280713 TxDqDly_Margin_A0==98 ps 10
365 05:44:24.283522 RxClkDly_Margin_A1==88 ps 9
366 05:44:24.284012 TxDqDly_Margin_A1==98 ps 10
367 05:44:24.289072 TrainedVREFDQ_A0==74
368 05:44:24.289559 TrainedVREFDQ_A1==74
369 05:44:24.294668 VrefDac_Margin_A0==24
370 05:44:24.295134 DeviceVref_Margin_A0==40
371 05:44:24.295575 VrefDac_Margin_A1==24
372 05:44:24.300264 DeviceVref_Margin_A1==40
373 05:44:24.300738
374 05:44:24.301186
375 05:44:24.301630 channel==1
376 05:44:24.302068 RxClkDly_Margin_A0==88 ps 9
377 05:44:24.303661 TxDqDly_Margin_A0==98 ps 10
378 05:44:24.309348 RxClkDly_Margin_A1==88 ps 9
379 05:44:24.309820 TxDqDly_Margin_A1==88 ps 9
380 05:44:24.310270 TrainedVREFDQ_A0==77
381 05:44:24.315096 TrainedVREFDQ_A1==77
382 05:44:24.315573 VrefDac_Margin_A0==23
383 05:44:24.320627 DeviceVref_Margin_A0==37
384 05:44:24.321099 VrefDac_Margin_A1==23
385 05:44:24.321541 DeviceVref_Margin_A1==37
386 05:44:24.321973
387 05:44:24.326087 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:44:24.326559
389 05:44:24.359715 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000017 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 05:44:24.360301 2D training succeed
391 05:44:24.365434 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:44:24.371087 auto size-- 65535DDR cs0 size: 2048MB
393 05:44:24.371557 DDR cs1 size: 2048MB
394 05:44:24.376493 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:44:24.376967 cs0 DataBus test pass
396 05:44:24.377414 cs1 DataBus test pass
397 05:44:24.382120 cs0 AddrBus test pass
398 05:44:24.382584 cs1 AddrBus test pass
399 05:44:24.383026
400 05:44:24.387657 100bdlr_step_size ps== 420
401 05:44:24.388175 result report
402 05:44:24.388625 boot times 0Enable ddr reg access
403 05:44:24.397414 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:44:24.410171 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 05:44:24.984577 0.0;M3 CHK:0;cm4_sp_mode 0
406 05:44:24.985182 MVN_1=0x00000000
407 05:44:24.990057 MVN_2=0x00000000
408 05:44:24.995763 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 05:44:24.996294 OPS=0x10
410 05:44:24.996744 ring efuse init
411 05:44:24.997176 chipver efuse init
412 05:44:25.001332 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 05:44:25.007028 [0.018961 Inits done]
414 05:44:25.007502 secure task start!
415 05:44:25.007946 high task start!
416 05:44:25.011318 low task start!
417 05:44:25.011775 run into bl31
418 05:44:25.018160 NOTICE: BL31: v1.3(release):4fc40b1
419 05:44:25.026069 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 05:44:25.026518 NOTICE: BL31: G12A normal boot!
421 05:44:25.051305 NOTICE: BL31: BL33 decompress pass
422 05:44:25.057076 ERROR: Error initializing runtime service opteed_fast
423 05:44:26.289966
424 05:44:26.290486
425 05:44:26.298366 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 05:44:26.298829
427 05:44:26.299252 Model: Libre Computer AML-A311D-CC Alta
428 05:44:26.505986 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 05:44:26.530106 DRAM: 2 GiB (effective 3.8 GiB)
430 05:44:26.673143 Core: 408 devices, 31 uclasses, devicetree: separate
431 05:44:26.679050 WDT: Not starting watchdog@f0d0
432 05:44:26.711284 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 05:44:26.723843 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 05:44:26.727789 ** Bad device specification mmc 0 **
435 05:44:26.739030 Card did not respond to voltage select! : -110
436 05:44:26.747452 ** Bad device specification mmc 0 **
437 05:44:26.747920 Couldn't find partition mmc 0
438 05:44:26.755052 Card did not respond to voltage select! : -110
439 05:44:26.760556 ** Bad device specification mmc 0 **
440 05:44:26.761012 Couldn't find partition mmc 0
441 05:44:26.765531 Error: could not access storage.
442 05:44:28.029269 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 05:44:28.029818 bl2_stage_init 0x01
444 05:44:28.030256 bl2_stage_init 0x81
445 05:44:28.034867 hw id: 0x0000 - pwm id 0x01
446 05:44:28.035319 bl2_stage_init 0xc1
447 05:44:28.035735 bl2_stage_init 0x02
448 05:44:28.036204
449 05:44:28.040420 L0:00000000
450 05:44:28.040865 L1:20000703
451 05:44:28.041275 L2:00008067
452 05:44:28.041677 L3:14000000
453 05:44:28.046029 B2:00402000
454 05:44:28.046469 B1:e0f83180
455 05:44:28.046880
456 05:44:28.047287 TE: 58159
457 05:44:28.047693
458 05:44:28.051638 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 05:44:28.052115
460 05:44:28.052533 Board ID = 1
461 05:44:28.057235 Set A53 clk to 24M
462 05:44:28.057682 Set A73 clk to 24M
463 05:44:28.058092 Set clk81 to 24M
464 05:44:28.062835 A53 clk: 1200 MHz
465 05:44:28.063274 A73 clk: 1200 MHz
466 05:44:28.063681 CLK81: 166.6M
467 05:44:28.064114 smccc: 00012ab5
468 05:44:28.068400 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 05:44:28.074051 board id: 1
470 05:44:28.079896 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 05:44:28.090633 fw parse done
472 05:44:28.096571 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 05:44:28.139180 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 05:44:28.150055 PIEI prepare done
475 05:44:28.150498 fastboot data load
476 05:44:28.150913 fastboot data verify
477 05:44:28.155687 verify result: 266
478 05:44:28.161272 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 05:44:28.161722 LPDDR4 probe
480 05:44:28.162134 ddr clk to 1584MHz
481 05:44:28.169273 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 05:44:28.206578
483 05:44:28.207033 dmc_version 0001
484 05:44:28.213214 Check phy result
485 05:44:28.219075 INFO : End of CA training
486 05:44:28.219514 INFO : End of initialization
487 05:44:28.224661 INFO : Training has run successfully!
488 05:44:28.225105 Check phy result
489 05:44:28.230251 INFO : End of initialization
490 05:44:28.230683 INFO : End of read enable training
491 05:44:28.235869 INFO : End of fine write leveling
492 05:44:28.241460 INFO : End of Write leveling coarse delay
493 05:44:28.241899 INFO : Training has run successfully!
494 05:44:28.242312 Check phy result
495 05:44:28.247092 INFO : End of initialization
496 05:44:28.247538 INFO : End of read dq deskew training
497 05:44:28.252629 INFO : End of MPR read delay center optimization
498 05:44:28.258246 INFO : End of write delay center optimization
499 05:44:28.263871 INFO : End of read delay center optimization
500 05:44:28.264348 INFO : End of max read latency training
501 05:44:28.269455 INFO : Training has run successfully!
502 05:44:28.269891 1D training succeed
503 05:44:28.278679 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 05:44:28.326309 Check phy result
505 05:44:28.326753 INFO : End of initialization
506 05:44:28.348691 INFO : End of 2D read delay Voltage center optimization
507 05:44:28.368708 INFO : End of 2D read delay Voltage center optimization
508 05:44:28.420719 INFO : End of 2D write delay Voltage center optimization
509 05:44:28.469906 INFO : End of 2D write delay Voltage center optimization
510 05:44:28.475504 INFO : Training has run successfully!
511 05:44:28.475955
512 05:44:28.476441 channel==0
513 05:44:28.481162 RxClkDly_Margin_A0==88 ps 9
514 05:44:28.481619 TxDqDly_Margin_A0==98 ps 10
515 05:44:28.486705 RxClkDly_Margin_A1==88 ps 9
516 05:44:28.487145 TxDqDly_Margin_A1==98 ps 10
517 05:44:28.487556 TrainedVREFDQ_A0==74
518 05:44:28.492275 TrainedVREFDQ_A1==74
519 05:44:28.492740 VrefDac_Margin_A0==24
520 05:44:28.493155 DeviceVref_Margin_A0==40
521 05:44:28.497908 VrefDac_Margin_A1==25
522 05:44:28.498351 DeviceVref_Margin_A1==40
523 05:44:28.498754
524 05:44:28.499154
525 05:44:28.503512 channel==1
526 05:44:28.503961 RxClkDly_Margin_A0==98 ps 10
527 05:44:28.504408 TxDqDly_Margin_A0==88 ps 9
528 05:44:28.509119 RxClkDly_Margin_A1==98 ps 10
529 05:44:28.509561 TxDqDly_Margin_A1==88 ps 9
530 05:44:28.514664 TrainedVREFDQ_A0==74
531 05:44:28.515108 TrainedVREFDQ_A1==77
532 05:44:28.515519 VrefDac_Margin_A0==22
533 05:44:28.520309 DeviceVref_Margin_A0==40
534 05:44:28.520753 VrefDac_Margin_A1==22
535 05:44:28.525853 DeviceVref_Margin_A1==37
536 05:44:28.526298
537 05:44:28.526711 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 05:44:28.527114
539 05:44:28.559506 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 05:44:28.560040 2D training succeed
541 05:44:28.565034 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 05:44:28.570638 auto size-- 65535DDR cs0 size: 2048MB
543 05:44:28.571092 DDR cs1 size: 2048MB
544 05:44:28.576290 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 05:44:28.576745 cs0 DataBus test pass
546 05:44:28.581825 cs1 DataBus test pass
547 05:44:28.582273 cs0 AddrBus test pass
548 05:44:28.582682 cs1 AddrBus test pass
549 05:44:28.583088
550 05:44:28.587597 100bdlr_step_size ps== 420
551 05:44:28.588092 result report
552 05:44:28.593101 boot times 0Enable ddr reg access
553 05:44:28.598436 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 05:44:28.611862 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 05:44:29.183855 0.0;M3 CHK:0;cm4_sp_mode 0
556 05:44:29.184442 MVN_1=0x00000000
557 05:44:29.189366 MVN_2=0x00000000
558 05:44:29.195183 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 05:44:29.195727 OPS=0x10
560 05:44:29.196208 ring efuse init
561 05:44:29.196599 chipver efuse init
562 05:44:29.200701 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 05:44:29.206302 [0.018960 Inits done]
564 05:44:29.206734 secure task start!
565 05:44:29.207120 high task start!
566 05:44:29.210848 low task start!
567 05:44:29.211273 run into bl31
568 05:44:29.217517 NOTICE: BL31: v1.3(release):4fc40b1
569 05:44:29.225348 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 05:44:29.225788 NOTICE: BL31: G12A normal boot!
571 05:44:29.250696 NOTICE: BL31: BL33 decompress pass
572 05:44:29.256382 ERROR: Error initializing runtime service opteed_fast
573 05:44:30.489516
574 05:44:30.490123
575 05:44:30.498054 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 05:44:30.498535
577 05:44:30.498959 Model: Libre Computer AML-A311D-CC Alta
578 05:44:30.706385 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 05:44:30.729637 DRAM: 2 GiB (effective 3.8 GiB)
580 05:44:30.872880 Core: 408 devices, 31 uclasses, devicetree: separate
581 05:44:30.878445 WDT: Not starting watchdog@f0d0
582 05:44:30.910672 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 05:44:30.923128 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 05:44:30.928157 ** Bad device specification mmc 0 **
585 05:44:30.938504 Card did not respond to voltage select! : -110
586 05:44:30.946193 ** Bad device specification mmc 0 **
587 05:44:30.946643 Couldn't find partition mmc 0
588 05:44:30.954488 Card did not respond to voltage select! : -110
589 05:44:30.960076 ** Bad device specification mmc 0 **
590 05:44:30.960550 Couldn't find partition mmc 0
591 05:44:30.965126 Error: could not access storage.
592 05:44:31.307676 Net: eth0: ethernet@ff3f0000
593 05:44:31.308246 starting USB...
594 05:44:31.559468 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 05:44:31.559961 Starting the controller
596 05:44:31.566375 USB XHCI 1.10
597 05:44:33.277877 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 05:44:33.278443 bl2_stage_init 0x01
599 05:44:33.278870 bl2_stage_init 0x81
600 05:44:33.283414 hw id: 0x0000 - pwm id 0x01
601 05:44:33.283870 bl2_stage_init 0xc1
602 05:44:33.284336 bl2_stage_init 0x02
603 05:44:33.284753
604 05:44:33.288955 L0:00000000
605 05:44:33.289404 L1:20000703
606 05:44:33.289823 L2:00008067
607 05:44:33.290229 L3:14000000
608 05:44:33.294550 B2:00402000
609 05:44:33.294995 B1:e0f83180
610 05:44:33.295405
611 05:44:33.295815 TE: 58124
612 05:44:33.296261
613 05:44:33.300216 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 05:44:33.300677
615 05:44:33.301095 Board ID = 1
616 05:44:33.305972 Set A53 clk to 24M
617 05:44:33.306428 Set A73 clk to 24M
618 05:44:33.306835 Set clk81 to 24M
619 05:44:33.311446 A53 clk: 1200 MHz
620 05:44:33.311896 A73 clk: 1200 MHz
621 05:44:33.312350 CLK81: 166.6M
622 05:44:33.312757 smccc: 00012a92
623 05:44:33.317022 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 05:44:33.322558 board id: 1
625 05:44:33.328475 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 05:44:33.339229 fw parse done
627 05:44:33.345165 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 05:44:33.387728 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 05:44:33.398643 PIEI prepare done
630 05:44:33.399098 fastboot data load
631 05:44:33.399511 fastboot data verify
632 05:44:33.404238 verify result: 266
633 05:44:33.410134 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 05:44:33.410585 LPDDR4 probe
635 05:44:33.410994 ddr clk to 1584MHz
636 05:44:33.416934 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 05:44:33.455158
638 05:44:33.455604 dmc_version 0001
639 05:44:33.461820 Check phy result
640 05:44:33.467653 INFO : End of CA training
641 05:44:33.468124 INFO : End of initialization
642 05:44:33.473235 INFO : Training has run successfully!
643 05:44:33.473677 Check phy result
644 05:44:33.478909 INFO : End of initialization
645 05:44:33.479362 INFO : End of read enable training
646 05:44:33.484416 INFO : End of fine write leveling
647 05:44:33.490010 INFO : End of Write leveling coarse delay
648 05:44:33.490459 INFO : Training has run successfully!
649 05:44:33.490865 Check phy result
650 05:44:33.495608 INFO : End of initialization
651 05:44:33.496081 INFO : End of read dq deskew training
652 05:44:33.501227 INFO : End of MPR read delay center optimization
653 05:44:33.506856 INFO : End of write delay center optimization
654 05:44:33.512454 INFO : End of read delay center optimization
655 05:44:33.512898 INFO : End of max read latency training
656 05:44:33.517976 INFO : Training has run successfully!
657 05:44:33.518419 1D training succeed
658 05:44:33.527385 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 05:44:33.574837 Check phy result
660 05:44:33.575283 INFO : End of initialization
661 05:44:33.596351 INFO : End of 2D read delay Voltage center optimization
662 05:44:33.615676 INFO : End of 2D read delay Voltage center optimization
663 05:44:33.668403 INFO : End of 2D write delay Voltage center optimization
664 05:44:33.717802 INFO : End of 2D write delay Voltage center optimization
665 05:44:33.723352 INFO : Training has run successfully!
666 05:44:33.723801
667 05:44:33.724280 channel==0
668 05:44:33.728862 RxClkDly_Margin_A0==88 ps 9
669 05:44:33.729308 TxDqDly_Margin_A0==98 ps 10
670 05:44:33.732204 RxClkDly_Margin_A1==88 ps 9
671 05:44:33.732641 TxDqDly_Margin_A1==88 ps 9
672 05:44:33.737670 TrainedVREFDQ_A0==74
673 05:44:33.738132 TrainedVREFDQ_A1==74
674 05:44:33.738550 VrefDac_Margin_A0==25
675 05:44:33.743481 DeviceVref_Margin_A0==40
676 05:44:33.743931 VrefDac_Margin_A1==25
677 05:44:33.748903 DeviceVref_Margin_A1==40
678 05:44:33.749352
679 05:44:33.749768
680 05:44:33.750173 channel==1
681 05:44:33.750573 RxClkDly_Margin_A0==98 ps 10
682 05:44:33.752344 TxDqDly_Margin_A0==98 ps 10
683 05:44:33.757921 RxClkDly_Margin_A1==98 ps 10
684 05:44:33.758375 TxDqDly_Margin_A1==88 ps 9
685 05:44:33.758788 TrainedVREFDQ_A0==77
686 05:44:33.763792 TrainedVREFDQ_A1==77
687 05:44:33.764273 VrefDac_Margin_A0==22
688 05:44:33.769127 DeviceVref_Margin_A0==37
689 05:44:33.769582 VrefDac_Margin_A1==22
690 05:44:33.769991 DeviceVref_Margin_A1==37
691 05:44:33.770394
692 05:44:33.778309 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 05:44:33.778764
694 05:44:33.806231 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
695 05:44:33.806733 2D training succeed
696 05:44:33.817284 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 05:44:33.817741 auto size-- 65535DDR cs0 size: 2048MB
698 05:44:33.818151 DDR cs1 size: 2048MB
699 05:44:33.822863 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 05:44:33.823321 cs0 DataBus test pass
701 05:44:33.828504 cs1 DataBus test pass
702 05:44:33.828954 cs0 AddrBus test pass
703 05:44:33.834046 cs1 AddrBus test pass
704 05:44:33.834490
705 05:44:33.834895 100bdlr_step_size ps== 420
706 05:44:33.835302 result report
707 05:44:33.839708 boot times 0Enable ddr reg access
708 05:44:33.846062 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 05:44:33.859537 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 05:44:34.431613 0.0;M3 CHK:0;cm4_sp_mode 0
711 05:44:34.432335 MVN_1=0x00000000
712 05:44:34.437169 MVN_2=0x00000000
713 05:44:34.442877 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 05:44:34.443472 OPS=0x10
715 05:44:34.443925 ring efuse init
716 05:44:34.444409 chipver efuse init
717 05:44:34.448471 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 05:44:34.454052 [0.018961 Inits done]
719 05:44:34.454585 secure task start!
720 05:44:34.455023 high task start!
721 05:44:34.458600 low task start!
722 05:44:34.459112 run into bl31
723 05:44:34.465317 NOTICE: BL31: v1.3(release):4fc40b1
724 05:44:34.473040 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 05:44:34.473573 NOTICE: BL31: G12A normal boot!
726 05:44:34.498466 NOTICE: BL31: BL33 decompress pass
727 05:44:34.504233 ERROR: Error initializing runtime service opteed_fast
728 05:44:35.737021
729 05:44:35.737676
730 05:44:35.745536 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 05:44:35.745912
732 05:44:35.746162 Model: Libre Computer AML-A311D-CC Alta
733 05:44:35.953958 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 05:44:35.977279 DRAM: 2 GiB (effective 3.8 GiB)
735 05:44:36.120366 Core: 408 devices, 31 uclasses, devicetree: separate
736 05:44:36.126211 WDT: Not starting watchdog@f0d0
737 05:44:36.158446 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 05:44:36.170823 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 05:44:36.175812 ** Bad device specification mmc 0 **
740 05:44:36.186227 Card did not respond to voltage select! : -110
741 05:44:36.193844 ** Bad device specification mmc 0 **
742 05:44:36.194395 Couldn't find partition mmc 0
743 05:44:36.202210 Card did not respond to voltage select! : -110
744 05:44:36.207757 ** Bad device specification mmc 0 **
745 05:44:36.208348 Couldn't find partition mmc 0
746 05:44:36.212719 Error: could not access storage.
747 05:44:36.555174 Net: eth0: ethernet@ff3f0000
748 05:44:36.555587 starting USB...
749 05:44:36.806930 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 05:44:36.807495 Starting the controller
751 05:44:36.813914 USB XHCI 1.10
752 05:44:38.978207 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 05:44:38.978631 bl2_stage_init 0x01
754 05:44:38.978853 bl2_stage_init 0x81
755 05:44:38.983723 hw id: 0x0000 - pwm id 0x01
756 05:44:38.984186 bl2_stage_init 0xc1
757 05:44:38.984514 bl2_stage_init 0x02
758 05:44:38.984832
759 05:44:38.989190 L0:00000000
760 05:44:38.989631 L1:20000703
761 05:44:38.989869 L2:00008067
762 05:44:38.990078 L3:14000000
763 05:44:38.994800 B2:00402000
764 05:44:38.995231 B1:e0f83180
765 05:44:38.995560
766 05:44:38.995878 TE: 58167
767 05:44:38.996220
768 05:44:39.000352 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 05:44:39.000680
770 05:44:39.000896 Board ID = 1
771 05:44:39.006148 Set A53 clk to 24M
772 05:44:39.006608 Set A73 clk to 24M
773 05:44:39.006939 Set clk81 to 24M
774 05:44:39.011818 A53 clk: 1200 MHz
775 05:44:39.012315 A73 clk: 1200 MHz
776 05:44:39.012555 CLK81: 166.6M
777 05:44:39.012945 smccc: 00012abe
778 05:44:39.017592 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 05:44:39.022815 board id: 1
780 05:44:39.028711 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 05:44:39.039372 fw parse done
782 05:44:39.045186 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 05:44:39.087862 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 05:44:39.098767 PIEI prepare done
785 05:44:39.099143 fastboot data load
786 05:44:39.099369 fastboot data verify
787 05:44:39.104346 verify result: 266
788 05:44:39.109999 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 05:44:39.110454 LPDDR4 probe
790 05:44:39.110785 ddr clk to 1584MHz
791 05:44:39.117946 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 05:44:39.155322
793 05:44:39.155732 dmc_version 0001
794 05:44:39.161912 Check phy result
795 05:44:39.167786 INFO : End of CA training
796 05:44:39.168250 INFO : End of initialization
797 05:44:39.173339 INFO : Training has run successfully!
798 05:44:39.173653 Check phy result
799 05:44:39.179039 INFO : End of initialization
800 05:44:39.179502 INFO : End of read enable training
801 05:44:39.184490 INFO : End of fine write leveling
802 05:44:39.190218 INFO : End of Write leveling coarse delay
803 05:44:39.190566 INFO : Training has run successfully!
804 05:44:39.190791 Check phy result
805 05:44:39.195785 INFO : End of initialization
806 05:44:39.196241 INFO : End of read dq deskew training
807 05:44:39.201417 INFO : End of MPR read delay center optimization
808 05:44:39.207123 INFO : End of write delay center optimization
809 05:44:39.212790 INFO : End of read delay center optimization
810 05:44:39.213085 INFO : End of max read latency training
811 05:44:39.218138 INFO : Training has run successfully!
812 05:44:39.218431 1D training succeed
813 05:44:39.227368 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 05:44:39.275185 Check phy result
815 05:44:39.275575 INFO : End of initialization
816 05:44:39.296523 INFO : End of 2D read delay Voltage center optimization
817 05:44:39.315800 INFO : End of 2D read delay Voltage center optimization
818 05:44:39.367767 INFO : End of 2D write delay Voltage center optimization
819 05:44:39.416859 INFO : End of 2D write delay Voltage center optimization
820 05:44:39.422437 INFO : Training has run successfully!
821 05:44:39.422748
822 05:44:39.422970 channel==0
823 05:44:39.428166 RxClkDly_Margin_A0==88 ps 9
824 05:44:39.428474 TxDqDly_Margin_A0==98 ps 10
825 05:44:39.433718 RxClkDly_Margin_A1==88 ps 9
826 05:44:39.434807 TxDqDly_Margin_A1==98 ps 10
827 05:44:39.435371 TrainedVREFDQ_A0==74
828 05:44:39.439333 TrainedVREFDQ_A1==74
829 05:44:39.439856 VrefDac_Margin_A0==25
830 05:44:39.440349 DeviceVref_Margin_A0==40
831 05:44:39.444898 VrefDac_Margin_A1==25
832 05:44:39.445383 DeviceVref_Margin_A1==40
833 05:44:39.445821
834 05:44:39.446251
835 05:44:39.450597 channel==1
836 05:44:39.451079 RxClkDly_Margin_A0==88 ps 9
837 05:44:39.451512 TxDqDly_Margin_A0==98 ps 10
838 05:44:39.456084 RxClkDly_Margin_A1==88 ps 9
839 05:44:39.456565 TxDqDly_Margin_A1==88 ps 9
840 05:44:39.462104 TrainedVREFDQ_A0==77
841 05:44:39.462591 TrainedVREFDQ_A1==77
842 05:44:39.463026 VrefDac_Margin_A0==23
843 05:44:39.467368 DeviceVref_Margin_A0==37
844 05:44:39.467847 VrefDac_Margin_A1==23
845 05:44:39.472898 DeviceVref_Margin_A1==37
846 05:44:39.473378
847 05:44:39.473812 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 05:44:39.474241
849 05:44:39.506465 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 05:44:39.507002 2D training succeed
851 05:44:39.512058 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 05:44:39.517663 auto size-- 65535DDR cs0 size: 2048MB
853 05:44:39.518148 DDR cs1 size: 2048MB
854 05:44:39.523285 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 05:44:39.523777 cs0 DataBus test pass
856 05:44:39.528869 cs1 DataBus test pass
857 05:44:39.529347 cs0 AddrBus test pass
858 05:44:39.529781 cs1 AddrBus test pass
859 05:44:39.530209
860 05:44:39.534443 100bdlr_step_size ps== 420
861 05:44:39.534956 result report
862 05:44:39.540099 boot times 0Enable ddr reg access
863 05:44:39.545443 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 05:44:39.558911 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 05:44:40.131055 0.0;M3 CHK:0;cm4_sp_mode 0
866 05:44:40.131731 MVN_1=0x00000000
867 05:44:40.136254 MVN_2=0x00000000
868 05:44:40.142285 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 05:44:40.142962 OPS=0x10
870 05:44:40.143451 ring efuse init
871 05:44:40.143915 chipver efuse init
872 05:44:40.147775 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 05:44:40.153417 [0.018961 Inits done]
874 05:44:40.154087 secure task start!
875 05:44:40.154526 high task start!
876 05:44:40.158035 low task start!
877 05:44:40.158616 run into bl31
878 05:44:40.164586 NOTICE: BL31: v1.3(release):4fc40b1
879 05:44:40.172546 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 05:44:40.173253 NOTICE: BL31: G12A normal boot!
881 05:44:40.198555 NOTICE: BL31: BL33 decompress pass
882 05:44:40.204684 ERROR: Error initializing runtime service opteed_fast
883 05:44:41.437089
884 05:44:41.437814
885 05:44:41.445544 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 05:44:41.445979
887 05:44:41.446212 Model: Libre Computer AML-A311D-CC Alta
888 05:44:41.653807 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 05:44:41.678043 DRAM: 2 GiB (effective 3.8 GiB)
890 05:44:41.820267 Core: 408 devices, 31 uclasses, devicetree: separate
891 05:44:41.825899 WDT: Not starting watchdog@f0d0
892 05:44:41.858262 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 05:44:41.870774 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 05:44:41.875782 ** Bad device specification mmc 0 **
895 05:44:41.885965 Card did not respond to voltage select! : -110
896 05:44:41.893571 ** Bad device specification mmc 0 **
897 05:44:41.893880 Couldn't find partition mmc 0
898 05:44:41.901873 Card did not respond to voltage select! : -110
899 05:44:41.907376 ** Bad device specification mmc 0 **
900 05:44:41.907808 Couldn't find partition mmc 0
901 05:44:41.912465 Error: could not access storage.
902 05:44:42.255071 Net: eth0: ethernet@ff3f0000
903 05:44:42.255486 starting USB...
904 05:44:42.506826 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 05:44:42.507242 Starting the controller
906 05:44:42.513803 USB XHCI 1.10
907 05:44:44.378632 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 05:44:44.379059 bl2_stage_init 0x01
909 05:44:44.379279 bl2_stage_init 0x81
910 05:44:44.384240 hw id: 0x0000 - pwm id 0x01
911 05:44:44.384521 bl2_stage_init 0xc1
912 05:44:44.384737 bl2_stage_init 0x02
913 05:44:44.384952
914 05:44:44.389784 L0:00000000
915 05:44:44.390175 L1:20000703
916 05:44:44.390499 L2:00008067
917 05:44:44.390812 L3:14000000
918 05:44:44.392849 B2:00402000
919 05:44:44.393116 B1:e0f83180
920 05:44:44.393324
921 05:44:44.393528 TE: 58167
922 05:44:44.393732
923 05:44:44.404005 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 05:44:44.404320
925 05:44:44.404528 Board ID = 1
926 05:44:44.404727 Set A53 clk to 24M
927 05:44:44.404931 Set A73 clk to 24M
928 05:44:44.409503 Set clk81 to 24M
929 05:44:44.409923 A53 clk: 1200 MHz
930 05:44:44.410256 A73 clk: 1200 MHz
931 05:44:44.415237 CLK81: 166.6M
932 05:44:44.415642 smccc: 00012abd
933 05:44:44.420801 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 05:44:44.421221 board id: 1
935 05:44:44.429388 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 05:44:44.439794 fw parse done
937 05:44:44.445764 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 05:44:44.488400 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 05:44:44.499330 PIEI prepare done
940 05:44:44.499897 fastboot data load
941 05:44:44.500397 fastboot data verify
942 05:44:44.504944 verify result: 266
943 05:44:44.510748 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 05:44:44.511305 LPDDR4 probe
945 05:44:44.511745 ddr clk to 1584MHz
946 05:44:44.518586 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 05:44:44.555833
948 05:44:44.556474 dmc_version 0001
949 05:44:44.562495 Check phy result
950 05:44:44.568341 INFO : End of CA training
951 05:44:44.568898 INFO : End of initialization
952 05:44:44.573964 INFO : Training has run successfully!
953 05:44:44.574548 Check phy result
954 05:44:44.579540 INFO : End of initialization
955 05:44:44.580132 INFO : End of read enable training
956 05:44:44.585165 INFO : End of fine write leveling
957 05:44:44.590724 INFO : End of Write leveling coarse delay
958 05:44:44.591294 INFO : Training has run successfully!
959 05:44:44.591769 Check phy result
960 05:44:44.596337 INFO : End of initialization
961 05:44:44.596893 INFO : End of read dq deskew training
962 05:44:44.601964 INFO : End of MPR read delay center optimization
963 05:44:44.607528 INFO : End of write delay center optimization
964 05:44:44.613175 INFO : End of read delay center optimization
965 05:44:44.613900 INFO : End of max read latency training
966 05:44:44.618799 INFO : Training has run successfully!
967 05:44:44.619371 1D training succeed
968 05:44:44.627909 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 05:44:44.675670 Check phy result
970 05:44:44.676348 INFO : End of initialization
971 05:44:44.697131 INFO : End of 2D read delay Voltage center optimization
972 05:44:44.716463 INFO : End of 2D read delay Voltage center optimization
973 05:44:44.768396 INFO : End of 2D write delay Voltage center optimization
974 05:44:44.817594 INFO : End of 2D write delay Voltage center optimization
975 05:44:44.823125 INFO : Training has run successfully!
976 05:44:44.823720
977 05:44:44.824260 channel==0
978 05:44:44.828759 RxClkDly_Margin_A0==88 ps 9
979 05:44:44.829314 TxDqDly_Margin_A0==98 ps 10
980 05:44:44.834285 RxClkDly_Margin_A1==88 ps 9
981 05:44:44.834825 TxDqDly_Margin_A1==98 ps 10
982 05:44:44.835296 TrainedVREFDQ_A0==74
983 05:44:44.839894 TrainedVREFDQ_A1==74
984 05:44:44.840506 VrefDac_Margin_A0==25
985 05:44:44.840974 DeviceVref_Margin_A0==40
986 05:44:44.845536 VrefDac_Margin_A1==25
987 05:44:44.846092 DeviceVref_Margin_A1==40
988 05:44:44.846551
989 05:44:44.847006
990 05:44:44.851079 channel==1
991 05:44:44.851633 RxClkDly_Margin_A0==88 ps 9
992 05:44:44.852174 TxDqDly_Margin_A0==98 ps 10
993 05:44:44.856770 RxClkDly_Margin_A1==88 ps 9
994 05:44:44.857364 TxDqDly_Margin_A1==88 ps 9
995 05:44:44.862413 TrainedVREFDQ_A0==77
996 05:44:44.862975 TrainedVREFDQ_A1==77
997 05:44:44.863515 VrefDac_Margin_A0==23
998 05:44:44.868106 DeviceVref_Margin_A0==37
999 05:44:44.868671 VrefDac_Margin_A1==24
1000 05:44:44.873612 DeviceVref_Margin_A1==37
1001 05:44:44.874158
1002 05:44:44.874630 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 05:44:44.875091
1004 05:44:44.907128 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1005 05:44:44.907748 2D training succeed
1006 05:44:44.912894 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 05:44:44.918368 auto size-- 65535DDR cs0 size: 2048MB
1008 05:44:44.918935 DDR cs1 size: 2048MB
1009 05:44:44.924044 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 05:44:44.924621 cs0 DataBus test pass
1011 05:44:44.929596 cs1 DataBus test pass
1012 05:44:44.930153 cs0 AddrBus test pass
1013 05:44:44.930624 cs1 AddrBus test pass
1014 05:44:44.931072
1015 05:44:44.935222 100bdlr_step_size ps== 420
1016 05:44:44.935794 result report
1017 05:44:44.940862 boot times 0Enable ddr reg access
1018 05:44:44.946031 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 05:44:44.959599 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 05:44:45.531393 0.0;M3 CHK:0;cm4_sp_mode 0
1021 05:44:45.531834 MVN_1=0x00000000
1022 05:44:45.536867 MVN_2=0x00000000
1023 05:44:45.542686 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 05:44:45.543290 OPS=0x10
1025 05:44:45.543588 ring efuse init
1026 05:44:45.543812 chipver efuse init
1027 05:44:45.548349 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 05:44:45.553799 [0.018961 Inits done]
1029 05:44:45.554197 secure task start!
1030 05:44:45.554430 high task start!
1031 05:44:45.558396 low task start!
1032 05:44:45.558795 run into bl31
1033 05:44:45.565087 NOTICE: BL31: v1.3(release):4fc40b1
1034 05:44:45.572883 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 05:44:45.573477 NOTICE: BL31: G12A normal boot!
1036 05:44:45.598869 NOTICE: BL31: BL33 decompress pass
1037 05:44:45.604974 ERROR: Error initializing runtime service opteed_fast
1038 05:44:46.837535
1039 05:44:46.838208
1040 05:44:46.845887 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 05:44:46.846427
1042 05:44:46.846889 Model: Libre Computer AML-A311D-CC Alta
1043 05:44:47.054364 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 05:44:47.077720 DRAM: 2 GiB (effective 3.8 GiB)
1045 05:44:47.220688 Core: 408 devices, 31 uclasses, devicetree: separate
1046 05:44:47.226532 WDT: Not starting watchdog@f0d0
1047 05:44:47.258816 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 05:44:47.271214 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 05:44:47.276281 ** Bad device specification mmc 0 **
1050 05:44:47.286587 Card did not respond to voltage select! : -110
1051 05:44:47.294234 ** Bad device specification mmc 0 **
1052 05:44:47.294748 Couldn't find partition mmc 0
1053 05:44:47.302593 Card did not respond to voltage select! : -110
1054 05:44:47.308187 ** Bad device specification mmc 0 **
1055 05:44:47.308707 Couldn't find partition mmc 0
1056 05:44:47.313236 Error: could not access storage.
1057 05:44:47.655580 Net: eth0: ethernet@ff3f0000
1058 05:44:47.656274 starting USB...
1059 05:44:47.907424 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 05:44:47.908112 Starting the controller
1061 05:44:47.914401 USB XHCI 1.10
1062 05:44:49.468688 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 05:44:49.477065 scanning usb for storage devices... 0 Storage Device(s) found
1065 05:44:49.528793 Hit any key to stop autoboot: 1
1066 05:44:49.529761 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 05:44:49.530450 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 05:44:49.530970 Setting prompt string to ['=>']
1069 05:44:49.531480 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 05:44:49.544463 0
1071 05:44:49.545414 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 05:44:49.545945 Sending with 10 millisecond of delay
1074 05:44:50.681263 => setenv autoload no
1075 05:44:50.692125 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 05:44:50.697586 setenv autoload no
1077 05:44:50.698587 Sending with 10 millisecond of delay
1079 05:44:52.496661 => setenv initrd_high 0xffffffff
1080 05:44:52.507528 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 05:44:52.508529 setenv initrd_high 0xffffffff
1082 05:44:52.509293 Sending with 10 millisecond of delay
1084 05:44:54.126050 => setenv fdt_high 0xffffffff
1085 05:44:54.136881 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 05:44:54.137768 setenv fdt_high 0xffffffff
1087 05:44:54.138536 Sending with 10 millisecond of delay
1089 05:44:54.430433 => dhcp
1090 05:44:54.441188 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 05:44:54.442050 dhcp
1092 05:44:54.442533 Speed: 1000, full duplex
1093 05:44:54.442987 BOOTP broadcast 1
1094 05:44:54.689113 BOOTP broadcast 2
1095 05:44:54.700691 DHCP client bound to address 192.168.6.33 (259 ms)
1096 05:44:54.701500 Sending with 10 millisecond of delay
1098 05:44:56.378377 => setenv serverip 192.168.6.2
1099 05:44:56.389183 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1100 05:44:56.390081 setenv serverip 192.168.6.2
1101 05:44:56.390837 Sending with 10 millisecond of delay
1103 05:45:00.114199 => tftpboot 0x01080000 796781/tftp-deploy-lr2clkzu/kernel/uImage
1104 05:45:00.125023 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1105 05:45:00.125963 tftpboot 0x01080000 796781/tftp-deploy-lr2clkzu/kernel/uImage
1106 05:45:00.126407 Speed: 1000, full duplex
1107 05:45:00.126804 Using ethernet@ff3f0000 device
1108 05:45:00.127714 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1109 05:45:00.133326 Filename '796781/tftp-deploy-lr2clkzu/kernel/uImage'.
1110 05:45:00.137180 Load address: 0x1080000
1111 05:45:03.465349 Loading: *################################################## 43.6 MiB
1112 05:45:03.465973 13.1 MiB/s
1113 05:45:03.466402 done
1114 05:45:03.469521 Bytes transferred = 45713984 (2b98a40 hex)
1115 05:45:03.470241 Sending with 10 millisecond of delay
1117 05:45:08.156498 => tftpboot 0x08000000 796781/tftp-deploy-lr2clkzu/ramdisk/ramdisk.cpio.gz.uboot
1118 05:45:08.169785 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1119 05:45:08.170353 tftpboot 0x08000000 796781/tftp-deploy-lr2clkzu/ramdisk/ramdisk.cpio.gz.uboot
1120 05:45:08.170607 Speed: 1000, full duplex
1121 05:45:08.170837 Using ethernet@ff3f0000 device
1122 05:45:08.172522 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1123 05:45:08.180998 Filename '796781/tftp-deploy-lr2clkzu/ramdisk/ramdisk.cpio.gz.uboot'.
1124 05:45:08.181311 Load address: 0x8000000
1125 05:45:15.104859 Loading: *##T ############################################### UDP wrong checksum 00000005 00009961
1126 05:45:20.107091 T UDP wrong checksum 00000005 00009961
1127 05:45:30.108493 T T UDP wrong checksum 00000005 00009961
1128 05:45:42.333389 T T UDP wrong checksum 000000ff 00002b04
1129 05:45:42.373284 UDP wrong checksum 000000ff 0000b0f6
1130 05:45:50.112418 T T UDP wrong checksum 00000005 00009961
1131 05:46:05.116726 T T
1132 05:46:05.117446 Retry count exceeded; starting again
1134 05:46:05.119286 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1137 05:46:05.120422 end: 2.4 uboot-commands (duration 00:01:53) [common]
1139 05:46:05.121212 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1141 05:46:05.121815 end: 2 uboot-action (duration 00:01:53) [common]
1143 05:46:05.124432 Cleaning after the job
1144 05:46:05.125097 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/ramdisk
1145 05:46:05.126816 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/kernel
1146 05:46:05.138927 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/dtb
1147 05:46:05.140489 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796781/tftp-deploy-lr2clkzu/modules
1148 05:46:05.147717 start: 4.1 power-off (timeout 00:00:30) [common]
1149 05:46:05.148950 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1150 05:46:05.185664 >> OK - accepted request
1151 05:46:05.187712 Returned 0 in 0 seconds
1152 05:46:05.289027 end: 4.1 power-off (duration 00:00:00) [common]
1154 05:46:05.290940 start: 4.2 read-feedback (timeout 00:10:00) [common]
1155 05:46:05.292280 Listened to connection for namespace 'common' for up to 1s
1156 05:46:06.292982 Finalising connection for namespace 'common'
1157 05:46:06.293780 Disconnecting from shell: Finalise
1158 05:46:06.294372 =>
1159 05:46:06.395456 end: 4.2 read-feedback (duration 00:00:01) [common]
1160 05:46:06.396237 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796781
1161 05:46:06.699882 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796781
1162 05:46:06.700501 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.