Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:46:34.552655 lava-dispatcher, installed at version: 2024.01
2 05:46:34.553456 start: 0 validate
3 05:46:34.553956 Start time: 2024-10-03 05:46:34.553927+00:00 (UTC)
4 05:46:34.554510 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:46:34.555050 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:46:34.598653 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:46:34.599245 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 05:46:34.631613 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:46:34.632322 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:46:34.665360 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:46:34.665861 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:46:34.695929 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:46:34.696472 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
14 05:46:34.737779 validate duration: 0.18
16 05:46:34.738631 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:46:34.738945 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:46:34.739249 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:46:34.739812 Not decompressing ramdisk as can be used compressed.
20 05:46:34.740288 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 05:46:34.740564 saving as /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/ramdisk/initrd.cpio.gz
22 05:46:34.740830 total size: 5628182 (5 MB)
23 05:46:34.780379 progress 0 % (0 MB)
24 05:46:34.785019 progress 5 % (0 MB)
25 05:46:34.792940 progress 10 % (0 MB)
26 05:46:34.799792 progress 15 % (0 MB)
27 05:46:34.807650 progress 20 % (1 MB)
28 05:46:34.811477 progress 25 % (1 MB)
29 05:46:34.815463 progress 30 % (1 MB)
30 05:46:34.819572 progress 35 % (1 MB)
31 05:46:34.823109 progress 40 % (2 MB)
32 05:46:34.827068 progress 45 % (2 MB)
33 05:46:34.830751 progress 50 % (2 MB)
34 05:46:34.834752 progress 55 % (2 MB)
35 05:46:34.838836 progress 60 % (3 MB)
36 05:46:34.842487 progress 65 % (3 MB)
37 05:46:34.846441 progress 70 % (3 MB)
38 05:46:34.849966 progress 75 % (4 MB)
39 05:46:34.853930 progress 80 % (4 MB)
40 05:46:34.857526 progress 85 % (4 MB)
41 05:46:34.861343 progress 90 % (4 MB)
42 05:46:34.865015 progress 95 % (5 MB)
43 05:46:34.868318 progress 100 % (5 MB)
44 05:46:34.868984 5 MB downloaded in 0.13 s (41.89 MB/s)
45 05:46:34.869533 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:46:34.870447 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:46:34.870743 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:46:34.871018 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:46:34.871499 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
51 05:46:34.871747 saving as /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/kernel/Image
52 05:46:34.871959 total size: 45713920 (43 MB)
53 05:46:34.872202 No compression specified
54 05:46:34.912717 progress 0 % (0 MB)
55 05:46:34.945104 progress 5 % (2 MB)
56 05:46:34.978656 progress 10 % (4 MB)
57 05:46:35.011682 progress 15 % (6 MB)
58 05:46:35.046066 progress 20 % (8 MB)
59 05:46:35.078689 progress 25 % (10 MB)
60 05:46:35.111536 progress 30 % (13 MB)
61 05:46:35.144279 progress 35 % (15 MB)
62 05:46:35.176944 progress 40 % (17 MB)
63 05:46:35.209855 progress 45 % (19 MB)
64 05:46:35.241231 progress 50 % (21 MB)
65 05:46:35.273096 progress 55 % (24 MB)
66 05:46:35.304010 progress 60 % (26 MB)
67 05:46:35.333977 progress 65 % (28 MB)
68 05:46:35.364581 progress 70 % (30 MB)
69 05:46:35.394227 progress 75 % (32 MB)
70 05:46:35.423887 progress 80 % (34 MB)
71 05:46:35.453274 progress 85 % (37 MB)
72 05:46:35.482956 progress 90 % (39 MB)
73 05:46:35.512453 progress 95 % (41 MB)
74 05:46:35.541004 progress 100 % (43 MB)
75 05:46:35.541525 43 MB downloaded in 0.67 s (65.11 MB/s)
76 05:46:35.542063 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:46:35.542888 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:46:35.543164 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:46:35.543430 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:46:35.543890 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:46:35.544263 saving as /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:46:35.544475 total size: 54703 (0 MB)
84 05:46:35.544685 No compression specified
85 05:46:35.577073 progress 59 % (0 MB)
86 05:46:35.577943 progress 100 % (0 MB)
87 05:46:35.578511 0 MB downloaded in 0.03 s (1.53 MB/s)
88 05:46:35.578994 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:46:35.579804 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:46:35.580199 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:46:35.580482 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:46:35.581029 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 05:46:35.581290 saving as /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/nfsrootfs/full.rootfs.tar
95 05:46:35.581496 total size: 107552908 (102 MB)
96 05:46:35.581706 Using unxz to decompress xz
97 05:46:35.620016 progress 0 % (0 MB)
98 05:46:36.275475 progress 5 % (5 MB)
99 05:46:37.003540 progress 10 % (10 MB)
100 05:46:37.732420 progress 15 % (15 MB)
101 05:46:38.491635 progress 20 % (20 MB)
102 05:46:39.063733 progress 25 % (25 MB)
103 05:46:39.684424 progress 30 % (30 MB)
104 05:46:40.426977 progress 35 % (35 MB)
105 05:46:40.785143 progress 40 % (41 MB)
106 05:46:41.243067 progress 45 % (46 MB)
107 05:46:42.007977 progress 50 % (51 MB)
108 05:46:42.758876 progress 55 % (56 MB)
109 05:46:43.542377 progress 60 % (61 MB)
110 05:46:44.309646 progress 65 % (66 MB)
111 05:46:45.061102 progress 70 % (71 MB)
112 05:46:45.908639 progress 75 % (76 MB)
113 05:46:46.729284 progress 80 % (82 MB)
114 05:46:47.507769 progress 85 % (87 MB)
115 05:46:48.292337 progress 90 % (92 MB)
116 05:46:49.121440 progress 95 % (97 MB)
117 05:46:50.036953 progress 100 % (102 MB)
118 05:46:50.052669 102 MB downloaded in 14.47 s (7.09 MB/s)
119 05:46:50.053578 end: 1.4.1 http-download (duration 00:00:14) [common]
121 05:46:50.055210 end: 1.4 download-retry (duration 00:00:14) [common]
122 05:46:50.055741 start: 1.5 download-retry (timeout 00:09:45) [common]
123 05:46:50.056334 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 05:46:50.057144 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
125 05:46:50.057610 saving as /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/modules/modules.tar
126 05:46:50.058027 total size: 11621592 (11 MB)
127 05:46:50.058456 Using unxz to decompress xz
128 05:46:50.106281 progress 0 % (0 MB)
129 05:46:50.177692 progress 5 % (0 MB)
130 05:46:50.257561 progress 10 % (1 MB)
131 05:46:50.344001 progress 15 % (1 MB)
132 05:46:50.421074 progress 20 % (2 MB)
133 05:46:50.504043 progress 25 % (2 MB)
134 05:46:50.584284 progress 30 % (3 MB)
135 05:46:50.664574 progress 35 % (3 MB)
136 05:46:50.738258 progress 40 % (4 MB)
137 05:46:50.815124 progress 45 % (5 MB)
138 05:46:50.894321 progress 50 % (5 MB)
139 05:46:50.970886 progress 55 % (6 MB)
140 05:46:51.051096 progress 60 % (6 MB)
141 05:46:51.137372 progress 65 % (7 MB)
142 05:46:51.220280 progress 70 % (7 MB)
143 05:46:51.313124 progress 75 % (8 MB)
144 05:46:51.408901 progress 80 % (8 MB)
145 05:46:51.490356 progress 85 % (9 MB)
146 05:46:51.565399 progress 90 % (10 MB)
147 05:46:51.637300 progress 95 % (10 MB)
148 05:46:51.713067 progress 100 % (11 MB)
149 05:46:51.726585 11 MB downloaded in 1.67 s (6.64 MB/s)
150 05:46:51.727169 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:46:51.728126 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:46:51.728885 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 05:46:51.729479 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 05:47:01.462710 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/796782/extract-nfsrootfs-5o294bjq
156 05:47:01.463314 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 05:47:01.463604 start: 1.6.2 lava-overlay (timeout 00:09:33) [common]
158 05:47:01.464333 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu
159 05:47:01.464789 makedir: /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin
160 05:47:01.465128 makedir: /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/tests
161 05:47:01.465479 makedir: /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/results
162 05:47:01.465824 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-add-keys
163 05:47:01.466365 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-add-sources
164 05:47:01.466875 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-background-process-start
165 05:47:01.467375 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-background-process-stop
166 05:47:01.467894 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-common-functions
167 05:47:01.468432 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-echo-ipv4
168 05:47:01.468958 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-install-packages
169 05:47:01.469473 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-installed-packages
170 05:47:01.469963 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-os-build
171 05:47:01.470445 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-probe-channel
172 05:47:01.470925 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-probe-ip
173 05:47:01.471406 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-target-ip
174 05:47:01.471903 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-target-mac
175 05:47:01.472438 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-target-storage
176 05:47:01.472933 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-test-case
177 05:47:01.473425 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-test-event
178 05:47:01.473908 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-test-feedback
179 05:47:01.474385 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-test-raise
180 05:47:01.474855 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-test-reference
181 05:47:01.475348 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-test-runner
182 05:47:01.475858 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-test-set
183 05:47:01.476394 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-test-shell
184 05:47:01.476889 Updating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-install-packages (oe)
185 05:47:01.477426 Updating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/bin/lava-installed-packages (oe)
186 05:47:01.477894 Creating /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/environment
187 05:47:01.478272 LAVA metadata
188 05:47:01.478533 - LAVA_JOB_ID=796782
189 05:47:01.478749 - LAVA_DISPATCHER_IP=192.168.6.2
190 05:47:01.479100 start: 1.6.2.1 ssh-authorize (timeout 00:09:33) [common]
191 05:47:01.480079 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 05:47:01.480399 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:33) [common]
193 05:47:01.480609 skipped lava-vland-overlay
194 05:47:01.480853 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 05:47:01.481108 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:33) [common]
196 05:47:01.481329 skipped lava-multinode-overlay
197 05:47:01.481570 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 05:47:01.481821 start: 1.6.2.4 test-definition (timeout 00:09:33) [common]
199 05:47:01.482072 Loading test definitions
200 05:47:01.482352 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:33) [common]
201 05:47:01.482574 Using /lava-796782 at stage 0
202 05:47:01.483742 uuid=796782_1.6.2.4.1 testdef=None
203 05:47:01.484064 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 05:47:01.484336 start: 1.6.2.4.2 test-overlay (timeout 00:09:33) [common]
205 05:47:01.486145 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 05:47:01.486933 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:33) [common]
208 05:47:01.489171 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 05:47:01.489994 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:33) [common]
211 05:47:01.492152 runner path: /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/0/tests/0_dmesg test_uuid 796782_1.6.2.4.1
212 05:47:01.492706 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 05:47:01.493465 Creating lava-test-runner.conf files
215 05:47:01.493667 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796782/lava-overlay-by3zcveu/lava-796782/0 for stage 0
216 05:47:01.494000 - 0_dmesg
217 05:47:01.494333 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 05:47:01.494606 start: 1.6.2.5 compress-overlay (timeout 00:09:33) [common]
219 05:47:01.515864 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 05:47:01.516263 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:33) [common]
221 05:47:01.516527 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 05:47:01.516793 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 05:47:01.517056 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
224 05:47:02.153493 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 05:47:02.153960 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 05:47:02.154205 extracting modules file /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796782/extract-nfsrootfs-5o294bjq
227 05:47:03.548155 extracting modules file /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796782/extract-overlay-ramdisk-utepuvlw/ramdisk
228 05:47:04.978955 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 05:47:04.979432 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 05:47:04.979712 [common] Applying overlay to NFS
231 05:47:04.979924 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796782/compress-overlay-zmywtiku/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796782/extract-nfsrootfs-5o294bjq
232 05:47:05.009950 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 05:47:05.010381 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 05:47:05.010648 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 05:47:05.010879 Converting downloaded kernel to a uImage
236 05:47:05.011189 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/kernel/Image /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/kernel/uImage
237 05:47:05.487137 output: Image Name:
238 05:47:05.487559 output: Created: Thu Oct 3 05:47:05 2024
239 05:47:05.487768 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 05:47:05.487975 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 05:47:05.488217 output: Load Address: 01080000
242 05:47:05.488421 output: Entry Point: 01080000
243 05:47:05.488621 output:
244 05:47:05.488955 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 05:47:05.489227 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 05:47:05.489495 start: 1.6.7 configure-preseed-file (timeout 00:09:29) [common]
247 05:47:05.489751 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 05:47:05.490010 start: 1.6.8 compress-ramdisk (timeout 00:09:29) [common]
249 05:47:05.490265 Building ramdisk /var/lib/lava/dispatcher/tmp/796782/extract-overlay-ramdisk-utepuvlw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796782/extract-overlay-ramdisk-utepuvlw/ramdisk
250 05:47:07.667232 >> 166933 blocks
251 05:47:15.650730 Adding RAMdisk u-boot header.
252 05:47:15.651450 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796782/extract-overlay-ramdisk-utepuvlw/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796782/extract-overlay-ramdisk-utepuvlw/ramdisk.cpio.gz.uboot
253 05:47:15.900212 output: Image Name:
254 05:47:15.900906 output: Created: Thu Oct 3 05:47:15 2024
255 05:47:15.901392 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 05:47:15.901844 output: Data Size: 23442389 Bytes = 22892.96 KiB = 22.36 MiB
257 05:47:15.902287 output: Load Address: 00000000
258 05:47:15.902722 output: Entry Point: 00000000
259 05:47:15.903158 output:
260 05:47:15.904470 rename /var/lib/lava/dispatcher/tmp/796782/extract-overlay-ramdisk-utepuvlw/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/ramdisk/ramdisk.cpio.gz.uboot
261 05:47:15.905272 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 05:47:15.905872 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 05:47:15.906453 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
264 05:47:15.906953 No LXC device requested
265 05:47:15.907503 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 05:47:15.908096 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
267 05:47:15.908654 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 05:47:15.909192 Checking files for TFTP limit of 4294967296 bytes.
269 05:47:15.912179 end: 1 tftp-deploy (duration 00:00:41) [common]
270 05:47:15.912813 start: 2 uboot-action (timeout 00:05:00) [common]
271 05:47:15.913397 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 05:47:15.913949 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 05:47:15.914506 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 05:47:15.915091 Using kernel file from prepare-kernel: 796782/tftp-deploy-5uq0a8fw/kernel/uImage
275 05:47:15.915779 substitutions:
276 05:47:15.916272 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 05:47:15.916724 - {DTB_ADDR}: 0x01070000
278 05:47:15.917167 - {DTB}: 796782/tftp-deploy-5uq0a8fw/dtb/meson-g12b-a311d-libretech-cc.dtb
279 05:47:15.917610 - {INITRD}: 796782/tftp-deploy-5uq0a8fw/ramdisk/ramdisk.cpio.gz.uboot
280 05:47:15.918048 - {KERNEL_ADDR}: 0x01080000
281 05:47:15.918481 - {KERNEL}: 796782/tftp-deploy-5uq0a8fw/kernel/uImage
282 05:47:15.918916 - {LAVA_MAC}: None
283 05:47:15.919393 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/796782/extract-nfsrootfs-5o294bjq
284 05:47:15.919832 - {NFS_SERVER_IP}: 192.168.6.2
285 05:47:15.920309 - {PRESEED_CONFIG}: None
286 05:47:15.920744 - {PRESEED_LOCAL}: None
287 05:47:15.921177 - {RAMDISK_ADDR}: 0x08000000
288 05:47:15.921603 - {RAMDISK}: 796782/tftp-deploy-5uq0a8fw/ramdisk/ramdisk.cpio.gz.uboot
289 05:47:15.922036 - {ROOT_PART}: None
290 05:47:15.922464 - {ROOT}: None
291 05:47:15.922895 - {SERVER_IP}: 192.168.6.2
292 05:47:15.923324 - {TEE_ADDR}: 0x83000000
293 05:47:15.923755 - {TEE}: None
294 05:47:15.924214 Parsed boot commands:
295 05:47:15.924635 - setenv autoload no
296 05:47:15.925063 - setenv initrd_high 0xffffffff
297 05:47:15.925490 - setenv fdt_high 0xffffffff
298 05:47:15.925918 - dhcp
299 05:47:15.926343 - setenv serverip 192.168.6.2
300 05:47:15.926768 - tftpboot 0x01080000 796782/tftp-deploy-5uq0a8fw/kernel/uImage
301 05:47:15.927193 - tftpboot 0x08000000 796782/tftp-deploy-5uq0a8fw/ramdisk/ramdisk.cpio.gz.uboot
302 05:47:15.927619 - tftpboot 0x01070000 796782/tftp-deploy-5uq0a8fw/dtb/meson-g12b-a311d-libretech-cc.dtb
303 05:47:15.928069 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/796782/extract-nfsrootfs-5o294bjq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 05:47:15.928514 - bootm 0x01080000 0x08000000 0x01070000
305 05:47:15.929072 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 05:47:15.930702 start: 2.3 connect-device (timeout 00:05:00) [common]
308 05:47:15.931161 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 05:47:15.946973 Setting prompt string to ['lava-test: # ']
310 05:47:15.948666 end: 2.3 connect-device (duration 00:00:00) [common]
311 05:47:15.949329 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 05:47:15.949972 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 05:47:15.950604 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 05:47:15.951865 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 05:47:15.989029 >> OK - accepted request
316 05:47:15.991251 Returned 0 in 0 seconds
317 05:47:16.093219 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 05:47:16.096219 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 05:47:16.098549 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 05:47:16.099450 Setting prompt string to ['Hit any key to stop autoboot']
322 05:47:16.100027 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 05:47:16.108040 Trying 192.168.56.21...
324 05:47:16.108658 Connected to conserv1.
325 05:47:16.109405 Escape character is '^]'.
326 05:47:16.109893
327 05:47:16.111002 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 05:47:16.113258
329 05:47:26.869989 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 05:47:26.870782 bl2_stage_init 0x01
331 05:47:26.871378 bl2_stage_init 0x81
332 05:47:26.875348 hw id: 0x0000 - pwm id 0x01
333 05:47:26.876048 bl2_stage_init 0xc1
334 05:47:26.876587 bl2_stage_init 0x02
335 05:47:26.877120
336 05:47:26.880925 L0:00000000
337 05:47:26.881522 L1:20000703
338 05:47:26.882038 L2:00008067
339 05:47:26.882543 L3:14000000
340 05:47:26.883958 B2:00402000
341 05:47:26.884589 B1:e0f83180
342 05:47:26.885101
343 05:47:26.885607 TE: 58124
344 05:47:26.886124
345 05:47:26.895094 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 05:47:26.895725
347 05:47:26.896286 Board ID = 1
348 05:47:26.896794 Set A53 clk to 24M
349 05:47:26.897297 Set A73 clk to 24M
350 05:47:26.900574 Set clk81 to 24M
351 05:47:26.901168 A53 clk: 1200 MHz
352 05:47:26.901675 A73 clk: 1200 MHz
353 05:47:26.906193 CLK81: 166.6M
354 05:47:26.906803 smccc: 00012a92
355 05:47:26.911875 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 05:47:26.912511 board id: 1
357 05:47:26.920488 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 05:47:26.931117 fw parse done
359 05:47:26.937090 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 05:47:26.979707 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 05:47:26.990480 PIEI prepare done
362 05:47:26.991101 fastboot data load
363 05:47:26.991622 fastboot data verify
364 05:47:26.996324 verify result: 266
365 05:47:27.001865 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 05:47:27.002474 LPDDR4 probe
367 05:47:27.003018 ddr clk to 1584MHz
368 05:47:27.009890 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 05:47:27.047145
370 05:47:27.047866 dmc_version 0001
371 05:47:27.053825 Check phy result
372 05:47:27.059662 INFO : End of CA training
373 05:47:27.060352 INFO : End of initialization
374 05:47:27.065222 INFO : Training has run successfully!
375 05:47:27.065838 Check phy result
376 05:47:27.070873 INFO : End of initialization
377 05:47:27.071498 INFO : End of read enable training
378 05:47:27.074234 INFO : End of fine write leveling
379 05:47:27.079855 INFO : End of Write leveling coarse delay
380 05:47:27.085448 INFO : Training has run successfully!
381 05:47:27.086054 Check phy result
382 05:47:27.086570 INFO : End of initialization
383 05:47:27.091075 INFO : End of read dq deskew training
384 05:47:27.094394 INFO : End of MPR read delay center optimization
385 05:47:27.099960 INFO : End of write delay center optimization
386 05:47:27.105574 INFO : End of read delay center optimization
387 05:47:27.106221 INFO : End of max read latency training
388 05:47:27.111219 INFO : Training has run successfully!
389 05:47:27.111841 1D training succeed
390 05:47:27.119285 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 05:47:27.166904 Check phy result
392 05:47:27.167592 INFO : End of initialization
393 05:47:27.188510 INFO : End of 2D read delay Voltage center optimization
394 05:47:27.210427 INFO : End of 2D read delay Voltage center optimization
395 05:47:27.260466 INFO : End of 2D write delay Voltage center optimization
396 05:47:27.309810 INFO : End of 2D write delay Voltage center optimization
397 05:47:27.315406 INFO : Training has run successfully!
398 05:47:27.316137
399 05:47:27.316669 channel==0
400 05:47:27.320871 RxClkDly_Margin_A0==88 ps 9
401 05:47:27.321463 TxDqDly_Margin_A0==98 ps 10
402 05:47:27.326465 RxClkDly_Margin_A1==88 ps 9
403 05:47:27.327053 TxDqDly_Margin_A1==98 ps 10
404 05:47:27.327573 TrainedVREFDQ_A0==74
405 05:47:27.332206 TrainedVREFDQ_A1==74
406 05:47:27.332821 VrefDac_Margin_A0==25
407 05:47:27.333347 DeviceVref_Margin_A0==40
408 05:47:27.337840 VrefDac_Margin_A1==25
409 05:47:27.338429 DeviceVref_Margin_A1==40
410 05:47:27.338940
411 05:47:27.339451
412 05:47:27.343390 channel==1
413 05:47:27.344023 RxClkDly_Margin_A0==98 ps 10
414 05:47:27.344545 TxDqDly_Margin_A0==88 ps 9
415 05:47:27.349039 RxClkDly_Margin_A1==88 ps 9
416 05:47:27.349633 TxDqDly_Margin_A1==88 ps 9
417 05:47:27.354552 TrainedVREFDQ_A0==77
418 05:47:27.355150 TrainedVREFDQ_A1==77
419 05:47:27.355664 VrefDac_Margin_A0==22
420 05:47:27.360197 DeviceVref_Margin_A0==37
421 05:47:27.360713 VrefDac_Margin_A1==24
422 05:47:27.365721 DeviceVref_Margin_A1==37
423 05:47:27.366186
424 05:47:27.366594 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 05:47:27.366994
426 05:47:27.399249 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 05:47:27.399811 2D training succeed
428 05:47:27.404822 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 05:47:27.410313 auto size-- 65535DDR cs0 size: 2048MB
430 05:47:27.410775 DDR cs1 size: 2048MB
431 05:47:27.415885 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 05:47:27.416380 cs0 DataBus test pass
433 05:47:27.421492 cs1 DataBus test pass
434 05:47:27.421963 cs0 AddrBus test pass
435 05:47:27.422362 cs1 AddrBus test pass
436 05:47:27.422755
437 05:47:27.427209 100bdlr_step_size ps== 420
438 05:47:27.427691 result report
439 05:47:27.432698 boot times 0Enable ddr reg access
440 05:47:27.437989 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 05:47:27.451472 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 05:47:28.023340 0.0;M3 CHK:0;cm4_sp_mode 0
443 05:47:28.023748 MVN_1=0x00000000
444 05:47:28.028793 MVN_2=0x00000000
445 05:47:28.034545 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 05:47:28.034858 OPS=0x10
447 05:47:28.035097 ring efuse init
448 05:47:28.035327 chipver efuse init
449 05:47:28.040231 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 05:47:28.045851 [0.018961 Inits done]
451 05:47:28.046342 secure task start!
452 05:47:28.046758 high task start!
453 05:47:28.050443 low task start!
454 05:47:28.050915 run into bl31
455 05:47:28.057130 NOTICE: BL31: v1.3(release):4fc40b1
456 05:47:28.065264 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 05:47:28.065779 NOTICE: BL31: G12A normal boot!
458 05:47:28.090986 NOTICE: BL31: BL33 decompress pass
459 05:47:28.096396 ERROR: Error initializing runtime service opteed_fast
460 05:47:29.329219
461 05:47:29.329662
462 05:47:29.337469 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 05:47:29.337812
464 05:47:29.338037 Model: Libre Computer AML-A311D-CC Alta
465 05:47:29.545950 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 05:47:29.569413 DRAM: 2 GiB (effective 3.8 GiB)
467 05:47:29.712487 Core: 408 devices, 31 uclasses, devicetree: separate
468 05:47:29.718275 WDT: Not starting watchdog@f0d0
469 05:47:29.750527 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 05:47:29.763030 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 05:47:29.768032 ** Bad device specification mmc 0 **
472 05:47:29.778394 Card did not respond to voltage select! : -110
473 05:47:29.786005 ** Bad device specification mmc 0 **
474 05:47:29.786469 Couldn't find partition mmc 0
475 05:47:29.794384 Card did not respond to voltage select! : -110
476 05:47:29.799853 ** Bad device specification mmc 0 **
477 05:47:29.800338 Couldn't find partition mmc 0
478 05:47:29.804940 Error: could not access storage.
479 05:47:31.070243 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 05:47:31.070828 bl2_stage_init 0x01
481 05:47:31.071252 bl2_stage_init 0x81
482 05:47:31.075896 hw id: 0x0000 - pwm id 0x01
483 05:47:31.076385 bl2_stage_init 0xc1
484 05:47:31.076797 bl2_stage_init 0x02
485 05:47:31.077198
486 05:47:31.081503 L0:00000000
487 05:47:31.081941 L1:20000703
488 05:47:31.082345 L2:00008067
489 05:47:31.082742 L3:14000000
490 05:47:31.084309 B2:00402000
491 05:47:31.084763 B1:e0f83180
492 05:47:31.085172
493 05:47:31.085570 TE: 58167
494 05:47:31.085967
495 05:47:31.095518 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 05:47:31.096007
497 05:47:31.096429 Board ID = 1
498 05:47:31.096830 Set A53 clk to 24M
499 05:47:31.097230 Set A73 clk to 24M
500 05:47:31.101025 Set clk81 to 24M
501 05:47:31.101466 A53 clk: 1200 MHz
502 05:47:31.101868 A73 clk: 1200 MHz
503 05:47:31.104406 CLK81: 166.6M
504 05:47:31.104846 smccc: 00012abe
505 05:47:31.110079 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 05:47:31.115588 board id: 1
507 05:47:31.120904 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 05:47:31.131617 fw parse done
509 05:47:31.137594 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 05:47:31.180204 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 05:47:31.191229 PIEI prepare done
512 05:47:31.191688 fastboot data load
513 05:47:31.192145 fastboot data verify
514 05:47:31.196897 verify result: 266
515 05:47:31.202487 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 05:47:31.202937 LPDDR4 probe
517 05:47:31.203365 ddr clk to 1584MHz
518 05:47:31.210360 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 05:47:31.247632
520 05:47:31.248114 dmc_version 0001
521 05:47:31.254263 Check phy result
522 05:47:31.260083 INFO : End of CA training
523 05:47:31.260533 INFO : End of initialization
524 05:47:31.265800 INFO : Training has run successfully!
525 05:47:31.266277 Check phy result
526 05:47:31.271326 INFO : End of initialization
527 05:47:31.271768 INFO : End of read enable training
528 05:47:31.277000 INFO : End of fine write leveling
529 05:47:31.282684 INFO : End of Write leveling coarse delay
530 05:47:31.283123 INFO : Training has run successfully!
531 05:47:31.283538 Check phy result
532 05:47:31.288126 INFO : End of initialization
533 05:47:31.288409 INFO : End of read dq deskew training
534 05:47:31.293716 INFO : End of MPR read delay center optimization
535 05:47:31.299353 INFO : End of write delay center optimization
536 05:47:31.304905 INFO : End of read delay center optimization
537 05:47:31.305352 INFO : End of max read latency training
538 05:47:31.310574 INFO : Training has run successfully!
539 05:47:31.311010 1D training succeed
540 05:47:31.319714 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 05:47:31.367417 Check phy result
542 05:47:31.367938 INFO : End of initialization
543 05:47:31.389063 INFO : End of 2D read delay Voltage center optimization
544 05:47:31.409272 INFO : End of 2D read delay Voltage center optimization
545 05:47:31.461328 INFO : End of 2D write delay Voltage center optimization
546 05:47:31.510820 INFO : End of 2D write delay Voltage center optimization
547 05:47:31.516301 INFO : Training has run successfully!
548 05:47:31.516756
549 05:47:31.517170 channel==0
550 05:47:31.521792 RxClkDly_Margin_A0==88 ps 9
551 05:47:31.522233 TxDqDly_Margin_A0==98 ps 10
552 05:47:31.527358 RxClkDly_Margin_A1==88 ps 9
553 05:47:31.527811 TxDqDly_Margin_A1==98 ps 10
554 05:47:31.528279 TrainedVREFDQ_A0==74
555 05:47:31.533009 TrainedVREFDQ_A1==74
556 05:47:31.533272 VrefDac_Margin_A0==25
557 05:47:31.533712 DeviceVref_Margin_A0==40
558 05:47:31.538664 VrefDac_Margin_A1==24
559 05:47:31.538973 DeviceVref_Margin_A1==40
560 05:47:31.539400
561 05:47:31.539810
562 05:47:31.544222 channel==1
563 05:47:31.544674 RxClkDly_Margin_A0==98 ps 10
564 05:47:31.545097 TxDqDly_Margin_A0==88 ps 9
565 05:47:31.549842 RxClkDly_Margin_A1==88 ps 9
566 05:47:31.550286 TxDqDly_Margin_A1==88 ps 9
567 05:47:31.555453 TrainedVREFDQ_A0==77
568 05:47:31.555942 TrainedVREFDQ_A1==77
569 05:47:31.556402 VrefDac_Margin_A0==22
570 05:47:31.561032 DeviceVref_Margin_A0==37
571 05:47:31.561484 VrefDac_Margin_A1==24
572 05:47:31.566665 DeviceVref_Margin_A1==37
573 05:47:31.567125
574 05:47:31.567539 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 05:47:31.567941
576 05:47:31.600319 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
577 05:47:31.600855 2D training succeed
578 05:47:31.605832 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 05:47:31.611452 auto size-- 65535DDR cs0 size: 2048MB
580 05:47:31.611888 DDR cs1 size: 2048MB
581 05:47:31.617054 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 05:47:31.617495 cs0 DataBus test pass
583 05:47:31.622669 cs1 DataBus test pass
584 05:47:31.623105 cs0 AddrBus test pass
585 05:47:31.623533 cs1 AddrBus test pass
586 05:47:31.623965
587 05:47:31.628355 100bdlr_step_size ps== 420
588 05:47:31.628839 result report
589 05:47:31.633854 boot times 0Enable ddr reg access
590 05:47:31.638210 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 05:47:31.652605 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 05:47:32.226304 0.0;M3 CHK:0;cm4_sp_mode 0
593 05:47:32.226937 MVN_1=0x00000000
594 05:47:32.231688 MVN_2=0x00000000
595 05:47:32.237483 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 05:47:32.237983 OPS=0x10
597 05:47:32.238431 ring efuse init
598 05:47:32.238877 chipver efuse init
599 05:47:32.243080 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 05:47:32.248683 [0.018961 Inits done]
601 05:47:32.249135 secure task start!
602 05:47:32.249531 high task start!
603 05:47:32.253236 low task start!
604 05:47:32.253660 run into bl31
605 05:47:32.259942 NOTICE: BL31: v1.3(release):4fc40b1
606 05:47:32.267763 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 05:47:32.268253 NOTICE: BL31: G12A normal boot!
608 05:47:32.293132 NOTICE: BL31: BL33 decompress pass
609 05:47:32.298772 ERROR: Error initializing runtime service opteed_fast
610 05:47:33.531750
611 05:47:33.532225
612 05:47:33.540287 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 05:47:33.540616
614 05:47:33.540838 Model: Libre Computer AML-A311D-CC Alta
615 05:47:33.748854 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 05:47:33.772285 DRAM: 2 GiB (effective 3.8 GiB)
617 05:47:33.915201 Core: 408 devices, 31 uclasses, devicetree: separate
618 05:47:33.920086 WDT: Not starting watchdog@f0d0
619 05:47:33.953256 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 05:47:33.965565 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 05:47:33.970634 ** Bad device specification mmc 0 **
622 05:47:33.981036 Card did not respond to voltage select! : -110
623 05:47:33.988645 ** Bad device specification mmc 0 **
624 05:47:33.989145 Couldn't find partition mmc 0
625 05:47:33.996854 Card did not respond to voltage select! : -110
626 05:47:34.002335 ** Bad device specification mmc 0 **
627 05:47:34.002798 Couldn't find partition mmc 0
628 05:47:34.007423 Error: could not access storage.
629 05:47:34.351167 Net: eth0: ethernet@ff3f0000
630 05:47:34.351825 starting USB...
631 05:47:34.602925 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 05:47:34.603358 Starting the controller
633 05:47:34.609832 USB XHCI 1.10
634 05:47:36.319151 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 05:47:36.319589 bl2_stage_init 0x01
636 05:47:36.319815 bl2_stage_init 0x81
637 05:47:36.324833 hw id: 0x0000 - pwm id 0x01
638 05:47:36.325442 bl2_stage_init 0xc1
639 05:47:36.325924 bl2_stage_init 0x02
640 05:47:36.326385
641 05:47:36.330451 L0:00000000
642 05:47:36.331235 L1:20000703
643 05:47:36.331744 L2:00008067
644 05:47:36.332241 L3:14000000
645 05:47:36.335957 B2:00402000
646 05:47:36.336566 B1:e0f83180
647 05:47:36.337018
648 05:47:36.337459 TE: 58159
649 05:47:36.337904
650 05:47:36.341350 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 05:47:36.341886
652 05:47:36.342329 Board ID = 1
653 05:47:36.347083 Set A53 clk to 24M
654 05:47:36.347612 Set A73 clk to 24M
655 05:47:36.348082 Set clk81 to 24M
656 05:47:36.352671 A53 clk: 1200 MHz
657 05:47:36.353059 A73 clk: 1200 MHz
658 05:47:36.353532 CLK81: 166.6M
659 05:47:36.353801 smccc: 00012ab5
660 05:47:36.358233 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 05:47:36.364025 board id: 1
662 05:47:36.369911 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 05:47:36.380529 fw parse done
664 05:47:36.386540 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 05:47:36.428942 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 05:47:36.439915 PIEI prepare done
667 05:47:36.440518 fastboot data load
668 05:47:36.440877 fastboot data verify
669 05:47:36.445432 verify result: 266
670 05:47:36.451027 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 05:47:36.451510 LPDDR4 probe
672 05:47:36.451934 ddr clk to 1584MHz
673 05:47:36.458991 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 05:47:36.496352
675 05:47:36.496977 dmc_version 0001
676 05:47:36.502907 Check phy result
677 05:47:36.508826 INFO : End of CA training
678 05:47:36.509328 INFO : End of initialization
679 05:47:36.514367 INFO : Training has run successfully!
680 05:47:36.514849 Check phy result
681 05:47:36.519960 INFO : End of initialization
682 05:47:36.520474 INFO : End of read enable training
683 05:47:36.525638 INFO : End of fine write leveling
684 05:47:36.531247 INFO : End of Write leveling coarse delay
685 05:47:36.531730 INFO : Training has run successfully!
686 05:47:36.532189 Check phy result
687 05:47:36.536873 INFO : End of initialization
688 05:47:36.537425 INFO : End of read dq deskew training
689 05:47:36.542436 INFO : End of MPR read delay center optimization
690 05:47:36.548098 INFO : End of write delay center optimization
691 05:47:36.553600 INFO : End of read delay center optimization
692 05:47:36.554077 INFO : End of max read latency training
693 05:47:36.559141 INFO : Training has run successfully!
694 05:47:36.559617 1D training succeed
695 05:47:36.568487 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 05:47:36.616145 Check phy result
697 05:47:36.616742 INFO : End of initialization
698 05:47:36.637801 INFO : End of 2D read delay Voltage center optimization
699 05:47:36.658016 INFO : End of 2D read delay Voltage center optimization
700 05:47:36.710079 INFO : End of 2D write delay Voltage center optimization
701 05:47:36.759603 INFO : End of 2D write delay Voltage center optimization
702 05:47:36.765011 INFO : Training has run successfully!
703 05:47:36.765493
704 05:47:36.765919 channel==0
705 05:47:36.770772 RxClkDly_Margin_A0==88 ps 9
706 05:47:36.771141 TxDqDly_Margin_A0==98 ps 10
707 05:47:36.774077 RxClkDly_Margin_A1==88 ps 9
708 05:47:36.774423 TxDqDly_Margin_A1==98 ps 10
709 05:47:36.779494 TrainedVREFDQ_A0==74
710 05:47:36.779845 TrainedVREFDQ_A1==75
711 05:47:36.785070 VrefDac_Margin_A0==25
712 05:47:36.785419 DeviceVref_Margin_A0==40
713 05:47:36.785688 VrefDac_Margin_A1==25
714 05:47:36.790652 DeviceVref_Margin_A1==39
715 05:47:36.790995
716 05:47:36.791243
717 05:47:36.791491 channel==1
718 05:47:36.791735 RxClkDly_Margin_A0==98 ps 10
719 05:47:36.796255 TxDqDly_Margin_A0==88 ps 9
720 05:47:36.796603 RxClkDly_Margin_A1==98 ps 10
721 05:47:36.801836 TxDqDly_Margin_A1==88 ps 9
722 05:47:36.802199 TrainedVREFDQ_A0==77
723 05:47:36.802452 TrainedVREFDQ_A1==77
724 05:47:36.807497 VrefDac_Margin_A0==22
725 05:47:36.807849 DeviceVref_Margin_A0==37
726 05:47:36.813359 VrefDac_Margin_A1==22
727 05:47:36.813708 DeviceVref_Margin_A1==37
728 05:47:36.813948
729 05:47:36.818663 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 05:47:36.818998
731 05:47:36.846521 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 05:47:36.852164 2D training succeed
733 05:47:36.857770 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 05:47:36.858110 auto size-- 65535DDR cs0 size: 2048MB
735 05:47:36.863366 DDR cs1 size: 2048MB
736 05:47:36.863711 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 05:47:36.868935 cs0 DataBus test pass
738 05:47:36.869265 cs1 DataBus test pass
739 05:47:36.869501 cs0 AddrBus test pass
740 05:47:36.874524 cs1 AddrBus test pass
741 05:47:36.874865
742 05:47:36.875101 100bdlr_step_size ps== 420
743 05:47:36.875344 result report
744 05:47:36.880159 boot times 0Enable ddr reg access
745 05:47:36.887863 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 05:47:36.901444 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 05:47:37.475213 0.0;M3 CHK:0;cm4_sp_mode 0
748 05:47:37.475833 MVN_1=0x00000000
749 05:47:37.480607 MVN_2=0x00000000
750 05:47:37.486359 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 05:47:37.486900 OPS=0x10
752 05:47:37.487307 ring efuse init
753 05:47:37.487703 chipver efuse init
754 05:47:37.494568 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 05:47:37.495033 [0.018961 Inits done]
756 05:47:37.501127 secure task start!
757 05:47:37.501621 high task start!
758 05:47:37.502018 low task start!
759 05:47:37.502429 run into bl31
760 05:47:37.508833 NOTICE: BL31: v1.3(release):4fc40b1
761 05:47:37.515550 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 05:47:37.516078 NOTICE: BL31: G12A normal boot!
763 05:47:37.542486 NOTICE: BL31: BL33 decompress pass
764 05:47:37.547272 ERROR: Error initializing runtime service opteed_fast
765 05:47:38.781067
766 05:47:38.781679
767 05:47:38.789469 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 05:47:38.790004
769 05:47:38.790438 Model: Libre Computer AML-A311D-CC Alta
770 05:47:38.997933 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 05:47:39.021329 DRAM: 2 GiB (effective 3.8 GiB)
772 05:47:39.164370 Core: 408 devices, 31 uclasses, devicetree: separate
773 05:47:39.170163 WDT: Not starting watchdog@f0d0
774 05:47:39.202535 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 05:47:39.214928 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 05:47:39.219862 ** Bad device specification mmc 0 **
777 05:47:39.230363 Card did not respond to voltage select! : -110
778 05:47:39.237895 ** Bad device specification mmc 0 **
779 05:47:39.238479 Couldn't find partition mmc 0
780 05:47:39.246256 Card did not respond to voltage select! : -110
781 05:47:39.251738 ** Bad device specification mmc 0 **
782 05:47:39.252336 Couldn't find partition mmc 0
783 05:47:39.256797 Error: could not access storage.
784 05:47:39.599307 Net: eth0: ethernet@ff3f0000
785 05:47:39.599943 starting USB...
786 05:47:39.851126 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 05:47:39.851744 Starting the controller
788 05:47:39.857991 USB XHCI 1.10
789 05:47:42.019201 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
790 05:47:42.019885 bl2_stage_init 0x81
791 05:47:42.024701 hw id: 0x0000 - pwm id 0x01
792 05:47:42.024996 bl2_stage_init 0xc1
793 05:47:42.025217 bl2_stage_init 0x02
794 05:47:42.025560
795 05:47:42.030414 L0:00000000
796 05:47:42.030913 L1:20000703
797 05:47:42.031366 L2:00008067
798 05:47:42.031792 L3:14000000
799 05:47:42.032156 B2:00402000
800 05:47:42.033076 B1:e0f83180
801 05:47:42.033525
802 05:47:42.033938 TE: 58150
803 05:47:42.034370
804 05:47:42.044282 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 05:47:42.044751
806 05:47:42.045165 Board ID = 1
807 05:47:42.045493 Set A53 clk to 24M
808 05:47:42.045705 Set A73 clk to 24M
809 05:47:42.050300 Set clk81 to 24M
810 05:47:42.050754 A53 clk: 1200 MHz
811 05:47:42.051163 A73 clk: 1200 MHz
812 05:47:42.055526 CLK81: 166.6M
813 05:47:42.055975 smccc: 00012aab
814 05:47:42.061028 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 05:47:42.061477 board id: 1
816 05:47:42.068790 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 05:47:42.080288 fw parse done
818 05:47:42.086237 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 05:47:42.128081 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 05:47:42.139946 PIEI prepare done
821 05:47:42.140504 fastboot data load
822 05:47:42.140931 fastboot data verify
823 05:47:42.145451 verify result: 266
824 05:47:42.151161 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 05:47:42.151665 LPDDR4 probe
826 05:47:42.152135 ddr clk to 1584MHz
827 05:47:42.159058 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 05:47:42.195867
829 05:47:42.196455 dmc_version 0001
830 05:47:42.202043 Check phy result
831 05:47:42.208806 INFO : End of CA training
832 05:47:42.209329 INFO : End of initialization
833 05:47:42.214427 INFO : Training has run successfully!
834 05:47:42.214909 Check phy result
835 05:47:42.220149 INFO : End of initialization
836 05:47:42.220624 INFO : End of read enable training
837 05:47:42.225652 INFO : End of fine write leveling
838 05:47:42.231219 INFO : End of Write leveling coarse delay
839 05:47:42.231689 INFO : Training has run successfully!
840 05:47:42.232194 Check phy result
841 05:47:42.236850 INFO : End of initialization
842 05:47:42.237304 INFO : End of read dq deskew training
843 05:47:42.242446 INFO : End of MPR read delay center optimization
844 05:47:42.248116 INFO : End of write delay center optimization
845 05:47:42.253633 INFO : End of read delay center optimization
846 05:47:42.254127 INFO : End of max read latency training
847 05:47:42.259344 INFO : Training has run successfully!
848 05:47:42.259851 1D training succeed
849 05:47:42.267518 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 05:47:42.316068 Check phy result
851 05:47:42.316635 INFO : End of initialization
852 05:47:42.337873 INFO : End of 2D read delay Voltage center optimization
853 05:47:42.357300 INFO : End of 2D read delay Voltage center optimization
854 05:47:42.409478 INFO : End of 2D write delay Voltage center optimization
855 05:47:42.458606 INFO : End of 2D write delay Voltage center optimization
856 05:47:42.464420 INFO : Training has run successfully!
857 05:47:42.464877
858 05:47:42.465288 channel==0
859 05:47:42.469769 RxClkDly_Margin_A0==88 ps 9
860 05:47:42.470215 TxDqDly_Margin_A0==98 ps 10
861 05:47:42.475424 RxClkDly_Margin_A1==78 ps 8
862 05:47:42.475900 TxDqDly_Margin_A1==98 ps 10
863 05:47:42.476371 TrainedVREFDQ_A0==74
864 05:47:42.480970 TrainedVREFDQ_A1==75
865 05:47:42.481470 VrefDac_Margin_A0==25
866 05:47:42.481902 DeviceVref_Margin_A0==40
867 05:47:42.486533 VrefDac_Margin_A1==25
868 05:47:42.486996 DeviceVref_Margin_A1==39
869 05:47:42.487381
870 05:47:42.487769
871 05:47:42.492308 channel==1
872 05:47:42.492750 RxClkDly_Margin_A0==88 ps 9
873 05:47:42.493142 TxDqDly_Margin_A0==88 ps 9
874 05:47:42.497787 RxClkDly_Margin_A1==88 ps 9
875 05:47:42.498220 TxDqDly_Margin_A1==98 ps 10
876 05:47:42.503422 TrainedVREFDQ_A0==77
877 05:47:42.503850 TrainedVREFDQ_A1==77
878 05:47:42.504276 VrefDac_Margin_A0==23
879 05:47:42.509141 DeviceVref_Margin_A0==37
880 05:47:42.509562 VrefDac_Margin_A1==24
881 05:47:42.514664 DeviceVref_Margin_A1==37
882 05:47:42.515103
883 05:47:42.515493 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 05:47:42.515882
885 05:47:42.547784 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
886 05:47:42.548389 2D training succeed
887 05:47:42.553472 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 05:47:42.558714 auto size-- 65535DDR cs0 size: 2048MB
889 05:47:42.559153 DDR cs1 size: 2048MB
890 05:47:42.564334 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 05:47:42.564768 cs0 DataBus test pass
892 05:47:42.569947 cs1 DataBus test pass
893 05:47:42.570452 cs0 AddrBus test pass
894 05:47:42.570847 cs1 AddrBus test pass
895 05:47:42.571233
896 05:47:42.575524 100bdlr_step_size ps== 420
897 05:47:42.575973 result report
898 05:47:42.581211 boot times 0Enable ddr reg access
899 05:47:42.586985 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 05:47:42.600432 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 05:47:43.174289 0.0;M3 CHK:0;cm4_sp_mode 0
902 05:47:43.174981 MVN_1=0x00000000
903 05:47:43.179692 MVN_2=0x00000000
904 05:47:43.185331 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 05:47:43.185828 OPS=0x10
906 05:47:43.186251 ring efuse init
907 05:47:43.186662 chipver efuse init
908 05:47:43.190968 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 05:47:43.196575 [0.018961 Inits done]
910 05:47:43.197136 secure task start!
911 05:47:43.197549 high task start!
912 05:47:43.201049 low task start!
913 05:47:43.201502 run into bl31
914 05:47:43.207755 NOTICE: BL31: v1.3(release):4fc40b1
915 05:47:43.215606 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 05:47:43.216181 NOTICE: BL31: G12A normal boot!
917 05:47:43.241071 NOTICE: BL31: BL33 decompress pass
918 05:47:43.248575 ERROR: Error initializing runtime service opteed_fast
919 05:47:44.479609
920 05:47:44.480094
921 05:47:44.487927 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 05:47:44.488407
923 05:47:44.488742 Model: Libre Computer AML-A311D-CC Alta
924 05:47:44.696493 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 05:47:44.719721 DRAM: 2 GiB (effective 3.8 GiB)
926 05:47:44.862769 Core: 408 devices, 31 uclasses, devicetree: separate
927 05:47:44.868617 WDT: Not starting watchdog@f0d0
928 05:47:44.900870 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 05:47:44.913398 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 05:47:44.918298 ** Bad device specification mmc 0 **
931 05:47:44.928645 Card did not respond to voltage select! : -110
932 05:47:44.936272 ** Bad device specification mmc 0 **
933 05:47:44.936716 Couldn't find partition mmc 0
934 05:47:44.944627 Card did not respond to voltage select! : -110
935 05:47:44.950140 ** Bad device specification mmc 0 **
936 05:47:44.950582 Couldn't find partition mmc 0
937 05:47:44.955232 Error: could not access storage.
938 05:47:45.297818 Net: eth0: ethernet@ff3f0000
939 05:47:45.298438 starting USB...
940 05:47:45.549725 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 05:47:45.550360 Starting the controller
942 05:47:45.556596 USB XHCI 1.10
943 05:47:47.110567 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
944 05:47:47.118942 scanning usb for storage devices... 0 Storage Device(s) found
946 05:47:47.170616 Hit any key to stop autoboot: 1
947 05:47:47.171504 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
948 05:47:47.172129 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
949 05:47:47.172625 Setting prompt string to ['=>']
950 05:47:47.173116 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
951 05:47:47.186342 0
952 05:47:47.187199 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
953 05:47:47.187686 Sending with 10 millisecond of delay
955 05:47:48.323043 => setenv autoload no
956 05:47:48.333850 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
957 05:47:48.338761 setenv autoload no
958 05:47:48.339481 Sending with 10 millisecond of delay
960 05:47:50.136805 => setenv initrd_high 0xffffffff
961 05:47:50.147641 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
962 05:47:50.148399 setenv initrd_high 0xffffffff
963 05:47:50.148939 Sending with 10 millisecond of delay
965 05:47:51.766164 => setenv fdt_high 0xffffffff
966 05:47:51.777011 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
967 05:47:51.777960 setenv fdt_high 0xffffffff
968 05:47:51.778697 Sending with 10 millisecond of delay
970 05:47:52.070442 => dhcp
971 05:47:52.081274 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
972 05:47:52.082137 dhcp
973 05:47:52.082584 Speed: 1000, full duplex
974 05:47:52.083001 BOOTP broadcast 1
975 05:47:52.329349 BOOTP broadcast 2
976 05:47:52.391959 DHCP client bound to address 192.168.6.33 (310 ms)
977 05:47:52.392806 Sending with 10 millisecond of delay
979 05:47:54.069280 => setenv serverip 192.168.6.2
980 05:47:54.080051 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
981 05:47:54.080887 setenv serverip 192.168.6.2
982 05:47:54.081659 Sending with 10 millisecond of delay
984 05:47:57.805820 => tftpboot 0x01080000 796782/tftp-deploy-5uq0a8fw/kernel/uImage
985 05:47:57.816611 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
986 05:47:57.817419 tftpboot 0x01080000 796782/tftp-deploy-5uq0a8fw/kernel/uImage
987 05:47:57.817862 Speed: 1000, full duplex
988 05:47:57.818277 Using ethernet@ff3f0000 device
989 05:47:57.819383 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
990 05:47:57.824845 Filename '796782/tftp-deploy-5uq0a8fw/kernel/uImage'.
991 05:47:57.828729 Load address: 0x1080000
992 05:48:01.395199 Loading: *################################################## 43.6 MiB
993 05:48:01.395817 12.2 MiB/s
994 05:48:01.396302 done
995 05:48:01.398902 Bytes transferred = 45713984 (2b98a40 hex)
996 05:48:01.399686 Sending with 10 millisecond of delay
998 05:48:06.087041 => tftpboot 0x08000000 796782/tftp-deploy-5uq0a8fw/ramdisk/ramdisk.cpio.gz.uboot
999 05:48:06.097827 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1000 05:48:06.098643 tftpboot 0x08000000 796782/tftp-deploy-5uq0a8fw/ramdisk/ramdisk.cpio.gz.uboot
1001 05:48:06.099084 Speed: 1000, full duplex
1002 05:48:06.099499 Using ethernet@ff3f0000 device
1003 05:48:06.100673 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1004 05:48:06.112536 Filename '796782/tftp-deploy-5uq0a8fw/ramdisk/ramdisk.cpio.gz.uboot'.
1005 05:48:06.113026 Load address: 0x8000000
1006 05:48:08.389570 Loading: *################################################# UDP wrong checksum 00000005 0000a1e4
1007 05:48:10.808898 UDP wrong checksum 000000ff 0000dbdc
1008 05:48:10.819640 UDP wrong checksum 000000ff 000060cf
1009 05:48:13.392436 T UDP wrong checksum 00000005 0000a1e4
1010 05:48:23.392993 T UDP wrong checksum 00000005 0000a1e4
1011 05:48:43.396886 T T T T UDP wrong checksum 00000005 0000a1e4
1012 05:49:03.403658 T T T T
1013 05:49:03.404374 Retry count exceeded; starting again
1015 05:49:03.405803 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1018 05:49:03.407642 end: 2.4 uboot-commands (duration 00:01:47) [common]
1020 05:49:03.409107 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1022 05:49:03.410108 end: 2 uboot-action (duration 00:01:47) [common]
1024 05:49:03.411617 Cleaning after the job
1025 05:49:03.412185 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/ramdisk
1026 05:49:03.413587 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/kernel
1027 05:49:03.420830 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/dtb
1028 05:49:03.422032 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/nfsrootfs
1029 05:49:03.470353 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796782/tftp-deploy-5uq0a8fw/modules
1030 05:49:03.481642 start: 4.1 power-off (timeout 00:00:30) [common]
1031 05:49:03.482231 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1032 05:49:03.514970 >> OK - accepted request
1033 05:49:03.517116 Returned 0 in 0 seconds
1034 05:49:03.618248 end: 4.1 power-off (duration 00:00:00) [common]
1036 05:49:03.619889 start: 4.2 read-feedback (timeout 00:10:00) [common]
1037 05:49:03.621040 Listened to connection for namespace 'common' for up to 1s
1038 05:49:04.621804 Finalising connection for namespace 'common'
1039 05:49:04.622687 Disconnecting from shell: Finalise
1040 05:49:04.623021 =>
1041 05:49:04.723943 end: 4.2 read-feedback (duration 00:00:01) [common]
1042 05:49:04.724751 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796782
1043 05:49:07.249559 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796782
1044 05:49:07.250162 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.