Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:13:53.464949 lava-dispatcher, installed at version: 2024.01
2 05:13:53.465779 start: 0 validate
3 05:13:53.466287 Start time: 2024-10-03 05:13:53.466255+00:00 (UTC)
4 05:13:53.466857 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:13:53.467424 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:13:53.507761 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:13:53.508358 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 05:13:54.557069 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:13:54.557711 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:14:01.637580 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:14:01.638077 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 05:14:02.703805 validate duration: 9.24
14 05:14:02.705757 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:14:02.706567 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:14:02.707321 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:14:02.708779 Not decompressing ramdisk as can be used compressed.
18 05:14:02.709747 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:14:02.710342 saving as /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/ramdisk/rootfs.cpio.gz
20 05:14:02.710974 total size: 8181887 (7 MB)
21 05:14:02.760391 progress 0 % (0 MB)
22 05:14:02.773613 progress 5 % (0 MB)
23 05:14:02.786254 progress 10 % (0 MB)
24 05:14:02.799888 progress 15 % (1 MB)
25 05:14:02.806339 progress 20 % (1 MB)
26 05:14:02.812998 progress 25 % (1 MB)
27 05:14:02.819160 progress 30 % (2 MB)
28 05:14:02.825800 progress 35 % (2 MB)
29 05:14:02.831855 progress 40 % (3 MB)
30 05:14:02.838409 progress 45 % (3 MB)
31 05:14:02.844586 progress 50 % (3 MB)
32 05:14:02.851356 progress 55 % (4 MB)
33 05:14:02.857799 progress 60 % (4 MB)
34 05:14:02.865361 progress 65 % (5 MB)
35 05:14:02.872459 progress 70 % (5 MB)
36 05:14:02.879360 progress 75 % (5 MB)
37 05:14:02.885551 progress 80 % (6 MB)
38 05:14:02.892290 progress 85 % (6 MB)
39 05:14:02.898435 progress 90 % (7 MB)
40 05:14:02.905094 progress 95 % (7 MB)
41 05:14:02.911117 progress 100 % (7 MB)
42 05:14:02.911931 7 MB downloaded in 0.20 s (38.83 MB/s)
43 05:14:02.912707 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:14:02.913932 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:14:02.914349 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:14:02.914728 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:14:02.915358 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 05:14:02.915690 saving as /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/kernel/Image
50 05:14:02.916014 total size: 66101760 (63 MB)
51 05:14:02.916317 No compression specified
52 05:14:02.955594 progress 0 % (0 MB)
53 05:14:02.995376 progress 5 % (3 MB)
54 05:14:03.035251 progress 10 % (6 MB)
55 05:14:03.075843 progress 15 % (9 MB)
56 05:14:03.116684 progress 20 % (12 MB)
57 05:14:03.155966 progress 25 % (15 MB)
58 05:14:03.195761 progress 30 % (18 MB)
59 05:14:03.235133 progress 35 % (22 MB)
60 05:14:03.274428 progress 40 % (25 MB)
61 05:14:03.313522 progress 45 % (28 MB)
62 05:14:03.353133 progress 50 % (31 MB)
63 05:14:03.392499 progress 55 % (34 MB)
64 05:14:03.431397 progress 60 % (37 MB)
65 05:14:03.470578 progress 65 % (41 MB)
66 05:14:03.509937 progress 70 % (44 MB)
67 05:14:03.550018 progress 75 % (47 MB)
68 05:14:03.589974 progress 80 % (50 MB)
69 05:14:03.630081 progress 85 % (53 MB)
70 05:14:03.670043 progress 90 % (56 MB)
71 05:14:03.710657 progress 95 % (59 MB)
72 05:14:03.750825 progress 100 % (63 MB)
73 05:14:03.751411 63 MB downloaded in 0.84 s (75.46 MB/s)
74 05:14:03.751886 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:14:03.752757 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:14:03.753034 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:14:03.753300 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:14:03.753767 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 05:14:03.754039 saving as /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/dtb/meson-g12b-a311d-libretech-cc.dtb
81 05:14:03.754249 total size: 54703 (0 MB)
82 05:14:03.754459 No compression specified
83 05:14:03.794292 progress 59 % (0 MB)
84 05:14:03.795140 progress 100 % (0 MB)
85 05:14:03.795701 0 MB downloaded in 0.04 s (1.26 MB/s)
86 05:14:03.796222 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:14:03.797057 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:14:03.797340 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:14:03.797605 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:14:03.798105 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 05:14:03.798379 saving as /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/modules/modules.tar
93 05:14:03.798583 total size: 16285276 (15 MB)
94 05:14:03.798794 Using unxz to decompress xz
95 05:14:03.842888 progress 0 % (0 MB)
96 05:14:03.949404 progress 5 % (0 MB)
97 05:14:04.071148 progress 10 % (1 MB)
98 05:14:04.187928 progress 15 % (2 MB)
99 05:14:04.306362 progress 20 % (3 MB)
100 05:14:04.422344 progress 25 % (3 MB)
101 05:14:04.536971 progress 30 % (4 MB)
102 05:14:04.646338 progress 35 % (5 MB)
103 05:14:04.760339 progress 40 % (6 MB)
104 05:14:04.876882 progress 45 % (7 MB)
105 05:14:04.987257 progress 50 % (7 MB)
106 05:14:05.102306 progress 55 % (8 MB)
107 05:14:05.220038 progress 60 % (9 MB)
108 05:14:05.337810 progress 65 % (10 MB)
109 05:14:05.449865 progress 70 % (10 MB)
110 05:14:05.589846 progress 75 % (11 MB)
111 05:14:05.727114 progress 80 % (12 MB)
112 05:14:05.840156 progress 85 % (13 MB)
113 05:14:05.963292 progress 90 % (14 MB)
114 05:14:06.069336 progress 95 % (14 MB)
115 05:14:06.184545 progress 100 % (15 MB)
116 05:14:06.200173 15 MB downloaded in 2.40 s (6.47 MB/s)
117 05:14:06.201130 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:14:06.202734 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:14:06.203255 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 05:14:06.203774 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 05:14:06.204311 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:14:06.204817 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 05:14:06.205809 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb
125 05:14:06.206639 makedir: /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin
126 05:14:06.207266 makedir: /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/tests
127 05:14:06.207871 makedir: /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/results
128 05:14:06.208529 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-add-keys
129 05:14:06.209483 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-add-sources
130 05:14:06.210400 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-background-process-start
131 05:14:06.211322 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-background-process-stop
132 05:14:06.212328 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-common-functions
133 05:14:06.213245 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-echo-ipv4
134 05:14:06.214135 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-install-packages
135 05:14:06.215016 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-installed-packages
136 05:14:06.215886 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-os-build
137 05:14:06.216816 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-probe-channel
138 05:14:06.217707 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-probe-ip
139 05:14:06.218581 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-target-ip
140 05:14:06.219461 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-target-mac
141 05:14:06.220451 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-target-storage
142 05:14:06.221385 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-test-case
143 05:14:06.222273 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-test-event
144 05:14:06.223153 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-test-feedback
145 05:14:06.224064 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-test-raise
146 05:14:06.224975 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-test-reference
147 05:14:06.225859 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-test-runner
148 05:14:06.226741 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-test-set
149 05:14:06.227628 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-test-shell
150 05:14:06.228556 Updating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-install-packages (oe)
151 05:14:06.229516 Updating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/bin/lava-installed-packages (oe)
152 05:14:06.230332 Creating /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/environment
153 05:14:06.231033 LAVA metadata
154 05:14:06.231512 - LAVA_JOB_ID=796465
155 05:14:06.231937 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:14:06.232643 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 05:14:06.234423 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:14:06.235012 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 05:14:06.235424 skipped lava-vland-overlay
160 05:14:06.235911 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:14:06.236461 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 05:14:06.236887 skipped lava-multinode-overlay
163 05:14:06.237368 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:14:06.237866 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 05:14:06.238340 Loading test definitions
166 05:14:06.238884 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 05:14:06.239322 Using /lava-796465 at stage 0
168 05:14:06.241545 uuid=796465_1.5.2.4.1 testdef=None
169 05:14:06.242127 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:14:06.242648 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 05:14:06.245137 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:14:06.245990 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 05:14:06.248292 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:14:06.249146 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 05:14:06.251347 runner path: /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/0/tests/0_dmesg test_uuid 796465_1.5.2.4.1
178 05:14:06.252015 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:14:06.252814 Creating lava-test-runner.conf files
181 05:14:06.253020 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796465/lava-overlay-3h5e94pb/lava-796465/0 for stage 0
182 05:14:06.253367 - 0_dmesg
183 05:14:06.253724 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:14:06.254007 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 05:14:06.277726 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:14:06.278129 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 05:14:06.278395 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:14:06.278665 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:14:06.278925 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 05:14:07.279923 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:14:07.280439 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 05:14:07.280692 extracting modules file /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796465/extract-overlay-ramdisk-7oqceqsd/ramdisk
193 05:14:08.841723 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 05:14:08.842203 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 05:14:08.842478 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796465/compress-overlay-etpe326z/overlay-1.5.2.5.tar.gz to ramdisk
196 05:14:08.842693 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796465/compress-overlay-etpe326z/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796465/extract-overlay-ramdisk-7oqceqsd/ramdisk
197 05:14:08.873025 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:14:08.873448 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 05:14:08.873719 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 05:14:08.873948 Converting downloaded kernel to a uImage
201 05:14:08.874251 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/kernel/Image /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/kernel/uImage
202 05:14:09.554818 output: Image Name:
203 05:14:09.555242 output: Created: Thu Oct 3 05:14:08 2024
204 05:14:09.555451 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:14:09.555656 output: Data Size: 66101760 Bytes = 64552.50 KiB = 63.04 MiB
206 05:14:09.555858 output: Load Address: 01080000
207 05:14:09.556100 output: Entry Point: 01080000
208 05:14:09.556303 output:
209 05:14:09.556637 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 05:14:09.556903 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 05:14:09.557170 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 05:14:09.557421 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:14:09.557677 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 05:14:09.557927 Building ramdisk /var/lib/lava/dispatcher/tmp/796465/extract-overlay-ramdisk-7oqceqsd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796465/extract-overlay-ramdisk-7oqceqsd/ramdisk
215 05:14:13.082260 >> 256175 blocks
216 05:14:24.771027 Adding RAMdisk u-boot header.
217 05:14:24.771456 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796465/extract-overlay-ramdisk-7oqceqsd/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796465/extract-overlay-ramdisk-7oqceqsd/ramdisk.cpio.gz.uboot
218 05:14:25.172764 output: Image Name:
219 05:14:25.173214 output: Created: Thu Oct 3 05:14:24 2024
220 05:14:25.173483 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:14:25.173730 output: Data Size: 33830255 Bytes = 33037.36 KiB = 32.26 MiB
222 05:14:25.173961 output: Load Address: 00000000
223 05:14:25.174180 output: Entry Point: 00000000
224 05:14:25.174391 output:
225 05:14:25.175225 rename /var/lib/lava/dispatcher/tmp/796465/extract-overlay-ramdisk-7oqceqsd/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/ramdisk/ramdisk.cpio.gz.uboot
226 05:14:25.175695 end: 1.5.8 compress-ramdisk (duration 00:00:16) [common]
227 05:14:25.176059 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 05:14:25.176363 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 05:14:25.176617 No LXC device requested
230 05:14:25.176882 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:14:25.177156 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 05:14:25.177429 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:14:25.177645 Checking files for TFTP limit of 4294967296 bytes.
234 05:14:25.179106 end: 1 tftp-deploy (duration 00:00:22) [common]
235 05:14:25.179441 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:14:25.179720 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:14:25.180002 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:14:25.180276 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:14:25.180566 Using kernel file from prepare-kernel: 796465/tftp-deploy-xxnkjl66/kernel/uImage
240 05:14:25.180897 substitutions:
241 05:14:25.181108 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:14:25.181311 - {DTB_ADDR}: 0x01070000
243 05:14:25.181512 - {DTB}: 796465/tftp-deploy-xxnkjl66/dtb/meson-g12b-a311d-libretech-cc.dtb
244 05:14:25.181712 - {INITRD}: 796465/tftp-deploy-xxnkjl66/ramdisk/ramdisk.cpio.gz.uboot
245 05:14:25.181916 - {KERNEL_ADDR}: 0x01080000
246 05:14:25.182122 - {KERNEL}: 796465/tftp-deploy-xxnkjl66/kernel/uImage
247 05:14:25.182323 - {LAVA_MAC}: None
248 05:14:25.182545 - {PRESEED_CONFIG}: None
249 05:14:25.182743 - {PRESEED_LOCAL}: None
250 05:14:25.182938 - {RAMDISK_ADDR}: 0x08000000
251 05:14:25.183132 - {RAMDISK}: 796465/tftp-deploy-xxnkjl66/ramdisk/ramdisk.cpio.gz.uboot
252 05:14:25.183331 - {ROOT_PART}: None
253 05:14:25.183527 - {ROOT}: None
254 05:14:25.183721 - {SERVER_IP}: 192.168.6.2
255 05:14:25.183918 - {TEE_ADDR}: 0x83000000
256 05:14:25.184138 - {TEE}: None
257 05:14:25.184337 Parsed boot commands:
258 05:14:25.184528 - setenv autoload no
259 05:14:25.184724 - setenv initrd_high 0xffffffff
260 05:14:25.184917 - setenv fdt_high 0xffffffff
261 05:14:25.185113 - dhcp
262 05:14:25.185306 - setenv serverip 192.168.6.2
263 05:14:25.185498 - tftpboot 0x01080000 796465/tftp-deploy-xxnkjl66/kernel/uImage
264 05:14:25.185694 - tftpboot 0x08000000 796465/tftp-deploy-xxnkjl66/ramdisk/ramdisk.cpio.gz.uboot
265 05:14:25.185895 - tftpboot 0x01070000 796465/tftp-deploy-xxnkjl66/dtb/meson-g12b-a311d-libretech-cc.dtb
266 05:14:25.186095 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:14:25.186299 - bootm 0x01080000 0x08000000 0x01070000
268 05:14:25.186583 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:14:25.187363 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:14:25.187602 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 05:14:25.198917 Setting prompt string to ['lava-test: # ']
273 05:14:25.199959 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:14:25.200425 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:14:25.200762 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:14:25.201063 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:14:25.201746 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 05:14:25.249592 >> OK - accepted request
279 05:14:25.252480 Returned 0 in 0 seconds
280 05:14:25.353740 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:14:25.355627 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:14:25.356379 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:14:25.356960 Setting prompt string to ['Hit any key to stop autoboot']
285 05:14:25.357458 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:14:25.359243 Trying 192.168.56.21...
287 05:14:25.359793 Connected to conserv1.
288 05:14:25.360299 Escape character is '^]'.
289 05:14:25.360772
290 05:14:25.361234 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 05:14:25.361703
292 05:14:37.186727 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 05:14:37.187170 bl2_stage_init 0x01
294 05:14:37.187407 bl2_stage_init 0x81
295 05:14:37.192278 hw id: 0x0000 - pwm id 0x01
296 05:14:37.192599 bl2_stage_init 0xc1
297 05:14:37.192821 bl2_stage_init 0x02
298 05:14:37.193040
299 05:14:37.197825 L0:00000000
300 05:14:37.198079 L1:20000703
301 05:14:37.198289 L2:00008067
302 05:14:37.198489 L3:14000000
303 05:14:37.203446 B2:00402000
304 05:14:37.203700 B1:e0f83180
305 05:14:37.203903
306 05:14:37.204140 TE: 58159
307 05:14:37.204344
308 05:14:37.209028 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 05:14:37.209306
310 05:14:37.209515 Board ID = 1
311 05:14:37.214662 Set A53 clk to 24M
312 05:14:37.214933 Set A73 clk to 24M
313 05:14:37.215142 Set clk81 to 24M
314 05:14:37.220255 A53 clk: 1200 MHz
315 05:14:37.220522 A73 clk: 1200 MHz
316 05:14:37.220720 CLK81: 166.6M
317 05:14:37.220914 smccc: 00012ab5
318 05:14:37.225830 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 05:14:37.231429 board id: 1
320 05:14:37.237335 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:14:37.248190 fw parse done
322 05:14:37.253955 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:14:37.296631 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:14:37.307491 PIEI prepare done
325 05:14:37.307949 fastboot data load
326 05:14:37.308404 fastboot data verify
327 05:14:37.313231 verify result: 266
328 05:14:37.318735 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 05:14:37.319184 LPDDR4 probe
330 05:14:37.319587 ddr clk to 1584MHz
331 05:14:37.326745 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:14:37.364052
333 05:14:37.364561 dmc_version 0001
334 05:14:37.370657 Check phy result
335 05:14:37.376502 INFO : End of CA training
336 05:14:37.376981 INFO : End of initialization
337 05:14:37.382124 INFO : Training has run successfully!
338 05:14:37.382594 Check phy result
339 05:14:37.387724 INFO : End of initialization
340 05:14:37.388211 INFO : End of read enable training
341 05:14:37.393282 INFO : End of fine write leveling
342 05:14:37.398905 INFO : End of Write leveling coarse delay
343 05:14:37.399367 INFO : Training has run successfully!
344 05:14:37.399776 Check phy result
345 05:14:37.404521 INFO : End of initialization
346 05:14:37.404981 INFO : End of read dq deskew training
347 05:14:37.410127 INFO : End of MPR read delay center optimization
348 05:14:37.415777 INFO : End of write delay center optimization
349 05:14:37.421305 INFO : End of read delay center optimization
350 05:14:37.421756 INFO : End of max read latency training
351 05:14:37.426947 INFO : Training has run successfully!
352 05:14:37.427402 1D training succeed
353 05:14:37.436213 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:14:37.483740 Check phy result
355 05:14:37.484268 INFO : End of initialization
356 05:14:37.506297 INFO : End of 2D read delay Voltage center optimization
357 05:14:37.526304 INFO : End of 2D read delay Voltage center optimization
358 05:14:37.578308 INFO : End of 2D write delay Voltage center optimization
359 05:14:37.627474 INFO : End of 2D write delay Voltage center optimization
360 05:14:37.632942 INFO : Training has run successfully!
361 05:14:37.633417
362 05:14:37.633836 channel==0
363 05:14:37.638551 RxClkDly_Margin_A0==88 ps 9
364 05:14:37.638997 TxDqDly_Margin_A0==98 ps 10
365 05:14:37.644158 RxClkDly_Margin_A1==88 ps 9
366 05:14:37.644604 TxDqDly_Margin_A1==98 ps 10
367 05:14:37.645020 TrainedVREFDQ_A0==74
368 05:14:37.649761 TrainedVREFDQ_A1==74
369 05:14:37.650209 VrefDac_Margin_A0==24
370 05:14:37.650625 DeviceVref_Margin_A0==40
371 05:14:37.655328 VrefDac_Margin_A1==25
372 05:14:37.655777 DeviceVref_Margin_A1==40
373 05:14:37.656227
374 05:14:37.656642
375 05:14:37.661021 channel==1
376 05:14:37.661408 RxClkDly_Margin_A0==98 ps 10
377 05:14:37.661639 TxDqDly_Margin_A0==98 ps 10
378 05:14:37.666600 RxClkDly_Margin_A1==98 ps 10
379 05:14:37.667080 TxDqDly_Margin_A1==88 ps 9
380 05:14:37.672224 TrainedVREFDQ_A0==77
381 05:14:37.672708 TrainedVREFDQ_A1==77
382 05:14:37.673076 VrefDac_Margin_A0==22
383 05:14:37.677834 DeviceVref_Margin_A0==37
384 05:14:37.678181 VrefDac_Margin_A1==22
385 05:14:37.683430 DeviceVref_Margin_A1==37
386 05:14:37.683900
387 05:14:37.684302 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:14:37.689010
389 05:14:37.716977 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 05:14:37.717437 2D training succeed
391 05:14:37.722615 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:14:37.728218 auto size-- 65535DDR cs0 size: 2048MB
393 05:14:37.728568 DDR cs1 size: 2048MB
394 05:14:37.733863 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:14:37.734376 cs0 DataBus test pass
396 05:14:37.739415 cs1 DataBus test pass
397 05:14:37.739758 cs0 AddrBus test pass
398 05:14:37.740009 cs1 AddrBus test pass
399 05:14:37.740399
400 05:14:37.745121 100bdlr_step_size ps== 420
401 05:14:37.745696 result report
402 05:14:37.750718 boot times 0Enable ddr reg access
403 05:14:37.756214 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:14:37.769158 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 05:14:38.341462 0.0;M3 CHK:0;cm4_sp_mode 0
406 05:14:38.342081 MVN_1=0x00000000
407 05:14:38.347050 MVN_2=0x00000000
408 05:14:38.352804 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 05:14:38.353319 OPS=0x10
410 05:14:38.353782 ring efuse init
411 05:14:38.354226 chipver efuse init
412 05:14:38.360950 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 05:14:38.361489 [0.018961 Inits done]
414 05:14:38.368540 secure task start!
415 05:14:38.369055 high task start!
416 05:14:38.369511 low task start!
417 05:14:38.369955 run into bl31
418 05:14:38.375287 NOTICE: BL31: v1.3(release):4fc40b1
419 05:14:38.383019 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 05:14:38.383561 NOTICE: BL31: G12A normal boot!
421 05:14:38.408412 NOTICE: BL31: BL33 decompress pass
422 05:14:38.413116 ERROR: Error initializing runtime service opteed_fast
423 05:14:39.647019
424 05:14:39.647687
425 05:14:39.655402 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 05:14:39.655936
427 05:14:39.656431 Model: Libre Computer AML-A311D-CC Alta
428 05:14:39.864017 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 05:14:39.887315 DRAM: 2 GiB (effective 3.8 GiB)
430 05:14:40.030315 Core: 408 devices, 31 uclasses, devicetree: separate
431 05:14:40.036184 WDT: Not starting watchdog@f0d0
432 05:14:40.068350 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 05:14:40.080867 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 05:14:40.085815 ** Bad device specification mmc 0 **
435 05:14:40.096215 Card did not respond to voltage select! : -110
436 05:14:40.103849 ** Bad device specification mmc 0 **
437 05:14:40.104430 Couldn't find partition mmc 0
438 05:14:40.112315 Card did not respond to voltage select! : -110
439 05:14:40.117672 ** Bad device specification mmc 0 **
440 05:14:40.118198 Couldn't find partition mmc 0
441 05:14:40.121950 Error: could not access storage.
442 05:14:41.387233 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 05:14:41.387626 bl2_stage_init 0x01
444 05:14:41.387860 bl2_stage_init 0x81
445 05:14:41.392814 hw id: 0x0000 - pwm id 0x01
446 05:14:41.393089 bl2_stage_init 0xc1
447 05:14:41.393322 bl2_stage_init 0x02
448 05:14:41.393547
449 05:14:41.398471 L0:00000000
450 05:14:41.398804 L1:20000703
451 05:14:41.399092 L2:00008067
452 05:14:41.399363 L3:14000000
453 05:14:41.401337 B2:00402000
454 05:14:41.401657 B1:e0f83180
455 05:14:41.401916
456 05:14:41.402193 TE: 58159
457 05:14:41.402456
458 05:14:41.412567 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 05:14:41.413235
460 05:14:41.413780 Board ID = 1
461 05:14:41.414299 Set A53 clk to 24M
462 05:14:41.414810 Set A73 clk to 24M
463 05:14:41.418095 Set clk81 to 24M
464 05:14:41.418652 A53 clk: 1200 MHz
465 05:14:41.419180 A73 clk: 1200 MHz
466 05:14:41.421810 CLK81: 166.6M
467 05:14:41.422361 smccc: 00012ab5
468 05:14:41.427234 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 05:14:41.433098 board id: 1
470 05:14:41.437132 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 05:14:41.448510 fw parse done
472 05:14:41.453472 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 05:14:41.496180 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 05:14:41.508030 PIEI prepare done
475 05:14:41.508612 fastboot data load
476 05:14:41.509151 fastboot data verify
477 05:14:41.513588 verify result: 266
478 05:14:41.519215 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 05:14:41.519774 LPDDR4 probe
480 05:14:41.520335 ddr clk to 1584MHz
481 05:14:41.527196 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 05:14:41.564429
483 05:14:41.565020 dmc_version 0001
484 05:14:41.570192 Check phy result
485 05:14:41.576957 INFO : End of CA training
486 05:14:41.577511 INFO : End of initialization
487 05:14:41.582568 INFO : Training has run successfully!
488 05:14:41.583193 Check phy result
489 05:14:41.588191 INFO : End of initialization
490 05:14:41.588756 INFO : End of read enable training
491 05:14:41.593904 INFO : End of fine write leveling
492 05:14:41.599395 INFO : End of Write leveling coarse delay
493 05:14:41.599944 INFO : Training has run successfully!
494 05:14:41.600511 Check phy result
495 05:14:41.604964 INFO : End of initialization
496 05:14:41.605517 INFO : End of read dq deskew training
497 05:14:41.610568 INFO : End of MPR read delay center optimization
498 05:14:41.616195 INFO : End of write delay center optimization
499 05:14:41.621793 INFO : End of read delay center optimization
500 05:14:41.622344 INFO : End of max read latency training
501 05:14:41.627364 INFO : Training has run successfully!
502 05:14:41.627937 1D training succeed
503 05:14:41.636576 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 05:14:41.684241 Check phy result
505 05:14:41.684865 INFO : End of initialization
506 05:14:41.705843 INFO : End of 2D read delay Voltage center optimization
507 05:14:41.725937 INFO : End of 2D read delay Voltage center optimization
508 05:14:41.777912 INFO : End of 2D write delay Voltage center optimization
509 05:14:41.827018 INFO : End of 2D write delay Voltage center optimization
510 05:14:41.832591 INFO : Training has run successfully!
511 05:14:41.833170
512 05:14:41.833706 channel==0
513 05:14:41.838176 RxClkDly_Margin_A0==88 ps 9
514 05:14:41.838726 TxDqDly_Margin_A0==98 ps 10
515 05:14:41.843772 RxClkDly_Margin_A1==88 ps 9
516 05:14:41.844371 TxDqDly_Margin_A1==98 ps 10
517 05:14:41.844906 TrainedVREFDQ_A0==74
518 05:14:41.849386 TrainedVREFDQ_A1==74
519 05:14:41.849957 VrefDac_Margin_A0==25
520 05:14:41.850489 DeviceVref_Margin_A0==40
521 05:14:41.854956 VrefDac_Margin_A1==25
522 05:14:41.855511 DeviceVref_Margin_A1==40
523 05:14:41.856062
524 05:14:41.856581
525 05:14:41.860623 channel==1
526 05:14:41.861185 RxClkDly_Margin_A0==98 ps 10
527 05:14:41.861712 TxDqDly_Margin_A0==98 ps 10
528 05:14:41.866158 RxClkDly_Margin_A1==98 ps 10
529 05:14:41.866707 TxDqDly_Margin_A1==88 ps 9
530 05:14:41.871762 TrainedVREFDQ_A0==77
531 05:14:41.872349 TrainedVREFDQ_A1==77
532 05:14:41.872867 VrefDac_Margin_A0==22
533 05:14:41.877385 DeviceVref_Margin_A0==37
534 05:14:41.877958 VrefDac_Margin_A1==24
535 05:14:41.883000 DeviceVref_Margin_A1==37
536 05:14:41.883567
537 05:14:41.884126 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 05:14:41.888559
539 05:14:41.916587 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 05:14:41.917255 2D training succeed
541 05:14:41.922141 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 05:14:41.927762 auto size-- 65535DDR cs0 size: 2048MB
543 05:14:41.928365 DDR cs1 size: 2048MB
544 05:14:41.933377 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 05:14:41.933937 cs0 DataBus test pass
546 05:14:41.938977 cs1 DataBus test pass
547 05:14:41.939535 cs0 AddrBus test pass
548 05:14:41.940089 cs1 AddrBus test pass
549 05:14:41.940613
550 05:14:41.944555 100bdlr_step_size ps== 420
551 05:14:41.945133 result report
552 05:14:41.950166 boot times 0Enable ddr reg access
553 05:14:41.955629 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 05:14:41.969091 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 05:14:42.541114 0.0;M3 CHK:0;cm4_sp_mode 0
556 05:14:42.541859 MVN_1=0x00000000
557 05:14:42.546594 MVN_2=0x00000000
558 05:14:42.552311 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 05:14:42.552913 OPS=0x10
560 05:14:42.553454 ring efuse init
561 05:14:42.554006 chipver efuse init
562 05:14:42.560506 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 05:14:42.561096 [0.018961 Inits done]
564 05:14:42.568104 secure task start!
565 05:14:42.568640 high task start!
566 05:14:42.569140 low task start!
567 05:14:42.569621 run into bl31
568 05:14:42.574805 NOTICE: BL31: v1.3(release):4fc40b1
569 05:14:42.582564 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 05:14:42.583159 NOTICE: BL31: G12A normal boot!
571 05:14:42.607936 NOTICE: BL31: BL33 decompress pass
572 05:14:42.613551 ERROR: Error initializing runtime service opteed_fast
573 05:14:43.846501
574 05:14:43.847259
575 05:14:43.854853 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 05:14:43.855429
577 05:14:43.855965 Model: Libre Computer AML-A311D-CC Alta
578 05:14:44.063337 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 05:14:44.086729 DRAM: 2 GiB (effective 3.8 GiB)
580 05:14:44.229693 Core: 408 devices, 31 uclasses, devicetree: separate
581 05:14:44.235478 WDT: Not starting watchdog@f0d0
582 05:14:44.267846 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 05:14:44.280261 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 05:14:44.284257 ** Bad device specification mmc 0 **
585 05:14:44.295523 Card did not respond to voltage select! : -110
586 05:14:44.302293 ** Bad device specification mmc 0 **
587 05:14:44.302854 Couldn't find partition mmc 0
588 05:14:44.311546 Card did not respond to voltage select! : -110
589 05:14:44.317026 ** Bad device specification mmc 0 **
590 05:14:44.317612 Couldn't find partition mmc 0
591 05:14:44.321208 Error: could not access storage.
592 05:14:44.663620 Net: eth0: ethernet@ff3f0000
593 05:14:44.664361 starting USB...
594 05:14:44.916342 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 05:14:44.916972 Starting the controller
596 05:14:44.923319 USB XHCI 1.10
597 05:14:46.637566 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 05:14:46.638375 bl2_stage_init 0x01
599 05:14:46.638966 bl2_stage_init 0x81
600 05:14:46.642988 hw id: 0x0000 - pwm id 0x01
601 05:14:46.643568 bl2_stage_init 0xc1
602 05:14:46.644155 bl2_stage_init 0x02
603 05:14:46.644704
604 05:14:46.648594 L0:00000000
605 05:14:46.649194 L1:20000703
606 05:14:46.649732 L2:00008067
607 05:14:46.650263 L3:14000000
608 05:14:46.651680 B2:00402000
609 05:14:46.652314 B1:e0f83180
610 05:14:46.652845
611 05:14:46.653368 TE: 58167
612 05:14:46.653882
613 05:14:46.662833 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 05:14:46.663406
615 05:14:46.663947 Board ID = 1
616 05:14:46.664519 Set A53 clk to 24M
617 05:14:46.665046 Set A73 clk to 24M
618 05:14:46.668382 Set clk81 to 24M
619 05:14:46.668940 A53 clk: 1200 MHz
620 05:14:46.669475 A73 clk: 1200 MHz
621 05:14:46.673866 CLK81: 166.6M
622 05:14:46.674422 smccc: 00012abe
623 05:14:46.679518 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 05:14:46.680106 board id: 1
625 05:14:46.688168 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 05:14:46.698601 fw parse done
627 05:14:46.704571 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 05:14:46.747196 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 05:14:46.758172 PIEI prepare done
630 05:14:46.758743 fastboot data load
631 05:14:46.759279 fastboot data verify
632 05:14:46.763788 verify result: 266
633 05:14:46.769321 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 05:14:46.769874 LPDDR4 probe
635 05:14:46.770400 ddr clk to 1584MHz
636 05:14:46.777358 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 05:14:46.814682
638 05:14:46.815269 dmc_version 0001
639 05:14:46.821268 Check phy result
640 05:14:46.827182 INFO : End of CA training
641 05:14:46.827728 INFO : End of initialization
642 05:14:46.832728 INFO : Training has run successfully!
643 05:14:46.833276 Check phy result
644 05:14:46.838338 INFO : End of initialization
645 05:14:46.838887 INFO : End of read enable training
646 05:14:46.841657 INFO : End of fine write leveling
647 05:14:46.847135 INFO : End of Write leveling coarse delay
648 05:14:46.852702 INFO : Training has run successfully!
649 05:14:46.853244 Check phy result
650 05:14:46.853769 INFO : End of initialization
651 05:14:46.858373 INFO : End of read dq deskew training
652 05:14:46.861845 INFO : End of MPR read delay center optimization
653 05:14:46.867488 INFO : End of write delay center optimization
654 05:14:46.872994 INFO : End of read delay center optimization
655 05:14:46.873560 INFO : End of max read latency training
656 05:14:46.878587 INFO : Training has run successfully!
657 05:14:46.879149 1D training succeed
658 05:14:46.886779 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 05:14:46.934304 Check phy result
660 05:14:46.934917 INFO : End of initialization
661 05:14:46.956138 INFO : End of 2D read delay Voltage center optimization
662 05:14:46.976447 INFO : End of 2D read delay Voltage center optimization
663 05:14:47.028525 INFO : End of 2D write delay Voltage center optimization
664 05:14:47.077804 INFO : End of 2D write delay Voltage center optimization
665 05:14:47.083342 INFO : Training has run successfully!
666 05:14:47.083964
667 05:14:47.084641 channel==0
668 05:14:47.088940 RxClkDly_Margin_A0==88 ps 9
669 05:14:47.089400 TxDqDly_Margin_A0==98 ps 10
670 05:14:47.094558 RxClkDly_Margin_A1==88 ps 9
671 05:14:47.095010 TxDqDly_Margin_A1==98 ps 10
672 05:14:47.095433 TrainedVREFDQ_A0==74
673 05:14:47.100170 TrainedVREFDQ_A1==74
674 05:14:47.100623 VrefDac_Margin_A0==25
675 05:14:47.101036 DeviceVref_Margin_A0==40
676 05:14:47.105776 VrefDac_Margin_A1==25
677 05:14:47.106228 DeviceVref_Margin_A1==40
678 05:14:47.106638
679 05:14:47.107048
680 05:14:47.111358 channel==1
681 05:14:47.111816 RxClkDly_Margin_A0==98 ps 10
682 05:14:47.112277 TxDqDly_Margin_A0==88 ps 9
683 05:14:47.116967 RxClkDly_Margin_A1==98 ps 10
684 05:14:47.117438 TxDqDly_Margin_A1==88 ps 9
685 05:14:47.122551 TrainedVREFDQ_A0==76
686 05:14:47.123016 TrainedVREFDQ_A1==77
687 05:14:47.123432 VrefDac_Margin_A0==22
688 05:14:47.128104 DeviceVref_Margin_A0==38
689 05:14:47.128569 VrefDac_Margin_A1==22
690 05:14:47.133671 DeviceVref_Margin_A1==37
691 05:14:47.134143
692 05:14:47.134560 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 05:14:47.134968
694 05:14:47.167278 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 05:14:47.167789 2D training succeed
696 05:14:47.172866 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 05:14:47.178509 auto size-- 65535DDR cs0 size: 2048MB
698 05:14:47.178967 DDR cs1 size: 2048MB
699 05:14:47.184073 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 05:14:47.184526 cs0 DataBus test pass
701 05:14:47.189648 cs1 DataBus test pass
702 05:14:47.190106 cs0 AddrBus test pass
703 05:14:47.190526 cs1 AddrBus test pass
704 05:14:47.190938
705 05:14:47.195257 100bdlr_step_size ps== 420
706 05:14:47.195749 result report
707 05:14:47.200876 boot times 0Enable ddr reg access
708 05:14:47.206267 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 05:14:47.219746 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 05:14:47.793381 0.0;M3 CHK:0;cm4_sp_mode 0
711 05:14:47.793961 MVN_1=0x00000000
712 05:14:47.798969 MVN_2=0x00000000
713 05:14:47.804665 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 05:14:47.805214 OPS=0x10
715 05:14:47.805612 ring efuse init
716 05:14:47.806001 chipver efuse init
717 05:14:47.813086 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 05:14:47.813547 [0.018961 Inits done]
719 05:14:47.820476 secure task start!
720 05:14:47.821005 high task start!
721 05:14:47.821405 low task start!
722 05:14:47.821796 run into bl31
723 05:14:47.827310 NOTICE: BL31: v1.3(release):4fc40b1
724 05:14:47.834534 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 05:14:47.835061 NOTICE: BL31: G12A normal boot!
726 05:14:47.860330 NOTICE: BL31: BL33 decompress pass
727 05:14:47.865236 ERROR: Error initializing runtime service opteed_fast
728 05:14:49.098862
729 05:14:49.099471
730 05:14:49.107094 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 05:14:49.107566
732 05:14:49.108038 Model: Libre Computer AML-A311D-CC Alta
733 05:14:49.315484 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 05:14:49.338891 DRAM: 2 GiB (effective 3.8 GiB)
735 05:14:49.693869 Core: 408 devices, 31 uclasses, devicetree: separate
736 05:14:49.694319 WDT: Not starting watchdog@f0d0
737 05:14:49.694578 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 05:14:49.694823 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 05:14:49.695059 ** Bad device specification mmc 0 **
740 05:14:49.695282 Card did not respond to voltage select! : -110
741 05:14:49.695511 ** Bad device specification mmc 0 **
742 05:14:49.695754 Couldn't find partition mmc 0
743 05:14:49.696026 Card did not respond to voltage select! : -110
744 05:14:49.696272 ** Bad device specification mmc 0 **
745 05:14:49.696494 Couldn't find partition mmc 0
746 05:14:49.697012 Error: could not access storage.
747 05:14:49.917894 Net: eth0: ethernet@ff3f0000
748 05:14:49.918335 starting USB...
749 05:14:50.169703 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 05:14:50.170308 Starting the controller
751 05:14:50.176615 USB XHCI 1.10
752 05:14:52.338734 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 05:14:52.339349 bl2_stage_init 0x01
754 05:14:52.339776 bl2_stage_init 0x81
755 05:14:52.344281 hw id: 0x0000 - pwm id 0x01
756 05:14:52.344740 bl2_stage_init 0xc1
757 05:14:52.345156 bl2_stage_init 0x02
758 05:14:52.345565
759 05:14:52.349997 L0:00000000
760 05:14:52.350442 L1:20000703
761 05:14:52.350852 L2:00008067
762 05:14:52.351252 L3:14000000
763 05:14:52.352783 B2:00402000
764 05:14:52.353233 B1:e0f83180
765 05:14:52.353646
766 05:14:52.354049 TE: 58124
767 05:14:52.354450
768 05:14:52.364021 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 05:14:52.364484
770 05:14:52.364898 Board ID = 1
771 05:14:52.365304 Set A53 clk to 24M
772 05:14:52.365701 Set A73 clk to 24M
773 05:14:52.369548 Set clk81 to 24M
774 05:14:52.369988 A53 clk: 1200 MHz
775 05:14:52.370389 A73 clk: 1200 MHz
776 05:14:52.375159 CLK81: 166.6M
777 05:14:52.375595 smccc: 00012a92
778 05:14:52.380748 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 05:14:52.381190 board id: 1
780 05:14:52.389366 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 05:14:52.400089 fw parse done
782 05:14:52.406132 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 05:14:52.448641 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 05:14:52.459538 PIEI prepare done
785 05:14:52.460032 fastboot data load
786 05:14:52.460464 fastboot data verify
787 05:14:52.465159 verify result: 266
788 05:14:52.470844 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 05:14:52.471292 LPDDR4 probe
790 05:14:52.471701 ddr clk to 1584MHz
791 05:14:52.478727 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 05:14:52.515975
793 05:14:52.516446 dmc_version 0001
794 05:14:52.522670 Check phy result
795 05:14:52.528540 INFO : End of CA training
796 05:14:52.528976 INFO : End of initialization
797 05:14:52.534145 INFO : Training has run successfully!
798 05:14:52.534582 Check phy result
799 05:14:52.539731 INFO : End of initialization
800 05:14:52.540197 INFO : End of read enable training
801 05:14:52.545342 INFO : End of fine write leveling
802 05:14:52.550955 INFO : End of Write leveling coarse delay
803 05:14:52.551391 INFO : Training has run successfully!
804 05:14:52.551797 Check phy result
805 05:14:52.556526 INFO : End of initialization
806 05:14:52.556961 INFO : End of read dq deskew training
807 05:14:52.562147 INFO : End of MPR read delay center optimization
808 05:14:52.567752 INFO : End of write delay center optimization
809 05:14:52.573348 INFO : End of read delay center optimization
810 05:14:52.573790 INFO : End of max read latency training
811 05:14:52.578949 INFO : Training has run successfully!
812 05:14:52.579384 1D training succeed
813 05:14:52.588189 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 05:14:52.635787 Check phy result
815 05:14:52.636262 INFO : End of initialization
816 05:14:52.657468 INFO : End of 2D read delay Voltage center optimization
817 05:14:52.677700 INFO : End of 2D read delay Voltage center optimization
818 05:14:52.729805 INFO : End of 2D write delay Voltage center optimization
819 05:14:52.779150 INFO : End of 2D write delay Voltage center optimization
820 05:14:52.784641 INFO : Training has run successfully!
821 05:14:52.785085
822 05:14:52.785497 channel==0
823 05:14:52.790246 RxClkDly_Margin_A0==88 ps 9
824 05:14:52.790678 TxDqDly_Margin_A0==98 ps 10
825 05:14:52.793573 RxClkDly_Margin_A1==88 ps 9
826 05:14:52.794011 TxDqDly_Margin_A1==98 ps 10
827 05:14:52.799203 TrainedVREFDQ_A0==74
828 05:14:52.799707 TrainedVREFDQ_A1==74
829 05:14:52.800185 VrefDac_Margin_A0==25
830 05:14:52.804770 DeviceVref_Margin_A0==40
831 05:14:52.805246 VrefDac_Margin_A1==25
832 05:14:52.810381 DeviceVref_Margin_A1==40
833 05:14:52.810805
834 05:14:52.811194
835 05:14:52.811582 channel==1
836 05:14:52.811967 RxClkDly_Margin_A0==98 ps 10
837 05:14:52.815954 TxDqDly_Margin_A0==98 ps 10
838 05:14:52.816408 RxClkDly_Margin_A1==98 ps 10
839 05:14:52.821540 TxDqDly_Margin_A1==88 ps 9
840 05:14:52.821968 TrainedVREFDQ_A0==77
841 05:14:52.822355 TrainedVREFDQ_A1==77
842 05:14:52.827174 VrefDac_Margin_A0==23
843 05:14:52.827592 DeviceVref_Margin_A0==37
844 05:14:52.832752 VrefDac_Margin_A1==24
845 05:14:52.833168 DeviceVref_Margin_A1==37
846 05:14:52.833553
847 05:14:52.838328 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 05:14:52.838746
849 05:14:52.866348 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 05:14:52.871932 2D training succeed
851 05:14:52.877510 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 05:14:52.877934 auto size-- 65535DDR cs0 size: 2048MB
853 05:14:52.883145 DDR cs1 size: 2048MB
854 05:14:52.883560 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 05:14:52.888774 cs0 DataBus test pass
856 05:14:52.889191 cs1 DataBus test pass
857 05:14:52.889575 cs0 AddrBus test pass
858 05:14:52.894401 cs1 AddrBus test pass
859 05:14:52.894813
860 05:14:52.895200 100bdlr_step_size ps== 420
861 05:14:52.895589 result report
862 05:14:52.900163 boot times 0Enable ddr reg access
863 05:14:52.907815 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 05:14:52.921452 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 05:14:53.494984 0.0;M3 CHK:0;cm4_sp_mode 0
866 05:14:53.495409 MVN_1=0x00000000
867 05:14:53.500436 MVN_2=0x00000000
868 05:14:53.506252 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 05:14:53.506716 OPS=0x10
870 05:14:53.507135 ring efuse init
871 05:14:53.507548 chipver efuse init
872 05:14:53.514582 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 05:14:53.515042 [0.018961 Inits done]
874 05:14:53.522181 secure task start!
875 05:14:53.522620 high task start!
876 05:14:53.523029 low task start!
877 05:14:53.523433 run into bl31
878 05:14:53.528699 NOTICE: BL31: v1.3(release):4fc40b1
879 05:14:53.536595 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 05:14:53.537041 NOTICE: BL31: G12A normal boot!
881 05:14:53.561861 NOTICE: BL31: BL33 decompress pass
882 05:14:53.567604 ERROR: Error initializing runtime service opteed_fast
883 05:14:54.800546
884 05:14:54.801159
885 05:14:54.808817 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 05:14:54.809278
887 05:14:54.809699 Model: Libre Computer AML-A311D-CC Alta
888 05:14:55.017218 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 05:14:55.040731 DRAM: 2 GiB (effective 3.8 GiB)
890 05:14:55.183625 Core: 408 devices, 31 uclasses, devicetree: separate
891 05:14:55.189412 WDT: Not starting watchdog@f0d0
892 05:14:55.221553 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 05:14:55.234108 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 05:14:55.239040 ** Bad device specification mmc 0 **
895 05:14:55.249382 Card did not respond to voltage select! : -110
896 05:14:55.257049 ** Bad device specification mmc 0 **
897 05:14:55.257493 Couldn't find partition mmc 0
898 05:14:55.265403 Card did not respond to voltage select! : -110
899 05:14:55.270907 ** Bad device specification mmc 0 **
900 05:14:55.271347 Couldn't find partition mmc 0
901 05:14:55.275962 Error: could not access storage.
902 05:14:55.619554 Net: eth0: ethernet@ff3f0000
903 05:14:55.620123 starting USB...
904 05:14:55.871193 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 05:14:55.871703 Starting the controller
906 05:14:55.878343 USB XHCI 1.10
907 05:14:57.432349 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 05:14:57.440618 scanning usb for storage devices... 0 Storage Device(s) found
910 05:14:57.492068 Hit any key to stop autoboot: 1
911 05:14:57.492820 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 05:14:57.493412 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 05:14:57.493881 Setting prompt string to ['=>']
914 05:14:57.494352 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 05:14:57.507960 0
916 05:14:57.508872 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 05:14:57.509371 Sending with 10 millisecond of delay
919 05:14:58.647770 => setenv autoload no
920 05:14:58.658633 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 05:14:58.663565 setenv autoload no
922 05:14:58.664308 Sending with 10 millisecond of delay
924 05:15:00.460865 => setenv initrd_high 0xffffffff
925 05:15:00.471649 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 05:15:00.472537 setenv initrd_high 0xffffffff
927 05:15:00.473249 Sending with 10 millisecond of delay
929 05:15:02.089258 => setenv fdt_high 0xffffffff
930 05:15:02.100061 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 05:15:02.100911 setenv fdt_high 0xffffffff
932 05:15:02.101618 Sending with 10 millisecond of delay
934 05:15:02.393391 => dhcp
935 05:15:02.404142 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 05:15:02.404967 dhcp
937 05:15:02.405396 Speed: 1000, full duplex
938 05:15:02.405804 BOOTP broadcast 1
939 05:15:02.651898 BOOTP broadcast 2
940 05:15:02.824387 DHCP client bound to address 192.168.6.33 (421 ms)
941 05:15:02.825163 Sending with 10 millisecond of delay
943 05:15:04.500756 => setenv serverip 192.168.6.2
944 05:15:04.511291 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
945 05:15:04.511796 setenv serverip 192.168.6.2
946 05:15:04.512274 Sending with 10 millisecond of delay
948 05:15:08.234651 => tftpboot 0x01080000 796465/tftp-deploy-xxnkjl66/kernel/uImage
949 05:15:08.245441 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
950 05:15:08.246237 tftpboot 0x01080000 796465/tftp-deploy-xxnkjl66/kernel/uImage
951 05:15:08.246682 Speed: 1000, full duplex
952 05:15:08.247098 Using ethernet@ff3f0000 device
953 05:15:08.248125 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
954 05:15:08.253713 Filename '796465/tftp-deploy-xxnkjl66/kernel/uImage'.
955 05:15:08.257610 Load address: 0x1080000
956 05:15:19.435216 Loading: *###########################################T ####### 63 MiB
957 05:15:19.435827 5.6 MiB/s
958 05:15:19.436307 done
959 05:15:19.439235 Bytes transferred = 66101824 (3f0a240 hex)
960 05:15:19.440036 Sending with 10 millisecond of delay
962 05:15:24.126971 => tftpboot 0x08000000 796465/tftp-deploy-xxnkjl66/ramdisk/ramdisk.cpio.gz.uboot
963 05:15:24.137771 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
964 05:15:24.138561 tftpboot 0x08000000 796465/tftp-deploy-xxnkjl66/ramdisk/ramdisk.cpio.gz.uboot
965 05:15:24.139017 Speed: 1000, full duplex
966 05:15:24.139431 Using ethernet@ff3f0000 device
967 05:15:24.140551 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
968 05:15:24.152559 Filename '796465/tftp-deploy-xxnkjl66/ramdisk/ramdisk.cpio.gz.uboot'.
969 05:15:24.153033 Load address: 0x8000000
970 05:15:27.700454 Loading: *################################################# UDP wrong checksum 00000007 0000c1ff
971 05:15:32.702469 T UDP wrong checksum 00000007 0000c1ff
972 05:15:42.704400 T T UDP wrong checksum 00000007 0000c1ff
973 05:16:02.708224 T T T T UDP wrong checksum 00000007 0000c1ff
974 05:16:22.713417 T T T
975 05:16:22.714036 Retry count exceeded; starting again
977 05:16:22.715463 end: 2.4.3 bootloader-commands (duration 00:01:25) [common]
980 05:16:22.717388 end: 2.4 uboot-commands (duration 00:01:58) [common]
982 05:16:22.718742 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
984 05:16:22.719734 end: 2 uboot-action (duration 00:01:58) [common]
986 05:16:22.721256 Cleaning after the job
987 05:16:22.721788 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/ramdisk
988 05:16:22.723129 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/kernel
989 05:16:22.733646 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/dtb
990 05:16:22.734856 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796465/tftp-deploy-xxnkjl66/modules
991 05:16:22.745164 start: 4.1 power-off (timeout 00:00:30) [common]
992 05:16:22.746183 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
993 05:16:22.781531 >> OK - accepted request
994 05:16:22.783601 Returned 0 in 0 seconds
995 05:16:22.884805 end: 4.1 power-off (duration 00:00:00) [common]
997 05:16:22.886462 start: 4.2 read-feedback (timeout 00:10:00) [common]
998 05:16:22.887552 Listened to connection for namespace 'common' for up to 1s
999 05:16:23.887826 Finalising connection for namespace 'common'
1000 05:16:23.888564 Disconnecting from shell: Finalise
1001 05:16:23.889074 =>
1002 05:16:23.990012 end: 4.2 read-feedback (duration 00:00:01) [common]
1003 05:16:23.990665 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796465
1004 05:16:24.292889 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796465
1005 05:16:24.293487 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.