Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:13:53.671419 lava-dispatcher, installed at version: 2024.01
2 05:13:53.672207 start: 0 validate
3 05:13:53.672668 Start time: 2024-10-03 05:13:53.672637+00:00 (UTC)
4 05:13:53.673246 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:13:53.673774 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:13:53.707463 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:13:53.708062 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 05:13:54.742026 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:13:54.742679 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 05:14:01.821696 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:14:01.822186 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 05:14:02.866784 validate duration: 9.19
14 05:14:02.867885 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:14:02.868272 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:14:02.868608 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:14:02.869219 Not decompressing ramdisk as can be used compressed.
18 05:14:02.869865 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:14:02.870177 saving as /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/ramdisk/rootfs.cpio.gz
20 05:14:02.870511 total size: 8181887 (7 MB)
21 05:14:02.910660 progress 0 % (0 MB)
22 05:14:02.917327 progress 5 % (0 MB)
23 05:14:02.923102 progress 10 % (0 MB)
24 05:14:02.933031 progress 15 % (1 MB)
25 05:14:02.938382 progress 20 % (1 MB)
26 05:14:02.944194 progress 25 % (1 MB)
27 05:14:02.949524 progress 30 % (2 MB)
28 05:14:02.955177 progress 35 % (2 MB)
29 05:14:02.960491 progress 40 % (3 MB)
30 05:14:02.966264 progress 45 % (3 MB)
31 05:14:02.971724 progress 50 % (3 MB)
32 05:14:02.977430 progress 55 % (4 MB)
33 05:14:02.982713 progress 60 % (4 MB)
34 05:14:02.988482 progress 65 % (5 MB)
35 05:14:02.993756 progress 70 % (5 MB)
36 05:14:02.999396 progress 75 % (5 MB)
37 05:14:03.004726 progress 80 % (6 MB)
38 05:14:03.010509 progress 85 % (6 MB)
39 05:14:03.015780 progress 90 % (7 MB)
40 05:14:03.021453 progress 95 % (7 MB)
41 05:14:03.026297 progress 100 % (7 MB)
42 05:14:03.026951 7 MB downloaded in 0.16 s (49.88 MB/s)
43 05:14:03.027510 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:14:03.028462 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:14:03.028780 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:14:03.029064 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:14:03.029556 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 05:14:03.029807 saving as /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/kernel/Image
50 05:14:03.030022 total size: 66101760 (63 MB)
51 05:14:03.030241 No compression specified
52 05:14:03.075690 progress 0 % (0 MB)
53 05:14:03.119965 progress 5 % (3 MB)
54 05:14:03.161924 progress 10 % (6 MB)
55 05:14:03.202442 progress 15 % (9 MB)
56 05:14:03.243209 progress 20 % (12 MB)
57 05:14:03.283687 progress 25 % (15 MB)
58 05:14:03.324286 progress 30 % (18 MB)
59 05:14:03.365107 progress 35 % (22 MB)
60 05:14:03.405333 progress 40 % (25 MB)
61 05:14:03.445904 progress 45 % (28 MB)
62 05:14:03.486618 progress 50 % (31 MB)
63 05:14:03.527838 progress 55 % (34 MB)
64 05:14:03.568596 progress 60 % (37 MB)
65 05:14:03.608809 progress 65 % (41 MB)
66 05:14:03.650946 progress 70 % (44 MB)
67 05:14:03.691786 progress 75 % (47 MB)
68 05:14:03.733239 progress 80 % (50 MB)
69 05:14:03.774833 progress 85 % (53 MB)
70 05:14:03.815472 progress 90 % (56 MB)
71 05:14:03.858360 progress 95 % (59 MB)
72 05:14:03.899581 progress 100 % (63 MB)
73 05:14:03.900233 63 MB downloaded in 0.87 s (72.44 MB/s)
74 05:14:03.900754 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:14:03.901577 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:14:03.901853 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:14:03.902115 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:14:03.902598 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 05:14:03.902870 saving as /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 05:14:03.903077 total size: 53209 (0 MB)
82 05:14:03.903290 No compression specified
83 05:14:03.937859 progress 61 % (0 MB)
84 05:14:03.938721 progress 100 % (0 MB)
85 05:14:03.939254 0 MB downloaded in 0.04 s (1.40 MB/s)
86 05:14:03.939735 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:14:03.940591 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:14:03.940850 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:14:03.941115 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:14:03.941593 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 05:14:03.941833 saving as /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/modules/modules.tar
93 05:14:03.942038 total size: 16285276 (15 MB)
94 05:14:03.942249 Using unxz to decompress xz
95 05:14:03.988508 progress 0 % (0 MB)
96 05:14:04.094724 progress 5 % (0 MB)
97 05:14:04.217145 progress 10 % (1 MB)
98 05:14:04.330977 progress 15 % (2 MB)
99 05:14:04.447345 progress 20 % (3 MB)
100 05:14:04.561058 progress 25 % (3 MB)
101 05:14:04.676393 progress 30 % (4 MB)
102 05:14:04.786214 progress 35 % (5 MB)
103 05:14:04.897902 progress 40 % (6 MB)
104 05:14:05.014014 progress 45 % (7 MB)
105 05:14:05.126174 progress 50 % (7 MB)
106 05:14:05.243191 progress 55 % (8 MB)
107 05:14:05.360780 progress 60 % (9 MB)
108 05:14:05.476851 progress 65 % (10 MB)
109 05:14:05.587912 progress 70 % (10 MB)
110 05:14:05.734884 progress 75 % (11 MB)
111 05:14:05.871429 progress 80 % (12 MB)
112 05:14:05.981929 progress 85 % (13 MB)
113 05:14:06.098921 progress 90 % (14 MB)
114 05:14:06.204260 progress 95 % (14 MB)
115 05:14:06.317811 progress 100 % (15 MB)
116 05:14:06.332996 15 MB downloaded in 2.39 s (6.50 MB/s)
117 05:14:06.333607 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:14:06.334435 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:14:06.334707 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 05:14:06.334975 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 05:14:06.335226 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:14:06.335481 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 05:14:06.336236 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44
125 05:14:06.337172 makedir: /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin
126 05:14:06.337871 makedir: /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/tests
127 05:14:06.338555 makedir: /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/results
128 05:14:06.339250 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-add-keys
129 05:14:06.340328 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-add-sources
130 05:14:06.341370 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-background-process-start
131 05:14:06.342394 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-background-process-stop
132 05:14:06.343451 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-common-functions
133 05:14:06.344480 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-echo-ipv4
134 05:14:06.345472 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-install-packages
135 05:14:06.346441 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-installed-packages
136 05:14:06.347404 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-os-build
137 05:14:06.348402 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-probe-channel
138 05:14:06.349379 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-probe-ip
139 05:14:06.350348 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-target-ip
140 05:14:06.351311 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-target-mac
141 05:14:06.352353 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-target-storage
142 05:14:06.353361 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-test-case
143 05:14:06.354330 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-test-event
144 05:14:06.355292 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-test-feedback
145 05:14:06.356330 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-test-raise
146 05:14:06.357364 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-test-reference
147 05:14:06.358509 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-test-runner
148 05:14:06.359505 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-test-set
149 05:14:06.360561 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-test-shell
150 05:14:06.361591 Updating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-install-packages (oe)
151 05:14:06.362653 Updating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/bin/lava-installed-packages (oe)
152 05:14:06.363546 Creating /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/environment
153 05:14:06.364355 LAVA metadata
154 05:14:06.364890 - LAVA_JOB_ID=796472
155 05:14:06.365362 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:14:06.366092 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 05:14:06.368123 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:14:06.368723 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 05:14:06.369153 skipped lava-vland-overlay
160 05:14:06.369691 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:14:06.370285 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 05:14:06.370725 skipped lava-multinode-overlay
163 05:14:06.371211 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:14:06.371714 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 05:14:06.372238 Loading test definitions
166 05:14:06.372787 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 05:14:06.373225 Using /lava-796472 at stage 0
168 05:14:06.375428 uuid=796472_1.5.2.4.1 testdef=None
169 05:14:06.376066 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:14:06.376356 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 05:14:06.378212 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:14:06.379049 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 05:14:06.381371 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:14:06.382207 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 05:14:06.384438 runner path: /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/0/tests/0_dmesg test_uuid 796472_1.5.2.4.1
178 05:14:06.385039 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:14:06.385812 Creating lava-test-runner.conf files
181 05:14:06.386016 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796472/lava-overlay-zd_oey44/lava-796472/0 for stage 0
182 05:14:06.386362 - 0_dmesg
183 05:14:06.386716 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:14:06.386999 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 05:14:06.410858 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:14:06.411268 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 05:14:06.411534 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:14:06.411804 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:14:06.412094 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 05:14:07.412641 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:14:07.413121 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 05:14:07.413385 extracting modules file /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796472/extract-overlay-ramdisk-qedrgctb/ramdisk
193 05:14:08.962034 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 05:14:08.962520 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 05:14:08.962813 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796472/compress-overlay-rdf06xj2/overlay-1.5.2.5.tar.gz to ramdisk
196 05:14:08.963028 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796472/compress-overlay-rdf06xj2/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796472/extract-overlay-ramdisk-qedrgctb/ramdisk
197 05:14:08.993666 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:14:08.994109 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 05:14:08.994388 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 05:14:08.994624 Converting downloaded kernel to a uImage
201 05:14:08.994949 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/kernel/Image /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/kernel/uImage
202 05:14:09.673282 output: Image Name:
203 05:14:09.673698 output: Created: Thu Oct 3 05:14:08 2024
204 05:14:09.673906 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:14:09.674110 output: Data Size: 66101760 Bytes = 64552.50 KiB = 63.04 MiB
206 05:14:09.674313 output: Load Address: 01080000
207 05:14:09.674512 output: Entry Point: 01080000
208 05:14:09.674711 output:
209 05:14:09.675047 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 05:14:09.675312 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 05:14:09.675583 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 05:14:09.675836 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:14:09.676147 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 05:14:09.676429 Building ramdisk /var/lib/lava/dispatcher/tmp/796472/extract-overlay-ramdisk-qedrgctb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796472/extract-overlay-ramdisk-qedrgctb/ramdisk
215 05:14:13.205142 >> 256175 blocks
216 05:14:24.967793 Adding RAMdisk u-boot header.
217 05:14:24.968535 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796472/extract-overlay-ramdisk-qedrgctb/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796472/extract-overlay-ramdisk-qedrgctb/ramdisk.cpio.gz.uboot
218 05:14:25.384619 output: Image Name:
219 05:14:25.385062 output: Created: Thu Oct 3 05:14:24 2024
220 05:14:25.385288 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:14:25.385499 output: Data Size: 33830063 Bytes = 33037.17 KiB = 32.26 MiB
222 05:14:25.385709 output: Load Address: 00000000
223 05:14:25.385916 output: Entry Point: 00000000
224 05:14:25.386118 output:
225 05:14:25.388876 rename /var/lib/lava/dispatcher/tmp/796472/extract-overlay-ramdisk-qedrgctb/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/ramdisk/ramdisk.cpio.gz.uboot
226 05:14:25.389610 end: 1.5.8 compress-ramdisk (duration 00:00:16) [common]
227 05:14:25.390086 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 05:14:25.390530 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
229 05:14:25.390914 No LXC device requested
230 05:14:25.391320 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:14:25.391734 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
232 05:14:25.392186 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:14:25.392597 Checking files for TFTP limit of 4294967296 bytes.
234 05:14:25.394309 end: 1 tftp-deploy (duration 00:00:23) [common]
235 05:14:25.394817 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:14:25.395138 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:14:25.395414 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:14:25.395683 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:14:25.396006 Using kernel file from prepare-kernel: 796472/tftp-deploy-tum0dv4s/kernel/uImage
240 05:14:25.396373 substitutions:
241 05:14:25.396622 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:14:25.396850 - {DTB_ADDR}: 0x01070000
243 05:14:25.397069 - {DTB}: 796472/tftp-deploy-tum0dv4s/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 05:14:25.397281 - {INITRD}: 796472/tftp-deploy-tum0dv4s/ramdisk/ramdisk.cpio.gz.uboot
245 05:14:25.397862 - {KERNEL_ADDR}: 0x01080000
246 05:14:25.398105 - {KERNEL}: 796472/tftp-deploy-tum0dv4s/kernel/uImage
247 05:14:25.398321 - {LAVA_MAC}: None
248 05:14:25.398564 - {PRESEED_CONFIG}: None
249 05:14:25.398785 - {PRESEED_LOCAL}: None
250 05:14:25.398995 - {RAMDISK_ADDR}: 0x08000000
251 05:14:25.399201 - {RAMDISK}: 796472/tftp-deploy-tum0dv4s/ramdisk/ramdisk.cpio.gz.uboot
252 05:14:25.399410 - {ROOT_PART}: None
253 05:14:25.399617 - {ROOT}: None
254 05:14:25.399822 - {SERVER_IP}: 192.168.6.2
255 05:14:25.400060 - {TEE_ADDR}: 0x83000000
256 05:14:25.400277 - {TEE}: None
257 05:14:25.400488 Parsed boot commands:
258 05:14:25.400691 - setenv autoload no
259 05:14:25.400897 - setenv initrd_high 0xffffffff
260 05:14:25.401107 - setenv fdt_high 0xffffffff
261 05:14:25.401314 - dhcp
262 05:14:25.401521 - setenv serverip 192.168.6.2
263 05:14:25.401724 - tftpboot 0x01080000 796472/tftp-deploy-tum0dv4s/kernel/uImage
264 05:14:25.401928 - tftpboot 0x08000000 796472/tftp-deploy-tum0dv4s/ramdisk/ramdisk.cpio.gz.uboot
265 05:14:25.402136 - tftpboot 0x01070000 796472/tftp-deploy-tum0dv4s/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 05:14:25.402341 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:14:25.402552 - bootm 0x01080000 0x08000000 0x01070000
268 05:14:25.402869 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:14:25.403724 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:14:25.404023 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 05:14:25.416586 Setting prompt string to ['lava-test: # ']
273 05:14:25.417625 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:14:25.418010 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:14:25.418332 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:14:25.418637 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:14:25.419286 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 05:14:25.453492 >> OK - accepted request
279 05:14:25.455561 Returned 0 in 0 seconds
280 05:14:25.556611 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:14:25.557827 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:14:25.558182 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:14:25.558497 Setting prompt string to ['Hit any key to stop autoboot']
285 05:14:25.558759 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:14:25.559745 Trying 192.168.56.21...
287 05:14:25.560094 Connected to conserv1.
288 05:14:25.560335 Escape character is '^]'.
289 05:14:25.560558
290 05:14:25.560798 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 05:14:25.561065
292 05:14:34.173372 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 05:14:34.174062 bl2_stage_init 0x01
294 05:14:34.174545 bl2_stage_init 0x81
295 05:14:34.178788 hw id: 0x0000 - pwm id 0x01
296 05:14:34.179336 bl2_stage_init 0xc1
297 05:14:34.184528 bl2_stage_init 0x02
298 05:14:34.185072
299 05:14:34.185519 L0:00000000
300 05:14:34.185956 L1:00000703
301 05:14:34.186390 L2:00008067
302 05:14:34.186819 L3:15000000
303 05:14:34.190022 S1:00000000
304 05:14:34.190536 B2:20282000
305 05:14:34.190976 B1:a0f83180
306 05:14:34.191407
307 05:14:34.191840 TE: 69623
308 05:14:34.192317
309 05:14:34.195665 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 05:14:34.196212
311 05:14:34.201234 Board ID = 1
312 05:14:34.201746 Set cpu clk to 24M
313 05:14:34.202182 Set clk81 to 24M
314 05:14:34.206804 Use GP1_pll as DSU clk.
315 05:14:34.207325 DSU clk: 1200 Mhz
316 05:14:34.207764 CPU clk: 1200 MHz
317 05:14:34.212487 Set clk81 to 166.6M
318 05:14:34.217976 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 05:14:34.218497 board id: 1
320 05:14:34.225119 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:14:34.235909 fw parse done
322 05:14:34.241779 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:14:34.284363 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:14:34.295259 PIEI prepare done
325 05:14:34.295795 fastboot data load
326 05:14:34.296278 fastboot data verify
327 05:14:34.301030 verify result: 266
328 05:14:34.306566 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 05:14:34.307077 LPDDR4 probe
330 05:14:34.307515 ddr clk to 1584MHz
331 05:14:34.314652 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:14:34.350941
333 05:14:34.351605 dmc_version 0001
334 05:14:34.358595 Check phy result
335 05:14:34.364403 INFO : End of CA training
336 05:14:34.364921 INFO : End of initialization
337 05:14:34.370023 INFO : Training has run successfully!
338 05:14:34.370535 Check phy result
339 05:14:34.375567 INFO : End of initialization
340 05:14:34.376118 INFO : End of read enable training
341 05:14:34.381234 INFO : End of fine write leveling
342 05:14:34.386838 INFO : End of Write leveling coarse delay
343 05:14:34.387384 INFO : Training has run successfully!
344 05:14:34.387827 Check phy result
345 05:14:34.392430 INFO : End of initialization
346 05:14:34.392961 INFO : End of read dq deskew training
347 05:14:34.398102 INFO : End of MPR read delay center optimization
348 05:14:34.403575 INFO : End of write delay center optimization
349 05:14:34.409243 INFO : End of read delay center optimization
350 05:14:34.409756 INFO : End of max read latency training
351 05:14:34.414843 INFO : Training has run successfully!
352 05:14:34.415359 1D training succeed
353 05:14:34.424095 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:14:34.471612 Check phy result
355 05:14:34.472315 INFO : End of initialization
356 05:14:34.493815 INFO : End of 2D read delay Voltage center optimization
357 05:14:34.513055 INFO : End of 2D read delay Voltage center optimization
358 05:14:34.564853 INFO : End of 2D write delay Voltage center optimization
359 05:14:34.614112 INFO : End of 2D write delay Voltage center optimization
360 05:14:34.619665 INFO : Training has run successfully!
361 05:14:34.620232
362 05:14:34.620683 channel==0
363 05:14:34.625282 RxClkDly_Margin_A0==88 ps 9
364 05:14:34.625797 TxDqDly_Margin_A0==98 ps 10
365 05:14:34.630850 RxClkDly_Margin_A1==88 ps 9
366 05:14:34.631354 TxDqDly_Margin_A1==98 ps 10
367 05:14:34.631797 TrainedVREFDQ_A0==74
368 05:14:34.636514 TrainedVREFDQ_A1==74
369 05:14:34.637027 VrefDac_Margin_A0==24
370 05:14:34.637462 DeviceVref_Margin_A0==40
371 05:14:34.642060 VrefDac_Margin_A1==23
372 05:14:34.642569 DeviceVref_Margin_A1==40
373 05:14:34.643008
374 05:14:34.643443
375 05:14:34.647709 channel==1
376 05:14:34.648264 RxClkDly_Margin_A0==88 ps 9
377 05:14:34.648701 TxDqDly_Margin_A0==98 ps 10
378 05:14:34.653308 RxClkDly_Margin_A1==78 ps 8
379 05:14:34.653816 TxDqDly_Margin_A1==88 ps 9
380 05:14:34.658848 TrainedVREFDQ_A0==78
381 05:14:34.659382 TrainedVREFDQ_A1==77
382 05:14:34.659822 VrefDac_Margin_A0==23
383 05:14:34.664547 DeviceVref_Margin_A0==36
384 05:14:34.665065 VrefDac_Margin_A1==22
385 05:14:34.670112 DeviceVref_Margin_A1==37
386 05:14:34.670618
387 05:14:34.671060 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:14:34.671493
389 05:14:34.703711 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 05:14:34.704398 2D training succeed
391 05:14:34.709333 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:14:34.714830 auto size-- 65535DDR cs0 size: 2048MB
393 05:14:34.715348 DDR cs1 size: 2048MB
394 05:14:34.720532 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:14:34.721048 cs0 DataBus test pass
396 05:14:34.726025 cs1 DataBus test pass
397 05:14:34.726547 cs0 AddrBus test pass
398 05:14:34.726981 cs1 AddrBus test pass
399 05:14:34.727411
400 05:14:34.731659 100bdlr_step_size ps== 478
401 05:14:34.732219 result report
402 05:14:34.737268 boot times 0Enable ddr reg access
403 05:14:34.742486 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:14:34.756246 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 05:14:35.412890 bl2z: ptr: 05129330, size: 00001e40
406 05:14:35.419809 0.0;M3 CHK:0;cm4_sp_mode 0
407 05:14:35.420397 MVN_1=0x00000000
408 05:14:35.420862 MVN_2=0x00000000
409 05:14:35.430956 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 05:14:35.431520 OPS=0x04
411 05:14:35.432031 ring efuse init
412 05:14:35.436234 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 05:14:35.436753 [0.017319 Inits done]
414 05:14:35.437208 secure task start!
415 05:14:35.443502 high task start!
416 05:14:35.444043 low task start!
417 05:14:35.444499 run into bl31
418 05:14:35.452103 NOTICE: BL31: v1.3(release):4fc40b1
419 05:14:35.459942 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 05:14:35.460501 NOTICE: BL31: G12A normal boot!
421 05:14:35.475686 NOTICE: BL31: BL33 decompress pass
422 05:14:35.481385 ERROR: Error initializing runtime service opteed_fast
423 05:14:38.221905 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 05:14:38.222591 bl2_stage_init 0x01
425 05:14:38.223068 bl2_stage_init 0x81
426 05:14:38.227641 hw id: 0x0000 - pwm id 0x01
427 05:14:38.228297 bl2_stage_init 0xc1
428 05:14:38.233136 bl2_stage_init 0x02
429 05:14:38.233767
430 05:14:38.234212 L0:00000000
431 05:14:38.234641 L1:00000703
432 05:14:38.235071 L2:00008067
433 05:14:38.235499 L3:15000000
434 05:14:38.238693 S1:00000000
435 05:14:38.239226 B2:20282000
436 05:14:38.239661 B1:a0f83180
437 05:14:38.240128
438 05:14:38.240564 TE: 68700
439 05:14:38.240995
440 05:14:38.244400 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 05:14:38.244944
442 05:14:38.249870 Board ID = 1
443 05:14:38.250421 Set cpu clk to 24M
444 05:14:38.250855 Set clk81 to 24M
445 05:14:38.255687 Use GP1_pll as DSU clk.
446 05:14:38.256271 DSU clk: 1200 Mhz
447 05:14:38.256707 CPU clk: 1200 MHz
448 05:14:38.261226 Set clk81 to 166.6M
449 05:14:38.266738 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 05:14:38.267278 board id: 1
451 05:14:38.273873 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 05:14:38.284564 fw parse done
453 05:14:38.290530 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 05:14:38.333105 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 05:14:38.344242 PIEI prepare done
456 05:14:38.344777 fastboot data load
457 05:14:38.345223 fastboot data verify
458 05:14:38.349774 verify result: 266
459 05:14:38.355321 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 05:14:38.355835 LPDDR4 probe
461 05:14:38.356318 ddr clk to 1584MHz
462 05:14:38.362416 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 05:14:38.400648
464 05:14:38.401245 dmc_version 0001
465 05:14:38.406454 Check phy result
466 05:14:38.413258 INFO : End of CA training
467 05:14:38.413790 INFO : End of initialization
468 05:14:38.418834 INFO : Training has run successfully!
469 05:14:38.419423 Check phy result
470 05:14:38.424530 INFO : End of initialization
471 05:14:38.425091 INFO : End of read enable training
472 05:14:38.430085 INFO : End of fine write leveling
473 05:14:38.435640 INFO : End of Write leveling coarse delay
474 05:14:38.436215 INFO : Training has run successfully!
475 05:14:38.436673 Check phy result
476 05:14:38.441234 INFO : End of initialization
477 05:14:38.441772 INFO : End of read dq deskew training
478 05:14:38.446833 INFO : End of MPR read delay center optimization
479 05:14:38.452405 INFO : End of write delay center optimization
480 05:14:38.458112 INFO : End of read delay center optimization
481 05:14:38.458654 INFO : End of max read latency training
482 05:14:38.463639 INFO : Training has run successfully!
483 05:14:38.464355 1D training succeed
484 05:14:38.472761 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 05:14:38.520365 Check phy result
486 05:14:38.520976 INFO : End of initialization
487 05:14:38.542706 INFO : End of 2D read delay Voltage center optimization
488 05:14:38.561877 INFO : End of 2D read delay Voltage center optimization
489 05:14:38.613334 INFO : End of 2D write delay Voltage center optimization
490 05:14:38.662963 INFO : End of 2D write delay Voltage center optimization
491 05:14:38.668573 INFO : Training has run successfully!
492 05:14:38.669076
493 05:14:38.669533 channel==0
494 05:14:38.674155 RxClkDly_Margin_A0==78 ps 8
495 05:14:38.674659 TxDqDly_Margin_A0==98 ps 10
496 05:14:38.677588 RxClkDly_Margin_A1==88 ps 9
497 05:14:38.678084 TxDqDly_Margin_A1==98 ps 10
498 05:14:38.683250 TrainedVREFDQ_A0==74
499 05:14:38.683753 TrainedVREFDQ_A1==74
500 05:14:38.684260 VrefDac_Margin_A0==24
501 05:14:38.688741 DeviceVref_Margin_A0==40
502 05:14:38.689243 VrefDac_Margin_A1==23
503 05:14:38.694332 DeviceVref_Margin_A1==40
504 05:14:38.694842
505 05:14:38.695293
506 05:14:38.695736 channel==1
507 05:14:38.696211 RxClkDly_Margin_A0==78 ps 8
508 05:14:38.700023 TxDqDly_Margin_A0==88 ps 9
509 05:14:38.700531 RxClkDly_Margin_A1==88 ps 9
510 05:14:38.705618 TxDqDly_Margin_A1==78 ps 8
511 05:14:38.706155 TrainedVREFDQ_A0==77
512 05:14:38.706611 TrainedVREFDQ_A1==75
513 05:14:38.711114 VrefDac_Margin_A0==22
514 05:14:38.711672 DeviceVref_Margin_A0==37
515 05:14:38.712166 VrefDac_Margin_A1==22
516 05:14:38.716813 DeviceVref_Margin_A1==38
517 05:14:38.717324
518 05:14:38.722401 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 05:14:38.722918
520 05:14:38.750289 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000018 00000015 00000018 00000016 00000018 00000018 00000017 00000017 00000018 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
521 05:14:38.756017 2D training succeed
522 05:14:38.761572 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 05:14:38.762106 auto size-- 65535DDR cs0 size: 2048MB
524 05:14:38.767164 DDR cs1 size: 2048MB
525 05:14:38.767705 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 05:14:38.772794 cs0 DataBus test pass
527 05:14:38.773298 cs1 DataBus test pass
528 05:14:38.773749 cs0 AddrBus test pass
529 05:14:38.778382 cs1 AddrBus test pass
530 05:14:38.778885
531 05:14:38.779342 100bdlr_step_size ps== 478
532 05:14:38.779799 result report
533 05:14:38.783975 boot times 0Enable ddr reg access
534 05:14:38.791337 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 05:14:38.805112 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 05:14:39.459954 bl2z: ptr: 05129330, size: 00001e40
537 05:14:39.466882 0.0;M3 CHK:0;cm4_sp_mode 0
538 05:14:39.467782 MVN_1=0x00000000
539 05:14:39.468107 MVN_2=0x00000000
540 05:14:39.478415 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 05:14:39.478938 OPS=0x04
542 05:14:39.479372 ring efuse init
543 05:14:39.481527 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 05:14:39.487655 [0.017310 Inits done]
545 05:14:39.488200 secure task start!
546 05:14:39.488638 high task start!
547 05:14:39.488956 low task start!
548 05:14:39.491911 run into bl31
549 05:14:39.500449 NOTICE: BL31: v1.3(release):4fc40b1
550 05:14:39.508288 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 05:14:39.508576 NOTICE: BL31: G12A normal boot!
552 05:14:39.523749 NOTICE: BL31: BL33 decompress pass
553 05:14:39.529607 ERROR: Error initializing runtime service opteed_fast
554 05:14:40.921866 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 05:14:40.922307 bl2_stage_init 0x01
556 05:14:40.922540 bl2_stage_init 0x81
557 05:14:40.927680 hw id: 0x0000 - pwm id 0x01
558 05:14:40.928037 bl2_stage_init 0xc1
559 05:14:40.932731 bl2_stage_init 0x02
560 05:14:40.933056
561 05:14:40.933327 L0:00000000
562 05:14:40.933585 L1:00000703
563 05:14:40.933815 L2:00008067
564 05:14:40.938190 L3:15000000
565 05:14:40.938528 S1:00000000
566 05:14:40.938777 B2:20282000
567 05:14:40.939022 B1:a0f83180
568 05:14:40.939255
569 05:14:40.939500 TE: 68156
570 05:14:40.939764
571 05:14:40.949571 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 05:14:40.949898
573 05:14:40.950155 Board ID = 1
574 05:14:40.950402 Set cpu clk to 24M
575 05:14:40.950639 Set clk81 to 24M
576 05:14:40.952852 Use GP1_pll as DSU clk.
577 05:14:40.953151 DSU clk: 1200 Mhz
578 05:14:40.958538 CPU clk: 1200 MHz
579 05:14:40.958837 Set clk81 to 166.6M
580 05:14:40.964058 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 05:14:40.964366 board id: 1
582 05:14:40.974048 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 05:14:40.985059 fw parse done
584 05:14:40.990802 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 05:14:41.033772 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 05:14:41.044782 PIEI prepare done
587 05:14:41.045106 fastboot data load
588 05:14:41.045352 fastboot data verify
589 05:14:41.050355 verify result: 266
590 05:14:41.055974 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 05:14:41.056307 LPDDR4 probe
592 05:14:41.056561 ddr clk to 1584MHz
593 05:14:41.064126 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 05:14:41.101737
595 05:14:41.102148 dmc_version 0001
596 05:14:41.108871 Check phy result
597 05:14:41.114834 INFO : End of CA training
598 05:14:41.115310 INFO : End of initialization
599 05:14:41.120383 INFO : Training has run successfully!
600 05:14:41.120852 Check phy result
601 05:14:41.126072 INFO : End of initialization
602 05:14:41.126535 INFO : End of read enable training
603 05:14:41.129288 INFO : End of fine write leveling
604 05:14:41.134873 INFO : End of Write leveling coarse delay
605 05:14:41.140509 INFO : Training has run successfully!
606 05:14:41.141099 Check phy result
607 05:14:41.141523 INFO : End of initialization
608 05:14:41.146126 INFO : End of read dq deskew training
609 05:14:41.149516 INFO : End of MPR read delay center optimization
610 05:14:41.155029 INFO : End of write delay center optimization
611 05:14:41.160694 INFO : End of read delay center optimization
612 05:14:41.161478 INFO : End of max read latency training
613 05:14:41.166292 INFO : Training has run successfully!
614 05:14:41.166854 1D training succeed
615 05:14:41.174576 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 05:14:41.222771 Check phy result
617 05:14:41.223183 INFO : End of initialization
618 05:14:41.250187 INFO : End of 2D read delay Voltage center optimization
619 05:14:41.274345 INFO : End of 2D read delay Voltage center optimization
620 05:14:41.330284 INFO : End of 2D write delay Voltage center optimization
621 05:14:41.385111 INFO : End of 2D write delay Voltage center optimization
622 05:14:41.390670 INFO : Training has run successfully!
623 05:14:41.391246
624 05:14:41.391769 channel==0
625 05:14:41.396422 RxClkDly_Margin_A0==69 ps 7
626 05:14:41.396995 TxDqDly_Margin_A0==98 ps 10
627 05:14:41.399540 RxClkDly_Margin_A1==88 ps 9
628 05:14:41.399832 TxDqDly_Margin_A1==98 ps 10
629 05:14:41.405191 TrainedVREFDQ_A0==74
630 05:14:41.405474 TrainedVREFDQ_A1==74
631 05:14:41.410586 VrefDac_Margin_A0==24
632 05:14:41.410875 DeviceVref_Margin_A0==40
633 05:14:41.411296 VrefDac_Margin_A1==23
634 05:14:41.416305 DeviceVref_Margin_A1==40
635 05:14:41.416761
636 05:14:41.417176
637 05:14:41.417585 channel==1
638 05:14:41.417983 RxClkDly_Margin_A0==78 ps 8
639 05:14:41.421748 TxDqDly_Margin_A0==98 ps 10
640 05:14:41.422212 RxClkDly_Margin_A1==88 ps 9
641 05:14:41.427515 TxDqDly_Margin_A1==88 ps 9
642 05:14:41.427970 TrainedVREFDQ_A0==75
643 05:14:41.428427 TrainedVREFDQ_A1==77
644 05:14:41.433252 VrefDac_Margin_A0==22
645 05:14:41.433705 DeviceVref_Margin_A0==39
646 05:14:41.438542 VrefDac_Margin_A1==22
647 05:14:41.439002 DeviceVref_Margin_A1==37
648 05:14:41.439418
649 05:14:41.444575 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 05:14:41.445047
651 05:14:41.472063 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000015 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000016 dram_vref_reg_value 0x 00000061
652 05:14:41.477657 2D training succeed
653 05:14:41.483275 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 05:14:41.483787 auto size-- 65535DDR cs0 size: 2048MB
655 05:14:41.488870 DDR cs1 size: 2048MB
656 05:14:41.489349 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 05:14:41.494447 cs0 DataBus test pass
658 05:14:41.494909 cs1 DataBus test pass
659 05:14:41.495327 cs0 AddrBus test pass
660 05:14:41.500081 cs1 AddrBus test pass
661 05:14:41.500546
662 05:14:41.500966 100bdlr_step_size ps== 471
663 05:14:41.501386 result report
664 05:14:41.505637 boot times 0Enable ddr reg access
665 05:14:41.512364 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 05:14:41.527249 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 05:14:42.186492 bl2z: ptr: 05129330, size: 00001e40
668 05:14:42.194387 0.0;M3 CHK:0;cm4_sp_mode 0
669 05:14:42.194896 MVN_1=0x00000000
670 05:14:42.195325 MVN_2=0x00000000
671 05:14:42.205890 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 05:14:42.206377 OPS=0x04
673 05:14:42.206806 ring efuse init
674 05:14:42.208935 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 05:14:42.214495 [0.017354 Inits done]
676 05:14:42.214952 secure task start!
677 05:14:42.215367 high task start!
678 05:14:42.215774 low task start!
679 05:14:42.218686 run into bl31
680 05:14:42.227419 NOTICE: BL31: v1.3(release):4fc40b1
681 05:14:42.235156 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 05:14:42.235630 NOTICE: BL31: G12A normal boot!
683 05:14:42.250713 NOTICE: BL31: BL33 decompress pass
684 05:14:42.256468 ERROR: Error initializing runtime service opteed_fast
685 05:14:43.051841
686 05:14:43.052465
687 05:14:43.057272 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 05:14:43.057735
689 05:14:43.060730 Model: Libre Computer AML-S905D3-CC Solitude
690 05:14:43.207779 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 05:14:43.223161 DRAM: 2 GiB (effective 3.8 GiB)
692 05:14:43.324143 Core: 406 devices, 33 uclasses, devicetree: separate
693 05:14:43.330119 WDT: Not starting watchdog@f0d0
694 05:14:43.355038 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 05:14:43.367305 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 05:14:43.372265 ** Bad device specification mmc 0 **
697 05:14:43.382335 Card did not respond to voltage select! : -110
698 05:14:43.390118 ** Bad device specification mmc 0 **
699 05:14:43.390579 Couldn't find partition mmc 0
700 05:14:43.398326 Card did not respond to voltage select! : -110
701 05:14:43.403816 ** Bad device specification mmc 0 **
702 05:14:43.404294 Couldn't find partition mmc 0
703 05:14:43.408869 Error: could not access storage.
704 05:14:43.706457 Net: eth0: ethernet@ff3f0000
705 05:14:43.707014 starting USB...
706 05:14:43.951102 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 05:14:43.951703 Starting the controller
708 05:14:43.958050 USB XHCI 1.10
709 05:14:45.512232 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 05:14:45.519523 scanning usb for storage devices... 0 Storage Device(s) found
712 05:14:45.571274 Hit any key to stop autoboot: 1
713 05:14:45.572220 end: 2.4.2 bootloader-interrupt (duration 00:00:20) [common]
714 05:14:45.572895 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
715 05:14:45.573459 Setting prompt string to ['=>']
716 05:14:45.574008 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
717 05:14:45.585591 0
718 05:14:45.586614 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 05:14:45.688076 => setenv autoload no
721 05:14:45.688875 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
722 05:14:45.694308 setenv autoload no
724 05:14:45.796020 => setenv initrd_high 0xffffffff
725 05:14:45.796820 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 05:14:45.801492 setenv initrd_high 0xffffffff
728 05:14:45.903139 => setenv fdt_high 0xffffffff
729 05:14:45.903932 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
730 05:14:45.908297 setenv fdt_high 0xffffffff
732 05:14:46.009987 => dhcp
733 05:14:46.010759 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
734 05:14:46.014861 dhcp
735 05:14:47.120025 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 05:14:47.120671 Speed: 1000, full duplex
737 05:14:47.121149 BOOTP broadcast 1
738 05:14:47.368918 BOOTP broadcast 2
739 05:14:47.868917 BOOTP broadcast 3
740 05:14:48.870826 BOOTP broadcast 4
741 05:14:50.871785 BOOTP broadcast 5
742 05:14:50.884017 DHCP client bound to address 192.168.6.12 (3763 ms)
744 05:14:50.985627 => setenv serverip 192.168.6.2
745 05:14:50.986372 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
746 05:14:50.990842 setenv serverip 192.168.6.2
748 05:14:51.092445 => tftpboot 0x01080000 796472/tftp-deploy-tum0dv4s/kernel/uImage
749 05:14:51.093196 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
750 05:14:51.099763 tftpboot 0x01080000 796472/tftp-deploy-tum0dv4s/kernel/uImage
751 05:14:51.100350 Speed: 1000, full duplex
752 05:14:51.100820 Using ethernet@ff3f0000 device
753 05:14:51.105221 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 05:14:51.110750 Filename '796472/tftp-deploy-tum0dv4s/kernel/uImage'.
755 05:14:51.114632 Load address: 0x1080000
756 05:15:02.825924 Loading: *######################################T ############ 63 MiB
757 05:15:02.826574 5.4 MiB/s
758 05:15:02.827057 done
759 05:15:02.830169 Bytes transferred = 66101824 (3f0a240 hex)
761 05:15:02.931951 => tftpboot 0x08000000 796472/tftp-deploy-tum0dv4s/ramdisk/ramdisk.cpio.gz.uboot
762 05:15:02.932767 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
763 05:15:02.939645 tftpboot 0x08000000 796472/tftp-deploy-tum0dv4s/ramdisk/ramdisk.cpio.gz.uboot
764 05:15:02.940199 Speed: 1000, full duplex
765 05:15:02.940644 Using ethernet@ff3f0000 device
766 05:15:02.945155 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
767 05:15:02.955065 Filename '796472/tftp-deploy-tum0dv4s/ramdisk/ramdisk.cpio.gz.uboot'.
768 05:15:02.955642 Load address: 0x8000000
769 05:15:05.567857 Loading: *################################################# UDP wrong checksum 00000007 0000b815
770 05:15:10.567930 T UDP wrong checksum 00000007 0000b815
771 05:15:20.569879 T T UDP wrong checksum 00000007 0000b815
772 05:15:40.572438 T T T UDP wrong checksum 00000007 0000b815
773 05:16:00.578686 T T T T
774 05:16:00.579326 Retry count exceeded; starting again
776 05:16:00.580900 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
779 05:16:00.582958 end: 2.4 uboot-commands (duration 00:01:35) [common]
781 05:16:00.584601 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
783 05:16:00.585727 end: 2 uboot-action (duration 00:01:35) [common]
785 05:16:00.587357 Cleaning after the job
786 05:16:00.587955 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/ramdisk
787 05:16:00.589439 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/kernel
788 05:16:00.600698 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/dtb
789 05:16:00.601923 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796472/tftp-deploy-tum0dv4s/modules
790 05:16:00.617466 start: 4.1 power-off (timeout 00:00:30) [common]
791 05:16:00.618562 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
792 05:16:00.654497 >> OK - accepted request
793 05:16:00.656568 Returned 0 in 0 seconds
794 05:16:00.757749 end: 4.1 power-off (duration 00:00:00) [common]
796 05:16:00.759522 start: 4.2 read-feedback (timeout 00:10:00) [common]
797 05:16:00.760755 Listened to connection for namespace 'common' for up to 1s
798 05:16:01.761548 Finalising connection for namespace 'common'
799 05:16:01.762302 Disconnecting from shell: Finalise
800 05:16:01.762861 =>
801 05:16:01.863875 end: 4.2 read-feedback (duration 00:00:01) [common]
802 05:16:01.864572 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796472
803 05:16:02.161220 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796472
804 05:16:02.161819 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.