Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:04:13.291158 lava-dispatcher, installed at version: 2024.01
2 05:04:13.292184 start: 0 validate
3 05:04:13.292775 Start time: 2024-10-03 05:04:13.292742+00:00 (UTC)
4 05:04:13.293406 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:04:13.294046 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:04:13.341222 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:04:13.341915 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 05:04:13.377418 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:04:13.378139 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:04:19.454467 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:04:19.455006 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 05:04:22.540845 validate duration: 9.25
14 05:04:22.542446 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:04:22.543125 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:04:22.543751 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:04:22.545355 Not decompressing ramdisk as can be used compressed.
18 05:04:22.546214 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:04:22.546722 saving as /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/ramdisk/rootfs.cpio.gz
20 05:04:22.547247 total size: 8181887 (7 MB)
21 05:04:22.588223 progress 0 % (0 MB)
22 05:04:22.600201 progress 5 % (0 MB)
23 05:04:22.611287 progress 10 % (0 MB)
24 05:04:22.623070 progress 15 % (1 MB)
25 05:04:22.630712 progress 20 % (1 MB)
26 05:04:22.636332 progress 25 % (1 MB)
27 05:04:22.641558 progress 30 % (2 MB)
28 05:04:22.647087 progress 35 % (2 MB)
29 05:04:22.652215 progress 40 % (3 MB)
30 05:04:22.657705 progress 45 % (3 MB)
31 05:04:22.662822 progress 50 % (3 MB)
32 05:04:22.668514 progress 55 % (4 MB)
33 05:04:22.673650 progress 60 % (4 MB)
34 05:04:22.679151 progress 65 % (5 MB)
35 05:04:22.684279 progress 70 % (5 MB)
36 05:04:22.689808 progress 75 % (5 MB)
37 05:04:22.694902 progress 80 % (6 MB)
38 05:04:22.700452 progress 85 % (6 MB)
39 05:04:22.705552 progress 90 % (7 MB)
40 05:04:22.710776 progress 95 % (7 MB)
41 05:04:22.715471 progress 100 % (7 MB)
42 05:04:22.716142 7 MB downloaded in 0.17 s (46.20 MB/s)
43 05:04:22.716705 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:04:22.717613 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:04:22.717922 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:04:22.718205 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:04:22.718845 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
49 05:04:22.719115 saving as /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/kernel/Image
50 05:04:22.719330 total size: 45998592 (43 MB)
51 05:04:22.719555 No compression specified
52 05:04:22.757446 progress 0 % (0 MB)
53 05:04:22.787115 progress 5 % (2 MB)
54 05:04:22.816458 progress 10 % (4 MB)
55 05:04:22.845378 progress 15 % (6 MB)
56 05:04:22.874865 progress 20 % (8 MB)
57 05:04:22.904473 progress 25 % (10 MB)
58 05:04:22.934430 progress 30 % (13 MB)
59 05:04:22.963593 progress 35 % (15 MB)
60 05:04:22.992740 progress 40 % (17 MB)
61 05:04:23.022203 progress 45 % (19 MB)
62 05:04:23.051356 progress 50 % (21 MB)
63 05:04:23.081305 progress 55 % (24 MB)
64 05:04:23.111020 progress 60 % (26 MB)
65 05:04:23.140468 progress 65 % (28 MB)
66 05:04:23.171303 progress 70 % (30 MB)
67 05:04:23.200735 progress 75 % (32 MB)
68 05:04:23.229934 progress 80 % (35 MB)
69 05:04:23.258788 progress 85 % (37 MB)
70 05:04:23.287953 progress 90 % (39 MB)
71 05:04:23.316773 progress 95 % (41 MB)
72 05:04:23.344745 progress 100 % (43 MB)
73 05:04:23.345503 43 MB downloaded in 0.63 s (70.06 MB/s)
74 05:04:23.345999 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:04:23.346816 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:04:23.347090 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:04:23.347354 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:04:23.347958 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 05:04:23.348304 saving as /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/dtb/meson-g12b-a311d-libretech-cc.dtb
81 05:04:23.348523 total size: 54703 (0 MB)
82 05:04:23.348753 No compression specified
83 05:04:23.384943 progress 59 % (0 MB)
84 05:04:23.385790 progress 100 % (0 MB)
85 05:04:23.386358 0 MB downloaded in 0.04 s (1.38 MB/s)
86 05:04:23.386834 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:04:23.387631 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:04:23.387891 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:04:23.388190 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:04:23.388705 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
92 05:04:23.388972 saving as /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/modules/modules.tar
93 05:04:23.389176 total size: 11614180 (11 MB)
94 05:04:23.389384 Using unxz to decompress xz
95 05:04:23.429612 progress 0 % (0 MB)
96 05:04:23.498811 progress 5 % (0 MB)
97 05:04:23.576997 progress 10 % (1 MB)
98 05:04:23.664940 progress 15 % (1 MB)
99 05:04:23.743442 progress 20 % (2 MB)
100 05:04:23.828768 progress 25 % (2 MB)
101 05:04:24.456369 progress 30 % (3 MB)
102 05:04:24.537512 progress 35 % (3 MB)
103 05:04:24.612080 progress 40 % (4 MB)
104 05:04:24.689239 progress 45 % (5 MB)
105 05:04:24.767834 progress 50 % (5 MB)
106 05:04:24.842194 progress 55 % (6 MB)
107 05:04:24.927841 progress 60 % (6 MB)
108 05:04:25.014574 progress 65 % (7 MB)
109 05:04:25.097676 progress 70 % (7 MB)
110 05:04:25.190733 progress 75 % (8 MB)
111 05:04:25.286747 progress 80 % (8 MB)
112 05:04:25.368427 progress 85 % (9 MB)
113 05:04:25.439923 progress 90 % (9 MB)
114 05:04:25.518620 progress 95 % (10 MB)
115 05:04:25.596284 progress 100 % (11 MB)
116 05:04:25.607863 11 MB downloaded in 2.22 s (4.99 MB/s)
117 05:04:25.608888 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:04:25.610663 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:04:25.611237 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 05:04:25.611809 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 05:04:25.612389 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:04:25.612941 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 05:04:25.613998 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw
125 05:04:25.614868 makedir: /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin
126 05:04:25.615553 makedir: /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/tests
127 05:04:25.616266 makedir: /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/results
128 05:04:25.616943 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-add-keys
129 05:04:25.617991 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-add-sources
130 05:04:25.618999 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-background-process-start
131 05:04:25.620076 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-background-process-stop
132 05:04:25.621183 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-common-functions
133 05:04:25.622170 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-echo-ipv4
134 05:04:25.623143 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-install-packages
135 05:04:25.624179 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-installed-packages
136 05:04:25.625156 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-os-build
137 05:04:25.626120 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-probe-channel
138 05:04:25.627091 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-probe-ip
139 05:04:25.628119 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-target-ip
140 05:04:25.629235 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-target-mac
141 05:04:25.630262 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-target-storage
142 05:04:25.631423 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-test-case
143 05:04:25.632549 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-test-event
144 05:04:25.633579 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-test-feedback
145 05:04:25.634698 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-test-raise
146 05:04:25.635730 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-test-reference
147 05:04:25.636798 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-test-runner
148 05:04:25.637787 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-test-set
149 05:04:25.638750 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-test-shell
150 05:04:25.639727 Updating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-install-packages (oe)
151 05:04:25.640859 Updating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/bin/lava-installed-packages (oe)
152 05:04:25.641762 Creating /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/environment
153 05:04:25.642540 LAVA metadata
154 05:04:25.643070 - LAVA_JOB_ID=796430
155 05:04:25.643542 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:04:25.644376 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 05:04:25.646240 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:04:25.646889 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 05:04:25.647345 skipped lava-vland-overlay
160 05:04:25.647889 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:04:25.648477 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 05:04:25.648914 skipped lava-multinode-overlay
163 05:04:25.649404 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:04:25.649976 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 05:04:25.650504 Loading test definitions
166 05:04:25.651104 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 05:04:25.651550 Using /lava-796430 at stage 0
168 05:04:25.653125 uuid=796430_1.5.2.4.1 testdef=None
169 05:04:25.653461 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:04:25.653732 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 05:04:25.655545 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:04:25.656391 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 05:04:25.658710 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:04:25.659561 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 05:04:25.661840 runner path: /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/0/tests/0_dmesg test_uuid 796430_1.5.2.4.1
178 05:04:25.662456 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:04:25.663235 Creating lava-test-runner.conf files
181 05:04:25.663438 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796430/lava-overlay-yhbcv3sw/lava-796430/0 for stage 0
182 05:04:25.663780 - 0_dmesg
183 05:04:25.664185 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:04:25.664474 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 05:04:25.688058 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:04:25.688474 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:04:25.688742 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:04:25.689013 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:04:25.689277 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:04:26.655119 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:04:26.655594 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 05:04:26.655843 extracting modules file /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796430/extract-overlay-ramdisk-4xlze7s1/ramdisk
193 05:04:28.004626 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 05:04:28.005109 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 05:04:28.005390 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796430/compress-overlay-g0h_giab/overlay-1.5.2.5.tar.gz to ramdisk
196 05:04:28.005607 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796430/compress-overlay-g0h_giab/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796430/extract-overlay-ramdisk-4xlze7s1/ramdisk
197 05:04:28.036320 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:04:28.036780 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 05:04:28.037053 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 05:04:28.037280 Converting downloaded kernel to a uImage
201 05:04:28.037592 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/kernel/Image /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/kernel/uImage
202 05:04:28.513036 output: Image Name:
203 05:04:28.513461 output: Created: Thu Oct 3 05:04:28 2024
204 05:04:28.513672 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:04:28.513873 output: Data Size: 45998592 Bytes = 44920.50 KiB = 43.87 MiB
206 05:04:28.514072 output: Load Address: 01080000
207 05:04:28.514267 output: Entry Point: 01080000
208 05:04:28.514462 output:
209 05:04:28.514789 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 05:04:28.515051 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 05:04:28.515319 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 05:04:28.515566 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:04:28.515819 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 05:04:28.516109 Building ramdisk /var/lib/lava/dispatcher/tmp/796430/extract-overlay-ramdisk-4xlze7s1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796430/extract-overlay-ramdisk-4xlze7s1/ramdisk
215 05:04:31.060136 >> 181660 blocks
216 05:04:39.484325 Adding RAMdisk u-boot header.
217 05:04:39.485024 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796430/extract-overlay-ramdisk-4xlze7s1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796430/extract-overlay-ramdisk-4xlze7s1/ramdisk.cpio.gz.uboot
218 05:04:39.780237 output: Image Name:
219 05:04:39.780659 output: Created: Thu Oct 3 05:04:39 2024
220 05:04:39.780867 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:04:39.781070 output: Data Size: 26054793 Bytes = 25444.13 KiB = 24.85 MiB
222 05:04:39.781269 output: Load Address: 00000000
223 05:04:39.781465 output: Entry Point: 00000000
224 05:04:39.781662 output:
225 05:04:39.782239 rename /var/lib/lava/dispatcher/tmp/796430/extract-overlay-ramdisk-4xlze7s1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/ramdisk/ramdisk.cpio.gz.uboot
226 05:04:39.782652 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 05:04:39.782931 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 05:04:39.783200 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 05:04:39.783439 No LXC device requested
230 05:04:39.783691 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:04:39.783947 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 05:04:39.784501 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:04:39.784957 Checking files for TFTP limit of 4294967296 bytes.
234 05:04:39.787876 end: 1 tftp-deploy (duration 00:00:17) [common]
235 05:04:39.788543 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:04:39.789116 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:04:39.789661 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:04:39.790208 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:04:39.790783 Using kernel file from prepare-kernel: 796430/tftp-deploy-efef138x/kernel/uImage
240 05:04:39.791467 substitutions:
241 05:04:39.791920 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:04:39.792391 - {DTB_ADDR}: 0x01070000
243 05:04:39.792830 - {DTB}: 796430/tftp-deploy-efef138x/dtb/meson-g12b-a311d-libretech-cc.dtb
244 05:04:39.793269 - {INITRD}: 796430/tftp-deploy-efef138x/ramdisk/ramdisk.cpio.gz.uboot
245 05:04:39.793705 - {KERNEL_ADDR}: 0x01080000
246 05:04:39.794135 - {KERNEL}: 796430/tftp-deploy-efef138x/kernel/uImage
247 05:04:39.794567 - {LAVA_MAC}: None
248 05:04:39.795039 - {PRESEED_CONFIG}: None
249 05:04:39.795474 - {PRESEED_LOCAL}: None
250 05:04:39.795906 - {RAMDISK_ADDR}: 0x08000000
251 05:04:39.796361 - {RAMDISK}: 796430/tftp-deploy-efef138x/ramdisk/ramdisk.cpio.gz.uboot
252 05:04:39.796798 - {ROOT_PART}: None
253 05:04:39.797232 - {ROOT}: None
254 05:04:39.797660 - {SERVER_IP}: 192.168.6.2
255 05:04:39.798091 - {TEE_ADDR}: 0x83000000
256 05:04:39.798519 - {TEE}: None
257 05:04:39.798945 Parsed boot commands:
258 05:04:39.799360 - setenv autoload no
259 05:04:39.799785 - setenv initrd_high 0xffffffff
260 05:04:39.800242 - setenv fdt_high 0xffffffff
261 05:04:39.800669 - dhcp
262 05:04:39.801096 - setenv serverip 192.168.6.2
263 05:04:39.801523 - tftpboot 0x01080000 796430/tftp-deploy-efef138x/kernel/uImage
264 05:04:39.801946 - tftpboot 0x08000000 796430/tftp-deploy-efef138x/ramdisk/ramdisk.cpio.gz.uboot
265 05:04:39.802372 - tftpboot 0x01070000 796430/tftp-deploy-efef138x/dtb/meson-g12b-a311d-libretech-cc.dtb
266 05:04:39.802801 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:04:39.803235 - bootm 0x01080000 0x08000000 0x01070000
268 05:04:39.803782 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:04:39.805442 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:04:39.805926 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 05:04:39.820946 Setting prompt string to ['lava-test: # ']
273 05:04:39.822554 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:04:39.823203 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:04:39.823793 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:04:39.824411 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:04:39.825671 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 05:04:39.861799 >> OK - accepted request
279 05:04:39.863911 Returned 0 in 0 seconds
280 05:04:39.965176 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:04:39.966940 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:04:39.967561 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:04:39.968169 Setting prompt string to ['Hit any key to stop autoboot']
285 05:04:39.968663 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:04:39.970404 Trying 192.168.56.21...
287 05:04:39.970912 Connected to conserv1.
288 05:04:39.971356 Escape character is '^]'.
289 05:04:39.971816
290 05:04:39.972318 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 05:04:39.972782
292 05:04:50.882556 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 05:04:50.883242 bl2_stage_init 0x81
294 05:04:50.888099 hw id: 0x0000 - pwm id 0x01
295 05:04:50.888608 bl2_stage_init 0xc1
296 05:04:50.889065 bl2_stage_init 0x02
297 05:04:50.889517
298 05:04:50.893721 L0:00000000
299 05:04:50.894210 L1:20000703
300 05:04:50.894658 L2:00008067
301 05:04:50.895100 L3:14000000
302 05:04:50.895526 B2:00402000
303 05:04:50.899220 B1:e0f83180
304 05:04:50.899675
305 05:04:50.900139 TE: 58150
306 05:04:50.900571
307 05:04:50.904816 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 05:04:50.905276
309 05:04:50.905708 Board ID = 1
310 05:04:50.910451 Set A53 clk to 24M
311 05:04:50.910923 Set A73 clk to 24M
312 05:04:50.911535 Set clk81 to 24M
313 05:04:50.916057 A53 clk: 1200 MHz
314 05:04:50.916518 A73 clk: 1200 MHz
315 05:04:50.916949 CLK81: 166.6M
316 05:04:50.917374 smccc: 00012aab
317 05:04:50.921690 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 05:04:50.927241 board id: 1
319 05:04:50.933060 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 05:04:50.943685 fw parse done
321 05:04:50.949685 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 05:04:50.992326 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 05:04:51.003165 PIEI prepare done
324 05:04:51.003644 fastboot data load
325 05:04:51.004110 fastboot data verify
326 05:04:51.008858 verify result: 266
327 05:04:51.014493 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 05:04:51.014958 LPDDR4 probe
329 05:04:51.015392 ddr clk to 1584MHz
330 05:04:51.022499 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 05:04:51.059815
332 05:04:51.060393 dmc_version 0001
333 05:04:51.066403 Check phy result
334 05:04:51.072224 INFO : End of CA training
335 05:04:51.072705 INFO : End of initialization
336 05:04:51.077830 INFO : Training has run successfully!
337 05:04:51.078296 Check phy result
338 05:04:51.083449 INFO : End of initialization
339 05:04:51.083914 INFO : End of read enable training
340 05:04:51.089022 INFO : End of fine write leveling
341 05:04:51.094726 INFO : End of Write leveling coarse delay
342 05:04:51.095251 INFO : Training has run successfully!
343 05:04:51.095687 Check phy result
344 05:04:51.100263 INFO : End of initialization
345 05:04:51.100740 INFO : End of read dq deskew training
346 05:04:51.105834 INFO : End of MPR read delay center optimization
347 05:04:51.111449 INFO : End of write delay center optimization
348 05:04:51.117035 INFO : End of read delay center optimization
349 05:04:51.117504 INFO : End of max read latency training
350 05:04:51.122756 INFO : Training has run successfully!
351 05:04:51.123219 1D training succeed
352 05:04:51.131873 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 05:04:51.179585 Check phy result
354 05:04:51.180227 INFO : End of initialization
355 05:04:51.201976 INFO : End of 2D read delay Voltage center optimization
356 05:04:51.222347 INFO : End of 2D read delay Voltage center optimization
357 05:04:51.273342 INFO : End of 2D write delay Voltage center optimization
358 05:04:51.323707 INFO : End of 2D write delay Voltage center optimization
359 05:04:51.329265 INFO : Training has run successfully!
360 05:04:51.329742
361 05:04:51.330221 channel==0
362 05:04:51.334813 RxClkDly_Margin_A0==78 ps 8
363 05:04:51.335336 TxDqDly_Margin_A0==98 ps 10
364 05:04:51.340436 RxClkDly_Margin_A1==88 ps 9
365 05:04:51.340933 TxDqDly_Margin_A1==98 ps 10
366 05:04:51.341372 TrainedVREFDQ_A0==74
367 05:04:51.346034 TrainedVREFDQ_A1==74
368 05:04:51.346502 VrefDac_Margin_A0==25
369 05:04:51.346936 DeviceVref_Margin_A0==40
370 05:04:51.351738 VrefDac_Margin_A1==25
371 05:04:51.352232 DeviceVref_Margin_A1==40
372 05:04:51.352666
373 05:04:51.353099
374 05:04:51.357236 channel==1
375 05:04:51.357707 RxClkDly_Margin_A0==98 ps 10
376 05:04:51.358155 TxDqDly_Margin_A0==98 ps 10
377 05:04:51.362801 RxClkDly_Margin_A1==98 ps 10
378 05:04:51.363276 TxDqDly_Margin_A1==88 ps 9
379 05:04:51.368431 TrainedVREFDQ_A0==77
380 05:04:51.368913 TrainedVREFDQ_A1==77
381 05:04:51.369354 VrefDac_Margin_A0==24
382 05:04:51.373987 DeviceVref_Margin_A0==37
383 05:04:51.374447 VrefDac_Margin_A1==23
384 05:04:51.379601 DeviceVref_Margin_A1==37
385 05:04:51.380078
386 05:04:51.380518 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 05:04:51.385239
388 05:04:51.413492 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000017 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000018 0000001a 00000018 00000018 00000019 0000001a 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
389 05:04:51.414176 2D training succeed
390 05:04:51.418900 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 05:04:51.424424 auto size-- 65535DDR cs0 size: 2048MB
392 05:04:51.424900 DDR cs1 size: 2048MB
393 05:04:51.430055 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 05:04:51.430617 cs0 DataBus test pass
395 05:04:51.435635 cs1 DataBus test pass
396 05:04:51.436185 cs0 AddrBus test pass
397 05:04:51.436625 cs1 AddrBus test pass
398 05:04:51.437052
399 05:04:51.441203 100bdlr_step_size ps== 420
400 05:04:51.441692 result report
401 05:04:51.446827 boot times 0Enable ddr reg access
402 05:04:51.451621 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 05:04:51.465976 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 05:04:52.039655 0.0;M3 CHK:0;cm4_sp_mode 0
405 05:04:52.040385 MVN_1=0x00000000
406 05:04:52.045180 MVN_2=0x00000000
407 05:04:52.052175 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 05:04:52.052753 OPS=0x10
409 05:04:52.053224 ring efuse init
410 05:04:52.053809 chipver efuse init
411 05:04:52.059075 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 05:04:52.059748 [0.018961 Inits done]
413 05:04:52.066953 secure task start!
414 05:04:52.067649 high task start!
415 05:04:52.068180 low task start!
416 05:04:52.068665 run into bl31
417 05:04:52.073900 NOTICE: BL31: v1.3(release):4fc40b1
418 05:04:52.080958 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 05:04:52.081386 NOTICE: BL31: G12A normal boot!
420 05:04:52.106452 NOTICE: BL31: BL33 decompress pass
421 05:04:52.111120 ERROR: Error initializing runtime service opteed_fast
422 05:04:53.344871
423 05:04:53.345282
424 05:04:53.353208 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 05:04:53.353493
426 05:04:53.353712 Model: Libre Computer AML-A311D-CC Alta
427 05:04:53.561839 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 05:04:53.585293 DRAM: 2 GiB (effective 3.8 GiB)
429 05:04:53.728387 Core: 408 devices, 31 uclasses, devicetree: separate
430 05:04:53.734174 WDT: Not starting watchdog@f0d0
431 05:04:53.766318 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 05:04:53.778878 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 05:04:53.783736 ** Bad device specification mmc 0 **
434 05:04:53.794273 Card did not respond to voltage select! : -110
435 05:04:53.801758 ** Bad device specification mmc 0 **
436 05:04:53.802298 Couldn't find partition mmc 0
437 05:04:53.810295 Card did not respond to voltage select! : -110
438 05:04:53.815676 ** Bad device specification mmc 0 **
439 05:04:53.816083 Couldn't find partition mmc 0
440 05:04:53.820725 Error: could not access storage.
441 05:04:55.083268 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
442 05:04:55.083817 bl2_stage_init 0x81
443 05:04:55.088820 hw id: 0x0000 - pwm id 0x01
444 05:04:55.089120 bl2_stage_init 0xc1
445 05:04:55.089386 bl2_stage_init 0x02
446 05:04:55.089624
447 05:04:55.094524 L0:00000000
448 05:04:55.094831 L1:20000703
449 05:04:55.095393 L2:00008067
450 05:04:55.095620 L3:14000000
451 05:04:55.095831 B2:00402000
452 05:04:55.097228 B1:e0f83180
453 05:04:55.097786
454 05:04:55.098271 TE: 58150
455 05:04:55.098496
456 05:04:55.108294 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
457 05:04:55.108834
458 05:04:55.109561 Board ID = 1
459 05:04:55.110340 Set A53 clk to 24M
460 05:04:55.110586 Set A73 clk to 24M
461 05:04:55.113820 Set clk81 to 24M
462 05:04:55.114112 A53 clk: 1200 MHz
463 05:04:55.114324 A73 clk: 1200 MHz
464 05:04:55.117581 CLK81: 166.6M
465 05:04:55.117877 smccc: 00012aac
466 05:04:55.123187 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
467 05:04:55.123475 board id: 1
468 05:04:55.132682 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
469 05:04:55.144561 fw parse done
470 05:04:55.149414 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
471 05:04:55.192916 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
472 05:04:55.204025 PIEI prepare done
473 05:04:55.204347 fastboot data load
474 05:04:55.204989 fastboot data verify
475 05:04:55.209329 verify result: 266
476 05:04:55.215148 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
477 05:04:55.215465 LPDDR4 probe
478 05:04:55.216114 ddr clk to 1584MHz
479 05:04:55.223169 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
480 05:04:55.260356
481 05:04:55.260890 dmc_version 0001
482 05:04:55.266827 Check phy result
483 05:04:55.272778 INFO : End of CA training
484 05:04:55.273083 INFO : End of initialization
485 05:04:55.278295 INFO : Training has run successfully!
486 05:04:55.279235 Check phy result
487 05:04:55.283952 INFO : End of initialization
488 05:04:55.284276 INFO : End of read enable training
489 05:04:55.287278 INFO : End of fine write leveling
490 05:04:55.292913 INFO : End of Write leveling coarse delay
491 05:04:55.298638 INFO : Training has run successfully!
492 05:04:55.298954 Check phy result
493 05:04:55.299162 INFO : End of initialization
494 05:04:55.304035 INFO : End of read dq deskew training
495 05:04:55.307372 INFO : End of MPR read delay center optimization
496 05:04:55.312950 INFO : End of write delay center optimization
497 05:04:55.318548 INFO : End of read delay center optimization
498 05:04:55.318849 INFO : End of max read latency training
499 05:04:55.324188 INFO : Training has run successfully!
500 05:04:55.324632 1D training succeed
501 05:04:55.332360 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 05:04:55.380108 Check phy result
503 05:04:55.380511 INFO : End of initialization
504 05:04:55.402400 INFO : End of 2D read delay Voltage center optimization
505 05:04:55.422644 INFO : End of 2D read delay Voltage center optimization
506 05:04:55.474616 INFO : End of 2D write delay Voltage center optimization
507 05:04:55.523747 INFO : End of 2D write delay Voltage center optimization
508 05:04:55.529313 INFO : Training has run successfully!
509 05:04:55.530244
510 05:04:55.530493 channel==0
511 05:04:55.534757 RxClkDly_Margin_A0==78 ps 8
512 05:04:55.535059 TxDqDly_Margin_A0==98 ps 10
513 05:04:55.538331 RxClkDly_Margin_A1==88 ps 9
514 05:04:55.538618 TxDqDly_Margin_A1==98 ps 10
515 05:04:55.543671 TrainedVREFDQ_A0==74
516 05:04:55.544131 TrainedVREFDQ_A1==75
517 05:04:55.544944 VrefDac_Margin_A0==26
518 05:04:55.549405 DeviceVref_Margin_A0==40
519 05:04:55.549710 VrefDac_Margin_A1==25
520 05:04:55.554866 DeviceVref_Margin_A1==39
521 05:04:55.555172
522 05:04:55.555771
523 05:04:55.556024 channel==1
524 05:04:55.556245 RxClkDly_Margin_A0==88 ps 9
525 05:04:55.560535 TxDqDly_Margin_A0==88 ps 9
526 05:04:55.560836 RxClkDly_Margin_A1==98 ps 10
527 05:04:55.566094 TxDqDly_Margin_A1==98 ps 10
528 05:04:55.567362 TrainedVREFDQ_A0==76
529 05:04:55.567766 TrainedVREFDQ_A1==78
530 05:04:55.571803 VrefDac_Margin_A0==23
531 05:04:55.572103 DeviceVref_Margin_A0==38
532 05:04:55.577296 VrefDac_Margin_A1==23
533 05:04:55.577598 DeviceVref_Margin_A1==36
534 05:04:55.577808
535 05:04:55.583074 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
536 05:04:55.583388
537 05:04:55.611334 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000017 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
538 05:04:55.616454 2D training succeed
539 05:04:55.622313 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
540 05:04:55.622623 auto size-- 65535DDR cs0 size: 2048MB
541 05:04:55.627697 DDR cs1 size: 2048MB
542 05:04:55.628135 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
543 05:04:55.633328 cs0 DataBus test pass
544 05:04:55.633620 cs1 DataBus test pass
545 05:04:55.633831 cs0 AddrBus test pass
546 05:04:55.638941 cs1 AddrBus test pass
547 05:04:55.640102
548 05:04:55.640791 100bdlr_step_size ps== 420
549 05:04:55.641013 result report
550 05:04:55.644468 boot times 0Enable ddr reg access
551 05:04:55.652116 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
552 05:04:55.665662 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
553 05:04:56.237786 0.0;M3 CHK:0;cm4_sp_mode 0
554 05:04:56.238214 MVN_1=0x00000000
555 05:04:56.243059 MVN_2=0x00000000
556 05:04:56.248832 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
557 05:04:56.249141 OPS=0x10
558 05:04:56.249352 ring efuse init
559 05:04:56.249954 chipver efuse init
560 05:04:56.254491 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
561 05:04:56.259925 [0.018961 Inits done]
562 05:04:56.260241 secure task start!
563 05:04:56.260450 high task start!
564 05:04:56.264578 low task start!
565 05:04:56.264872 run into bl31
566 05:04:56.271504 NOTICE: BL31: v1.3(release):4fc40b1
567 05:04:56.278959 NOTICE: BL31: Built : 15:58:17, May 22 2019
568 05:04:56.279386 NOTICE: BL31: G12A normal boot!
569 05:04:56.304377 NOTICE: BL31: BL33 decompress pass
570 05:04:56.310058 ERROR: Error initializing runtime service opteed_fast
571 05:04:57.543025
572 05:04:57.543439
573 05:04:57.550456 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
574 05:04:57.550762
575 05:04:57.550974 Model: Libre Computer AML-A311D-CC Alta
576 05:04:57.759874 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
577 05:04:57.783390 DRAM: 2 GiB (effective 3.8 GiB)
578 05:04:57.926373 Core: 408 devices, 31 uclasses, devicetree: separate
579 05:04:57.932195 WDT: Not starting watchdog@f0d0
580 05:04:57.964428 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
581 05:04:57.976914 Loading Environment from FAT... Card did not respond to voltage select! : -110
582 05:04:57.981910 ** Bad device specification mmc 0 **
583 05:04:57.992207 Card did not respond to voltage select! : -110
584 05:04:57.999832 ** Bad device specification mmc 0 **
585 05:04:58.000391 Couldn't find partition mmc 0
586 05:04:58.008210 Card did not respond to voltage select! : -110
587 05:04:58.013699 ** Bad device specification mmc 0 **
588 05:04:58.014226 Couldn't find partition mmc 0
589 05:04:58.018770 Error: could not access storage.
590 05:04:58.361222 Net: eth0: ethernet@ff3f0000
591 05:04:58.361865 starting USB...
592 05:04:58.613028 Bus usb@ff500000: Register 3000140 NbrPorts 3
593 05:04:58.613653 Starting the controller
594 05:04:58.620052 USB XHCI 1.10
595 05:05:00.334662 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
596 05:05:00.335085 bl2_stage_init 0x01
597 05:05:00.335300 bl2_stage_init 0x81
598 05:05:00.340605 hw id: 0x0000 - pwm id 0x01
599 05:05:00.341024 bl2_stage_init 0xc1
600 05:05:00.341364 bl2_stage_init 0x02
601 05:05:00.341686
602 05:05:00.345987 L0:00000000
603 05:05:00.346440 L1:20000703
604 05:05:00.346686 L2:00008067
605 05:05:00.346900 L3:14000000
606 05:05:00.351480 B2:00402000
607 05:05:00.351907 B1:e0f83180
608 05:05:00.352282
609 05:05:00.352609 TE: 58159
610 05:05:00.352922
611 05:05:00.357090 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
612 05:05:00.357396
613 05:05:00.357614 Board ID = 1
614 05:05:00.362687 Set A53 clk to 24M
615 05:05:00.363101 Set A73 clk to 24M
616 05:05:00.363441 Set clk81 to 24M
617 05:05:00.368315 A53 clk: 1200 MHz
618 05:05:00.368746 A73 clk: 1200 MHz
619 05:05:00.369075 CLK81: 166.6M
620 05:05:00.369393 smccc: 00012ab5
621 05:05:00.374046 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
622 05:05:00.379478 board id: 1
623 05:05:00.385138 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
624 05:05:00.395999 fw parse done
625 05:05:00.402106 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
626 05:05:00.443716 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
627 05:05:00.455461 PIEI prepare done
628 05:05:00.455787 fastboot data load
629 05:05:00.456038 fastboot data verify
630 05:05:00.461071 verify result: 266
631 05:05:00.466695 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
632 05:05:00.467127 LPDDR4 probe
633 05:05:00.467374 ddr clk to 1584MHz
634 05:05:00.474690 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
635 05:05:00.511954
636 05:05:00.512328 dmc_version 0001
637 05:05:00.518622 Check phy result
638 05:05:00.524535 INFO : End of CA training
639 05:05:00.524972 INFO : End of initialization
640 05:05:00.530166 INFO : Training has run successfully!
641 05:05:00.530460 Check phy result
642 05:05:00.535919 INFO : End of initialization
643 05:05:00.536241 INFO : End of read enable training
644 05:05:00.539244 INFO : End of fine write leveling
645 05:05:00.544728 INFO : End of Write leveling coarse delay
646 05:05:00.550275 INFO : Training has run successfully!
647 05:05:00.550564 Check phy result
648 05:05:00.550788 INFO : End of initialization
649 05:05:00.555844 INFO : End of read dq deskew training
650 05:05:00.561449 INFO : End of MPR read delay center optimization
651 05:05:00.561749 INFO : End of write delay center optimization
652 05:05:00.567088 INFO : End of read delay center optimization
653 05:05:00.572655 INFO : End of max read latency training
654 05:05:00.572952 INFO : Training has run successfully!
655 05:05:00.578211 1D training succeed
656 05:05:00.584225 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
657 05:05:00.631723 Check phy result
658 05:05:00.632116 INFO : End of initialization
659 05:05:00.653364 INFO : End of 2D read delay Voltage center optimization
660 05:05:00.673524 INFO : End of 2D read delay Voltage center optimization
661 05:05:00.725443 INFO : End of 2D write delay Voltage center optimization
662 05:05:00.774826 INFO : End of 2D write delay Voltage center optimization
663 05:05:00.780195 INFO : Training has run successfully!
664 05:05:00.780492
665 05:05:00.780705 channel==0
666 05:05:00.785749 RxClkDly_Margin_A0==69 ps 7
667 05:05:00.786043 TxDqDly_Margin_A0==98 ps 10
668 05:05:00.791422 RxClkDly_Margin_A1==88 ps 9
669 05:05:00.791709 TxDqDly_Margin_A1==98 ps 10
670 05:05:00.791923 TrainedVREFDQ_A0==74
671 05:05:00.797100 TrainedVREFDQ_A1==74
672 05:05:00.797394 VrefDac_Margin_A0==25
673 05:05:00.797602 DeviceVref_Margin_A0==40
674 05:05:00.802576 VrefDac_Margin_A1==25
675 05:05:00.802866 DeviceVref_Margin_A1==40
676 05:05:00.803074
677 05:05:00.803288
678 05:05:00.808218 channel==1
679 05:05:00.808516 RxClkDly_Margin_A0==88 ps 9
680 05:05:00.808737 TxDqDly_Margin_A0==98 ps 10
681 05:05:00.813699 RxClkDly_Margin_A1==98 ps 10
682 05:05:00.814002 TxDqDly_Margin_A1==88 ps 9
683 05:05:00.819363 TrainedVREFDQ_A0==77
684 05:05:00.819662 TrainedVREFDQ_A1==77
685 05:05:00.819887 VrefDac_Margin_A0==23
686 05:05:00.825132 DeviceVref_Margin_A0==37
687 05:05:00.825420 VrefDac_Margin_A1==23
688 05:05:00.830526 DeviceVref_Margin_A1==37
689 05:05:00.830823
690 05:05:00.831040 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
691 05:05:00.831249
692 05:05:00.864189 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
693 05:05:00.864556 2D training succeed
694 05:05:00.869791 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
695 05:05:00.875358 auto size-- 65535DDR cs0 size: 2048MB
696 05:05:00.875647 DDR cs1 size: 2048MB
697 05:05:00.881015 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
698 05:05:00.881306 cs0 DataBus test pass
699 05:05:00.886600 cs1 DataBus test pass
700 05:05:00.886887 cs0 AddrBus test pass
701 05:05:00.887102 cs1 AddrBus test pass
702 05:05:00.887304
703 05:05:00.892189 100bdlr_step_size ps== 420
704 05:05:00.892477 result report
705 05:05:00.897722 boot times 0Enable ddr reg access
706 05:05:00.902226 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
707 05:05:00.916597 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
708 05:05:01.488499 0.0;M3 CHK:0;cm4_sp_mode 0
709 05:05:01.488925 MVN_1=0x00000000
710 05:05:01.494056 MVN_2=0x00000000
711 05:05:01.499708 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
712 05:05:01.500022 OPS=0x10
713 05:05:01.500240 ring efuse init
714 05:05:01.500443 chipver efuse init
715 05:05:01.505326 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
716 05:05:01.511040 [0.018961 Inits done]
717 05:05:01.511315 secure task start!
718 05:05:01.511519 high task start!
719 05:05:01.515516 low task start!
720 05:05:01.515791 run into bl31
721 05:05:01.522167 NOTICE: BL31: v1.3(release):4fc40b1
722 05:05:01.529971 NOTICE: BL31: Built : 15:58:17, May 22 2019
723 05:05:01.530264 NOTICE: BL31: G12A normal boot!
724 05:05:01.555442 NOTICE: BL31: BL33 decompress pass
725 05:05:01.561124 ERROR: Error initializing runtime service opteed_fast
726 05:05:02.794069
727 05:05:02.794503
728 05:05:02.802360 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
729 05:05:02.802673
730 05:05:02.802896 Model: Libre Computer AML-A311D-CC Alta
731 05:05:03.010814 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
732 05:05:03.034367 DRAM: 2 GiB (effective 3.8 GiB)
733 05:05:03.177356 Core: 408 devices, 31 uclasses, devicetree: separate
734 05:05:03.183100 WDT: Not starting watchdog@f0d0
735 05:05:03.215371 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
736 05:05:03.227800 Loading Environment from FAT... Card did not respond to voltage select! : -110
737 05:05:03.232786 ** Bad device specification mmc 0 **
738 05:05:03.243100 Card did not respond to voltage select! : -110
739 05:05:03.250743 ** Bad device specification mmc 0 **
740 05:05:03.251089 Couldn't find partition mmc 0
741 05:05:03.259121 Card did not respond to voltage select! : -110
742 05:05:03.264637 ** Bad device specification mmc 0 **
743 05:05:03.265109 Couldn't find partition mmc 0
744 05:05:03.269657 Error: could not access storage.
745 05:05:03.612245 Net: eth0: ethernet@ff3f0000
746 05:05:03.612894 starting USB...
747 05:05:03.863969 Bus usb@ff500000: Register 3000140 NbrPorts 3
748 05:05:03.864603 Starting the controller
749 05:05:03.870944 USB XHCI 1.10
750 05:05:06.033376 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
751 05:05:06.034034 bl2_stage_init 0x01
752 05:05:06.034505 bl2_stage_init 0x81
753 05:05:06.038881 hw id: 0x0000 - pwm id 0x01
754 05:05:06.039375 bl2_stage_init 0xc1
755 05:05:06.039828 bl2_stage_init 0x02
756 05:05:06.040334
757 05:05:06.044361 L0:00000000
758 05:05:06.044851 L1:20000703
759 05:05:06.045300 L2:00008067
760 05:05:06.045746 L3:14000000
761 05:05:06.047238 B2:00402000
762 05:05:06.047728 B1:e0f83180
763 05:05:06.048212
764 05:05:06.048659 TE: 58124
765 05:05:06.049102
766 05:05:06.058480 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 05:05:06.058997
768 05:05:06.059454 Board ID = 1
769 05:05:06.059896 Set A53 clk to 24M
770 05:05:06.060373 Set A73 clk to 24M
771 05:05:06.063976 Set clk81 to 24M
772 05:05:06.064488 A53 clk: 1200 MHz
773 05:05:06.064933 A73 clk: 1200 MHz
774 05:05:06.069674 CLK81: 166.6M
775 05:05:06.070156 smccc: 00012a92
776 05:05:06.075132 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 05:05:06.075609 board id: 1
778 05:05:06.083876 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 05:05:06.094499 fw parse done
780 05:05:06.100395 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 05:05:06.143031 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 05:05:06.153852 PIEI prepare done
783 05:05:06.154348 fastboot data load
784 05:05:06.154805 fastboot data verify
785 05:05:06.159467 verify result: 266
786 05:05:06.165070 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 05:05:06.165607 LPDDR4 probe
788 05:05:06.166060 ddr clk to 1584MHz
789 05:05:06.172205 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 05:05:06.210341
791 05:05:06.210852 dmc_version 0001
792 05:05:06.217003 Check phy result
793 05:05:06.222841 INFO : End of CA training
794 05:05:06.223325 INFO : End of initialization
795 05:05:06.228591 INFO : Training has run successfully!
796 05:05:06.229088 Check phy result
797 05:05:06.234101 INFO : End of initialization
798 05:05:06.234584 INFO : End of read enable training
799 05:05:06.237396 INFO : End of fine write leveling
800 05:05:06.242974 INFO : End of Write leveling coarse delay
801 05:05:06.248545 INFO : Training has run successfully!
802 05:05:06.249018 Check phy result
803 05:05:06.249462 INFO : End of initialization
804 05:05:06.254172 INFO : End of read dq deskew training
805 05:05:06.257587 INFO : End of MPR read delay center optimization
806 05:05:06.263205 INFO : End of write delay center optimization
807 05:05:06.268853 INFO : End of read delay center optimization
808 05:05:06.269329 INFO : End of max read latency training
809 05:05:06.274360 INFO : Training has run successfully!
810 05:05:06.274834 1D training succeed
811 05:05:06.282543 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 05:05:06.330166 Check phy result
813 05:05:06.330781 INFO : End of initialization
814 05:05:06.351801 INFO : End of 2D read delay Voltage center optimization
815 05:05:06.372772 INFO : End of 2D read delay Voltage center optimization
816 05:05:06.424681 INFO : End of 2D write delay Voltage center optimization
817 05:05:06.473957 INFO : End of 2D write delay Voltage center optimization
818 05:05:06.479480 INFO : Training has run successfully!
819 05:05:06.480074
820 05:05:06.480557 channel==0
821 05:05:06.485124 RxClkDly_Margin_A0==88 ps 9
822 05:05:06.485685 TxDqDly_Margin_A0==98 ps 10
823 05:05:06.490627 RxClkDly_Margin_A1==88 ps 9
824 05:05:06.491174 TxDqDly_Margin_A1==98 ps 10
825 05:05:06.491661 TrainedVREFDQ_A0==74
826 05:05:06.496362 TrainedVREFDQ_A1==74
827 05:05:06.496941 VrefDac_Margin_A0==25
828 05:05:06.497411 DeviceVref_Margin_A0==40
829 05:05:06.501869 VrefDac_Margin_A1==25
830 05:05:06.502424 DeviceVref_Margin_A1==40
831 05:05:06.502858
832 05:05:06.503288
833 05:05:06.507473 channel==1
834 05:05:06.508025 RxClkDly_Margin_A0==98 ps 10
835 05:05:06.508473 TxDqDly_Margin_A0==98 ps 10
836 05:05:06.513014 RxClkDly_Margin_A1==98 ps 10
837 05:05:06.513538 TxDqDly_Margin_A1==88 ps 9
838 05:05:06.518699 TrainedVREFDQ_A0==77
839 05:05:06.519268 TrainedVREFDQ_A1==77
840 05:05:06.519753 VrefDac_Margin_A0==23
841 05:05:06.524317 DeviceVref_Margin_A0==37
842 05:05:06.524853 VrefDac_Margin_A1==24
843 05:05:06.529951 DeviceVref_Margin_A1==37
844 05:05:06.530479
845 05:05:06.530914 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 05:05:06.535431
847 05:05:06.563340 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
848 05:05:06.563944 2D training succeed
849 05:05:06.569031 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 05:05:06.574568 auto size-- 65535DDR cs0 size: 2048MB
851 05:05:06.575095 DDR cs1 size: 2048MB
852 05:05:06.580227 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 05:05:06.580758 cs0 DataBus test pass
854 05:05:06.585720 cs1 DataBus test pass
855 05:05:06.586249 cs0 AddrBus test pass
856 05:05:06.586679 cs1 AddrBus test pass
857 05:05:06.587104
858 05:05:06.591361 100bdlr_step_size ps== 420
859 05:05:06.591902 result report
860 05:05:06.596956 boot times 0Enable ddr reg access
861 05:05:06.602373 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 05:05:06.615954 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 05:05:07.187635 0.0;M3 CHK:0;cm4_sp_mode 0
864 05:05:07.188103 MVN_1=0x00000000
865 05:05:07.193176 MVN_2=0x00000000
866 05:05:07.198933 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 05:05:07.199239 OPS=0x10
868 05:05:07.199448 ring efuse init
869 05:05:07.199653 chipver efuse init
870 05:05:07.207109 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 05:05:07.207442 [0.018961 Inits done]
872 05:05:07.214708 secure task start!
873 05:05:07.215028 high task start!
874 05:05:07.215237 low task start!
875 05:05:07.215451 run into bl31
876 05:05:07.221442 NOTICE: BL31: v1.3(release):4fc40b1
877 05:05:07.229263 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 05:05:07.229593 NOTICE: BL31: G12A normal boot!
879 05:05:07.255166 NOTICE: BL31: BL33 decompress pass
880 05:05:07.260887 ERROR: Error initializing runtime service opteed_fast
881 05:05:08.493812
882 05:05:08.494480
883 05:05:08.501729 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 05:05:08.502299
885 05:05:08.502801 Model: Libre Computer AML-A311D-CC Alta
886 05:05:08.710664 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 05:05:08.734178 DRAM: 2 GiB (effective 3.8 GiB)
888 05:05:08.877079 Core: 408 devices, 31 uclasses, devicetree: separate
889 05:05:08.882947 WDT: Not starting watchdog@f0d0
890 05:05:08.915631 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 05:05:08.927704 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 05:05:08.931745 ** Bad device specification mmc 0 **
893 05:05:08.942986 Card did not respond to voltage select! : -110
894 05:05:08.950544 ** Bad device specification mmc 0 **
895 05:05:08.951105 Couldn't find partition mmc 0
896 05:05:08.958930 Card did not respond to voltage select! : -110
897 05:05:08.964452 ** Bad device specification mmc 0 **
898 05:05:08.964994 Couldn't find partition mmc 0
899 05:05:08.969487 Error: could not access storage.
900 05:05:09.312597 Net: eth0: ethernet@ff3f0000
901 05:05:09.313224 starting USB...
902 05:05:09.563840 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 05:05:09.564506 Starting the controller
904 05:05:09.570716 USB XHCI 1.10
905 05:05:11.432999 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
906 05:05:11.433690 bl2_stage_init 0x81
907 05:05:11.438740 hw id: 0x0000 - pwm id 0x01
908 05:05:11.439305 bl2_stage_init 0xc1
909 05:05:11.439809 bl2_stage_init 0x02
910 05:05:11.440366
911 05:05:11.444263 L0:00000000
912 05:05:11.444797 L1:20000703
913 05:05:11.445258 L2:00008067
914 05:05:11.445706 L3:14000000
915 05:05:11.446146 B2:00402000
916 05:05:11.449781 B1:e0f83180
917 05:05:11.450294
918 05:05:11.450753 TE: 58150
919 05:05:11.451205
920 05:05:11.455375 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
921 05:05:11.455901
922 05:05:11.456399 Board ID = 1
923 05:05:11.461002 Set A53 clk to 24M
924 05:05:11.461519 Set A73 clk to 24M
925 05:05:11.461972 Set clk81 to 24M
926 05:05:11.466615 A53 clk: 1200 MHz
927 05:05:11.467125 A73 clk: 1200 MHz
928 05:05:11.467577 CLK81: 166.6M
929 05:05:11.468049 smccc: 00012aac
930 05:05:11.472215 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
931 05:05:11.477767 board id: 1
932 05:05:11.483566 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
933 05:05:11.494253 fw parse done
934 05:05:11.500266 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
935 05:05:11.542832 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
936 05:05:11.554016 PIEI prepare done
937 05:05:11.554556 fastboot data load
938 05:05:11.554993 fastboot data verify
939 05:05:11.559547 verify result: 266
940 05:05:11.565148 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
941 05:05:11.565671 LPDDR4 probe
942 05:05:11.566105 ddr clk to 1584MHz
943 05:05:11.573161 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
944 05:05:11.610486
945 05:05:11.611027 dmc_version 0001
946 05:05:11.617209 Check phy result
947 05:05:11.622898 INFO : End of CA training
948 05:05:11.623421 INFO : End of initialization
949 05:05:11.628472 INFO : Training has run successfully!
950 05:05:11.629013 Check phy result
951 05:05:11.634250 INFO : End of initialization
952 05:05:11.634785 INFO : End of read enable training
953 05:05:11.637544 INFO : End of fine write leveling
954 05:05:11.643070 INFO : End of Write leveling coarse delay
955 05:05:11.648751 INFO : Training has run successfully!
956 05:05:11.649269 Check phy result
957 05:05:11.649721 INFO : End of initialization
958 05:05:11.654148 INFO : End of read dq deskew training
959 05:05:11.657679 INFO : End of MPR read delay center optimization
960 05:05:11.663284 INFO : End of write delay center optimization
961 05:05:11.668836 INFO : End of read delay center optimization
962 05:05:11.669347 INFO : End of max read latency training
963 05:05:11.674451 INFO : Training has run successfully!
964 05:05:11.674964 1D training succeed
965 05:05:11.682467 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
966 05:05:11.730046 Check phy result
967 05:05:11.730583 INFO : End of initialization
968 05:05:11.752697 INFO : End of 2D read delay Voltage center optimization
969 05:05:11.772098 INFO : End of 2D read delay Voltage center optimization
970 05:05:11.825037 INFO : End of 2D write delay Voltage center optimization
971 05:05:11.874473 INFO : End of 2D write delay Voltage center optimization
972 05:05:11.880075 INFO : Training has run successfully!
973 05:05:11.880617
974 05:05:11.881100 channel==0
975 05:05:11.885594 RxClkDly_Margin_A0==78 ps 8
976 05:05:11.886122 TxDqDly_Margin_A0==98 ps 10
977 05:05:11.888830 RxClkDly_Margin_A1==88 ps 9
978 05:05:11.889353 TxDqDly_Margin_A1==98 ps 10
979 05:05:11.894464 TrainedVREFDQ_A0==74
980 05:05:11.894987 TrainedVREFDQ_A1==74
981 05:05:11.895442 VrefDac_Margin_A0==25
982 05:05:11.900075 DeviceVref_Margin_A0==40
983 05:05:11.900602 VrefDac_Margin_A1==25
984 05:05:11.905717 DeviceVref_Margin_A1==40
985 05:05:11.906230
986 05:05:11.906687
987 05:05:11.907132 channel==1
988 05:05:11.907570 RxClkDly_Margin_A0==98 ps 10
989 05:05:11.909054 TxDqDly_Margin_A0==98 ps 10
990 05:05:11.914533 RxClkDly_Margin_A1==98 ps 10
991 05:05:11.915046 TxDqDly_Margin_A1==98 ps 10
992 05:05:11.920272 TrainedVREFDQ_A0==77
993 05:05:11.920797 TrainedVREFDQ_A1==77
994 05:05:11.921252 VrefDac_Margin_A0==23
995 05:05:11.925792 DeviceVref_Margin_A0==37
996 05:05:11.926310 VrefDac_Margin_A1==23
997 05:05:11.926758 DeviceVref_Margin_A1==37
998 05:05:11.927197
999 05:05:11.931492 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1000 05:05:11.932039
1001 05:05:11.964805 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1002 05:05:11.965390 2D training succeed
1003 05:05:11.970483 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1004 05:05:11.976092 auto size-- 65535DDR cs0 size: 2048MB
1005 05:05:11.976613 DDR cs1 size: 2048MB
1006 05:05:11.981703 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1007 05:05:11.982219 cs0 DataBus test pass
1008 05:05:11.982673 cs1 DataBus test pass
1009 05:05:11.987251 cs0 AddrBus test pass
1010 05:05:11.987803 cs1 AddrBus test pass
1011 05:05:11.988334
1012 05:05:11.992877 100bdlr_step_size ps== 420
1013 05:05:11.993419 result report
1014 05:05:11.993854 boot times 0Enable ddr reg access
1015 05:05:12.002871 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1016 05:05:12.016320 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1017 05:05:12.589284 0.0;M3 CHK:0;cm4_sp_mode 0
1018 05:05:12.589959 MVN_1=0x00000000
1019 05:05:12.594755 MVN_2=0x00000000
1020 05:05:12.600496 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1021 05:05:12.601023 OPS=0x10
1022 05:05:12.601490 ring efuse init
1023 05:05:12.601939 chipver efuse init
1024 05:05:12.606089 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1025 05:05:12.611750 [0.018961 Inits done]
1026 05:05:12.612309 secure task start!
1027 05:05:12.612769 high task start!
1028 05:05:12.616376 low task start!
1029 05:05:12.616889 run into bl31
1030 05:05:12.622972 NOTICE: BL31: v1.3(release):4fc40b1
1031 05:05:12.630756 NOTICE: BL31: Built : 15:58:17, May 22 2019
1032 05:05:12.631297 NOTICE: BL31: G12A normal boot!
1033 05:05:12.656274 NOTICE: BL31: BL33 decompress pass
1034 05:05:12.661893 ERROR: Error initializing runtime service opteed_fast
1035 05:05:13.894789
1036 05:05:13.895441
1037 05:05:13.903202 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1038 05:05:13.903748
1039 05:05:13.904268 Model: Libre Computer AML-A311D-CC Alta
1040 05:05:14.111667 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1041 05:05:14.134975 DRAM: 2 GiB (effective 3.8 GiB)
1042 05:05:14.277965 Core: 408 devices, 31 uclasses, devicetree: separate
1043 05:05:14.283836 WDT: Not starting watchdog@f0d0
1044 05:05:14.316122 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1045 05:05:14.328515 Loading Environment from FAT... Card did not respond to voltage select! : -110
1046 05:05:14.333600 ** Bad device specification mmc 0 **
1047 05:05:14.344028 Card did not respond to voltage select! : -110
1048 05:05:14.351515 ** Bad device specification mmc 0 **
1049 05:05:14.352059 Couldn't find partition mmc 0
1050 05:05:14.360157 Card did not respond to voltage select! : -110
1051 05:05:14.365359 ** Bad device specification mmc 0 **
1052 05:05:14.365871 Couldn't find partition mmc 0
1053 05:05:14.370429 Error: could not access storage.
1054 05:05:14.712899 Net: eth0: ethernet@ff3f0000
1055 05:05:14.713546 starting USB...
1056 05:05:14.964696 Bus usb@ff500000: Register 3000140 NbrPorts 3
1057 05:05:14.965344 Starting the controller
1058 05:05:14.971734 USB XHCI 1.10
1059 05:05:16.525648 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1060 05:05:16.533915 scanning usb for storage devices... 0 Storage Device(s) found
1062 05:05:16.585029 Hit any key to stop autoboot: 1
1063 05:05:16.585651 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1064 05:05:16.586050 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1065 05:05:16.586349 Setting prompt string to ['=>']
1066 05:05:16.586648 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1067 05:05:16.591364 0
1068 05:05:16.592043 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1069 05:05:16.592416 Sending with 10 millisecond of delay
1071 05:05:17.726761 => setenv autoload no
1072 05:05:17.737626 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1073 05:05:17.741954 setenv autoload no
1074 05:05:17.742722 Sending with 10 millisecond of delay
1076 05:05:19.540126 => setenv initrd_high 0xffffffff
1077 05:05:19.550933 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1078 05:05:19.777902 setenv initrd_high 0xffffffff
1079 05:05:19.778671 Sending with 10 millisecond of delay
1081 05:05:21.394588 => setenv fdt_high 0xffffffff
1082 05:05:21.405371 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1083 05:05:21.406169 setenv fdt_high 0xffffffff
1084 05:05:21.406873 Sending with 10 millisecond of delay
1086 05:05:21.698657 => dhcp
1087 05:05:21.709452 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1088 05:05:21.710315 dhcp
1089 05:05:21.710731 Speed: 1000, full duplex
1090 05:05:21.711124 BOOTP broadcast 1
1091 05:05:21.873943 DHCP client bound to address 192.168.6.33 (164 ms)
1092 05:05:21.874791 Sending with 10 millisecond of delay
1094 05:05:23.550995 => setenv serverip 192.168.6.2
1095 05:05:23.561777 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1096 05:05:23.562582 setenv serverip 192.168.6.2
1097 05:05:23.563279 Sending with 10 millisecond of delay
1099 05:05:27.286452 => tftpboot 0x01080000 796430/tftp-deploy-efef138x/kernel/uImage
1100 05:05:27.297499 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1101 05:05:27.298663 tftpboot 0x01080000 796430/tftp-deploy-efef138x/kernel/uImage
1102 05:05:27.299227 Speed: 1000, full duplex
1103 05:05:27.299737 Using ethernet@ff3f0000 device
1104 05:05:27.300407 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1105 05:05:27.305720 Filename '796430/tftp-deploy-efef138x/kernel/uImage'.
1106 05:05:27.309642 Load address: 0x1080000
1107 05:05:31.475573 Loading: *################################################## 43.9 MiB
1108 05:05:31.476437 10.5 MiB/s
1109 05:05:31.476996 done
1110 05:05:31.479586 Bytes transferred = 45998656 (2bde240 hex)
1111 05:05:31.480521 Sending with 10 millisecond of delay
1113 05:05:36.166976 => tftpboot 0x08000000 796430/tftp-deploy-efef138x/ramdisk/ramdisk.cpio.gz.uboot
1114 05:05:36.177978 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1115 05:05:36.179093 tftpboot 0x08000000 796430/tftp-deploy-efef138x/ramdisk/ramdisk.cpio.gz.uboot
1116 05:05:36.179646 Speed: 1000, full duplex
1117 05:05:36.180305 Using ethernet@ff3f0000 device
1118 05:05:36.180915 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1119 05:05:36.189319 Filename '796430/tftp-deploy-efef138x/ramdisk/ramdisk.cpio.gz.uboot'.
1120 05:05:36.189905 Load address: 0x8000000
1121 05:05:39.247805 Loading: *################################################# UDP wrong checksum 00000005 0000e64a
1122 05:05:44.249100 T UDP wrong checksum 00000005 0000e64a
1123 05:05:54.252727 T T UDP wrong checksum 00000005 0000e64a
1124 05:06:14.256664 T T T T UDP wrong checksum 00000005 0000e64a
1125 05:06:34.261717 T T T
1126 05:06:34.262367 Retry count exceeded; starting again
1128 05:06:34.263920 end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
1131 05:06:34.266036 end: 2.4 uboot-commands (duration 00:01:54) [common]
1133 05:06:34.268502 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1135 05:06:34.269639 end: 2 uboot-action (duration 00:01:54) [common]
1137 05:06:34.271289 Cleaning after the job
1138 05:06:34.271884 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/ramdisk
1139 05:06:34.273347 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/kernel
1140 05:06:34.281454 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/dtb
1141 05:06:34.282798 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796430/tftp-deploy-efef138x/modules
1142 05:06:34.307280 start: 4.1 power-off (timeout 00:00:30) [common]
1143 05:06:34.308489 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1144 05:06:34.345763 >> OK - accepted request
1145 05:06:34.347609 Returned 0 in 0 seconds
1146 05:06:34.448953 end: 4.1 power-off (duration 00:00:00) [common]
1148 05:06:34.451012 start: 4.2 read-feedback (timeout 00:10:00) [common]
1149 05:06:34.452489 Listened to connection for namespace 'common' for up to 1s
1150 05:06:35.453164 Finalising connection for namespace 'common'
1151 05:06:35.453966 Disconnecting from shell: Finalise
1152 05:06:35.454595 =>
1153 05:06:35.555746 end: 4.2 read-feedback (duration 00:00:01) [common]
1154 05:06:35.556600 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796430
1155 05:06:35.848343 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796430
1156 05:06:35.848938 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.