Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:04:13.712432 lava-dispatcher, installed at version: 2024.01
2 05:04:13.713237 start: 0 validate
3 05:04:13.713705 Start time: 2024-10-03 05:04:13.713675+00:00 (UTC)
4 05:04:13.714256 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:04:13.714782 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 05:04:13.752807 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:04:13.753425 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 05:04:13.783075 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:04:13.783707 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 05:04:20.856169 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:04:20.856657 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 05:04:22.903525 validate duration: 9.19
14 05:04:22.905186 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:04:22.905537 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:04:22.905857 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:04:22.906750 Not decompressing ramdisk as can be used compressed.
18 05:04:22.907846 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 05:04:22.908494 saving as /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/ramdisk/rootfs.cpio.gz
20 05:04:22.909065 total size: 8181887 (7 MB)
21 05:04:22.950805 progress 0 % (0 MB)
22 05:04:22.962908 progress 5 % (0 MB)
23 05:04:22.974696 progress 10 % (0 MB)
24 05:04:22.985420 progress 15 % (1 MB)
25 05:04:22.990900 progress 20 % (1 MB)
26 05:04:22.996799 progress 25 % (1 MB)
27 05:04:23.002136 progress 30 % (2 MB)
28 05:04:23.007787 progress 35 % (2 MB)
29 05:04:23.013346 progress 40 % (3 MB)
30 05:04:23.019089 progress 45 % (3 MB)
31 05:04:23.024570 progress 50 % (3 MB)
32 05:04:23.030241 progress 55 % (4 MB)
33 05:04:23.035497 progress 60 % (4 MB)
34 05:04:23.041400 progress 65 % (5 MB)
35 05:04:23.046666 progress 70 % (5 MB)
36 05:04:23.052291 progress 75 % (5 MB)
37 05:04:23.057535 progress 80 % (6 MB)
38 05:04:23.063190 progress 85 % (6 MB)
39 05:04:23.068498 progress 90 % (7 MB)
40 05:04:23.074227 progress 95 % (7 MB)
41 05:04:23.079114 progress 100 % (7 MB)
42 05:04:23.079775 7 MB downloaded in 0.17 s (45.71 MB/s)
43 05:04:23.080344 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:04:23.081232 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:04:23.081523 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:04:23.081800 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:04:23.082353 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
49 05:04:23.082627 saving as /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/kernel/Image
50 05:04:23.082834 total size: 45998592 (43 MB)
51 05:04:23.083043 No compression specified
52 05:04:23.124843 progress 0 % (0 MB)
53 05:04:23.153726 progress 5 % (2 MB)
54 05:04:23.182404 progress 10 % (4 MB)
55 05:04:23.211122 progress 15 % (6 MB)
56 05:04:23.239524 progress 20 % (8 MB)
57 05:04:23.268185 progress 25 % (10 MB)
58 05:04:23.297449 progress 30 % (13 MB)
59 05:04:23.325703 progress 35 % (15 MB)
60 05:04:23.354138 progress 40 % (17 MB)
61 05:04:23.382984 progress 45 % (19 MB)
62 05:04:23.412316 progress 50 % (21 MB)
63 05:04:23.441240 progress 55 % (24 MB)
64 05:04:23.469867 progress 60 % (26 MB)
65 05:04:23.498843 progress 65 % (28 MB)
66 05:04:23.527479 progress 70 % (30 MB)
67 05:04:23.556863 progress 75 % (32 MB)
68 05:04:23.585820 progress 80 % (35 MB)
69 05:04:23.615104 progress 85 % (37 MB)
70 05:04:23.644000 progress 90 % (39 MB)
71 05:04:23.672570 progress 95 % (41 MB)
72 05:04:23.701401 progress 100 % (43 MB)
73 05:04:23.702148 43 MB downloaded in 0.62 s (70.83 MB/s)
74 05:04:23.702645 end: 1.2.1 http-download (duration 00:00:01) [common]
76 05:04:23.703471 end: 1.2 download-retry (duration 00:00:01) [common]
77 05:04:23.703767 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:04:23.704061 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:04:23.704587 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 05:04:23.704903 saving as /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 05:04:23.705123 total size: 53209 (0 MB)
82 05:04:23.705356 No compression specified
83 05:04:23.737390 progress 61 % (0 MB)
84 05:04:23.738266 progress 100 % (0 MB)
85 05:04:23.738839 0 MB downloaded in 0.03 s (1.51 MB/s)
86 05:04:23.739333 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:04:23.740275 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:04:23.740568 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:04:23.740857 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:04:23.741374 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
92 05:04:23.741654 saving as /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/modules/modules.tar
93 05:04:23.741871 total size: 11614180 (11 MB)
94 05:04:23.742097 Using unxz to decompress xz
95 05:04:23.782209 progress 0 % (0 MB)
96 05:04:23.853264 progress 5 % (0 MB)
97 05:04:23.932077 progress 10 % (1 MB)
98 05:04:24.025007 progress 15 % (1 MB)
99 05:04:24.102895 progress 20 % (2 MB)
100 05:04:24.186619 progress 25 % (2 MB)
101 05:04:24.268554 progress 30 % (3 MB)
102 05:04:24.349031 progress 35 % (3 MB)
103 05:04:24.424497 progress 40 % (4 MB)
104 05:04:24.503840 progress 45 % (5 MB)
105 05:04:24.583027 progress 50 % (5 MB)
106 05:04:24.887798 progress 55 % (6 MB)
107 05:04:24.973159 progress 60 % (6 MB)
108 05:04:25.063167 progress 65 % (7 MB)
109 05:04:25.145926 progress 70 % (7 MB)
110 05:04:25.239109 progress 75 % (8 MB)
111 05:04:25.335458 progress 80 % (8 MB)
112 05:04:25.417365 progress 85 % (9 MB)
113 05:04:25.489990 progress 90 % (9 MB)
114 05:04:25.567815 progress 95 % (10 MB)
115 05:04:25.646687 progress 100 % (11 MB)
116 05:04:25.658285 11 MB downloaded in 1.92 s (5.78 MB/s)
117 05:04:25.658878 end: 1.4.1 http-download (duration 00:00:02) [common]
119 05:04:25.659697 end: 1.4 download-retry (duration 00:00:02) [common]
120 05:04:25.659966 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 05:04:25.660563 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 05:04:25.661074 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:04:25.661571 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 05:04:25.662526 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x
125 05:04:25.663375 makedir: /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin
126 05:04:25.664037 makedir: /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/tests
127 05:04:25.664658 makedir: /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/results
128 05:04:25.665264 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-add-keys
129 05:04:25.666246 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-add-sources
130 05:04:25.667189 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-background-process-start
131 05:04:25.668165 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-background-process-stop
132 05:04:25.669175 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-common-functions
133 05:04:25.670121 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-echo-ipv4
134 05:04:25.671060 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-install-packages
135 05:04:25.671964 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-installed-packages
136 05:04:25.672904 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-os-build
137 05:04:25.673803 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-probe-channel
138 05:04:25.674700 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-probe-ip
139 05:04:25.675591 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-target-ip
140 05:04:25.676526 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-target-mac
141 05:04:25.677429 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-target-storage
142 05:04:25.678341 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-test-case
143 05:04:25.679275 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-test-event
144 05:04:25.680395 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-test-feedback
145 05:04:25.681332 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-test-raise
146 05:04:25.682224 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-test-reference
147 05:04:25.683117 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-test-runner
148 05:04:25.684055 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-test-set
149 05:04:25.684960 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-test-shell
150 05:04:25.685894 Updating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-install-packages (oe)
151 05:04:25.686857 Updating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/bin/lava-installed-packages (oe)
152 05:04:25.687688 Creating /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/environment
153 05:04:25.688480 LAVA metadata
154 05:04:25.688975 - LAVA_JOB_ID=796437
155 05:04:25.689400 - LAVA_DISPATCHER_IP=192.168.6.2
156 05:04:25.690066 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 05:04:25.691883 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 05:04:25.692519 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 05:04:25.692931 skipped lava-vland-overlay
160 05:04:25.693417 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 05:04:25.693923 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 05:04:25.694349 skipped lava-multinode-overlay
163 05:04:25.694831 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 05:04:25.695327 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 05:04:25.695800 Loading test definitions
166 05:04:25.696265 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 05:04:25.696498 Using /lava-796437 at stage 0
168 05:04:25.697770 uuid=796437_1.5.2.4.1 testdef=None
169 05:04:25.698095 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 05:04:25.698368 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 05:04:25.700257 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 05:04:25.701080 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 05:04:25.703392 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 05:04:25.704280 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 05:04:25.706529 runner path: /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/0/tests/0_dmesg test_uuid 796437_1.5.2.4.1
178 05:04:25.707124 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 05:04:25.707904 Creating lava-test-runner.conf files
181 05:04:25.708149 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796437/lava-overlay-4ma43s6x/lava-796437/0 for stage 0
182 05:04:25.708508 - 0_dmesg
183 05:04:25.708875 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 05:04:25.709162 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 05:04:25.733225 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 05:04:25.733674 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 05:04:25.733943 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 05:04:25.734214 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 05:04:25.734481 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 05:04:26.762847 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 05:04:26.763341 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 05:04:26.763592 extracting modules file /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796437/extract-overlay-ramdisk-w33o8y2o/ramdisk
193 05:04:28.114873 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 05:04:28.115372 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 05:04:28.115651 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796437/compress-overlay-558zo84k/overlay-1.5.2.5.tar.gz to ramdisk
196 05:04:28.115866 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796437/compress-overlay-558zo84k/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796437/extract-overlay-ramdisk-w33o8y2o/ramdisk
197 05:04:28.146804 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 05:04:28.147259 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 05:04:28.147533 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 05:04:28.147771 Converting downloaded kernel to a uImage
201 05:04:28.148114 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/kernel/Image /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/kernel/uImage
202 05:04:28.629779 output: Image Name:
203 05:04:28.630201 output: Created: Thu Oct 3 05:04:28 2024
204 05:04:28.630425 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 05:04:28.630638 output: Data Size: 45998592 Bytes = 44920.50 KiB = 43.87 MiB
206 05:04:28.630844 output: Load Address: 01080000
207 05:04:28.631045 output: Entry Point: 01080000
208 05:04:28.631245 output:
209 05:04:28.631583 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 05:04:28.631862 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 05:04:28.632184 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 05:04:28.632453 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 05:04:28.632721 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 05:04:28.632983 Building ramdisk /var/lib/lava/dispatcher/tmp/796437/extract-overlay-ramdisk-w33o8y2o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796437/extract-overlay-ramdisk-w33o8y2o/ramdisk
215 05:04:31.180542 >> 181660 blocks
216 05:04:39.690809 Adding RAMdisk u-boot header.
217 05:04:39.691242 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796437/extract-overlay-ramdisk-w33o8y2o/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796437/extract-overlay-ramdisk-w33o8y2o/ramdisk.cpio.gz.uboot
218 05:04:39.991393 output: Image Name:
219 05:04:39.991802 output: Created: Thu Oct 3 05:04:39 2024
220 05:04:39.992269 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 05:04:39.992683 output: Data Size: 26055281 Bytes = 25444.61 KiB = 24.85 MiB
222 05:04:39.993080 output: Load Address: 00000000
223 05:04:39.993473 output: Entry Point: 00000000
224 05:04:39.993863 output:
225 05:04:39.994829 rename /var/lib/lava/dispatcher/tmp/796437/extract-overlay-ramdisk-w33o8y2o/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/ramdisk/ramdisk.cpio.gz.uboot
226 05:04:39.995530 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 05:04:39.996109 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 05:04:39.996649 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 05:04:39.997104 No LXC device requested
230 05:04:39.997608 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 05:04:39.998121 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 05:04:39.998619 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 05:04:39.999032 Checking files for TFTP limit of 4294967296 bytes.
234 05:04:40.001724 end: 1 tftp-deploy (duration 00:00:17) [common]
235 05:04:40.002299 start: 2 uboot-action (timeout 00:05:00) [common]
236 05:04:40.002834 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 05:04:40.003338 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 05:04:40.003845 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 05:04:40.004409 Using kernel file from prepare-kernel: 796437/tftp-deploy-gyv4nfqq/kernel/uImage
240 05:04:40.005042 substitutions:
241 05:04:40.005458 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 05:04:40.005862 - {DTB_ADDR}: 0x01070000
243 05:04:40.006261 - {DTB}: 796437/tftp-deploy-gyv4nfqq/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 05:04:40.006659 - {INITRD}: 796437/tftp-deploy-gyv4nfqq/ramdisk/ramdisk.cpio.gz.uboot
245 05:04:40.007056 - {KERNEL_ADDR}: 0x01080000
246 05:04:40.007447 - {KERNEL}: 796437/tftp-deploy-gyv4nfqq/kernel/uImage
247 05:04:40.007841 - {LAVA_MAC}: None
248 05:04:40.008309 - {PRESEED_CONFIG}: None
249 05:04:40.008715 - {PRESEED_LOCAL}: None
250 05:04:40.009106 - {RAMDISK_ADDR}: 0x08000000
251 05:04:40.009496 - {RAMDISK}: 796437/tftp-deploy-gyv4nfqq/ramdisk/ramdisk.cpio.gz.uboot
252 05:04:40.009888 - {ROOT_PART}: None
253 05:04:40.010277 - {ROOT}: None
254 05:04:40.010664 - {SERVER_IP}: 192.168.6.2
255 05:04:40.011053 - {TEE_ADDR}: 0x83000000
256 05:04:40.011442 - {TEE}: None
257 05:04:40.011833 Parsed boot commands:
258 05:04:40.012281 - setenv autoload no
259 05:04:40.012681 - setenv initrd_high 0xffffffff
260 05:04:40.013073 - setenv fdt_high 0xffffffff
261 05:04:40.013461 - dhcp
262 05:04:40.013848 - setenv serverip 192.168.6.2
263 05:04:40.014235 - tftpboot 0x01080000 796437/tftp-deploy-gyv4nfqq/kernel/uImage
264 05:04:40.014624 - tftpboot 0x08000000 796437/tftp-deploy-gyv4nfqq/ramdisk/ramdisk.cpio.gz.uboot
265 05:04:40.015011 - tftpboot 0x01070000 796437/tftp-deploy-gyv4nfqq/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 05:04:40.015400 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 05:04:40.015795 - bootm 0x01080000 0x08000000 0x01070000
268 05:04:40.016324 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 05:04:40.017809 start: 2.3 connect-device (timeout 00:05:00) [common]
271 05:04:40.018260 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 05:04:40.032596 Setting prompt string to ['lava-test: # ']
273 05:04:40.034035 end: 2.3 connect-device (duration 00:00:00) [common]
274 05:04:40.034648 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 05:04:40.035212 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 05:04:40.035757 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 05:04:40.036951 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 05:04:40.071582 >> OK - accepted request
279 05:04:40.074594 Returned 0 in 0 seconds
280 05:04:40.175523 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 05:04:40.177255 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 05:04:40.177857 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 05:04:40.178367 Setting prompt string to ['Hit any key to stop autoboot']
285 05:04:40.178827 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 05:04:40.180503 Trying 192.168.56.21...
287 05:04:40.181002 Connected to conserv1.
288 05:04:40.181424 Escape character is '^]'.
289 05:04:40.181849
290 05:04:40.182279 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 05:04:40.182728
292 05:04:47.870319 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 05:04:47.870791 bl2_stage_init 0x01
294 05:04:47.871073 bl2_stage_init 0x81
295 05:04:47.875660 hw id: 0x0000 - pwm id 0x01
296 05:04:47.876128 bl2_stage_init 0xc1
297 05:04:47.880433 bl2_stage_init 0x02
298 05:04:47.880824
299 05:04:47.881078 L0:00000000
300 05:04:47.881314 L1:00000703
301 05:04:47.881550 L2:00008067
302 05:04:47.885793 L3:15000000
303 05:04:47.886172 S1:00000000
304 05:04:47.886419 B2:20282000
305 05:04:47.886647 B1:a0f83180
306 05:04:47.886871
307 05:04:47.887102 TE: 69304
308 05:04:47.887331
309 05:04:47.896865 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 05:04:47.897287
311 05:04:47.897541 Board ID = 1
312 05:04:47.897775 Set cpu clk to 24M
313 05:04:47.898011 Set clk81 to 24M
314 05:04:47.902494 Use GP1_pll as DSU clk.
315 05:04:47.902873 DSU clk: 1200 Mhz
316 05:04:47.903109 CPU clk: 1200 MHz
317 05:04:47.908051 Set clk81 to 166.6M
318 05:04:47.913678 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 05:04:47.914077 board id: 1
320 05:04:47.921984 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 05:04:47.932630 fw parse done
322 05:04:47.938596 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 05:04:47.981240 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 05:04:47.992084 PIEI prepare done
325 05:04:47.992454 fastboot data load
326 05:04:47.992699 fastboot data verify
327 05:04:47.997778 verify result: 266
328 05:04:48.003335 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 05:04:48.003677 LPDDR4 probe
330 05:04:48.003915 ddr clk to 1584MHz
331 05:04:48.011274 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 05:04:48.048593
333 05:04:48.049009 dmc_version 0001
334 05:04:48.055262 Check phy result
335 05:04:48.061239 INFO : End of CA training
336 05:04:48.061630 INFO : End of initialization
337 05:04:48.066758 INFO : Training has run successfully!
338 05:04:48.067123 Check phy result
339 05:04:48.072473 INFO : End of initialization
340 05:04:48.072834 INFO : End of read enable training
341 05:04:48.077996 INFO : End of fine write leveling
342 05:04:48.083521 INFO : End of Write leveling coarse delay
343 05:04:48.083878 INFO : Training has run successfully!
344 05:04:48.084156 Check phy result
345 05:04:48.089106 INFO : End of initialization
346 05:04:48.089454 INFO : End of read dq deskew training
347 05:04:48.094729 INFO : End of MPR read delay center optimization
348 05:04:48.100344 INFO : End of write delay center optimization
349 05:04:48.106000 INFO : End of read delay center optimization
350 05:04:48.106360 INFO : End of max read latency training
351 05:04:48.111578 INFO : Training has run successfully!
352 05:04:48.111941 1D training succeed
353 05:04:48.120768 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 05:04:48.168321 Check phy result
355 05:04:48.168703 INFO : End of initialization
356 05:04:48.190852 INFO : End of 2D read delay Voltage center optimization
357 05:04:48.209876 INFO : End of 2D read delay Voltage center optimization
358 05:04:48.261957 INFO : End of 2D write delay Voltage center optimization
359 05:04:48.311050 INFO : End of 2D write delay Voltage center optimization
360 05:04:48.316569 INFO : Training has run successfully!
361 05:04:48.317084
362 05:04:48.317535 channel==0
363 05:04:48.322066 RxClkDly_Margin_A0==78 ps 8
364 05:04:48.322553 TxDqDly_Margin_A0==98 ps 10
365 05:04:48.325405 RxClkDly_Margin_A1==88 ps 9
366 05:04:48.325885 TxDqDly_Margin_A1==88 ps 9
367 05:04:48.330983 TrainedVREFDQ_A0==74
368 05:04:48.331473 TrainedVREFDQ_A1==74
369 05:04:48.331920 VrefDac_Margin_A0==25
370 05:04:48.336506 DeviceVref_Margin_A0==40
371 05:04:48.336975 VrefDac_Margin_A1==23
372 05:04:48.342153 DeviceVref_Margin_A1==40
373 05:04:48.342623
374 05:04:48.343064
375 05:04:48.343500 channel==1
376 05:04:48.343932 RxClkDly_Margin_A0==78 ps 8
377 05:04:48.345592 TxDqDly_Margin_A0==98 ps 10
378 05:04:48.351160 RxClkDly_Margin_A1==98 ps 10
379 05:04:48.351632 TxDqDly_Margin_A1==98 ps 10
380 05:04:48.352104 TrainedVREFDQ_A0==78
381 05:04:48.355341 TrainedVREFDQ_A1==77
382 05:04:48.358566 VrefDac_Margin_A0==22
383 05:04:48.359044 DeviceVref_Margin_A0==36
384 05:04:48.364231 VrefDac_Margin_A1==21
385 05:04:48.364706 DeviceVref_Margin_A1==37
386 05:04:48.365138
387 05:04:48.369755 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 05:04:48.370230
389 05:04:48.397730 soc_vref_reg_value 0x 0000001a 00000019 00000018 00000017 00000018 00000015 00000018 00000016 00000018 00000017 00000017 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
390 05:04:48.403326 2D training succeed
391 05:04:48.408959 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 05:04:48.409448 auto size-- 65535DDR cs0 size: 2048MB
393 05:04:48.414518 DDR cs1 size: 2048MB
394 05:04:48.414995 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 05:04:48.420194 cs0 DataBus test pass
396 05:04:48.420672 cs1 DataBus test pass
397 05:04:48.421109 cs0 AddrBus test pass
398 05:04:48.425730 cs1 AddrBus test pass
399 05:04:48.426217
400 05:04:48.426653 100bdlr_step_size ps== 478
401 05:04:48.431333 result report
402 05:04:48.431813 boot times 0Enable ddr reg access
403 05:04:48.438571 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 05:04:48.453288 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 05:04:49.108473 bl2z: ptr: 05129330, size: 00001e40
406 05:04:49.115203 0.0;M3 CHK:0;cm4_sp_mode 0
407 05:04:49.115569 MVN_1=0x00000000
408 05:04:49.115822 MVN_2=0x00000000
409 05:04:49.126687 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 05:04:49.127094 OPS=0x04
411 05:04:49.127346 ring efuse init
412 05:04:49.132290 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 05:04:49.132631 [0.017310 Inits done]
414 05:04:49.132871 secure task start!
415 05:04:49.140311 high task start!
416 05:04:49.140666 low task start!
417 05:04:49.140907 run into bl31
418 05:04:49.148998 NOTICE: BL31: v1.3(release):4fc40b1
419 05:04:49.156753 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 05:04:49.157132 NOTICE: BL31: G12A normal boot!
421 05:04:49.172207 NOTICE: BL31: BL33 decompress pass
422 05:04:49.177931 ERROR: Error initializing runtime service opteed_fast
423 05:04:51.917403 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 05:04:51.917825 bl2_stage_init 0x01
425 05:04:51.918053 bl2_stage_init 0x81
426 05:04:51.922925 hw id: 0x0000 - pwm id 0x01
427 05:04:51.923385 bl2_stage_init 0xc1
428 05:04:51.928422 bl2_stage_init 0x02
429 05:04:51.928998
430 05:04:51.929264 L0:00000000
431 05:04:51.929521 L1:00000703
432 05:04:51.929763 L2:00008067
433 05:04:51.930016 L3:15000000
434 05:04:51.934072 S1:00000000
435 05:04:51.934506 B2:20282000
436 05:04:51.934759 B1:a0f83180
437 05:04:51.934999
438 05:04:51.935233 TE: 68055
439 05:04:51.935467
440 05:04:51.939721 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 05:04:51.940186
442 05:04:51.945306 Board ID = 1
443 05:04:51.945746 Set cpu clk to 24M
444 05:04:51.945972 Set clk81 to 24M
445 05:04:51.951081 Use GP1_pll as DSU clk.
446 05:04:51.951515 DSU clk: 1200 Mhz
447 05:04:51.951746 CPU clk: 1200 MHz
448 05:04:51.956670 Set clk81 to 166.6M
449 05:04:51.963197 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 05:04:51.963700 board id: 1
451 05:04:51.969977 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 05:04:51.979941 fw parse done
453 05:04:51.986022 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 05:04:52.028738 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 05:04:52.039654 PIEI prepare done
456 05:04:52.040359 fastboot data load
457 05:04:52.040825 fastboot data verify
458 05:04:52.045384 verify result: 266
459 05:04:52.050940 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 05:04:52.051617 LPDDR4 probe
461 05:04:52.052121 ddr clk to 1584MHz
462 05:04:52.057888 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 05:04:52.095914
464 05:04:52.096577 dmc_version 0001
465 05:04:52.104604 Check phy result
466 05:04:52.108558 INFO : End of CA training
467 05:04:52.109187 INFO : End of initialization
468 05:04:52.114378 INFO : Training has run successfully!
469 05:04:52.114971 Check phy result
470 05:04:52.119950 INFO : End of initialization
471 05:04:52.120601 INFO : End of read enable training
472 05:04:52.125412 INFO : End of fine write leveling
473 05:04:52.135516 INFO : End of Write leveling coarse delay
474 05:04:52.136444 INFO : Training has run successfully!
475 05:04:52.136970 Check phy result
476 05:04:52.137770 INFO : End of initialization
477 05:04:52.138238 INFO : End of read dq deskew training
478 05:04:52.142231 INFO : End of MPR read delay center optimization
479 05:04:52.147838 INFO : End of write delay center optimization
480 05:04:52.153486 INFO : End of read delay center optimization
481 05:04:52.154191 INFO : End of max read latency training
482 05:04:52.159247 INFO : Training has run successfully!
483 05:04:52.159929 1D training succeed
484 05:04:52.168113 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 05:04:52.215805 Check phy result
486 05:04:52.216522 INFO : End of initialization
487 05:04:52.238171 INFO : End of 2D read delay Voltage center optimization
488 05:04:52.257262 INFO : End of 2D read delay Voltage center optimization
489 05:04:52.309268 INFO : End of 2D write delay Voltage center optimization
490 05:04:52.358320 INFO : End of 2D write delay Voltage center optimization
491 05:04:52.363970 INFO : Training has run successfully!
492 05:04:52.364556
493 05:04:52.365023 channel==0
494 05:04:52.369489 RxClkDly_Margin_A0==88 ps 9
495 05:04:52.370021 TxDqDly_Margin_A0==98 ps 10
496 05:04:52.375485 RxClkDly_Margin_A1==88 ps 9
497 05:04:52.376061 TxDqDly_Margin_A1==98 ps 10
498 05:04:52.376528 TrainedVREFDQ_A0==74
499 05:04:52.380681 TrainedVREFDQ_A1==75
500 05:04:52.381208 VrefDac_Margin_A0==25
501 05:04:52.381666 DeviceVref_Margin_A0==40
502 05:04:52.386284 VrefDac_Margin_A1==23
503 05:04:52.386806 DeviceVref_Margin_A1==39
504 05:04:52.387268
505 05:04:52.387719
506 05:04:52.391881 channel==1
507 05:04:52.392440 RxClkDly_Margin_A0==88 ps 9
508 05:04:52.392899 TxDqDly_Margin_A0==78 ps 8
509 05:04:52.397483 RxClkDly_Margin_A1==88 ps 9
510 05:04:52.398006 TxDqDly_Margin_A1==88 ps 9
511 05:04:52.403127 TrainedVREFDQ_A0==75
512 05:04:52.403665 TrainedVREFDQ_A1==77
513 05:04:52.404166 VrefDac_Margin_A0==23
514 05:04:52.408669 DeviceVref_Margin_A0==39
515 05:04:52.409184 VrefDac_Margin_A1==21
516 05:04:52.414290 DeviceVref_Margin_A1==37
517 05:04:52.414807
518 05:04:52.415266 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 05:04:52.415715
520 05:04:52.447854 soc_vref_reg_value 0x 0000001a 00000019 00000018 00000017 00000019 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000018 00000019 00000018 00000019 00000018 00000017 00000019 00000014 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
521 05:04:52.448503 2D training succeed
522 05:04:52.453516 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 05:04:52.459087 auto size-- 65535DDR cs0 size: 2048MB
524 05:04:52.459681 DDR cs1 size: 2048MB
525 05:04:52.464572 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 05:04:52.465087 cs0 DataBus test pass
527 05:04:52.470205 cs1 DataBus test pass
528 05:04:52.470705 cs0 AddrBus test pass
529 05:04:52.471163 cs1 AddrBus test pass
530 05:04:52.471607
531 05:04:52.475813 100bdlr_step_size ps== 478
532 05:04:52.476373 result report
533 05:04:52.481375 boot times 0Enable ddr reg access
534 05:04:52.485719 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 05:04:52.500365 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 05:04:53.154733 bl2z: ptr: 05129330, size: 00001e40
537 05:04:53.161452 0.0;M3 CHK:0;cm4_sp_mode 0
538 05:04:53.162025 MVN_1=0x00000000
539 05:04:53.162488 MVN_2=0x00000000
540 05:04:53.173036 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 05:04:53.173554 OPS=0x04
542 05:04:53.174011 ring efuse init
543 05:04:53.178506 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 05:04:53.179003 [0.017319 Inits done]
545 05:04:53.179456 secure task start!
546 05:04:53.186729 high task start!
547 05:04:53.187267 low task start!
548 05:04:53.187733 run into bl31
549 05:04:53.195278 NOTICE: BL31: v1.3(release):4fc40b1
550 05:04:53.202978 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 05:04:53.203508 NOTICE: BL31: G12A normal boot!
552 05:04:53.218481 NOTICE: BL31: BL33 decompress pass
553 05:04:53.224211 ERROR: Error initializing runtime service opteed_fast
554 05:04:54.620207 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 05:04:54.620835 bl2_stage_init 0x01
556 05:04:54.621313 bl2_stage_init 0x81
557 05:04:54.625587 hw id: 0x0000 - pwm id 0x01
558 05:04:54.626084 bl2_stage_init 0xc1
559 05:04:54.631145 bl2_stage_init 0x02
560 05:04:54.631633
561 05:04:54.632132 L0:00000000
562 05:04:54.632584 L1:00000703
563 05:04:54.633023 L2:00008067
564 05:04:54.633466 L3:15000000
565 05:04:54.636875 S1:00000000
566 05:04:54.637361 B2:20282000
567 05:04:54.637805 B1:a0f83180
568 05:04:54.638245
569 05:04:54.638686 TE: 70131
570 05:04:54.639125
571 05:04:54.642548 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 05:04:54.643041
573 05:04:54.647940 Board ID = 1
574 05:04:54.648462 Set cpu clk to 24M
575 05:04:54.648910 Set clk81 to 24M
576 05:04:54.653639 Use GP1_pll as DSU clk.
577 05:04:54.654130 DSU clk: 1200 Mhz
578 05:04:54.654576 CPU clk: 1200 MHz
579 05:04:54.659246 Set clk81 to 166.6M
580 05:04:54.664730 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 05:04:54.665228 board id: 1
582 05:04:54.671898 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 05:04:54.682481 fw parse done
584 05:04:54.688409 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 05:04:54.731139 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 05:04:54.742195 PIEI prepare done
587 05:04:54.742796 fastboot data load
588 05:04:54.743279 fastboot data verify
589 05:04:54.747774 verify result: 266
590 05:04:54.753379 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 05:04:54.753933 LPDDR4 probe
592 05:04:54.754399 ddr clk to 1584MHz
593 05:04:54.761422 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 05:04:54.798643
595 05:04:54.799231 dmc_version 0001
596 05:04:54.805297 Check phy result
597 05:04:54.811250 INFO : End of CA training
598 05:04:54.811806 INFO : End of initialization
599 05:04:54.816847 INFO : Training has run successfully!
600 05:04:54.817402 Check phy result
601 05:04:54.822482 INFO : End of initialization
602 05:04:54.823035 INFO : End of read enable training
603 05:04:54.825912 INFO : End of fine write leveling
604 05:04:54.831393 INFO : End of Write leveling coarse delay
605 05:04:54.836895 INFO : Training has run successfully!
606 05:04:54.837516 Check phy result
607 05:04:54.838026 INFO : End of initialization
608 05:04:54.842561 INFO : End of read dq deskew training
609 05:04:54.848100 INFO : End of MPR read delay center optimization
610 05:04:54.848439 INFO : End of write delay center optimization
611 05:04:54.853699 INFO : End of read delay center optimization
612 05:04:54.859261 INFO : End of max read latency training
613 05:04:54.859716 INFO : Training has run successfully!
614 05:04:54.864790 1D training succeed
615 05:04:54.870788 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 05:04:54.918351 Check phy result
617 05:04:54.918871 INFO : End of initialization
618 05:04:54.940640 INFO : End of 2D read delay Voltage center optimization
619 05:04:54.959906 INFO : End of 2D read delay Voltage center optimization
620 05:04:55.011873 INFO : End of 2D write delay Voltage center optimization
621 05:04:55.060788 INFO : End of 2D write delay Voltage center optimization
622 05:04:55.066571 INFO : Training has run successfully!
623 05:04:55.067062
624 05:04:55.067495 channel==0
625 05:04:55.072169 RxClkDly_Margin_A0==78 ps 8
626 05:04:55.072647 TxDqDly_Margin_A0==88 ps 9
627 05:04:55.075278 RxClkDly_Margin_A1==69 ps 7
628 05:04:55.075733 TxDqDly_Margin_A1==98 ps 10
629 05:04:55.080974 TrainedVREFDQ_A0==74
630 05:04:55.081446 TrainedVREFDQ_A1==75
631 05:04:55.081874 VrefDac_Margin_A0==24
632 05:04:55.087148 DeviceVref_Margin_A0==40
633 05:04:55.087680 VrefDac_Margin_A1==23
634 05:04:55.092263 DeviceVref_Margin_A1==39
635 05:04:55.092740
636 05:04:55.093165
637 05:04:55.093577 channel==1
638 05:04:55.094001 RxClkDly_Margin_A0==88 ps 9
639 05:04:55.095845 TxDqDly_Margin_A0==98 ps 10
640 05:04:55.101169 RxClkDly_Margin_A1==88 ps 9
641 05:04:55.101638 TxDqDly_Margin_A1==88 ps 9
642 05:04:55.102059 TrainedVREFDQ_A0==78
643 05:04:55.106943 TrainedVREFDQ_A1==75
644 05:04:55.107410 VrefDac_Margin_A0==23
645 05:04:55.112679 DeviceVref_Margin_A0==36
646 05:04:55.113189 VrefDac_Margin_A1==21
647 05:04:55.113625 DeviceVref_Margin_A1==38
648 05:04:55.114045
649 05:04:55.121895 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 05:04:55.122384
651 05:04:55.149765 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
652 05:04:55.150302 2D training succeed
653 05:04:55.155421 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 05:04:55.160951 auto size-- 65535DDR cs0 size: 2048MB
655 05:04:55.161427 DDR cs1 size: 2048MB
656 05:04:55.166644 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 05:04:55.167132 cs0 DataBus test pass
658 05:04:55.172279 cs1 DataBus test pass
659 05:04:55.172749 cs0 AddrBus test pass
660 05:04:55.173164 cs1 AddrBus test pass
661 05:04:55.173570
662 05:04:55.177831 100bdlr_step_size ps== 464
663 05:04:55.178317 result report
664 05:04:55.183627 boot times 0Enable ddr reg access
665 05:04:55.188403 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 05:04:55.202058 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 05:04:55.857973 bl2z: ptr: 05129330, size: 00001e40
668 05:04:55.865123 0.0;M3 CHK:0;cm4_sp_mode 0
669 05:04:55.865468 MVN_1=0x00000000
670 05:04:55.865899 MVN_2=0x00000000
671 05:04:55.876619 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 05:04:55.877128 OPS=0x04
673 05:04:55.877569 ring efuse init
674 05:04:55.879568 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 05:04:55.885852 [0.017319 Inits done]
676 05:04:55.886317 secure task start!
677 05:04:55.886734 high task start!
678 05:04:55.887142 low task start!
679 05:04:55.890055 run into bl31
680 05:04:55.898778 NOTICE: BL31: v1.3(release):4fc40b1
681 05:04:55.906602 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 05:04:55.907078 NOTICE: BL31: G12A normal boot!
683 05:04:55.922035 NOTICE: BL31: BL33 decompress pass
684 05:04:55.927702 ERROR: Error initializing runtime service opteed_fast
685 05:04:56.723090
686 05:04:56.723512
687 05:04:56.728538 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 05:04:56.728855
689 05:04:56.731929 Model: Libre Computer AML-S905D3-CC Solitude
690 05:04:56.879076 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 05:04:56.894396 DRAM: 2 GiB (effective 3.8 GiB)
692 05:04:56.995417 Core: 406 devices, 33 uclasses, devicetree: separate
693 05:04:57.001234 WDT: Not starting watchdog@f0d0
694 05:04:57.026298 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 05:04:57.038558 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 05:04:57.043490 ** Bad device specification mmc 0 **
697 05:04:57.053616 Card did not respond to voltage select! : -110
698 05:04:57.060268 ** Bad device specification mmc 0 **
699 05:04:57.060712 Couldn't find partition mmc 0
700 05:04:57.069594 Card did not respond to voltage select! : -110
701 05:04:57.075053 ** Bad device specification mmc 0 **
702 05:04:57.075494 Couldn't find partition mmc 0
703 05:04:57.080149 Error: could not access storage.
704 05:04:57.377698 Net: eth0: ethernet@ff3f0000
705 05:04:57.378316 starting USB...
706 05:04:57.622278 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 05:04:57.622881 Starting the controller
708 05:04:57.629202 USB XHCI 1.10
709 05:04:59.183373 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 05:04:59.191661 scanning usb for storage devices... 0 Storage Device(s) found
712 05:04:59.243208 Hit any key to stop autoboot: 1
713 05:04:59.244048 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 05:04:59.244707 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 05:04:59.245192 Setting prompt string to ['=>']
716 05:04:59.245696 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 05:04:59.257714 0
718 05:04:59.258747 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 05:04:59.360057 => setenv autoload no
721 05:04:59.360819 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 05:04:59.365616 setenv autoload no
724 05:04:59.467116 => setenv initrd_high 0xffffffff
725 05:04:59.467867 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 05:04:59.472137 setenv initrd_high 0xffffffff
728 05:04:59.573557 => setenv fdt_high 0xffffffff
729 05:04:59.574281 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 05:04:59.578545 setenv fdt_high 0xffffffff
732 05:04:59.680026 => dhcp
733 05:04:59.680747 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 05:04:59.684751 dhcp
735 05:05:00.290477 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 05:05:00.291085 Speed: 1000, full duplex
737 05:05:00.291517 BOOTP broadcast 1
738 05:05:00.538323 BOOTP broadcast 2
739 05:05:01.039963 BOOTP broadcast 3
740 05:05:02.041083 BOOTP broadcast 4
741 05:05:04.042062 BOOTP broadcast 5
742 05:05:04.058622 DHCP client bound to address 192.168.6.12 (3768 ms)
744 05:05:04.159719 => setenv serverip 192.168.6.2
745 05:05:04.160278 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
746 05:05:04.164674 setenv serverip 192.168.6.2
748 05:05:04.265662 => tftpboot 0x01080000 796437/tftp-deploy-gyv4nfqq/kernel/uImage
749 05:05:04.266179 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
750 05:05:04.272714 tftpboot 0x01080000 796437/tftp-deploy-gyv4nfqq/kernel/uImage
751 05:05:04.273005 Speed: 1000, full duplex
752 05:05:04.273220 Using ethernet@ff3f0000 device
753 05:05:04.278176 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 05:05:04.283735 Filename '796437/tftp-deploy-gyv4nfqq/kernel/uImage'.
755 05:05:04.287635 Load address: 0x1080000
756 05:05:08.926695 Loading: *################################################## 43.9 MiB
757 05:05:08.927092 9.4 MiB/s
758 05:05:08.927316 done
759 05:05:08.930598 Bytes transferred = 45998656 (2bde240 hex)
761 05:05:09.032591 => tftpboot 0x08000000 796437/tftp-deploy-gyv4nfqq/ramdisk/ramdisk.cpio.gz.uboot
762 05:05:09.033373 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
763 05:05:09.039943 tftpboot 0x08000000 796437/tftp-deploy-gyv4nfqq/ramdisk/ramdisk.cpio.gz.uboot
764 05:05:09.040520 Speed: 1000, full duplex
765 05:05:09.040991 Using ethernet@ff3f0000 device
766 05:05:09.045426 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
767 05:05:09.055378 Filename '796437/tftp-deploy-gyv4nfqq/ramdisk/ramdisk.cpio.gz.uboot'.
768 05:05:09.055962 Load address: 0x8000000
769 05:05:16.653538 Loading: *####T ############################################# UDP wrong checksum 00000005 0000ad52
770 05:05:21.654215 T UDP wrong checksum 00000005 0000ad52
771 05:05:24.782626 UDP wrong checksum 000000ff 0000e31d
772 05:05:24.822038 UDP wrong checksum 000000ff 00006c10
773 05:05:31.656130 T T UDP wrong checksum 00000005 0000ad52
774 05:05:51.660143 T T T T UDP wrong checksum 00000005 0000ad52
775 05:06:06.664091 T T
776 05:06:06.664731 Retry count exceeded; starting again
778 05:06:06.666266 end: 2.4.3 bootloader-commands (duration 00:01:07) [common]
781 05:06:06.668586 end: 2.4 uboot-commands (duration 00:01:27) [common]
783 05:06:06.670205 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
785 05:06:06.671225 end: 2 uboot-action (duration 00:01:27) [common]
787 05:06:06.672760 Cleaning after the job
788 05:06:06.673316 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/ramdisk
789 05:06:06.674619 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/kernel
790 05:06:06.682043 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/dtb
791 05:06:06.683268 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796437/tftp-deploy-gyv4nfqq/modules
792 05:06:06.702650 start: 4.1 power-off (timeout 00:00:30) [common]
793 05:06:06.703714 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
794 05:06:06.738229 >> OK - accepted request
795 05:06:06.740497 Returned 0 in 0 seconds
796 05:06:06.841553 end: 4.1 power-off (duration 00:00:00) [common]
798 05:06:06.843708 start: 4.2 read-feedback (timeout 00:10:00) [common]
799 05:06:06.845074 Listened to connection for namespace 'common' for up to 1s
800 05:06:07.845781 Finalising connection for namespace 'common'
801 05:06:07.846287 Disconnecting from shell: Finalise
802 05:06:07.846587 =>
803 05:06:07.947380 end: 4.2 read-feedback (duration 00:00:01) [common]
804 05:06:07.948201 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796437
805 05:06:08.270216 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796437
806 05:06:08.270950 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.