Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 05:07:13.206186 lava-dispatcher, installed at version: 2024.01
2 05:07:13.206934 start: 0 validate
3 05:07:13.207423 Start time: 2024-10-03 05:07:13.207393+00:00 (UTC)
4 05:07:13.207954 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:07:13.208503 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 05:07:13.245058 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:07:13.245632 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 05:07:13.278559 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:07:13.279187 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 05:07:13.312298 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:07:13.312777 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:07:13.344480 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:07:13.344944 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
14 05:07:13.385739 validate duration: 0.18
16 05:07:13.386577 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:07:13.386895 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:07:13.387197 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:07:13.387767 Not decompressing ramdisk as can be used compressed.
20 05:07:13.388237 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 05:07:13.388515 saving as /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/ramdisk/initrd.cpio.gz
22 05:07:13.388783 total size: 5628182 (5 MB)
23 05:07:13.428440 progress 0 % (0 MB)
24 05:07:13.435704 progress 5 % (0 MB)
25 05:07:13.443414 progress 10 % (0 MB)
26 05:07:13.450586 progress 15 % (0 MB)
27 05:07:13.457458 progress 20 % (1 MB)
28 05:07:13.461051 progress 25 % (1 MB)
29 05:07:13.465065 progress 30 % (1 MB)
30 05:07:13.469003 progress 35 % (1 MB)
31 05:07:13.472580 progress 40 % (2 MB)
32 05:07:13.476492 progress 45 % (2 MB)
33 05:07:13.480004 progress 50 % (2 MB)
34 05:07:13.483940 progress 55 % (2 MB)
35 05:07:13.487864 progress 60 % (3 MB)
36 05:07:13.491493 progress 65 % (3 MB)
37 05:07:13.495384 progress 70 % (3 MB)
38 05:07:13.498922 progress 75 % (4 MB)
39 05:07:13.502869 progress 80 % (4 MB)
40 05:07:13.506393 progress 85 % (4 MB)
41 05:07:13.510324 progress 90 % (4 MB)
42 05:07:13.514160 progress 95 % (5 MB)
43 05:07:13.517399 progress 100 % (5 MB)
44 05:07:13.518050 5 MB downloaded in 0.13 s (41.53 MB/s)
45 05:07:13.518598 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:07:13.519482 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:07:13.519766 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:07:13.520057 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:07:13.520545 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
51 05:07:13.520796 saving as /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/kernel/Image
52 05:07:13.521008 total size: 45998592 (43 MB)
53 05:07:13.521218 No compression specified
54 05:07:13.559328 progress 0 % (0 MB)
55 05:07:13.587884 progress 5 % (2 MB)
56 05:07:13.616144 progress 10 % (4 MB)
57 05:07:13.644091 progress 15 % (6 MB)
58 05:07:13.672159 progress 20 % (8 MB)
59 05:07:13.700477 progress 25 % (10 MB)
60 05:07:13.729199 progress 30 % (13 MB)
61 05:07:13.757353 progress 35 % (15 MB)
62 05:07:13.785603 progress 40 % (17 MB)
63 05:07:13.814033 progress 45 % (19 MB)
64 05:07:13.842302 progress 50 % (21 MB)
65 05:07:13.870907 progress 55 % (24 MB)
66 05:07:13.899195 progress 60 % (26 MB)
67 05:07:13.927375 progress 65 % (28 MB)
68 05:07:13.955482 progress 70 % (30 MB)
69 05:07:13.983615 progress 75 % (32 MB)
70 05:07:14.012300 progress 80 % (35 MB)
71 05:07:14.040482 progress 85 % (37 MB)
72 05:07:14.068837 progress 90 % (39 MB)
73 05:07:14.097406 progress 95 % (41 MB)
74 05:07:14.125704 progress 100 % (43 MB)
75 05:07:14.126470 43 MB downloaded in 0.61 s (72.45 MB/s)
76 05:07:14.126955 end: 1.2.1 http-download (duration 00:00:01) [common]
78 05:07:14.127783 end: 1.2 download-retry (duration 00:00:01) [common]
79 05:07:14.128087 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:07:14.128361 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:07:14.128833 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 05:07:14.129105 saving as /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/dtb/meson-g12b-a311d-libretech-cc.dtb
83 05:07:14.129316 total size: 54703 (0 MB)
84 05:07:14.129526 No compression specified
85 05:07:14.167786 progress 59 % (0 MB)
86 05:07:14.168691 progress 100 % (0 MB)
87 05:07:14.169277 0 MB downloaded in 0.04 s (1.31 MB/s)
88 05:07:14.169784 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:07:14.170606 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:07:14.170872 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:07:14.171137 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:07:14.171603 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 05:07:14.171851 saving as /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/nfsrootfs/full.rootfs.tar
95 05:07:14.172083 total size: 107552908 (102 MB)
96 05:07:14.172298 Using unxz to decompress xz
97 05:07:14.210190 progress 0 % (0 MB)
98 05:07:14.859858 progress 5 % (5 MB)
99 05:07:15.590126 progress 10 % (10 MB)
100 05:07:16.317770 progress 15 % (15 MB)
101 05:07:17.074187 progress 20 % (20 MB)
102 05:07:17.646165 progress 25 % (25 MB)
103 05:07:18.263038 progress 30 % (30 MB)
104 05:07:19.007430 progress 35 % (35 MB)
105 05:07:19.354138 progress 40 % (41 MB)
106 05:07:19.778344 progress 45 % (46 MB)
107 05:07:20.470635 progress 50 % (51 MB)
108 05:07:21.158758 progress 55 % (56 MB)
109 05:07:21.917840 progress 60 % (61 MB)
110 05:07:22.668276 progress 65 % (66 MB)
111 05:07:23.392265 progress 70 % (71 MB)
112 05:07:24.162234 progress 75 % (76 MB)
113 05:07:24.839021 progress 80 % (82 MB)
114 05:07:25.550119 progress 85 % (87 MB)
115 05:07:26.268479 progress 90 % (92 MB)
116 05:07:26.968271 progress 95 % (97 MB)
117 05:07:27.698254 progress 100 % (102 MB)
118 05:07:27.710228 102 MB downloaded in 13.54 s (7.58 MB/s)
119 05:07:27.711179 end: 1.4.1 http-download (duration 00:00:14) [common]
121 05:07:27.713038 end: 1.4 download-retry (duration 00:00:14) [common]
122 05:07:27.713622 start: 1.5 download-retry (timeout 00:09:46) [common]
123 05:07:27.714201 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 05:07:27.715266 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
125 05:07:27.715552 saving as /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/modules/modules.tar
126 05:07:27.715774 total size: 11614180 (11 MB)
127 05:07:27.716013 Using unxz to decompress xz
128 05:07:27.759874 progress 0 % (0 MB)
129 05:07:27.829574 progress 5 % (0 MB)
130 05:07:27.906294 progress 10 % (1 MB)
131 05:07:27.993601 progress 15 % (1 MB)
132 05:07:28.069078 progress 20 % (2 MB)
133 05:07:28.150792 progress 25 % (2 MB)
134 05:07:28.229724 progress 30 % (3 MB)
135 05:07:28.308310 progress 35 % (3 MB)
136 05:07:28.380892 progress 40 % (4 MB)
137 05:07:28.457037 progress 45 % (5 MB)
138 05:07:28.533817 progress 50 % (5 MB)
139 05:07:28.605109 progress 55 % (6 MB)
140 05:07:28.688727 progress 60 % (6 MB)
141 05:07:28.773762 progress 65 % (7 MB)
142 05:07:28.854181 progress 70 % (7 MB)
143 05:07:28.945660 progress 75 % (8 MB)
144 05:07:29.040161 progress 80 % (8 MB)
145 05:07:29.121106 progress 85 % (9 MB)
146 05:07:29.190709 progress 90 % (9 MB)
147 05:07:29.266693 progress 95 % (10 MB)
148 05:07:29.342143 progress 100 % (11 MB)
149 05:07:29.354071 11 MB downloaded in 1.64 s (6.76 MB/s)
150 05:07:29.354710 end: 1.5.1 http-download (duration 00:00:02) [common]
152 05:07:29.355548 end: 1.5 download-retry (duration 00:00:02) [common]
153 05:07:29.355825 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 05:07:29.356283 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 05:07:39.530129 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/796434/extract-nfsrootfs-hefywh9j
156 05:07:39.530729 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 05:07:39.531018 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 05:07:39.531639 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg
159 05:07:39.532101 makedir: /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin
160 05:07:39.532441 makedir: /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/tests
161 05:07:39.532758 makedir: /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/results
162 05:07:39.533091 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-add-keys
163 05:07:39.533618 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-add-sources
164 05:07:39.534132 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-background-process-start
165 05:07:39.534631 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-background-process-stop
166 05:07:39.535159 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-common-functions
167 05:07:39.535661 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-echo-ipv4
168 05:07:39.536179 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-install-packages
169 05:07:39.536687 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-installed-packages
170 05:07:39.537166 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-os-build
171 05:07:39.537669 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-probe-channel
172 05:07:39.538170 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-probe-ip
173 05:07:39.538673 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-target-ip
174 05:07:39.539152 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-target-mac
175 05:07:39.539630 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-target-storage
176 05:07:39.540141 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-test-case
177 05:07:39.540641 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-test-event
178 05:07:39.541117 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-test-feedback
179 05:07:39.541595 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-test-raise
180 05:07:39.542082 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-test-reference
181 05:07:39.542579 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-test-runner
182 05:07:39.543065 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-test-set
183 05:07:39.543537 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-test-shell
184 05:07:39.544048 Updating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-install-packages (oe)
185 05:07:39.544603 Updating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/bin/lava-installed-packages (oe)
186 05:07:39.545047 Creating /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/environment
187 05:07:39.545419 LAVA metadata
188 05:07:39.545678 - LAVA_JOB_ID=796434
189 05:07:39.545893 - LAVA_DISPATCHER_IP=192.168.6.2
190 05:07:39.546244 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 05:07:39.547184 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 05:07:39.547492 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 05:07:39.547701 skipped lava-vland-overlay
194 05:07:39.547943 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 05:07:39.548232 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 05:07:39.548450 skipped lava-multinode-overlay
197 05:07:39.548692 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 05:07:39.548941 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 05:07:39.549189 Loading test definitions
200 05:07:39.549464 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 05:07:39.549683 Using /lava-796434 at stage 0
202 05:07:39.550933 uuid=796434_1.6.2.4.1 testdef=None
203 05:07:39.551248 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 05:07:39.551511 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 05:07:39.553339 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 05:07:39.554122 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 05:07:39.556364 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 05:07:39.557187 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 05:07:39.559344 runner path: /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/0/tests/0_dmesg test_uuid 796434_1.6.2.4.1
212 05:07:39.559890 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 05:07:39.560676 Creating lava-test-runner.conf files
215 05:07:39.560875 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796434/lava-overlay-co1xstyg/lava-796434/0 for stage 0
216 05:07:39.561210 - 0_dmesg
217 05:07:39.561547 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 05:07:39.561822 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 05:07:39.583588 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 05:07:39.583963 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 05:07:39.584253 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 05:07:39.584521 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 05:07:39.584783 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 05:07:40.194347 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 05:07:40.194814 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 05:07:40.195085 extracting modules file /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796434/extract-nfsrootfs-hefywh9j
227 05:07:41.549535 extracting modules file /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796434/extract-overlay-ramdisk-e9gez5xq/ramdisk
228 05:07:42.940835 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 05:07:42.941295 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 05:07:42.941596 [common] Applying overlay to NFS
231 05:07:42.941829 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796434/compress-overlay-uhhpoiua/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796434/extract-nfsrootfs-hefywh9j
232 05:07:42.971043 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 05:07:42.971409 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 05:07:42.971701 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 05:07:42.971938 Converting downloaded kernel to a uImage
236 05:07:42.972279 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/kernel/Image /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/kernel/uImage
237 05:07:43.460287 output: Image Name:
238 05:07:43.460718 output: Created: Thu Oct 3 05:07:42 2024
239 05:07:43.460927 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 05:07:43.461131 output: Data Size: 45998592 Bytes = 44920.50 KiB = 43.87 MiB
241 05:07:43.461334 output: Load Address: 01080000
242 05:07:43.461534 output: Entry Point: 01080000
243 05:07:43.461731 output:
244 05:07:43.462071 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 05:07:43.462336 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 05:07:43.462605 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 05:07:43.462861 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 05:07:43.463118 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 05:07:43.463373 Building ramdisk /var/lib/lava/dispatcher/tmp/796434/extract-overlay-ramdisk-e9gez5xq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796434/extract-overlay-ramdisk-e9gez5xq/ramdisk
250 05:07:45.576784 >> 166877 blocks
251 05:07:53.314000 Adding RAMdisk u-boot header.
252 05:07:53.314719 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796434/extract-overlay-ramdisk-e9gez5xq/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796434/extract-overlay-ramdisk-e9gez5xq/ramdisk.cpio.gz.uboot
253 05:07:53.565775 output: Image Name:
254 05:07:53.566197 output: Created: Thu Oct 3 05:07:53 2024
255 05:07:53.566671 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 05:07:53.567134 output: Data Size: 23425911 Bytes = 22876.87 KiB = 22.34 MiB
257 05:07:53.567586 output: Load Address: 00000000
258 05:07:53.568083 output: Entry Point: 00000000
259 05:07:53.568536 output:
260 05:07:53.569733 rename /var/lib/lava/dispatcher/tmp/796434/extract-overlay-ramdisk-e9gez5xq/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/ramdisk/ramdisk.cpio.gz.uboot
261 05:07:53.570527 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 05:07:53.571142 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 05:07:53.571734 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 05:07:53.572294 No LXC device requested
265 05:07:53.572870 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 05:07:53.573443 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 05:07:53.573998 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 05:07:53.574457 Checking files for TFTP limit of 4294967296 bytes.
269 05:07:53.577445 end: 1 tftp-deploy (duration 00:00:40) [common]
270 05:07:53.578116 start: 2 uboot-action (timeout 00:05:00) [common]
271 05:07:53.578713 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 05:07:53.579288 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 05:07:53.579862 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 05:07:53.580576 Using kernel file from prepare-kernel: 796434/tftp-deploy-zclwk40v/kernel/uImage
275 05:07:53.581291 substitutions:
276 05:07:53.581757 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 05:07:53.582216 - {DTB_ADDR}: 0x01070000
278 05:07:53.582666 - {DTB}: 796434/tftp-deploy-zclwk40v/dtb/meson-g12b-a311d-libretech-cc.dtb
279 05:07:53.583115 - {INITRD}: 796434/tftp-deploy-zclwk40v/ramdisk/ramdisk.cpio.gz.uboot
280 05:07:53.583558 - {KERNEL_ADDR}: 0x01080000
281 05:07:53.584039 - {KERNEL}: 796434/tftp-deploy-zclwk40v/kernel/uImage
282 05:07:53.584495 - {LAVA_MAC}: None
283 05:07:53.584986 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/796434/extract-nfsrootfs-hefywh9j
284 05:07:53.585435 - {NFS_SERVER_IP}: 192.168.6.2
285 05:07:53.585874 - {PRESEED_CONFIG}: None
286 05:07:53.586313 - {PRESEED_LOCAL}: None
287 05:07:53.586749 - {RAMDISK_ADDR}: 0x08000000
288 05:07:53.587180 - {RAMDISK}: 796434/tftp-deploy-zclwk40v/ramdisk/ramdisk.cpio.gz.uboot
289 05:07:53.587612 - {ROOT_PART}: None
290 05:07:53.588079 - {ROOT}: None
291 05:07:53.588525 - {SERVER_IP}: 192.168.6.2
292 05:07:53.588958 - {TEE_ADDR}: 0x83000000
293 05:07:53.589390 - {TEE}: None
294 05:07:53.589824 Parsed boot commands:
295 05:07:53.590249 - setenv autoload no
296 05:07:53.590678 - setenv initrd_high 0xffffffff
297 05:07:53.591109 - setenv fdt_high 0xffffffff
298 05:07:53.591540 - dhcp
299 05:07:53.591968 - setenv serverip 192.168.6.2
300 05:07:53.592432 - tftpboot 0x01080000 796434/tftp-deploy-zclwk40v/kernel/uImage
301 05:07:53.592869 - tftpboot 0x08000000 796434/tftp-deploy-zclwk40v/ramdisk/ramdisk.cpio.gz.uboot
302 05:07:53.593301 - tftpboot 0x01070000 796434/tftp-deploy-zclwk40v/dtb/meson-g12b-a311d-libretech-cc.dtb
303 05:07:53.593734 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/796434/extract-nfsrootfs-hefywh9j,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 05:07:53.594177 - bootm 0x01080000 0x08000000 0x01070000
305 05:07:53.594734 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 05:07:53.596429 start: 2.3 connect-device (timeout 00:05:00) [common]
308 05:07:53.596904 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 05:07:53.613376 Setting prompt string to ['lava-test: # ']
310 05:07:53.614958 end: 2.3 connect-device (duration 00:00:00) [common]
311 05:07:53.615643 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 05:07:53.616333 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 05:07:53.616930 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 05:07:53.618185 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 05:07:53.653837 >> OK - accepted request
316 05:07:53.655973 Returned 0 in 0 seconds
317 05:07:53.757239 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 05:07:53.758991 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 05:07:53.759641 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 05:07:53.760309 Setting prompt string to ['Hit any key to stop autoboot']
322 05:07:53.760854 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 05:07:53.762548 Trying 192.168.56.21...
324 05:07:53.763069 Connected to conserv1.
325 05:07:53.763533 Escape character is '^]'.
326 05:07:53.764028
327 05:07:53.764517 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 05:07:53.764999
329 05:08:05.144360 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 05:08:05.145013 bl2_stage_init 0x01
331 05:08:05.145489 bl2_stage_init 0x81
332 05:08:05.150061 hw id: 0x0000 - pwm id 0x01
333 05:08:05.150569 bl2_stage_init 0xc1
334 05:08:05.151030 bl2_stage_init 0x02
335 05:08:05.151464
336 05:08:05.155601 L0:00000000
337 05:08:05.156115 L1:20000703
338 05:08:05.156553 L2:00008067
339 05:08:05.156980 L3:14000000
340 05:08:05.158598 B2:00402000
341 05:08:05.159069 B1:e0f83180
342 05:08:05.159509
343 05:08:05.159939 TE: 58124
344 05:08:05.160409
345 05:08:05.169757 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 05:08:05.170231
347 05:08:05.170668 Board ID = 1
348 05:08:05.171096 Set A53 clk to 24M
349 05:08:05.171525 Set A73 clk to 24M
350 05:08:05.175445 Set clk81 to 24M
351 05:08:05.175907 A53 clk: 1200 MHz
352 05:08:05.176372 A73 clk: 1200 MHz
353 05:08:05.181048 CLK81: 166.6M
354 05:08:05.181513 smccc: 00012a91
355 05:08:05.186613 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 05:08:05.187081 board id: 1
357 05:08:05.194389 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 05:08:05.205564 fw parse done
359 05:08:05.211534 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 05:08:05.254145 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 05:08:05.265061 PIEI prepare done
362 05:08:05.265529 fastboot data load
363 05:08:05.265968 fastboot data verify
364 05:08:05.270840 verify result: 266
365 05:08:05.276334 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 05:08:05.276799 LPDDR4 probe
367 05:08:05.277235 ddr clk to 1584MHz
368 05:08:05.284316 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 05:08:05.321593
370 05:08:05.322081 dmc_version 0001
371 05:08:05.328261 Check phy result
372 05:08:05.334075 INFO : End of CA training
373 05:08:05.334541 INFO : End of initialization
374 05:08:05.339689 INFO : Training has run successfully!
375 05:08:05.340191 Check phy result
376 05:08:05.345311 INFO : End of initialization
377 05:08:05.345770 INFO : End of read enable training
378 05:08:05.350902 INFO : End of fine write leveling
379 05:08:05.356485 INFO : End of Write leveling coarse delay
380 05:08:05.356949 INFO : Training has run successfully!
381 05:08:05.357390 Check phy result
382 05:08:05.362070 INFO : End of initialization
383 05:08:05.362545 INFO : End of read dq deskew training
384 05:08:05.367715 INFO : End of MPR read delay center optimization
385 05:08:05.373292 INFO : End of write delay center optimization
386 05:08:05.378869 INFO : End of read delay center optimization
387 05:08:05.379334 INFO : End of max read latency training
388 05:08:05.384484 INFO : Training has run successfully!
389 05:08:05.385014 1D training succeed
390 05:08:05.393696 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 05:08:05.441249 Check phy result
392 05:08:05.441731 INFO : End of initialization
393 05:08:05.462977 INFO : End of 2D read delay Voltage center optimization
394 05:08:05.483274 INFO : End of 2D read delay Voltage center optimization
395 05:08:05.535279 INFO : End of 2D write delay Voltage center optimization
396 05:08:05.584721 INFO : End of 2D write delay Voltage center optimization
397 05:08:05.590309 INFO : Training has run successfully!
398 05:08:05.590769
399 05:08:05.591209 channel==0
400 05:08:05.595845 RxClkDly_Margin_A0==88 ps 9
401 05:08:05.596366 TxDqDly_Margin_A0==98 ps 10
402 05:08:05.601518 RxClkDly_Margin_A1==88 ps 9
403 05:08:05.601978 TxDqDly_Margin_A1==98 ps 10
404 05:08:05.602419 TrainedVREFDQ_A0==74
405 05:08:05.607056 TrainedVREFDQ_A1==75
406 05:08:05.607521 VrefDac_Margin_A0==25
407 05:08:05.607955 DeviceVref_Margin_A0==40
408 05:08:05.612775 VrefDac_Margin_A1==25
409 05:08:05.613230 DeviceVref_Margin_A1==39
410 05:08:05.613663
411 05:08:05.614098
412 05:08:05.618254 channel==1
413 05:08:05.618711 RxClkDly_Margin_A0==88 ps 9
414 05:08:05.619147 TxDqDly_Margin_A0==88 ps 9
415 05:08:05.623848 RxClkDly_Margin_A1==98 ps 10
416 05:08:05.624338 TxDqDly_Margin_A1==88 ps 9
417 05:08:05.629538 TrainedVREFDQ_A0==76
418 05:08:05.630000 TrainedVREFDQ_A1==77
419 05:08:05.630436 VrefDac_Margin_A0==22
420 05:08:05.635084 DeviceVref_Margin_A0==38
421 05:08:05.635541 VrefDac_Margin_A1==22
422 05:08:05.640686 DeviceVref_Margin_A1==37
423 05:08:05.641142
424 05:08:05.641575 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 05:08:05.642005
426 05:08:05.674238 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 05:08:05.674783 2D training succeed
428 05:08:05.679849 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 05:08:05.685566 auto size-- 65535DDR cs0 size: 2048MB
430 05:08:05.686031 DDR cs1 size: 2048MB
431 05:08:05.691047 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 05:08:05.691505 cs0 DataBus test pass
433 05:08:05.696690 cs1 DataBus test pass
434 05:08:05.697145 cs0 AddrBus test pass
435 05:08:05.697579 cs1 AddrBus test pass
436 05:08:05.698007
437 05:08:05.702235 100bdlr_step_size ps== 420
438 05:08:05.702701 result report
439 05:08:05.707856 boot times 0Enable ddr reg access
440 05:08:05.713122 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 05:08:05.726600 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 05:08:06.300242 0.0;M3 CHK:0;cm4_sp_mode 0
443 05:08:06.300805 MVN_1=0x00000000
444 05:08:06.305640 MVN_2=0x00000000
445 05:08:06.311373 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 05:08:06.311846 OPS=0x10
447 05:08:06.312370 ring efuse init
448 05:08:06.312824 chipver efuse init
449 05:08:06.317071 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 05:08:06.322588 [0.018961 Inits done]
451 05:08:06.323059 secure task start!
452 05:08:06.323511 high task start!
453 05:08:06.327149 low task start!
454 05:08:06.327625 run into bl31
455 05:08:06.333849 NOTICE: BL31: v1.3(release):4fc40b1
456 05:08:06.341636 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 05:08:06.342118 NOTICE: BL31: G12A normal boot!
458 05:08:06.367063 NOTICE: BL31: BL33 decompress pass
459 05:08:06.372678 ERROR: Error initializing runtime service opteed_fast
460 05:08:07.605567
461 05:08:07.606220
462 05:08:07.613939 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 05:08:07.614431
464 05:08:07.614889 Model: Libre Computer AML-A311D-CC Alta
465 05:08:07.822311 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 05:08:07.845726 DRAM: 2 GiB (effective 3.8 GiB)
467 05:08:07.988806 Core: 408 devices, 31 uclasses, devicetree: separate
468 05:08:07.994624 WDT: Not starting watchdog@f0d0
469 05:08:08.026837 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 05:08:08.039325 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 05:08:08.044365 ** Bad device specification mmc 0 **
472 05:08:08.054622 Card did not respond to voltage select! : -110
473 05:08:08.062260 ** Bad device specification mmc 0 **
474 05:08:08.062737 Couldn't find partition mmc 0
475 05:08:08.070597 Card did not respond to voltage select! : -110
476 05:08:08.076163 ** Bad device specification mmc 0 **
477 05:08:08.076638 Couldn't find partition mmc 0
478 05:08:08.081216 Error: could not access storage.
479 05:08:09.344705 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 05:08:09.345345 bl2_stage_init 0x01
481 05:08:09.345820 bl2_stage_init 0x81
482 05:08:09.350303 hw id: 0x0000 - pwm id 0x01
483 05:08:09.350803 bl2_stage_init 0xc1
484 05:08:09.351262 bl2_stage_init 0x02
485 05:08:09.351708
486 05:08:09.355961 L0:00000000
487 05:08:09.356477 L1:20000703
488 05:08:09.356930 L2:00008067
489 05:08:09.357376 L3:14000000
490 05:08:09.361476 B2:00402000
491 05:08:09.361948 B1:e0f83180
492 05:08:09.362397
493 05:08:09.362840 TE: 58124
494 05:08:09.363283
495 05:08:09.367084 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 05:08:09.367584
497 05:08:09.368072 Board ID = 1
498 05:08:09.372659 Set A53 clk to 24M
499 05:08:09.373137 Set A73 clk to 24M
500 05:08:09.373585 Set clk81 to 24M
501 05:08:09.378256 A53 clk: 1200 MHz
502 05:08:09.378728 A73 clk: 1200 MHz
503 05:08:09.379180 CLK81: 166.6M
504 05:08:09.379626 smccc: 00012a92
505 05:08:09.383965 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 05:08:09.389461 board id: 1
507 05:08:09.395375 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 05:08:09.406019 fw parse done
509 05:08:09.412066 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 05:08:09.454621 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 05:08:09.465543 PIEI prepare done
512 05:08:09.466016 fastboot data load
513 05:08:09.466468 fastboot data verify
514 05:08:09.471188 verify result: 266
515 05:08:09.476819 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 05:08:09.477290 LPDDR4 probe
517 05:08:09.477738 ddr clk to 1584MHz
518 05:08:09.484767 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 05:08:09.522008
520 05:08:09.522479 dmc_version 0001
521 05:08:09.528680 Check phy result
522 05:08:09.534548 INFO : End of CA training
523 05:08:09.535020 INFO : End of initialization
524 05:08:09.540164 INFO : Training has run successfully!
525 05:08:09.540632 Check phy result
526 05:08:09.545761 INFO : End of initialization
527 05:08:09.546228 INFO : End of read enable training
528 05:08:09.549078 INFO : End of fine write leveling
529 05:08:09.554598 INFO : End of Write leveling coarse delay
530 05:08:09.560249 INFO : Training has run successfully!
531 05:08:09.560722 Check phy result
532 05:08:09.561170 INFO : End of initialization
533 05:08:09.565819 INFO : End of read dq deskew training
534 05:08:09.571397 INFO : End of MPR read delay center optimization
535 05:08:09.571867 INFO : End of write delay center optimization
536 05:08:09.577060 INFO : End of read delay center optimization
537 05:08:09.582583 INFO : End of max read latency training
538 05:08:09.583070 INFO : Training has run successfully!
539 05:08:09.588219 1D training succeed
540 05:08:09.594126 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 05:08:09.641779 Check phy result
542 05:08:09.642253 INFO : End of initialization
543 05:08:09.664292 INFO : End of 2D read delay Voltage center optimization
544 05:08:09.684536 INFO : End of 2D read delay Voltage center optimization
545 05:08:09.736547 INFO : End of 2D write delay Voltage center optimization
546 05:08:09.785923 INFO : End of 2D write delay Voltage center optimization
547 05:08:09.791517 INFO : Training has run successfully!
548 05:08:09.792036
549 05:08:09.792504 channel==0
550 05:08:09.797098 RxClkDly_Margin_A0==88 ps 9
551 05:08:09.797582 TxDqDly_Margin_A0==98 ps 10
552 05:08:09.800428 RxClkDly_Margin_A1==88 ps 9
553 05:08:09.800897 TxDqDly_Margin_A1==98 ps 10
554 05:08:09.806107 TrainedVREFDQ_A0==74
555 05:08:09.806578 TrainedVREFDQ_A1==74
556 05:08:09.807027 VrefDac_Margin_A0==24
557 05:08:09.811650 DeviceVref_Margin_A0==40
558 05:08:09.812148 VrefDac_Margin_A1==24
559 05:08:09.817240 DeviceVref_Margin_A1==40
560 05:08:09.817720
561 05:08:09.818169
562 05:08:09.818613 channel==1
563 05:08:09.819048 RxClkDly_Margin_A0==98 ps 10
564 05:08:09.820521 TxDqDly_Margin_A0==88 ps 9
565 05:08:09.826091 RxClkDly_Margin_A1==98 ps 10
566 05:08:09.826559 TxDqDly_Margin_A1==88 ps 9
567 05:08:09.827008 TrainedVREFDQ_A0==77
568 05:08:09.831670 TrainedVREFDQ_A1==77
569 05:08:09.832172 VrefDac_Margin_A0==22
570 05:08:09.837296 DeviceVref_Margin_A0==37
571 05:08:09.837760 VrefDac_Margin_A1==22
572 05:08:09.838204 DeviceVref_Margin_A1==37
573 05:08:09.838641
574 05:08:09.842871 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 05:08:09.843342
576 05:08:09.876493 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 05:08:09.877010 2D training succeed
578 05:08:09.882087 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 05:08:09.887639 auto size-- 65535DDR cs0 size: 2048MB
580 05:08:09.888138 DDR cs1 size: 2048MB
581 05:08:09.893246 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 05:08:09.893718 cs0 DataBus test pass
583 05:08:09.894166 cs1 DataBus test pass
584 05:08:09.898897 cs0 AddrBus test pass
585 05:08:09.899370 cs1 AddrBus test pass
586 05:08:09.899815
587 05:08:09.904507 100bdlr_step_size ps== 420
588 05:08:09.904993 result report
589 05:08:09.905437 boot times 0Enable ddr reg access
590 05:08:09.914446 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 05:08:09.927970 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 05:08:10.501831 0.0;M3 CHK:0;cm4_sp_mode 0
593 05:08:10.502429 MVN_1=0x00000000
594 05:08:10.507284 MVN_2=0x00000000
595 05:08:10.513133 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 05:08:10.513647 OPS=0x10
597 05:08:10.514121 ring efuse init
598 05:08:10.514599 chipver efuse init
599 05:08:10.521568 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 05:08:10.522092 [0.018961 Inits done]
601 05:08:10.522529 secure task start!
602 05:08:10.528897 high task start!
603 05:08:10.529357 low task start!
604 05:08:10.529788 run into bl31
605 05:08:10.535490 NOTICE: BL31: v1.3(release):4fc40b1
606 05:08:10.543496 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 05:08:10.543965 NOTICE: BL31: G12A normal boot!
608 05:08:10.568512 NOTICE: BL31: BL33 decompress pass
609 05:08:10.574287 ERROR: Error initializing runtime service opteed_fast
610 05:08:11.807148
611 05:08:11.807809
612 05:08:11.815613 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 05:08:11.816140
614 05:08:11.816597 Model: Libre Computer AML-A311D-CC Alta
615 05:08:12.024277 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 05:08:12.047888 DRAM: 2 GiB (effective 3.8 GiB)
617 05:08:12.192995 Core: 408 devices, 31 uclasses, devicetree: separate
618 05:08:12.196489 WDT: Not starting watchdog@f0d0
619 05:08:12.229299 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 05:08:12.252985 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 05:08:12.253400 ** Bad device specification mmc 0 **
622 05:08:12.256350 Card did not respond to voltage select! : -110
623 05:08:12.263969 ** Bad device specification mmc 0 **
624 05:08:12.264515 Couldn't find partition mmc 0
625 05:08:12.272261 Card did not respond to voltage select! : -110
626 05:08:12.277729 ** Bad device specification mmc 0 **
627 05:08:12.278204 Couldn't find partition mmc 0
628 05:08:12.282882 Error: could not access storage.
629 05:08:12.625383 Net: eth0: ethernet@ff3f0000
630 05:08:12.625815 starting USB...
631 05:08:12.877054 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 05:08:12.877614 Starting the controller
633 05:08:12.884048 USB XHCI 1.10
634 05:08:14.595121 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 05:08:14.595530 bl2_stage_init 0x01
636 05:08:14.595742 bl2_stage_init 0x81
637 05:08:14.600556 hw id: 0x0000 - pwm id 0x01
638 05:08:14.600920 bl2_stage_init 0xc1
639 05:08:14.601229 bl2_stage_init 0x02
640 05:08:14.601531
641 05:08:14.606196 L0:00000000
642 05:08:14.606576 L1:20000703
643 05:08:14.606806 L2:00008067
644 05:08:14.607012 L3:14000000
645 05:08:14.611779 B2:00402000
646 05:08:14.612170 B1:e0f83180
647 05:08:14.612477
648 05:08:14.612774 TE: 58167
649 05:08:14.613068
650 05:08:14.617402 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 05:08:14.617669
652 05:08:14.617875 Board ID = 1
653 05:08:14.623031 Set A53 clk to 24M
654 05:08:14.623421 Set A73 clk to 24M
655 05:08:14.623731 Set clk81 to 24M
656 05:08:14.628542 A53 clk: 1200 MHz
657 05:08:14.628900 A73 clk: 1200 MHz
658 05:08:14.629130 CLK81: 166.6M
659 05:08:14.629328 smccc: 00012abd
660 05:08:14.634203 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 05:08:14.639763 board id: 1
662 05:08:14.645717 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 05:08:14.656318 fw parse done
664 05:08:14.662459 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 05:08:14.704904 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 05:08:14.715790 PIEI prepare done
667 05:08:14.716323 fastboot data load
668 05:08:14.716792 fastboot data verify
669 05:08:14.721461 verify result: 266
670 05:08:14.727065 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 05:08:14.727547 LPDDR4 probe
672 05:08:14.728036 ddr clk to 1584MHz
673 05:08:14.735026 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 05:08:14.772329
675 05:08:14.772843 dmc_version 0001
676 05:08:14.778981 Check phy result
677 05:08:14.784852 INFO : End of CA training
678 05:08:14.785341 INFO : End of initialization
679 05:08:14.790435 INFO : Training has run successfully!
680 05:08:14.790924 Check phy result
681 05:08:14.796066 INFO : End of initialization
682 05:08:14.796557 INFO : End of read enable training
683 05:08:14.801664 INFO : End of fine write leveling
684 05:08:14.807246 INFO : End of Write leveling coarse delay
685 05:08:14.807733 INFO : Training has run successfully!
686 05:08:14.808230 Check phy result
687 05:08:14.812845 INFO : End of initialization
688 05:08:14.813335 INFO : End of read dq deskew training
689 05:08:14.818515 INFO : End of MPR read delay center optimization
690 05:08:14.824103 INFO : End of write delay center optimization
691 05:08:14.829669 INFO : End of read delay center optimization
692 05:08:14.830155 INFO : End of max read latency training
693 05:08:14.835304 INFO : Training has run successfully!
694 05:08:14.835796 1D training succeed
695 05:08:14.844436 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 05:08:14.892076 Check phy result
697 05:08:14.892596 INFO : End of initialization
698 05:08:14.914688 INFO : End of 2D read delay Voltage center optimization
699 05:08:14.934973 INFO : End of 2D read delay Voltage center optimization
700 05:08:14.986973 INFO : End of 2D write delay Voltage center optimization
701 05:08:15.036426 INFO : End of 2D write delay Voltage center optimization
702 05:08:15.041915 INFO : Training has run successfully!
703 05:08:15.042405
704 05:08:15.042869 channel==0
705 05:08:15.047596 RxClkDly_Margin_A0==88 ps 9
706 05:08:15.048130 TxDqDly_Margin_A0==98 ps 10
707 05:08:15.050960 RxClkDly_Margin_A1==88 ps 9
708 05:08:15.051452 TxDqDly_Margin_A1==98 ps 10
709 05:08:15.056566 TrainedVREFDQ_A0==74
710 05:08:15.057086 TrainedVREFDQ_A1==74
711 05:08:15.057553 VrefDac_Margin_A0==24
712 05:08:15.062290 DeviceVref_Margin_A0==40
713 05:08:15.062785 VrefDac_Margin_A1==24
714 05:08:15.067803 DeviceVref_Margin_A1==40
715 05:08:15.068322
716 05:08:15.068787
717 05:08:15.069237 channel==1
718 05:08:15.069678 RxClkDly_Margin_A0==88 ps 9
719 05:08:15.071153 TxDqDly_Margin_A0==98 ps 10
720 05:08:15.076711 RxClkDly_Margin_A1==88 ps 9
721 05:08:15.077213 TxDqDly_Margin_A1==98 ps 10
722 05:08:15.077681 TrainedVREFDQ_A0==77
723 05:08:15.082318 TrainedVREFDQ_A1==78
724 05:08:15.082825 VrefDac_Margin_A0==22
725 05:08:15.087922 DeviceVref_Margin_A0==37
726 05:08:15.088438 VrefDac_Margin_A1==24
727 05:08:15.088898 DeviceVref_Margin_A1==36
728 05:08:15.089477
729 05:08:15.096933 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 05:08:15.097439
731 05:08:15.124892 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 05:08:15.125449 2D training succeed
733 05:08:15.136004 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 05:08:15.136519 auto size-- 65535DDR cs0 size: 2048MB
735 05:08:15.136983 DDR cs1 size: 2048MB
736 05:08:15.141597 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 05:08:15.142095 cs0 DataBus test pass
738 05:08:15.147199 cs1 DataBus test pass
739 05:08:15.147695 cs0 AddrBus test pass
740 05:08:15.152831 cs1 AddrBus test pass
741 05:08:15.153329
742 05:08:15.153793 100bdlr_step_size ps== 420
743 05:08:15.154248 result report
744 05:08:15.158379 boot times 0Enable ddr reg access
745 05:08:15.164903 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 05:08:15.178290 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 05:08:15.752090 0.0;M3 CHK:0;cm4_sp_mode 0
748 05:08:15.752749 MVN_1=0x00000000
749 05:08:15.757394 MVN_2=0x00000000
750 05:08:15.763194 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 05:08:15.763784 OPS=0x10
752 05:08:15.764297 ring efuse init
753 05:08:15.764733 chipver efuse init
754 05:08:15.771507 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 05:08:15.772034 [0.018961 Inits done]
756 05:08:15.772482 secure task start!
757 05:08:15.778976 high task start!
758 05:08:15.779452 low task start!
759 05:08:15.779885 run into bl31
760 05:08:15.785556 NOTICE: BL31: v1.3(release):4fc40b1
761 05:08:15.793481 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 05:08:15.794071 NOTICE: BL31: G12A normal boot!
763 05:08:15.818989 NOTICE: BL31: BL33 decompress pass
764 05:08:15.824503 ERROR: Error initializing runtime service opteed_fast
765 05:08:17.057364
766 05:08:17.057995
767 05:08:17.065728 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 05:08:17.066239
769 05:08:17.066708 Model: Libre Computer AML-A311D-CC Alta
770 05:08:17.274109 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 05:08:17.297525 DRAM: 2 GiB (effective 3.8 GiB)
772 05:08:17.440489 Core: 408 devices, 31 uclasses, devicetree: separate
773 05:08:17.446367 WDT: Not starting watchdog@f0d0
774 05:08:17.478820 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 05:08:17.491312 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 05:08:17.496375 ** Bad device specification mmc 0 **
777 05:08:17.506627 Card did not respond to voltage select! : -110
778 05:08:17.514378 ** Bad device specification mmc 0 **
779 05:08:17.515005 Couldn't find partition mmc 0
780 05:08:17.522487 Card did not respond to voltage select! : -110
781 05:08:17.527957 ** Bad device specification mmc 0 **
782 05:08:17.528694 Couldn't find partition mmc 0
783 05:08:17.533091 Error: could not access storage.
784 05:08:17.875517 Net: eth0: ethernet@ff3f0000
785 05:08:17.876184 starting USB...
786 05:08:18.127352 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 05:08:18.127967 Starting the controller
788 05:08:18.134426 USB XHCI 1.10
789 05:08:20.296709 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 05:08:20.297337 bl2_stage_init 0x01
791 05:08:20.297825 bl2_stage_init 0x81
792 05:08:20.302408 hw id: 0x0000 - pwm id 0x01
793 05:08:20.302966 bl2_stage_init 0xc1
794 05:08:20.303438 bl2_stage_init 0x02
795 05:08:20.303892
796 05:08:20.308003 L0:00000000
797 05:08:20.308555 L1:20000703
798 05:08:20.309024 L2:00008067
799 05:08:20.309473 L3:14000000
800 05:08:20.313574 B2:00402000
801 05:08:20.314117 B1:e0f83180
802 05:08:20.314578
803 05:08:20.315031 TE: 58124
804 05:08:20.315481
805 05:08:20.319191 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 05:08:20.319739
807 05:08:20.320251 Board ID = 1
808 05:08:20.324753 Set A53 clk to 24M
809 05:08:20.325307 Set A73 clk to 24M
810 05:08:20.325770 Set clk81 to 24M
811 05:08:20.330434 A53 clk: 1200 MHz
812 05:08:20.331009 A73 clk: 1200 MHz
813 05:08:20.331475 CLK81: 166.6M
814 05:08:20.331925 smccc: 00012a91
815 05:08:20.335881 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 05:08:20.341571 board id: 1
817 05:08:20.347580 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 05:08:20.357966 fw parse done
819 05:08:20.363973 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 05:08:20.406723 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 05:08:20.417499 PIEI prepare done
822 05:08:20.418049 fastboot data load
823 05:08:20.418519 fastboot data verify
824 05:08:20.423110 verify result: 266
825 05:08:20.428697 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 05:08:20.429247 LPDDR4 probe
827 05:08:20.429712 ddr clk to 1584MHz
828 05:08:20.436794 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 05:08:20.474000
830 05:08:20.474573 dmc_version 0001
831 05:08:20.480733 Check phy result
832 05:08:20.486469 INFO : End of CA training
833 05:08:20.487003 INFO : End of initialization
834 05:08:20.492157 INFO : Training has run successfully!
835 05:08:20.492727 Check phy result
836 05:08:20.497841 INFO : End of initialization
837 05:08:20.498387 INFO : End of read enable training
838 05:08:20.503422 INFO : End of fine write leveling
839 05:08:20.508949 INFO : End of Write leveling coarse delay
840 05:08:20.509503 INFO : Training has run successfully!
841 05:08:20.509975 Check phy result
842 05:08:20.514509 INFO : End of initialization
843 05:08:20.515060 INFO : End of read dq deskew training
844 05:08:20.520126 INFO : End of MPR read delay center optimization
845 05:08:20.525652 INFO : End of write delay center optimization
846 05:08:20.531262 INFO : End of read delay center optimization
847 05:08:20.531804 INFO : End of max read latency training
848 05:08:20.536952 INFO : Training has run successfully!
849 05:08:20.537493 1D training succeed
850 05:08:20.546131 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 05:08:20.593611 Check phy result
852 05:08:20.594175 INFO : End of initialization
853 05:08:20.615509 INFO : End of 2D read delay Voltage center optimization
854 05:08:20.635852 INFO : End of 2D read delay Voltage center optimization
855 05:08:20.687892 INFO : End of 2D write delay Voltage center optimization
856 05:08:20.737116 INFO : End of 2D write delay Voltage center optimization
857 05:08:20.742838 INFO : Training has run successfully!
858 05:08:20.743379
859 05:08:20.743845 channel==0
860 05:08:20.748297 RxClkDly_Margin_A0==88 ps 9
861 05:08:20.748838 TxDqDly_Margin_A0==98 ps 10
862 05:08:20.751618 RxClkDly_Margin_A1==88 ps 9
863 05:08:20.752187 TxDqDly_Margin_A1==98 ps 10
864 05:08:20.757265 TrainedVREFDQ_A0==74
865 05:08:20.757804 TrainedVREFDQ_A1==74
866 05:08:20.758291 VrefDac_Margin_A0==25
867 05:08:20.762811 DeviceVref_Margin_A0==40
868 05:08:20.763414 VrefDac_Margin_A1==25
869 05:08:20.768448 DeviceVref_Margin_A1==40
870 05:08:20.769013
871 05:08:20.769455
872 05:08:20.769885 channel==1
873 05:08:20.770314 RxClkDly_Margin_A0==98 ps 10
874 05:08:20.771797 TxDqDly_Margin_A0==88 ps 9
875 05:08:20.777374 RxClkDly_Margin_A1==98 ps 10
876 05:08:20.777898 TxDqDly_Margin_A1==88 ps 9
877 05:08:20.778339 TrainedVREFDQ_A0==77
878 05:08:20.782876 TrainedVREFDQ_A1==77
879 05:08:20.783409 VrefDac_Margin_A0==22
880 05:08:20.788526 DeviceVref_Margin_A0==37
881 05:08:20.789047 VrefDac_Margin_A1==22
882 05:08:20.789480 DeviceVref_Margin_A1==37
883 05:08:20.789905
884 05:08:20.794137 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 05:08:20.794661
886 05:08:20.827707 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 05:08:20.828314 2D training succeed
888 05:08:20.833326 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 05:08:20.838906 auto size-- 65535DDR cs0 size: 2048MB
890 05:08:20.839428 DDR cs1 size: 2048MB
891 05:08:20.844526 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 05:08:20.845051 cs0 DataBus test pass
893 05:08:20.845487 cs1 DataBus test pass
894 05:08:20.850116 cs0 AddrBus test pass
895 05:08:20.850640 cs1 AddrBus test pass
896 05:08:20.851078
897 05:08:20.855748 100bdlr_step_size ps== 420
898 05:08:20.856327 result report
899 05:08:20.856762 boot times 0Enable ddr reg access
900 05:08:20.865550 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 05:08:20.879061 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 05:08:21.452139 0.0;M3 CHK:0;cm4_sp_mode 0
903 05:08:21.452777 MVN_1=0x00000000
904 05:08:21.457730 MVN_2=0x00000000
905 05:08:21.463467 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 05:08:21.464050 OPS=0x10
907 05:08:21.464527 ring efuse init
908 05:08:21.464982 chipver efuse init
909 05:08:21.469074 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 05:08:21.474667 [0.018961 Inits done]
911 05:08:21.475205 secure task start!
912 05:08:21.475671 high task start!
913 05:08:21.479234 low task start!
914 05:08:21.479773 run into bl31
915 05:08:21.485933 NOTICE: BL31: v1.3(release):4fc40b1
916 05:08:21.493682 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 05:08:21.494227 NOTICE: BL31: G12A normal boot!
918 05:08:21.519035 NOTICE: BL31: BL33 decompress pass
919 05:08:21.524724 ERROR: Error initializing runtime service opteed_fast
920 05:08:22.757564
921 05:08:22.758192
922 05:08:22.766090 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 05:08:22.766638
924 05:08:22.767116 Model: Libre Computer AML-A311D-CC Alta
925 05:08:22.974312 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 05:08:22.997725 DRAM: 2 GiB (effective 3.8 GiB)
927 05:08:23.140688 Core: 408 devices, 31 uclasses, devicetree: separate
928 05:08:23.146653 WDT: Not starting watchdog@f0d0
929 05:08:23.178808 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 05:08:23.191333 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 05:08:23.196416 ** Bad device specification mmc 0 **
932 05:08:23.206580 Card did not respond to voltage select! : -110
933 05:08:23.214308 ** Bad device specification mmc 0 **
934 05:08:23.214855 Couldn't find partition mmc 0
935 05:08:23.222588 Card did not respond to voltage select! : -110
936 05:08:23.228108 ** Bad device specification mmc 0 **
937 05:08:23.228645 Couldn't find partition mmc 0
938 05:08:23.233213 Error: could not access storage.
939 05:08:23.575691 Net: eth0: ethernet@ff3f0000
940 05:08:23.576370 starting USB...
941 05:08:23.827561 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 05:08:23.828190 Starting the controller
943 05:08:23.834553 USB XHCI 1.10
944 05:08:25.696562 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 05:08:25.697308 bl2_stage_init 0x01
946 05:08:25.697807 bl2_stage_init 0x81
947 05:08:25.702100 hw id: 0x0000 - pwm id 0x01
948 05:08:25.702643 bl2_stage_init 0xc1
949 05:08:25.703110 bl2_stage_init 0x02
950 05:08:25.703568
951 05:08:25.707747 L0:00000000
952 05:08:25.708342 L1:20000703
953 05:08:25.708814 L2:00008067
954 05:08:25.709267 L3:14000000
955 05:08:25.710715 B2:00402000
956 05:08:25.711246 B1:e0f83180
957 05:08:25.711877
958 05:08:25.712435 TE: 58124
959 05:08:25.712924
960 05:08:25.721911 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 05:08:25.722468
962 05:08:25.722939 Board ID = 1
963 05:08:25.723392 Set A53 clk to 24M
964 05:08:25.723835 Set A73 clk to 24M
965 05:08:25.727489 Set clk81 to 24M
966 05:08:25.728051 A53 clk: 1200 MHz
967 05:08:25.728518 A73 clk: 1200 MHz
968 05:08:25.730908 CLK81: 166.6M
969 05:08:25.731429 smccc: 00012a91
970 05:08:25.736471 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 05:08:25.741998 board id: 1
972 05:08:25.747215 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 05:08:25.757920 fw parse done
974 05:08:25.763856 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 05:08:25.806472 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 05:08:25.817431 PIEI prepare done
977 05:08:25.817954 fastboot data load
978 05:08:25.818394 fastboot data verify
979 05:08:25.822920 verify result: 266
980 05:08:25.828516 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 05:08:25.829031 LPDDR4 probe
982 05:08:25.829465 ddr clk to 1584MHz
983 05:08:25.836475 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 05:08:25.873777
985 05:08:25.874339 dmc_version 0001
986 05:08:25.880528 Check phy result
987 05:08:25.886415 INFO : End of CA training
988 05:08:25.886929 INFO : End of initialization
989 05:08:25.892020 INFO : Training has run successfully!
990 05:08:25.892714 Check phy result
991 05:08:25.897472 INFO : End of initialization
992 05:08:25.897977 INFO : End of read enable training
993 05:08:25.903022 INFO : End of fine write leveling
994 05:08:25.908632 INFO : End of Write leveling coarse delay
995 05:08:25.909121 INFO : Training has run successfully!
996 05:08:25.909566 Check phy result
997 05:08:25.914249 INFO : End of initialization
998 05:08:25.914731 INFO : End of read dq deskew training
999 05:08:25.919848 INFO : End of MPR read delay center optimization
1000 05:08:25.925483 INFO : End of write delay center optimization
1001 05:08:25.931117 INFO : End of read delay center optimization
1002 05:08:25.931602 INFO : End of max read latency training
1003 05:08:25.936661 INFO : Training has run successfully!
1004 05:08:25.937144 1D training succeed
1005 05:08:25.945940 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 05:08:25.993570 Check phy result
1007 05:08:25.994047 INFO : End of initialization
1008 05:08:26.016006 INFO : End of 2D read delay Voltage center optimization
1009 05:08:26.036281 INFO : End of 2D read delay Voltage center optimization
1010 05:08:26.088342 INFO : End of 2D write delay Voltage center optimization
1011 05:08:26.137660 INFO : End of 2D write delay Voltage center optimization
1012 05:08:26.143712 INFO : Training has run successfully!
1013 05:08:26.144243
1014 05:08:26.144695 channel==0
1015 05:08:26.148878 RxClkDly_Margin_A0==88 ps 9
1016 05:08:26.149361 TxDqDly_Margin_A0==98 ps 10
1017 05:08:26.152167 RxClkDly_Margin_A1==88 ps 9
1018 05:08:26.152644 TxDqDly_Margin_A1==98 ps 10
1019 05:08:26.157687 TrainedVREFDQ_A0==74
1020 05:08:26.158167 TrainedVREFDQ_A1==74
1021 05:08:26.163345 VrefDac_Margin_A0==25
1022 05:08:26.163822 DeviceVref_Margin_A0==40
1023 05:08:26.164295 VrefDac_Margin_A1==25
1024 05:08:26.168800 DeviceVref_Margin_A1==40
1025 05:08:26.169273
1026 05:08:26.169713
1027 05:08:26.170151 channel==1
1028 05:08:26.170583 RxClkDly_Margin_A0==88 ps 9
1029 05:08:26.174492 TxDqDly_Margin_A0==98 ps 10
1030 05:08:26.174971 RxClkDly_Margin_A1==98 ps 10
1031 05:08:26.180108 TxDqDly_Margin_A1==88 ps 9
1032 05:08:26.180606 TrainedVREFDQ_A0==77
1033 05:08:26.181046 TrainedVREFDQ_A1==77
1034 05:08:26.185622 VrefDac_Margin_A0==22
1035 05:08:26.186099 DeviceVref_Margin_A0==37
1036 05:08:26.191306 VrefDac_Margin_A1==24
1037 05:08:26.191779 DeviceVref_Margin_A1==37
1038 05:08:26.192251
1039 05:08:26.196989 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 05:08:26.197466
1041 05:08:26.224714 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 05:08:26.230301 2D training succeed
1043 05:08:26.235964 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 05:08:26.236491 auto size-- 65535DDR cs0 size: 2048MB
1045 05:08:26.241606 DDR cs1 size: 2048MB
1046 05:08:26.242082 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 05:08:26.247122 cs0 DataBus test pass
1048 05:08:26.247600 cs1 DataBus test pass
1049 05:08:26.248074 cs0 AddrBus test pass
1050 05:08:26.252886 cs1 AddrBus test pass
1051 05:08:26.253364
1052 05:08:26.253801 100bdlr_step_size ps== 420
1053 05:08:26.254241 result report
1054 05:08:26.258445 boot times 0Enable ddr reg access
1055 05:08:26.266055 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 05:08:26.279561 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 05:08:26.853283 0.0;M3 CHK:0;cm4_sp_mode 0
1058 05:08:26.853844 MVN_1=0x00000000
1059 05:08:26.858761 MVN_2=0x00000000
1060 05:08:26.864493 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 05:08:26.864998 OPS=0x10
1062 05:08:26.865466 ring efuse init
1063 05:08:26.865919 chipver efuse init
1064 05:08:26.870105 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 05:08:26.875712 [0.018961 Inits done]
1066 05:08:26.876260 secure task start!
1067 05:08:26.876728 high task start!
1068 05:08:26.880290 low task start!
1069 05:08:26.880789 run into bl31
1070 05:08:26.886965 NOTICE: BL31: v1.3(release):4fc40b1
1071 05:08:26.894767 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 05:08:26.895270 NOTICE: BL31: G12A normal boot!
1073 05:08:26.920120 NOTICE: BL31: BL33 decompress pass
1074 05:08:26.925867 ERROR: Error initializing runtime service opteed_fast
1075 05:08:28.158780
1076 05:08:28.159372
1077 05:08:28.167061 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 05:08:28.167573
1079 05:08:28.168085 Model: Libre Computer AML-A311D-CC Alta
1080 05:08:28.375440 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 05:08:28.398890 DRAM: 2 GiB (effective 3.8 GiB)
1082 05:08:28.541874 Core: 408 devices, 31 uclasses, devicetree: separate
1083 05:08:28.547736 WDT: Not starting watchdog@f0d0
1084 05:08:28.579949 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 05:08:28.592426 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 05:08:28.597392 ** Bad device specification mmc 0 **
1087 05:08:28.607772 Card did not respond to voltage select! : -110
1088 05:08:28.615398 ** Bad device specification mmc 0 **
1089 05:08:28.615909 Couldn't find partition mmc 0
1090 05:08:28.623762 Card did not respond to voltage select! : -110
1091 05:08:28.629251 ** Bad device specification mmc 0 **
1092 05:08:28.629758 Couldn't find partition mmc 0
1093 05:08:28.634327 Error: could not access storage.
1094 05:08:28.976825 Net: eth0: ethernet@ff3f0000
1095 05:08:28.977433 starting USB...
1096 05:08:29.228697 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 05:08:29.229237 Starting the controller
1098 05:08:29.235559 USB XHCI 1.10
1099 05:08:30.792734 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 05:08:30.801098 scanning usb for storage devices... 0 Storage Device(s) found
1102 05:08:30.852774 Hit any key to stop autoboot: 1
1103 05:08:30.853610 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 05:08:30.854245 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 05:08:30.854752 Setting prompt string to ['=>']
1106 05:08:30.855265 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 05:08:30.868444 0
1108 05:08:30.869359 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 05:08:30.869891 Sending with 10 millisecond of delay
1111 05:08:32.004570 => setenv autoload no
1112 05:08:32.015366 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 05:08:32.020715 setenv autoload no
1114 05:08:32.021520 Sending with 10 millisecond of delay
1116 05:08:33.818304 => setenv initrd_high 0xffffffff
1117 05:08:33.829089 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 05:08:33.829980 setenv initrd_high 0xffffffff
1119 05:08:33.830745 Sending with 10 millisecond of delay
1121 05:08:35.446973 => setenv fdt_high 0xffffffff
1122 05:08:35.457779 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 05:08:35.458643 setenv fdt_high 0xffffffff
1124 05:08:35.459404 Sending with 10 millisecond of delay
1126 05:08:35.751358 => dhcp
1127 05:08:35.762074 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 05:08:35.762926 dhcp
1129 05:08:35.763401 Speed: 1000, full duplex
1130 05:08:35.763854 BOOTP broadcast 1
1131 05:08:36.010320 BOOTP broadcast 2
1132 05:08:36.223581 DHCP client bound to address 192.168.6.33 (461 ms)
1133 05:08:36.224521 Sending with 10 millisecond of delay
1135 05:08:37.900979 => setenv serverip 192.168.6.2
1136 05:08:37.911773 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1137 05:08:37.912689 setenv serverip 192.168.6.2
1138 05:08:37.913442 Sending with 10 millisecond of delay
1140 05:08:41.636796 => tftpboot 0x01080000 796434/tftp-deploy-zclwk40v/kernel/uImage
1141 05:08:41.647659 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1142 05:08:41.648649 tftpboot 0x01080000 796434/tftp-deploy-zclwk40v/kernel/uImage
1143 05:08:41.649125 Speed: 1000, full duplex
1144 05:08:41.649566 Using ethernet@ff3f0000 device
1145 05:08:41.650482 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1146 05:08:41.655966 Filename '796434/tftp-deploy-zclwk40v/kernel/uImage'.
1147 05:08:41.659837 Load address: 0x1080000
1148 05:08:46.840059 Loading: *################################################## 43.9 MiB
1149 05:08:46.840710 8.5 MiB/s
1150 05:08:46.841157 done
1151 05:08:46.844295 Bytes transferred = 45998656 (2bde240 hex)
1152 05:08:46.845058 Sending with 10 millisecond of delay
1154 05:08:51.531209 => tftpboot 0x08000000 796434/tftp-deploy-zclwk40v/ramdisk/ramdisk.cpio.gz.uboot
1155 05:08:51.542001 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
1156 05:08:51.542854 tftpboot 0x08000000 796434/tftp-deploy-zclwk40v/ramdisk/ramdisk.cpio.gz.uboot
1157 05:08:51.543340 Speed: 1000, full duplex
1158 05:08:51.543795 Using ethernet@ff3f0000 device
1159 05:08:51.544846 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1160 05:08:51.556741 Filename '796434/tftp-deploy-zclwk40v/ramdisk/ramdisk.cpio.gz.uboot'.
1161 05:08:51.557237 Load address: 0x8000000
1162 05:08:53.564985 Loading: *################################################# UDP wrong checksum 00000005 0000bddb
1163 05:08:58.566839 T UDP wrong checksum 00000005 0000bddb
1164 05:09:08.568432 T T UDP wrong checksum 00000005 0000bddb
1165 05:09:10.840731 UDP wrong checksum 000000ff 00005ce2
1166 05:09:10.889673 UDP wrong checksum 000000ff 0000e3d4
1167 05:09:28.572789 T T T T UDP wrong checksum 00000005 0000bddb
1168 05:09:38.694841 T T UDP wrong checksum 000000ff 00008906
1169 05:09:38.706376 UDP wrong checksum 000000ff 00000bf9
1170 05:09:41.860564 UDP wrong checksum 000000ff 00006e32
1171 05:09:41.871047 UDP wrong checksum 000000ff 0000f224
1172 05:09:48.577924 T
1173 05:09:48.578603 Retry count exceeded; starting again
1175 05:09:48.580225 end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
1178 05:09:48.582233 end: 2.4 uboot-commands (duration 00:01:55) [common]
1180 05:09:48.583759 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1182 05:09:48.584976 end: 2 uboot-action (duration 00:01:55) [common]
1184 05:09:48.586692 Cleaning after the job
1185 05:09:48.587306 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/ramdisk
1186 05:09:48.588671 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/kernel
1187 05:09:48.620002 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/dtb
1188 05:09:48.620846 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/nfsrootfs
1189 05:09:48.771447 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796434/tftp-deploy-zclwk40v/modules
1190 05:09:48.792440 start: 4.1 power-off (timeout 00:00:30) [common]
1191 05:09:48.793080 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1192 05:09:48.827331 >> OK - accepted request
1193 05:09:48.829393 Returned 0 in 0 seconds
1194 05:09:48.930146 end: 4.1 power-off (duration 00:00:00) [common]
1196 05:09:48.931107 start: 4.2 read-feedback (timeout 00:10:00) [common]
1197 05:09:48.931760 Listened to connection for namespace 'common' for up to 1s
1198 05:09:49.932529 Finalising connection for namespace 'common'
1199 05:09:49.933046 Disconnecting from shell: Finalise
1200 05:09:49.933359 =>
1201 05:09:50.034125 end: 4.2 read-feedback (duration 00:00:01) [common]
1202 05:09:50.034886 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796434
1203 05:09:51.755879 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796434
1204 05:09:51.756525 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.