Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:08:11.760741 lava-dispatcher, installed at version: 2024.01
2 06:08:11.761796 start: 0 validate
3 06:08:11.762266 Start time: 2024-10-03 06:08:11.762235+00:00 (UTC)
4 06:08:11.762823 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:08:11.763344 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 06:08:11.803203 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:08:11.803734 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:08:11.833741 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:08:11.834362 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 06:08:11.866869 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:08:11.867390 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 06:08:11.903088 validate duration: 0.14
14 06:08:11.903949 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:08:11.904312 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:08:11.904631 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:08:11.905395 Not decompressing ramdisk as can be used compressed.
18 06:08:11.905877 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 06:08:11.906169 saving as /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/ramdisk/rootfs.cpio.gz
20 06:08:11.906451 total size: 47897469 (45 MB)
21 06:08:11.946832 progress 0 % (0 MB)
22 06:08:11.989408 progress 5 % (2 MB)
23 06:08:12.030179 progress 10 % (4 MB)
24 06:08:12.072623 progress 15 % (6 MB)
25 06:08:12.103922 progress 20 % (9 MB)
26 06:08:12.134771 progress 25 % (11 MB)
27 06:08:12.165611 progress 30 % (13 MB)
28 06:08:12.198222 progress 35 % (16 MB)
29 06:08:12.230026 progress 40 % (18 MB)
30 06:08:12.260455 progress 45 % (20 MB)
31 06:08:12.291616 progress 50 % (22 MB)
32 06:08:12.322156 progress 55 % (25 MB)
33 06:08:12.353995 progress 60 % (27 MB)
34 06:08:12.384752 progress 65 % (29 MB)
35 06:08:12.415581 progress 70 % (32 MB)
36 06:08:12.447396 progress 75 % (34 MB)
37 06:08:12.478062 progress 80 % (36 MB)
38 06:08:12.509279 progress 85 % (38 MB)
39 06:08:12.539768 progress 90 % (41 MB)
40 06:08:12.570360 progress 95 % (43 MB)
41 06:08:12.600577 progress 100 % (45 MB)
42 06:08:12.601310 45 MB downloaded in 0.69 s (65.74 MB/s)
43 06:08:12.601866 end: 1.1.1 http-download (duration 00:00:01) [common]
45 06:08:12.602754 end: 1.1 download-retry (duration 00:00:01) [common]
46 06:08:12.603045 start: 1.2 download-retry (timeout 00:09:59) [common]
47 06:08:12.603315 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 06:08:12.603799 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig/gcc-12/kernel/Image
49 06:08:12.604080 saving as /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/kernel/Image
50 06:08:12.604292 total size: 45713920 (43 MB)
51 06:08:12.604504 No compression specified
52 06:08:12.644568 progress 0 % (0 MB)
53 06:08:12.672993 progress 5 % (2 MB)
54 06:08:12.701090 progress 10 % (4 MB)
55 06:08:12.729084 progress 15 % (6 MB)
56 06:08:12.757539 progress 20 % (8 MB)
57 06:08:12.785143 progress 25 % (10 MB)
58 06:08:12.813253 progress 30 % (13 MB)
59 06:08:12.841207 progress 35 % (15 MB)
60 06:08:12.869493 progress 40 % (17 MB)
61 06:08:12.897253 progress 45 % (19 MB)
62 06:08:12.925162 progress 50 % (21 MB)
63 06:08:12.953251 progress 55 % (24 MB)
64 06:08:12.980989 progress 60 % (26 MB)
65 06:08:13.008311 progress 65 % (28 MB)
66 06:08:13.035894 progress 70 % (30 MB)
67 06:08:13.063811 progress 75 % (32 MB)
68 06:08:13.092377 progress 80 % (34 MB)
69 06:08:13.119600 progress 85 % (37 MB)
70 06:08:13.147838 progress 90 % (39 MB)
71 06:08:13.176263 progress 95 % (41 MB)
72 06:08:13.203966 progress 100 % (43 MB)
73 06:08:13.204524 43 MB downloaded in 0.60 s (72.63 MB/s)
74 06:08:13.205010 end: 1.2.1 http-download (duration 00:00:01) [common]
76 06:08:13.205824 end: 1.2 download-retry (duration 00:00:01) [common]
77 06:08:13.206102 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:08:13.206368 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:08:13.206820 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 06:08:13.207067 saving as /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 06:08:13.207275 total size: 53209 (0 MB)
82 06:08:13.207484 No compression specified
83 06:08:13.248204 progress 61 % (0 MB)
84 06:08:13.249035 progress 100 % (0 MB)
85 06:08:13.249569 0 MB downloaded in 0.04 s (1.20 MB/s)
86 06:08:13.250044 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:08:13.250865 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:08:13.251128 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:08:13.251394 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:08:13.251849 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig/gcc-12/modules.tar.xz
92 06:08:13.252128 saving as /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/modules/modules.tar
93 06:08:13.252336 total size: 11627692 (11 MB)
94 06:08:13.252547 Using unxz to decompress xz
95 06:08:13.290195 progress 0 % (0 MB)
96 06:08:13.360653 progress 5 % (0 MB)
97 06:08:13.441264 progress 10 % (1 MB)
98 06:08:13.530137 progress 15 % (1 MB)
99 06:08:13.607795 progress 20 % (2 MB)
100 06:08:13.693435 progress 25 % (2 MB)
101 06:08:13.775690 progress 30 % (3 MB)
102 06:08:13.859477 progress 35 % (3 MB)
103 06:08:13.935960 progress 40 % (4 MB)
104 06:08:14.015054 progress 45 % (5 MB)
105 06:08:14.094829 progress 50 % (5 MB)
106 06:08:14.173647 progress 55 % (6 MB)
107 06:08:14.255523 progress 60 % (6 MB)
108 06:08:14.343063 progress 65 % (7 MB)
109 06:08:14.427064 progress 70 % (7 MB)
110 06:08:14.527009 progress 75 % (8 MB)
111 06:08:14.618818 progress 80 % (8 MB)
112 06:08:14.701269 progress 85 % (9 MB)
113 06:08:14.779304 progress 90 % (10 MB)
114 06:08:14.856303 progress 95 % (10 MB)
115 06:08:14.931013 progress 100 % (11 MB)
116 06:08:14.948089 11 MB downloaded in 1.70 s (6.54 MB/s)
117 06:08:14.949068 end: 1.4.1 http-download (duration 00:00:02) [common]
119 06:08:14.950836 end: 1.4 download-retry (duration 00:00:02) [common]
120 06:08:14.951415 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 06:08:14.952012 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 06:08:14.952568 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:08:14.953137 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 06:08:14.954253 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w
125 06:08:14.955144 makedir: /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin
126 06:08:14.955829 makedir: /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/tests
127 06:08:14.956580 makedir: /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/results
128 06:08:14.957249 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-add-keys
129 06:08:14.958273 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-add-sources
130 06:08:14.959374 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-background-process-start
131 06:08:14.960485 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-background-process-stop
132 06:08:14.961577 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-common-functions
133 06:08:14.962627 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-echo-ipv4
134 06:08:14.963642 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-install-packages
135 06:08:14.964734 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-installed-packages
136 06:08:14.965747 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-os-build
137 06:08:14.966728 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-probe-channel
138 06:08:14.967760 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-probe-ip
139 06:08:14.968818 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-target-ip
140 06:08:14.969871 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-target-mac
141 06:08:14.970925 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-target-storage
142 06:08:14.971970 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-test-case
143 06:08:14.973050 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-test-event
144 06:08:14.974076 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-test-feedback
145 06:08:14.975074 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-test-raise
146 06:08:14.976185 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-test-reference
147 06:08:14.977232 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-test-runner
148 06:08:14.978281 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-test-set
149 06:08:14.979272 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-test-shell
150 06:08:14.980337 Updating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-install-packages (oe)
151 06:08:14.981504 Updating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/bin/lava-installed-packages (oe)
152 06:08:14.982478 Creating /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/environment
153 06:08:14.983270 LAVA metadata
154 06:08:14.983798 - LAVA_JOB_ID=796667
155 06:08:14.984320 - LAVA_DISPATCHER_IP=192.168.6.2
156 06:08:14.985049 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 06:08:14.987104 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 06:08:14.987762 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 06:08:14.988261 skipped lava-vland-overlay
160 06:08:14.988804 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 06:08:14.989362 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 06:08:14.989833 skipped lava-multinode-overlay
163 06:08:14.990365 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 06:08:14.990916 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 06:08:14.991442 Loading test definitions
166 06:08:14.992105 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 06:08:14.992583 Using /lava-796667 at stage 0
168 06:08:14.994777 uuid=796667_1.5.2.4.1 testdef=None
169 06:08:14.995343 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 06:08:14.995855 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 06:08:14.997752 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 06:08:14.998554 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 06:08:15.000768 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 06:08:15.001604 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 06:08:15.003739 runner path: /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/0/tests/0_igt-gpu-panfrost test_uuid 796667_1.5.2.4.1
178 06:08:15.004389 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 06:08:15.005201 Creating lava-test-runner.conf files
181 06:08:15.005409 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796667/lava-overlay-bta44w9w/lava-796667/0 for stage 0
182 06:08:15.005757 - 0_igt-gpu-panfrost
183 06:08:15.006106 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 06:08:15.006387 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 06:08:15.030026 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 06:08:15.030440 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 06:08:15.030706 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 06:08:15.030974 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 06:08:15.031236 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 06:08:22.426962 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 06:08:22.427423 start: 1.5.4 extract-modules (timeout 00:09:49) [common]
192 06:08:22.427673 extracting modules file /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796667/extract-overlay-ramdisk-jvf2_ubj/ramdisk
193 06:08:23.836203 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 06:08:23.836651 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 06:08:23.836932 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796667/compress-overlay-teak1_xe/overlay-1.5.2.5.tar.gz to ramdisk
196 06:08:23.837149 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796667/compress-overlay-teak1_xe/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796667/extract-overlay-ramdisk-jvf2_ubj/ramdisk
197 06:08:23.866988 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 06:08:23.867392 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 06:08:23.867666 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 06:08:23.867894 Converting downloaded kernel to a uImage
201 06:08:23.868239 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/kernel/Image /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/kernel/uImage
202 06:08:24.337315 output: Image Name:
203 06:08:24.337719 output: Created: Thu Oct 3 06:08:23 2024
204 06:08:24.337945 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 06:08:24.338158 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 06:08:24.338364 output: Load Address: 01080000
207 06:08:24.338566 output: Entry Point: 01080000
208 06:08:24.338770 output:
209 06:08:24.339138 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 06:08:24.339436 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 06:08:24.339727 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 06:08:24.340020 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 06:08:24.340303 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 06:08:24.340569 Building ramdisk /var/lib/lava/dispatcher/tmp/796667/extract-overlay-ramdisk-jvf2_ubj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796667/extract-overlay-ramdisk-jvf2_ubj/ramdisk
215 06:08:30.863240 >> 502520 blocks
216 06:08:51.813438 Adding RAMdisk u-boot header.
217 06:08:51.814315 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796667/extract-overlay-ramdisk-jvf2_ubj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796667/extract-overlay-ramdisk-jvf2_ubj/ramdisk.cpio.gz.uboot
218 06:08:52.490794 output: Image Name:
219 06:08:52.491197 output: Created: Thu Oct 3 06:08:51 2024
220 06:08:52.491403 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 06:08:52.491605 output: Data Size: 65724021 Bytes = 64183.61 KiB = 62.68 MiB
222 06:08:52.491805 output: Load Address: 00000000
223 06:08:52.492101 output: Entry Point: 00000000
224 06:08:52.492546 output:
225 06:08:52.493623 rename /var/lib/lava/dispatcher/tmp/796667/extract-overlay-ramdisk-jvf2_ubj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/ramdisk/ramdisk.cpio.gz.uboot
226 06:08:52.494395 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 06:08:52.494988 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 06:08:52.495563 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 06:08:52.496087 No LXC device requested
230 06:08:52.496645 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 06:08:52.497210 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 06:08:52.497747 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 06:08:52.498206 Checking files for TFTP limit of 4294967296 bytes.
234 06:08:52.501159 end: 1 tftp-deploy (duration 00:00:41) [common]
235 06:08:52.501795 start: 2 uboot-action (timeout 00:05:00) [common]
236 06:08:52.502363 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 06:08:52.502906 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 06:08:52.503452 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 06:08:52.504059 Using kernel file from prepare-kernel: 796667/tftp-deploy-c3l90zt3/kernel/uImage
240 06:08:52.504735 substitutions:
241 06:08:52.505188 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 06:08:52.505631 - {DTB_ADDR}: 0x01070000
243 06:08:52.506068 - {DTB}: 796667/tftp-deploy-c3l90zt3/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 06:08:52.506505 - {INITRD}: 796667/tftp-deploy-c3l90zt3/ramdisk/ramdisk.cpio.gz.uboot
245 06:08:52.506940 - {KERNEL_ADDR}: 0x01080000
246 06:08:52.507373 - {KERNEL}: 796667/tftp-deploy-c3l90zt3/kernel/uImage
247 06:08:52.507807 - {LAVA_MAC}: None
248 06:08:52.508318 - {PRESEED_CONFIG}: None
249 06:08:52.508762 - {PRESEED_LOCAL}: None
250 06:08:52.509196 - {RAMDISK_ADDR}: 0x08000000
251 06:08:52.509625 - {RAMDISK}: 796667/tftp-deploy-c3l90zt3/ramdisk/ramdisk.cpio.gz.uboot
252 06:08:52.510062 - {ROOT_PART}: None
253 06:08:52.510491 - {ROOT}: None
254 06:08:52.510923 - {SERVER_IP}: 192.168.6.2
255 06:08:52.511357 - {TEE_ADDR}: 0x83000000
256 06:08:52.511786 - {TEE}: None
257 06:08:52.512250 Parsed boot commands:
258 06:08:52.512671 - setenv autoload no
259 06:08:52.513098 - setenv initrd_high 0xffffffff
260 06:08:52.513523 - setenv fdt_high 0xffffffff
261 06:08:52.513949 - dhcp
262 06:08:52.514373 - setenv serverip 192.168.6.2
263 06:08:52.514798 - tftpboot 0x01080000 796667/tftp-deploy-c3l90zt3/kernel/uImage
264 06:08:52.515227 - tftpboot 0x08000000 796667/tftp-deploy-c3l90zt3/ramdisk/ramdisk.cpio.gz.uboot
265 06:08:52.515655 - tftpboot 0x01070000 796667/tftp-deploy-c3l90zt3/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 06:08:52.516108 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 06:08:52.516546 - bootm 0x01080000 0x08000000 0x01070000
268 06:08:52.517103 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 06:08:52.518733 start: 2.3 connect-device (timeout 00:05:00) [common]
271 06:08:52.519215 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 06:08:52.534415 Setting prompt string to ['lava-test: # ']
273 06:08:52.536074 end: 2.3 connect-device (duration 00:00:00) [common]
274 06:08:52.536724 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 06:08:52.537318 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 06:08:52.537879 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 06:08:52.539118 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 06:08:52.574458 >> OK - accepted request
279 06:08:52.576574 Returned 0 in 0 seconds
280 06:08:52.677729 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 06:08:52.679469 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 06:08:52.680126 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 06:08:52.680694 Setting prompt string to ['Hit any key to stop autoboot']
285 06:08:52.681199 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 06:08:52.682913 Trying 192.168.56.21...
287 06:08:52.683443 Connected to conserv1.
288 06:08:52.683915 Escape character is '^]'.
289 06:08:52.684422
290 06:08:52.684884 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 06:08:52.685346
292 06:08:59.800933 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 06:08:59.801362 bl2_stage_init 0x01
294 06:08:59.801599 bl2_stage_init 0x81
295 06:08:59.806500 hw id: 0x0000 - pwm id 0x01
296 06:08:59.806765 bl2_stage_init 0xc1
297 06:08:59.812074 bl2_stage_init 0x02
298 06:08:59.812319
299 06:08:59.812529 L0:00000000
300 06:08:59.812743 L1:00000703
301 06:08:59.812943 L2:00008067
302 06:08:59.813139 L3:15000000
303 06:08:59.813573 S1:00000000
304 06:08:59.818566 B2:20282000
305 06:08:59.818808 B1:a0f83180
306 06:08:59.819014
307 06:08:59.819216 TE: 69386
308 06:08:59.819418
309 06:08:59.824093 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 06:08:59.824338
311 06:08:59.829763 Board ID = 1
312 06:08:59.830021 Set cpu clk to 24M
313 06:08:59.830229 Set clk81 to 24M
314 06:08:59.830427 Use GP1_pll as DSU clk.
315 06:08:59.833266 DSU clk: 1200 Mhz
316 06:08:59.833508 CPU clk: 1200 MHz
317 06:08:59.838775 Set clk81 to 166.6M
318 06:08:59.844268 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 06:08:59.844539 board id: 1
320 06:08:59.852890 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 06:08:59.863357 fw parse done
322 06:08:59.869333 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 06:08:59.912130 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 06:08:59.923000 PIEI prepare done
325 06:08:59.923253 fastboot data load
326 06:08:59.923461 fastboot data verify
327 06:08:59.928506 verify result: 266
328 06:08:59.934084 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 06:08:59.934335 LPDDR4 probe
330 06:08:59.934536 ddr clk to 1584MHz
331 06:08:59.942089 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 06:08:59.979454
333 06:08:59.979724 dmc_version 0001
334 06:08:59.986179 Check phy result
335 06:08:59.992064 INFO : End of CA training
336 06:08:59.992309 INFO : End of initialization
337 06:08:59.997653 INFO : Training has run successfully!
338 06:08:59.997915 Check phy result
339 06:09:00.003208 INFO : End of initialization
340 06:09:00.003459 INFO : End of read enable training
341 06:09:00.006480 INFO : End of fine write leveling
342 06:09:00.012070 INFO : End of Write leveling coarse delay
343 06:09:00.017686 INFO : Training has run successfully!
344 06:09:00.017921 Check phy result
345 06:09:00.018127 INFO : End of initialization
346 06:09:00.023263 INFO : End of read dq deskew training
347 06:09:00.028940 INFO : End of MPR read delay center optimization
348 06:09:00.029193 INFO : End of write delay center optimization
349 06:09:00.034471 INFO : End of read delay center optimization
350 06:09:00.040172 INFO : End of max read latency training
351 06:09:00.040444 INFO : Training has run successfully!
352 06:09:00.045650 1D training succeed
353 06:09:00.051684 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 06:09:00.099290 Check phy result
355 06:09:00.099618 INFO : End of initialization
356 06:09:00.121831 INFO : End of 2D read delay Voltage center optimization
357 06:09:00.140808 INFO : End of 2D read delay Voltage center optimization
358 06:09:00.477173 INFO : End of 2D write delay Voltage center optimization
359 06:09:00.477578 INFO : End of 2D write delay Voltage center optimization
360 06:09:00.477792 INFO : Training has run successfully!
361 06:09:00.477997
362 06:09:00.478197 channel==0
363 06:09:00.478394 RxClkDly_Margin_A0==78 ps 8
364 06:09:00.478591 TxDqDly_Margin_A0==98 ps 10
365 06:09:00.478789 RxClkDly_Margin_A1==88 ps 9
366 06:09:00.478985 TxDqDly_Margin_A1==88 ps 9
367 06:09:00.479182 TrainedVREFDQ_A0==74
368 06:09:00.479377 TrainedVREFDQ_A1==74
369 06:09:00.479575 VrefDac_Margin_A0==23
370 06:09:00.479769 DeviceVref_Margin_A0==40
371 06:09:00.479967 VrefDac_Margin_A1==23
372 06:09:00.480212 DeviceVref_Margin_A1==40
373 06:09:00.480417
374 06:09:00.480616
375 06:09:00.480812 channel==1
376 06:09:00.481006 RxClkDly_Margin_A0==88 ps 9
377 06:09:00.481202 TxDqDly_Margin_A0==98 ps 10
378 06:09:00.481400 RxClkDly_Margin_A1==78 ps 8
379 06:09:00.481595 TxDqDly_Margin_A1==88 ps 9
380 06:09:00.481792 TrainedVREFDQ_A0==78
381 06:09:00.481986 TrainedVREFDQ_A1==77
382 06:09:00.482179 VrefDac_Margin_A0==22
383 06:09:00.482373 DeviceVref_Margin_A0==36
384 06:09:00.482563 VrefDac_Margin_A1==22
385 06:09:00.482754 DeviceVref_Margin_A1==37
386 06:09:00.482944
387 06:09:00.483136 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 06:09:00.483327
389 06:09:00.483519 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 06:09:00.483758 2D training succeed
391 06:09:00.483959 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 06:09:00.484461 auto size-- 65535DDR cs0 size: 2048MB
393 06:09:00.484696 DDR cs1 size: 2048MB
394 06:09:00.484896 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 06:09:00.485095 cs0 DataBus test pass
396 06:09:00.485289 cs1 DataBus test pass
397 06:09:00.485481 cs0 AddrBus test pass
398 06:09:00.485672 cs1 AddrBus test pass
399 06:09:00.485863
400 06:09:00.486056 100bdlr_step_size ps== 471
401 06:09:00.486252 result report
402 06:09:00.486443 boot times 0Enable ddr reg access
403 06:09:00.486635 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 06:09:00.486828 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 06:09:01.038744 bl2z: ptr: 05129330, size: 00001e40
406 06:09:01.045935 0.0;M3 CHK:0;cm4_sp_mode 0
407 06:09:01.046228 MVN_1=0x00000000
408 06:09:01.046437 MVN_2=0x00000000
409 06:09:01.057505 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 06:09:01.057886 OPS=0x04
411 06:09:01.058201 ring efuse init
412 06:09:01.060420 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 06:09:01.065869 [0.017319 Inits done]
414 06:09:01.066249 secure task start!
415 06:09:01.066482 high task start!
416 06:09:01.066683 low task start!
417 06:09:01.070256 run into bl31
418 06:09:01.078778 NOTICE: BL31: v1.3(release):4fc40b1
419 06:09:01.086585 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 06:09:01.086952 NOTICE: BL31: G12A normal boot!
421 06:09:01.102369 NOTICE: BL31: BL33 decompress pass
422 06:09:01.107918 ERROR: Error initializing runtime service opteed_fast
423 06:09:03.854049 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 06:09:03.854707 bl2_stage_init 0x01
425 06:09:03.855187 bl2_stage_init 0x81
426 06:09:03.859627 hw id: 0x0000 - pwm id 0x01
427 06:09:03.860184 bl2_stage_init 0xc1
428 06:09:03.863678 bl2_stage_init 0x02
429 06:09:03.864251
430 06:09:03.864697 L0:00000000
431 06:09:03.865126 L1:00000703
432 06:09:03.869160 L2:00008067
433 06:09:03.869625 L3:15000000
434 06:09:03.870057 S1:00000000
435 06:09:03.870485 B2:20282000
436 06:09:03.870909 B1:a0f83180
437 06:09:03.871329
438 06:09:03.874735 TE: 71168
439 06:09:03.875191
440 06:09:03.880436 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 06:09:03.880898
442 06:09:03.881327 Board ID = 1
443 06:09:03.881745 Set cpu clk to 24M
444 06:09:03.885918 Set clk81 to 24M
445 06:09:03.886362 Use GP1_pll as DSU clk.
446 06:09:03.886788 DSU clk: 1200 Mhz
447 06:09:03.891428 CPU clk: 1200 MHz
448 06:09:03.891893 Set clk81 to 166.6M
449 06:09:03.897073 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 06:09:03.897539 board id: 1
451 06:09:03.906093 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 06:09:03.916702 fw parse done
453 06:09:03.922588 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 06:09:03.964386 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 06:09:03.976243 PIEI prepare done
456 06:09:03.976694 fastboot data load
457 06:09:03.977121 fastboot data verify
458 06:09:03.981733 verify result: 266
459 06:09:03.987344 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 06:09:03.987795 LPDDR4 probe
461 06:09:03.988273 ddr clk to 1584MHz
462 06:09:03.995331 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 06:09:04.032583
464 06:09:04.033056 dmc_version 0001
465 06:09:04.039301 Check phy result
466 06:09:04.045242 INFO : End of CA training
467 06:09:04.045698 INFO : End of initialization
468 06:09:04.050769 INFO : Training has run successfully!
469 06:09:04.051228 Check phy result
470 06:09:04.056500 INFO : End of initialization
471 06:09:04.056975 INFO : End of read enable training
472 06:09:04.062006 INFO : End of fine write leveling
473 06:09:04.067587 INFO : End of Write leveling coarse delay
474 06:09:04.068082 INFO : Training has run successfully!
475 06:09:04.068532 Check phy result
476 06:09:04.073248 INFO : End of initialization
477 06:09:04.073713 INFO : End of read dq deskew training
478 06:09:04.078809 INFO : End of MPR read delay center optimization
479 06:09:04.084514 INFO : End of write delay center optimization
480 06:09:04.090031 INFO : End of read delay center optimization
481 06:09:04.090505 INFO : End of max read latency training
482 06:09:04.095672 INFO : Training has run successfully!
483 06:09:04.096191 1D training succeed
484 06:09:04.104863 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 06:09:04.152379 Check phy result
486 06:09:04.152870 INFO : End of initialization
487 06:09:04.174771 INFO : End of 2D read delay Voltage center optimization
488 06:09:04.193892 INFO : End of 2D read delay Voltage center optimization
489 06:09:04.245735 INFO : End of 2D write delay Voltage center optimization
490 06:09:04.294875 INFO : End of 2D write delay Voltage center optimization
491 06:09:04.300580 INFO : Training has run successfully!
492 06:09:04.301044
493 06:09:04.301487 channel==0
494 06:09:04.306117 RxClkDly_Margin_A0==78 ps 8
495 06:09:04.306576 TxDqDly_Margin_A0==98 ps 10
496 06:09:04.311747 RxClkDly_Margin_A1==88 ps 9
497 06:09:04.312274 TxDqDly_Margin_A1==98 ps 10
498 06:09:04.312719 TrainedVREFDQ_A0==74
499 06:09:04.317371 TrainedVREFDQ_A1==75
500 06:09:04.317845 VrefDac_Margin_A0==22
501 06:09:04.318286 DeviceVref_Margin_A0==40
502 06:09:04.322948 VrefDac_Margin_A1==23
503 06:09:04.323412 DeviceVref_Margin_A1==39
504 06:09:04.323854
505 06:09:04.324329
506 06:09:04.328603 channel==1
507 06:09:04.329063 RxClkDly_Margin_A0==88 ps 9
508 06:09:04.329502 TxDqDly_Margin_A0==98 ps 10
509 06:09:04.334102 RxClkDly_Margin_A1==78 ps 8
510 06:09:04.334566 TxDqDly_Margin_A1==88 ps 9
511 06:09:04.339768 TrainedVREFDQ_A0==78
512 06:09:04.340259 TrainedVREFDQ_A1==78
513 06:09:04.340699 VrefDac_Margin_A0==22
514 06:09:04.345343 DeviceVref_Margin_A0==36
515 06:09:04.345800 VrefDac_Margin_A1==22
516 06:09:04.350871 DeviceVref_Margin_A1==36
517 06:09:04.351333
518 06:09:04.351776 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 06:09:04.352247
520 06:09:04.384477 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 06:09:04.385012 2D training succeed
522 06:09:04.389997 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 06:09:04.395615 auto size-- 65535DDR cs0 size: 2048MB
524 06:09:04.396106 DDR cs1 size: 2048MB
525 06:09:04.401241 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 06:09:04.401719 cs0 DataBus test pass
527 06:09:04.406800 cs1 DataBus test pass
528 06:09:04.407261 cs0 AddrBus test pass
529 06:09:04.407702 cs1 AddrBus test pass
530 06:09:04.408165
531 06:09:04.412490 100bdlr_step_size ps== 478
532 06:09:04.412963 result report
533 06:09:04.417998 boot times 0Enable ddr reg access
534 06:09:04.423307 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 06:09:04.437097 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 06:09:05.091612 bl2z: ptr: 05129330, size: 00001e40
537 06:09:05.098159 0.0;M3 CHK:0;cm4_sp_mode 0
538 06:09:05.098649 MVN_1=0x00000000
539 06:09:05.099090 MVN_2=0x00000000
540 06:09:05.109660 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 06:09:05.110139 OPS=0x04
542 06:09:05.110588 ring efuse init
543 06:09:05.115325 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 06:09:05.115804 [0.017310 Inits done]
545 06:09:05.116288 secure task start!
546 06:09:05.122840 high task start!
547 06:09:05.123306 low task start!
548 06:09:05.123746 run into bl31
549 06:09:05.131435 NOTICE: BL31: v1.3(release):4fc40b1
550 06:09:05.139236 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 06:09:05.139711 NOTICE: BL31: G12A normal boot!
552 06:09:05.154724 NOTICE: BL31: BL33 decompress pass
553 06:09:05.160107 ERROR: Error initializing runtime service opteed_fast
554 06:09:06.551235 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 06:09:06.551902 bl2_stage_init 0x01
556 06:09:06.552427 bl2_stage_init 0x81
557 06:09:06.556846 hw id: 0x0000 - pwm id 0x01
558 06:09:06.557362 bl2_stage_init 0xc1
559 06:09:06.561879 bl2_stage_init 0x02
560 06:09:06.562379
561 06:09:06.562831 L0:00000000
562 06:09:06.563271 L1:00000703
563 06:09:06.563704 L2:00008067
564 06:09:06.567404 L3:15000000
565 06:09:06.567912 S1:00000000
566 06:09:06.568395 B2:20282000
567 06:09:06.568830 B1:a0f83180
568 06:09:06.569262
569 06:09:06.569695 TE: 69550
570 06:09:06.570136
571 06:09:06.578540 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 06:09:06.579074
573 06:09:06.579521 Board ID = 1
574 06:09:06.579961 Set cpu clk to 24M
575 06:09:06.580437 Set clk81 to 24M
576 06:09:06.584194 Use GP1_pll as DSU clk.
577 06:09:06.584695 DSU clk: 1200 Mhz
578 06:09:06.585140 CPU clk: 1200 MHz
579 06:09:06.589757 Set clk81 to 166.6M
580 06:09:06.595361 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 06:09:06.595960 board id: 1
582 06:09:06.603149 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 06:09:06.613804 fw parse done
584 06:09:06.619869 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 06:09:06.662413 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 06:09:06.673319 PIEI prepare done
587 06:09:06.673845 fastboot data load
588 06:09:06.674304 fastboot data verify
589 06:09:06.678896 verify result: 266
590 06:09:06.684533 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 06:09:06.685047 LPDDR4 probe
592 06:09:06.685494 ddr clk to 1584MHz
593 06:09:06.692499 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 06:09:06.728841
595 06:09:06.729453 dmc_version 0001
596 06:09:06.736418 Check phy result
597 06:09:06.742325 INFO : End of CA training
598 06:09:06.742905 INFO : End of initialization
599 06:09:06.747942 INFO : Training has run successfully!
600 06:09:06.748484 Check phy result
601 06:09:06.753583 INFO : End of initialization
602 06:09:06.754264 INFO : End of read enable training
603 06:09:06.756860 INFO : End of fine write leveling
604 06:09:06.762419 INFO : End of Write leveling coarse delay
605 06:09:06.768029 INFO : Training has run successfully!
606 06:09:06.768564 Check phy result
607 06:09:06.769021 INFO : End of initialization
608 06:09:06.773605 INFO : End of read dq deskew training
609 06:09:06.779143 INFO : End of MPR read delay center optimization
610 06:09:06.779647 INFO : End of write delay center optimization
611 06:09:06.784916 INFO : End of read delay center optimization
612 06:09:06.790416 INFO : End of max read latency training
613 06:09:06.790942 INFO : Training has run successfully!
614 06:09:06.796031 1D training succeed
615 06:09:06.801993 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 06:09:06.849506 Check phy result
617 06:09:06.850084 INFO : End of initialization
618 06:09:06.871932 INFO : End of 2D read delay Voltage center optimization
619 06:09:06.891079 INFO : End of 2D read delay Voltage center optimization
620 06:09:06.942988 INFO : End of 2D write delay Voltage center optimization
621 06:09:06.992203 INFO : End of 2D write delay Voltage center optimization
622 06:09:06.997722 INFO : Training has run successfully!
623 06:09:06.998241
624 06:09:06.999747 channel==0
625 06:09:07.003301 RxClkDly_Margin_A0==88 ps 9
626 06:09:07.003814 TxDqDly_Margin_A0==98 ps 10
627 06:09:07.006637 RxClkDly_Margin_A1==88 ps 9
628 06:09:07.007136 TxDqDly_Margin_A1==88 ps 9
629 06:09:07.012145 TrainedVREFDQ_A0==74
630 06:09:07.012653 TrainedVREFDQ_A1==74
631 06:09:07.013110 VrefDac_Margin_A0==23
632 06:09:07.017869 DeviceVref_Margin_A0==40
633 06:09:07.018386 VrefDac_Margin_A1==23
634 06:09:07.023331 DeviceVref_Margin_A1==40
635 06:09:07.023832
636 06:09:07.024319
637 06:09:07.025993 channel==1
638 06:09:07.026444 RxClkDly_Margin_A0==78 ps 8
639 06:09:07.028912 TxDqDly_Margin_A0==98 ps 10
640 06:09:07.029424 RxClkDly_Margin_A1==78 ps 8
641 06:09:07.034531 TxDqDly_Margin_A1==88 ps 9
642 06:09:07.035062 TrainedVREFDQ_A0==78
643 06:09:07.035818 TrainedVREFDQ_A1==75
644 06:09:07.040455 VrefDac_Margin_A0==23
645 06:09:07.040976 DeviceVref_Margin_A0==36
646 06:09:07.045858 VrefDac_Margin_A1==22
647 06:09:07.046359 DeviceVref_Margin_A1==39
648 06:09:07.046807
649 06:09:07.051329 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 06:09:07.051847
651 06:09:07.079310 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000019 00000017 00000019 00000015 00000018 00000014 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 06:09:07.084927 2D training succeed
653 06:09:07.090622 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 06:09:07.091158 auto size-- 65535DDR cs0 size: 2048MB
655 06:09:07.096131 DDR cs1 size: 2048MB
656 06:09:07.096652 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 06:09:07.101733 cs0 DataBus test pass
658 06:09:07.102238 cs1 DataBus test pass
659 06:09:07.103098 cs0 AddrBus test pass
660 06:09:07.107370 cs1 AddrBus test pass
661 06:09:07.107881
662 06:09:07.108394 100bdlr_step_size ps== 464
663 06:09:07.108859 result report
664 06:09:07.112912 boot times 0Enable ddr reg access
665 06:09:07.120492 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 06:09:07.134280 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 06:09:07.789225 bl2z: ptr: 05129330, size: 00001e40
668 06:09:07.797356 0.0;M3 CHK:0;cm4_sp_mode 0
669 06:09:07.797866 MVN_1=0x00000000
670 06:09:07.798320 MVN_2=0x00000000
671 06:09:07.808827 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 06:09:07.809341 OPS=0x04
673 06:09:07.809795 ring efuse init
674 06:09:07.812077 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 06:09:07.816794 [0.017320 Inits done]
676 06:09:07.817323 secure task start!
677 06:09:07.817778 high task start!
678 06:09:07.822028 low task start!
679 06:09:07.822507 run into bl31
680 06:09:07.830593 NOTICE: BL31: v1.3(release):4fc40b1
681 06:09:07.838376 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 06:09:07.838863 NOTICE: BL31: G12A normal boot!
683 06:09:07.853800 NOTICE: BL31: BL33 decompress pass
684 06:09:07.859487 ERROR: Error initializing runtime service opteed_fast
685 06:09:08.653718
686 06:09:08.654323
687 06:09:08.659081 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 06:09:08.659567
689 06:09:08.662530 Model: Libre Computer AML-S905D3-CC Solitude
690 06:09:08.809459 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 06:09:08.824805 DRAM: 2 GiB (effective 3.8 GiB)
692 06:09:08.925771 Core: 406 devices, 33 uclasses, devicetree: separate
693 06:09:08.931653 WDT: Not starting watchdog@f0d0
694 06:09:08.956690 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 06:09:08.968926 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 06:09:08.973934 ** Bad device specification mmc 0 **
697 06:09:08.983933 Card did not respond to voltage select! : -110
698 06:09:08.991594 ** Bad device specification mmc 0 **
699 06:09:08.992089 Couldn't find partition mmc 0
700 06:09:08.999938 Card did not respond to voltage select! : -110
701 06:09:09.005466 ** Bad device specification mmc 0 **
702 06:09:09.005922 Couldn't find partition mmc 0
703 06:09:09.010484 Error: could not access storage.
704 06:09:09.307001 Net: eth0: ethernet@ff3f0000
705 06:09:09.307618 starting USB...
706 06:09:09.551785 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 06:09:09.552399 Starting the controller
708 06:09:09.558727 USB XHCI 1.10
709 06:09:11.112576 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 06:09:11.120887 scanning usb for storage devices... 0 Storage Device(s) found
712 06:09:11.172385 Hit any key to stop autoboot: 1
713 06:09:11.173201 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
714 06:09:11.173830 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 06:09:11.174344 Setting prompt string to ['=>']
716 06:09:11.174867 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 06:09:11.186903 0
718 06:09:11.187795 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 06:09:11.289167 => setenv autoload no
721 06:09:11.289849 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 06:09:11.295019 setenv autoload no
724 06:09:11.396553 => setenv initrd_high 0xffffffff
725 06:09:11.397179 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 06:09:11.401818 setenv initrd_high 0xffffffff
728 06:09:11.503263 => setenv fdt_high 0xffffffff
729 06:09:11.503888 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 06:09:11.508752 setenv fdt_high 0xffffffff
732 06:09:11.610229 => dhcp
733 06:09:11.610854 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 06:09:11.615304 dhcp
735 06:09:12.220684 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 06:09:12.221195 Speed: 1000, full duplex
737 06:09:12.221647 BOOTP broadcast 1
738 06:09:12.468923 BOOTP broadcast 2
739 06:09:12.969999 BOOTP broadcast 3
740 06:09:13.970938 BOOTP broadcast 4
741 06:09:15.972164 BOOTP broadcast 5
742 06:09:15.983424 DHCP client bound to address 192.168.6.12 (3762 ms)
744 06:09:16.084919 => setenv serverip 192.168.6.2
745 06:09:16.085562 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
746 06:09:16.090102 setenv serverip 192.168.6.2
748 06:09:16.191615 => tftpboot 0x01080000 796667/tftp-deploy-c3l90zt3/kernel/uImage
749 06:09:16.192268 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
750 06:09:16.198985 tftpboot 0x01080000 796667/tftp-deploy-c3l90zt3/kernel/uImage
751 06:09:16.199466 Speed: 1000, full duplex
752 06:09:16.199915 Using ethernet@ff3f0000 device
753 06:09:16.204491 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 06:09:16.210003 Filename '796667/tftp-deploy-c3l90zt3/kernel/uImage'.
755 06:09:16.213798 Load address: 0x1080000
756 06:09:20.016424 Loading: *################################################## 43.6 MiB
757 06:09:20.017064 11.5 MiB/s
758 06:09:20.017543 done
759 06:09:20.020803 Bytes transferred = 45713984 (2b98a40 hex)
761 06:09:20.122436 => tftpboot 0x08000000 796667/tftp-deploy-c3l90zt3/ramdisk/ramdisk.cpio.gz.uboot
762 06:09:20.123130 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
763 06:09:20.130028 tftpboot 0x08000000 796667/tftp-deploy-c3l90zt3/ramdisk/ramdisk.cpio.gz.uboot
764 06:09:20.130526 Speed: 1000, full duplex
765 06:09:20.130959 Using ethernet@ff3f0000 device
766 06:09:20.135460 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
767 06:09:20.145306 Filename '796667/tftp-deploy-c3l90zt3/ramdisk/ramdisk.cpio.gz.uboot'.
768 06:09:20.145832 Load address: 0x8000000
769 06:09:31.952482 Loading: *###########T ###################################### UDP wrong checksum 0000000f 00004b70
770 06:09:36.952874 T UDP wrong checksum 0000000f 00004b70
771 06:09:46.955095 T T UDP wrong checksum 0000000f 00004b70
772 06:09:58.418921 T T UDP wrong checksum 000000ff 0000cf51
773 06:09:58.433630 UDP wrong checksum 000000ff 00006244
774 06:10:06.960126 T T UDP wrong checksum 0000000f 00004b70
775 06:10:12.905034 T UDP wrong checksum 000000ff 00000422
776 06:10:12.935518 UDP wrong checksum 000000ff 00009c14
777 06:10:16.744222 UDP wrong checksum 000000ff 00007fe3
778 06:10:16.776008 UDP wrong checksum 000000ff 000019d6
779 06:10:21.962639 T
780 06:10:21.963043 Retry count exceeded; starting again
782 06:10:21.964068 end: 2.4.3 bootloader-commands (duration 00:01:11) [common]
785 06:10:21.965305 end: 2.4 uboot-commands (duration 00:01:29) [common]
787 06:10:21.966017 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
789 06:10:21.966575 end: 2 uboot-action (duration 00:01:29) [common]
791 06:10:21.967388 Cleaning after the job
792 06:10:21.967705 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/ramdisk
793 06:10:21.968879 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/kernel
794 06:10:21.973037 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/dtb
795 06:10:21.973924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796667/tftp-deploy-c3l90zt3/modules
796 06:10:21.977357 start: 4.1 power-off (timeout 00:00:30) [common]
797 06:10:21.978052 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
798 06:10:22.011292 >> OK - accepted request
799 06:10:22.013985 Returned 0 in 0 seconds
800 06:10:22.115190 end: 4.1 power-off (duration 00:00:00) [common]
802 06:10:22.117008 start: 4.2 read-feedback (timeout 00:10:00) [common]
803 06:10:22.118200 Listened to connection for namespace 'common' for up to 1s
804 06:10:23.118935 Finalising connection for namespace 'common'
805 06:10:23.119631 Disconnecting from shell: Finalise
806 06:10:23.120256 =>
807 06:10:23.221269 end: 4.2 read-feedback (duration 00:00:01) [common]
808 06:10:23.221937 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796667
809 06:10:24.185667 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796667
810 06:10:24.186295 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.