Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:09:32.478256 lava-dispatcher, installed at version: 2024.01
2 06:09:32.479051 start: 0 validate
3 06:09:32.479539 Start time: 2024-10-03 06:09:32.479509+00:00 (UTC)
4 06:09:32.480113 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:09:32.480694 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 06:09:32.520306 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:09:32.520887 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:09:32.551144 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:09:32.551804 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:09:32.580681 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:09:32.581215 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:09:32.613459 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 06:09:32.614022 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 06:09:32.650816 validate duration: 0.17
16 06:09:32.651656 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:09:32.651969 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:09:32.652301 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:09:32.652887 Not decompressing ramdisk as can be used compressed.
20 06:09:32.653335 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 06:09:32.653608 saving as /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/ramdisk/initrd.cpio.gz
22 06:09:32.653867 total size: 5628169 (5 MB)
23 06:09:32.696823 progress 0 % (0 MB)
24 06:09:32.706589 progress 5 % (0 MB)
25 06:09:32.716583 progress 10 % (0 MB)
26 06:09:32.721209 progress 15 % (0 MB)
27 06:09:32.726283 progress 20 % (1 MB)
28 06:09:32.730833 progress 25 % (1 MB)
29 06:09:32.735910 progress 30 % (1 MB)
30 06:09:32.741103 progress 35 % (1 MB)
31 06:09:32.745591 progress 40 % (2 MB)
32 06:09:32.750615 progress 45 % (2 MB)
33 06:09:32.755152 progress 50 % (2 MB)
34 06:09:32.760186 progress 55 % (2 MB)
35 06:09:32.765316 progress 60 % (3 MB)
36 06:09:32.769907 progress 65 % (3 MB)
37 06:09:32.774945 progress 70 % (3 MB)
38 06:09:32.779368 progress 75 % (4 MB)
39 06:09:32.784359 progress 80 % (4 MB)
40 06:09:32.788783 progress 85 % (4 MB)
41 06:09:32.793662 progress 90 % (4 MB)
42 06:09:32.798132 progress 95 % (5 MB)
43 06:09:32.802209 progress 100 % (5 MB)
44 06:09:32.803062 5 MB downloaded in 0.15 s (35.98 MB/s)
45 06:09:32.803726 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:09:32.804858 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:09:32.805219 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:09:32.805550 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:09:32.806137 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig/gcc-12/kernel/Image
51 06:09:32.806460 saving as /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/kernel/Image
52 06:09:32.806720 total size: 45713920 (43 MB)
53 06:09:32.806980 No compression specified
54 06:09:32.841969 progress 0 % (0 MB)
55 06:09:32.878144 progress 5 % (2 MB)
56 06:09:32.912993 progress 10 % (4 MB)
57 06:09:32.947565 progress 15 % (6 MB)
58 06:09:32.981968 progress 20 % (8 MB)
59 06:09:33.016706 progress 25 % (10 MB)
60 06:09:33.053239 progress 30 % (13 MB)
61 06:09:33.088633 progress 35 % (15 MB)
62 06:09:33.123366 progress 40 % (17 MB)
63 06:09:33.157446 progress 45 % (19 MB)
64 06:09:33.192389 progress 50 % (21 MB)
65 06:09:33.226939 progress 55 % (24 MB)
66 06:09:33.261095 progress 60 % (26 MB)
67 06:09:33.295039 progress 65 % (28 MB)
68 06:09:33.329219 progress 70 % (30 MB)
69 06:09:33.363156 progress 75 % (32 MB)
70 06:09:33.397246 progress 80 % (34 MB)
71 06:09:33.429979 progress 85 % (37 MB)
72 06:09:33.458741 progress 90 % (39 MB)
73 06:09:33.487319 progress 95 % (41 MB)
74 06:09:33.515464 progress 100 % (43 MB)
75 06:09:33.516081 43 MB downloaded in 0.71 s (61.46 MB/s)
76 06:09:33.516571 end: 1.2.1 http-download (duration 00:00:01) [common]
78 06:09:33.517390 end: 1.2 download-retry (duration 00:00:01) [common]
79 06:09:33.517665 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:09:33.517930 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:09:33.518414 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 06:09:33.518661 saving as /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/dtb/meson-g12b-a311d-libretech-cc.dtb
83 06:09:33.518869 total size: 54703 (0 MB)
84 06:09:33.519079 No compression specified
85 06:09:33.563290 progress 59 % (0 MB)
86 06:09:33.564420 progress 100 % (0 MB)
87 06:09:33.565162 0 MB downloaded in 0.05 s (1.13 MB/s)
88 06:09:33.565764 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:09:33.566799 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:09:33.567148 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:09:33.567485 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:09:33.568096 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 06:09:33.568440 saving as /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/nfsrootfs/full.rootfs.tar
95 06:09:33.568709 total size: 120894716 (115 MB)
96 06:09:33.568987 Using unxz to decompress xz
97 06:09:33.608443 progress 0 % (0 MB)
98 06:09:34.424794 progress 5 % (5 MB)
99 06:09:35.278812 progress 10 % (11 MB)
100 06:09:36.079421 progress 15 % (17 MB)
101 06:09:36.828505 progress 20 % (23 MB)
102 06:09:37.439915 progress 25 % (28 MB)
103 06:09:38.364146 progress 30 % (34 MB)
104 06:09:39.166082 progress 35 % (40 MB)
105 06:09:39.531813 progress 40 % (46 MB)
106 06:09:39.917852 progress 45 % (51 MB)
107 06:09:40.645517 progress 50 % (57 MB)
108 06:09:41.538256 progress 55 % (63 MB)
109 06:09:42.327164 progress 60 % (69 MB)
110 06:09:43.092035 progress 65 % (74 MB)
111 06:09:43.877417 progress 70 % (80 MB)
112 06:09:44.712993 progress 75 % (86 MB)
113 06:09:45.517931 progress 80 % (92 MB)
114 06:09:46.290889 progress 85 % (98 MB)
115 06:09:47.201377 progress 90 % (103 MB)
116 06:09:48.026191 progress 95 % (109 MB)
117 06:09:48.910016 progress 100 % (115 MB)
118 06:09:48.923102 115 MB downloaded in 15.35 s (7.51 MB/s)
119 06:09:48.923718 end: 1.4.1 http-download (duration 00:00:15) [common]
121 06:09:48.925290 end: 1.4 download-retry (duration 00:00:15) [common]
122 06:09:48.925862 start: 1.5 download-retry (timeout 00:09:44) [common]
123 06:09:48.926419 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 06:09:48.927309 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig/gcc-12/modules.tar.xz
125 06:09:48.927807 saving as /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/modules/modules.tar
126 06:09:48.928291 total size: 11627692 (11 MB)
127 06:09:48.928750 Using unxz to decompress xz
128 06:09:48.972185 progress 0 % (0 MB)
129 06:09:49.042258 progress 5 % (0 MB)
130 06:09:49.123595 progress 10 % (1 MB)
131 06:09:49.213476 progress 15 % (1 MB)
132 06:09:49.291312 progress 20 % (2 MB)
133 06:09:49.376013 progress 25 % (2 MB)
134 06:09:49.457548 progress 30 % (3 MB)
135 06:09:49.537623 progress 35 % (3 MB)
136 06:09:49.612712 progress 40 % (4 MB)
137 06:09:49.691107 progress 45 % (5 MB)
138 06:09:49.770362 progress 50 % (5 MB)
139 06:09:49.847810 progress 55 % (6 MB)
140 06:09:49.930067 progress 60 % (6 MB)
141 06:09:50.017822 progress 65 % (7 MB)
142 06:09:50.100862 progress 70 % (7 MB)
143 06:09:50.200235 progress 75 % (8 MB)
144 06:09:50.290835 progress 80 % (8 MB)
145 06:09:50.373156 progress 85 % (9 MB)
146 06:09:50.450127 progress 90 % (10 MB)
147 06:09:50.528737 progress 95 % (10 MB)
148 06:09:50.602543 progress 100 % (11 MB)
149 06:09:50.617061 11 MB downloaded in 1.69 s (6.57 MB/s)
150 06:09:50.618217 end: 1.5.1 http-download (duration 00:00:02) [common]
152 06:09:50.620493 end: 1.5 download-retry (duration 00:00:02) [common]
153 06:09:50.621264 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 06:09:50.621913 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 06:10:10.055751 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/796671/extract-nfsrootfs-525oehj8
156 06:10:10.056378 end: 1.6.1 extract-nfsrootfs (duration 00:00:19) [common]
157 06:10:10.056709 start: 1.6.2 lava-overlay (timeout 00:09:23) [common]
158 06:10:10.057356 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1
159 06:10:10.057837 makedir: /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin
160 06:10:10.058238 makedir: /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/tests
161 06:10:10.058622 makedir: /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/results
162 06:10:10.059029 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-add-keys
163 06:10:10.059598 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-add-sources
164 06:10:10.060231 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-background-process-start
165 06:10:10.060761 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-background-process-stop
166 06:10:10.061289 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-common-functions
167 06:10:10.061785 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-echo-ipv4
168 06:10:10.062265 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-install-packages
169 06:10:10.062748 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-installed-packages
170 06:10:10.063226 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-os-build
171 06:10:10.063748 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-probe-channel
172 06:10:10.064388 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-probe-ip
173 06:10:10.064929 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-target-ip
174 06:10:10.065416 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-target-mac
175 06:10:10.065908 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-target-storage
176 06:10:10.066401 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-test-case
177 06:10:10.066890 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-test-event
178 06:10:10.067376 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-test-feedback
179 06:10:10.067857 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-test-raise
180 06:10:10.068571 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-test-reference
181 06:10:10.069089 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-test-runner
182 06:10:10.069582 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-test-set
183 06:10:10.070065 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-test-shell
184 06:10:10.070675 Updating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-add-keys (debian)
185 06:10:10.071236 Updating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-add-sources (debian)
186 06:10:10.071748 Updating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-install-packages (debian)
187 06:10:10.072306 Updating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-installed-packages (debian)
188 06:10:10.072822 Updating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/bin/lava-os-build (debian)
189 06:10:10.073287 Creating /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/environment
190 06:10:10.073686 LAVA metadata
191 06:10:10.073961 - LAVA_JOB_ID=796671
192 06:10:10.074178 - LAVA_DISPATCHER_IP=192.168.6.2
193 06:10:10.074557 start: 1.6.2.1 ssh-authorize (timeout 00:09:23) [common]
194 06:10:10.075564 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 06:10:10.075877 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:23) [common]
196 06:10:10.076112 skipped lava-vland-overlay
197 06:10:10.076357 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 06:10:10.076612 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:23) [common]
199 06:10:10.076831 skipped lava-multinode-overlay
200 06:10:10.077073 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 06:10:10.077322 start: 1.6.2.4 test-definition (timeout 00:09:23) [common]
202 06:10:10.077569 Loading test definitions
203 06:10:10.077845 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:23) [common]
204 06:10:10.078064 Using /lava-796671 at stage 0
205 06:10:10.079139 uuid=796671_1.6.2.4.1 testdef=None
206 06:10:10.079440 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 06:10:10.079702 start: 1.6.2.4.2 test-overlay (timeout 00:09:23) [common]
208 06:10:10.081322 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 06:10:10.082110 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:23) [common]
211 06:10:10.084043 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 06:10:10.084874 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:23) [common]
214 06:10:10.086845 runner path: /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/0/tests/0_timesync-off test_uuid 796671_1.6.2.4.1
215 06:10:10.087407 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 06:10:10.088250 start: 1.6.2.4.5 git-repo-action (timeout 00:09:23) [common]
218 06:10:10.088476 Using /lava-796671 at stage 0
219 06:10:10.088831 Fetching tests from https://github.com/kernelci/test-definitions.git
220 06:10:10.089122 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/0/tests/1_kselftest-alsa'
221 06:10:13.390926 Running '/usr/bin/git checkout kernelci.org
222 06:10:13.714206 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 06:10:13.715651 uuid=796671_1.6.2.4.5 testdef=None
224 06:10:13.716017 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 06:10:13.716791 start: 1.6.2.4.6 test-overlay (timeout 00:09:19) [common]
227 06:10:13.719672 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 06:10:13.720532 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:19) [common]
230 06:10:13.724427 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 06:10:13.725329 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:19) [common]
233 06:10:13.729051 runner path: /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/0/tests/1_kselftest-alsa test_uuid 796671_1.6.2.4.5
234 06:10:13.729362 BOARD='meson-g12b-a311d-libretech-cc'
235 06:10:13.729571 BRANCH='next'
236 06:10:13.729769 SKIPFILE='/dev/null'
237 06:10:13.729968 SKIP_INSTALL='True'
238 06:10:13.730164 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 06:10:13.730367 TST_CASENAME=''
240 06:10:13.730566 TST_CMDFILES='alsa'
241 06:10:13.731173 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 06:10:13.732003 Creating lava-test-runner.conf files
244 06:10:13.732218 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796671/lava-overlay-yk98rtu1/lava-796671/0 for stage 0
245 06:10:13.732664 - 0_timesync-off
246 06:10:13.732922 - 1_kselftest-alsa
247 06:10:13.733264 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 06:10:13.733553 start: 1.6.2.5 compress-overlay (timeout 00:09:19) [common]
249 06:10:37.002816 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 06:10:37.003264 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:56) [common]
251 06:10:37.003532 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 06:10:37.003803 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 06:10:37.004096 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:56) [common]
254 06:10:37.715257 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 06:10:37.715745 start: 1.6.4 extract-modules (timeout 00:08:55) [common]
256 06:10:37.716034 extracting modules file /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796671/extract-nfsrootfs-525oehj8
257 06:10:39.260435 extracting modules file /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796671/extract-overlay-ramdisk-o27svrx3/ramdisk
258 06:10:40.669109 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 06:10:40.669609 start: 1.6.5 apply-overlay-tftp (timeout 00:08:52) [common]
260 06:10:40.669908 [common] Applying overlay to NFS
261 06:10:40.670135 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796671/compress-overlay-zdl7beov/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796671/extract-nfsrootfs-525oehj8
262 06:10:43.476385 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 06:10:43.476857 start: 1.6.6 prepare-kernel (timeout 00:08:49) [common]
264 06:10:43.477165 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:49) [common]
265 06:10:43.477428 Converting downloaded kernel to a uImage
266 06:10:43.477759 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/kernel/Image /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/kernel/uImage
267 06:10:44.012083 output: Image Name:
268 06:10:44.012584 output: Created: Thu Oct 3 06:10:43 2024
269 06:10:44.012821 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 06:10:44.013037 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 06:10:44.013245 output: Load Address: 01080000
272 06:10:44.013451 output: Entry Point: 01080000
273 06:10:44.013654 output:
274 06:10:44.014054 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 06:10:44.014335 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 06:10:44.014614 start: 1.6.7 configure-preseed-file (timeout 00:08:49) [common]
277 06:10:44.014926 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 06:10:44.015208 start: 1.6.8 compress-ramdisk (timeout 00:08:49) [common]
279 06:10:44.015475 Building ramdisk /var/lib/lava/dispatcher/tmp/796671/extract-overlay-ramdisk-o27svrx3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796671/extract-overlay-ramdisk-o27svrx3/ramdisk
280 06:10:46.301264 >> 166933 blocks
281 06:10:53.999740 Adding RAMdisk u-boot header.
282 06:10:54.000419 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796671/extract-overlay-ramdisk-o27svrx3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796671/extract-overlay-ramdisk-o27svrx3/ramdisk.cpio.gz.uboot
283 06:10:54.296537 output: Image Name:
284 06:10:54.296963 output: Created: Thu Oct 3 06:10:54 2024
285 06:10:54.297178 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 06:10:54.297384 output: Data Size: 23442747 Bytes = 22893.31 KiB = 22.36 MiB
287 06:10:54.297587 output: Load Address: 00000000
288 06:10:54.297788 output: Entry Point: 00000000
289 06:10:54.297989 output:
290 06:10:54.298563 rename /var/lib/lava/dispatcher/tmp/796671/extract-overlay-ramdisk-o27svrx3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/ramdisk/ramdisk.cpio.gz.uboot
291 06:10:54.298984 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 06:10:54.299266 end: 1.6 prepare-tftp-overlay (duration 00:01:04) [common]
293 06:10:54.299540 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:38) [common]
294 06:10:54.299780 No LXC device requested
295 06:10:54.300248 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 06:10:54.300978 start: 1.8 deploy-device-env (timeout 00:08:38) [common]
297 06:10:54.301547 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 06:10:54.302012 Checking files for TFTP limit of 4294967296 bytes.
299 06:10:54.305152 end: 1 tftp-deploy (duration 00:01:22) [common]
300 06:10:54.305817 start: 2 uboot-action (timeout 00:05:00) [common]
301 06:10:54.306401 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 06:10:54.306955 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 06:10:54.307516 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 06:10:54.308141 Using kernel file from prepare-kernel: 796671/tftp-deploy-kmrholan/kernel/uImage
305 06:10:54.308855 substitutions:
306 06:10:54.309315 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 06:10:54.309763 - {DTB_ADDR}: 0x01070000
308 06:10:54.310208 - {DTB}: 796671/tftp-deploy-kmrholan/dtb/meson-g12b-a311d-libretech-cc.dtb
309 06:10:54.310654 - {INITRD}: 796671/tftp-deploy-kmrholan/ramdisk/ramdisk.cpio.gz.uboot
310 06:10:54.311099 - {KERNEL_ADDR}: 0x01080000
311 06:10:54.311538 - {KERNEL}: 796671/tftp-deploy-kmrholan/kernel/uImage
312 06:10:54.312005 - {LAVA_MAC}: None
313 06:10:54.312495 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/796671/extract-nfsrootfs-525oehj8
314 06:10:54.312941 - {NFS_SERVER_IP}: 192.168.6.2
315 06:10:54.313375 - {PRESEED_CONFIG}: None
316 06:10:54.313810 - {PRESEED_LOCAL}: None
317 06:10:54.314244 - {RAMDISK_ADDR}: 0x08000000
318 06:10:54.314673 - {RAMDISK}: 796671/tftp-deploy-kmrholan/ramdisk/ramdisk.cpio.gz.uboot
319 06:10:54.315104 - {ROOT_PART}: None
320 06:10:54.315533 - {ROOT}: None
321 06:10:54.315963 - {SERVER_IP}: 192.168.6.2
322 06:10:54.316419 - {TEE_ADDR}: 0x83000000
323 06:10:54.316849 - {TEE}: None
324 06:10:54.317277 Parsed boot commands:
325 06:10:54.317694 - setenv autoload no
326 06:10:54.318121 - setenv initrd_high 0xffffffff
327 06:10:54.318550 - setenv fdt_high 0xffffffff
328 06:10:54.318975 - dhcp
329 06:10:54.319399 - setenv serverip 192.168.6.2
330 06:10:54.319830 - tftpboot 0x01080000 796671/tftp-deploy-kmrholan/kernel/uImage
331 06:10:54.320289 - tftpboot 0x08000000 796671/tftp-deploy-kmrholan/ramdisk/ramdisk.cpio.gz.uboot
332 06:10:54.320724 - tftpboot 0x01070000 796671/tftp-deploy-kmrholan/dtb/meson-g12b-a311d-libretech-cc.dtb
333 06:10:54.321157 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/796671/extract-nfsrootfs-525oehj8,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 06:10:54.321601 - bootm 0x01080000 0x08000000 0x01070000
335 06:10:54.322157 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 06:10:54.323794 start: 2.3 connect-device (timeout 00:05:00) [common]
338 06:10:54.324311 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 06:10:54.341398 Setting prompt string to ['lava-test: # ']
340 06:10:54.342953 end: 2.3 connect-device (duration 00:00:00) [common]
341 06:10:54.343571 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 06:10:54.344168 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 06:10:54.344784 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 06:10:54.346071 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 06:10:54.380423 >> OK - accepted request
346 06:10:54.382550 Returned 0 in 0 seconds
347 06:10:54.483703 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 06:10:54.485419 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 06:10:54.485976 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 06:10:54.486477 Setting prompt string to ['Hit any key to stop autoboot']
352 06:10:54.486927 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 06:10:54.488514 Trying 192.168.56.21...
354 06:10:54.489017 Connected to conserv1.
355 06:10:54.489435 Escape character is '^]'.
356 06:10:54.489854
357 06:10:54.490274 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 06:10:54.490716
359 06:11:06.518194 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 06:11:06.518820 bl2_stage_init 0x01
361 06:11:06.519240 bl2_stage_init 0x81
362 06:11:06.523660 hw id: 0x0000 - pwm id 0x01
363 06:11:06.524234 bl2_stage_init 0xc1
364 06:11:06.524660 bl2_stage_init 0x02
365 06:11:06.525067
366 06:11:06.529219 L0:00000000
367 06:11:06.529694 L1:20000703
368 06:11:06.530105 L2:00008067
369 06:11:06.530506 L3:14000000
370 06:11:06.532175 B2:00402000
371 06:11:06.532616 B1:e0f83180
372 06:11:06.533025
373 06:11:06.533421 TE: 58159
374 06:11:06.533814
375 06:11:06.543229 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 06:11:06.543666
377 06:11:06.544095 Board ID = 1
378 06:11:06.544491 Set A53 clk to 24M
379 06:11:06.544880 Set A73 clk to 24M
380 06:11:06.549585 Set clk81 to 24M
381 06:11:06.550015 A53 clk: 1200 MHz
382 06:11:06.550408 A73 clk: 1200 MHz
383 06:11:06.554527 CLK81: 166.6M
384 06:11:06.555084 smccc: 00012ab5
385 06:11:06.560245 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 06:11:06.560777 board id: 1
387 06:11:06.565760 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 06:11:06.579509 fw parse done
389 06:11:06.585381 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 06:11:06.627933 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 06:11:06.638887 PIEI prepare done
392 06:11:06.639566 fastboot data load
393 06:11:06.640076 fastboot data verify
394 06:11:06.644479 verify result: 266
395 06:11:06.649994 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 06:11:06.650412 LPDDR4 probe
397 06:11:06.650642 ddr clk to 1584MHz
398 06:11:06.657216 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 06:11:06.695277
400 06:11:06.695844 dmc_version 0001
401 06:11:06.701952 Check phy result
402 06:11:06.707793 INFO : End of CA training
403 06:11:06.708224 INFO : End of initialization
404 06:11:06.713326 INFO : Training has run successfully!
405 06:11:06.713699 Check phy result
406 06:11:06.719293 INFO : End of initialization
407 06:11:06.719846 INFO : End of read enable training
408 06:11:06.728143 INFO : End of fine write leveling
409 06:11:06.732123 INFO : End of Write leveling coarse delay
410 06:11:06.732519 INFO : Training has run successfully!
411 06:11:06.732732 Check phy result
412 06:11:06.735849 INFO : End of initialization
413 06:11:06.736254 INFO : End of read dq deskew training
414 06:11:06.744053 INFO : End of MPR read delay center optimization
415 06:11:06.747302 INFO : End of write delay center optimization
416 06:11:06.753376 INFO : End of read delay center optimization
417 06:11:06.753802 INFO : End of max read latency training
418 06:11:06.759445 INFO : Training has run successfully!
419 06:11:06.759882 1D training succeed
420 06:11:06.768762 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 06:11:06.814977 Check phy result
422 06:11:06.815485 INFO : End of initialization
423 06:11:06.836953 INFO : End of 2D read delay Voltage center optimization
424 06:11:06.856333 INFO : End of 2D read delay Voltage center optimization
425 06:11:06.908200 INFO : End of 2D write delay Voltage center optimization
426 06:11:06.957394 INFO : End of 2D write delay Voltage center optimization
427 06:11:06.963064 INFO : Training has run successfully!
428 06:11:06.963546
429 06:11:06.964047 channel==0
430 06:11:06.969127 RxClkDly_Margin_A0==88 ps 9
431 06:11:06.969610 TxDqDly_Margin_A0==98 ps 10
432 06:11:06.972114 RxClkDly_Margin_A1==88 ps 9
433 06:11:06.972581 TxDqDly_Margin_A1==98 ps 10
434 06:11:06.977624 TrainedVREFDQ_A0==74
435 06:11:06.978096 TrainedVREFDQ_A1==74
436 06:11:06.983203 VrefDac_Margin_A0==25
437 06:11:06.983678 DeviceVref_Margin_A0==40
438 06:11:06.984162 VrefDac_Margin_A1==25
439 06:11:06.988730 DeviceVref_Margin_A1==40
440 06:11:06.989197
441 06:11:06.989641
442 06:11:06.990081 channel==1
443 06:11:06.990518 RxClkDly_Margin_A0==88 ps 9
444 06:11:06.994481 TxDqDly_Margin_A0==88 ps 9
445 06:11:06.994957 RxClkDly_Margin_A1==88 ps 9
446 06:11:06.999903 TxDqDly_Margin_A1==98 ps 10
447 06:11:07.000404 TrainedVREFDQ_A0==76
448 06:11:07.000844 TrainedVREFDQ_A1==77
449 06:11:07.005569 VrefDac_Margin_A0==23
450 06:11:07.006057 DeviceVref_Margin_A0==38
451 06:11:07.011185 VrefDac_Margin_A1==24
452 06:11:07.011651 DeviceVref_Margin_A1==37
453 06:11:07.012119
454 06:11:07.016775 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 06:11:07.017245
456 06:11:07.044745 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 06:11:07.050477 2D training succeed
458 06:11:07.056050 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 06:11:07.056537 auto size-- 65535DDR cs0 size: 2048MB
460 06:11:07.061384 DDR cs1 size: 2048MB
461 06:11:07.061861 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 06:11:07.067099 cs0 DataBus test pass
463 06:11:07.067649 cs1 DataBus test pass
464 06:11:07.068173 cs0 AddrBus test pass
465 06:11:07.072637 cs1 AddrBus test pass
466 06:11:07.073151
467 06:11:07.073603 100bdlr_step_size ps== 420
468 06:11:07.074052 result report
469 06:11:07.078326 boot times 0Enable ddr reg access
470 06:11:07.085868 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 06:11:07.099398 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 06:11:07.673183 0.0;M3 CHK:0;cm4_sp_mode 0
473 06:11:07.673866 MVN_1=0x00000000
474 06:11:07.678558 MVN_2=0x00000000
475 06:11:07.684406 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 06:11:07.684893 OPS=0x10
477 06:11:07.685341 ring efuse init
478 06:11:07.685781 chipver efuse init
479 06:11:07.689906 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 06:11:07.695486 [0.018960 Inits done]
481 06:11:07.695967 secure task start!
482 06:11:07.696450 high task start!
483 06:11:07.700103 low task start!
484 06:11:07.700577 run into bl31
485 06:11:07.706689 NOTICE: BL31: v1.3(release):4fc40b1
486 06:11:07.714509 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 06:11:07.715013 NOTICE: BL31: G12A normal boot!
488 06:11:07.739969 NOTICE: BL31: BL33 decompress pass
489 06:11:07.745631 ERROR: Error initializing runtime service opteed_fast
490 06:11:08.978606
491 06:11:08.979030
492 06:11:08.986866 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 06:11:08.987173
494 06:11:08.987380 Model: Libre Computer AML-A311D-CC Alta
495 06:11:09.195289 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 06:11:09.218725 DRAM: 2 GiB (effective 3.8 GiB)
497 06:11:09.361855 Core: 408 devices, 31 uclasses, devicetree: separate
498 06:11:09.366775 WDT: Not starting watchdog@f0d0
499 06:11:09.400032 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 06:11:09.412838 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 06:11:09.416361 ** Bad device specification mmc 0 **
502 06:11:09.427741 Card did not respond to voltage select! : -110
503 06:11:09.435259 ** Bad device specification mmc 0 **
504 06:11:09.435814 Couldn't find partition mmc 0
505 06:11:09.443682 Card did not respond to voltage select! : -110
506 06:11:09.449165 ** Bad device specification mmc 0 **
507 06:11:09.449765 Couldn't find partition mmc 0
508 06:11:09.454200 Error: could not access storage.
509 06:11:10.718264 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 06:11:10.718845 bl2_stage_init 0x01
511 06:11:10.719287 bl2_stage_init 0x81
512 06:11:10.723822 hw id: 0x0000 - pwm id 0x01
513 06:11:10.724290 bl2_stage_init 0xc1
514 06:11:10.724645 bl2_stage_init 0x02
515 06:11:10.724962
516 06:11:10.729461 L0:00000000
517 06:11:10.729843 L1:20000703
518 06:11:10.730187 L2:00008067
519 06:11:10.730525 L3:14000000
520 06:11:10.732299 B2:00402000
521 06:11:10.732670 B1:e0f83180
522 06:11:10.733005
523 06:11:10.733319 TE: 58159
524 06:11:10.733651
525 06:11:10.743478 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 06:11:10.743911
527 06:11:10.744297 Board ID = 1
528 06:11:10.744625 Set A53 clk to 24M
529 06:11:10.744969 Set A73 clk to 24M
530 06:11:10.749118 Set clk81 to 24M
531 06:11:10.749430 A53 clk: 1200 MHz
532 06:11:10.749678 A73 clk: 1200 MHz
533 06:11:10.752448 CLK81: 166.6M
534 06:11:10.752743 smccc: 00012ab5
535 06:11:10.758031 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 06:11:10.763720 board id: 1
537 06:11:10.768904 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 06:11:10.779582 fw parse done
539 06:11:10.785561 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 06:11:10.828245 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 06:11:10.839166 PIEI prepare done
542 06:11:10.839700 fastboot data load
543 06:11:10.840205 fastboot data verify
544 06:11:10.844794 verify result: 266
545 06:11:10.850298 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 06:11:10.850781 LPDDR4 probe
547 06:11:10.851251 ddr clk to 1584MHz
548 06:11:10.858325 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 06:11:10.895588
550 06:11:10.896197 dmc_version 0001
551 06:11:10.902223 Check phy result
552 06:11:10.908193 INFO : End of CA training
553 06:11:10.908737 INFO : End of initialization
554 06:11:10.913886 INFO : Training has run successfully!
555 06:11:10.914396 Check phy result
556 06:11:10.919360 INFO : End of initialization
557 06:11:10.919890 INFO : End of read enable training
558 06:11:10.925013 INFO : End of fine write leveling
559 06:11:10.930682 INFO : End of Write leveling coarse delay
560 06:11:10.931222 INFO : Training has run successfully!
561 06:11:10.931687 Check phy result
562 06:11:10.936141 INFO : End of initialization
563 06:11:10.936647 INFO : End of read dq deskew training
564 06:11:10.941871 INFO : End of MPR read delay center optimization
565 06:11:10.947325 INFO : End of write delay center optimization
566 06:11:10.952969 INFO : End of read delay center optimization
567 06:11:10.953471 INFO : End of max read latency training
568 06:11:10.958568 INFO : Training has run successfully!
569 06:11:10.959062 1D training succeed
570 06:11:10.967670 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 06:11:11.015381 Check phy result
572 06:11:11.016040 INFO : End of initialization
573 06:11:11.037898 INFO : End of 2D read delay Voltage center optimization
574 06:11:11.056485 INFO : End of 2D read delay Voltage center optimization
575 06:11:11.108496 INFO : End of 2D write delay Voltage center optimization
576 06:11:11.157938 INFO : End of 2D write delay Voltage center optimization
577 06:11:11.163366 INFO : Training has run successfully!
578 06:11:11.163880
579 06:11:11.164394 channel==0
580 06:11:11.169088 RxClkDly_Margin_A0==88 ps 9
581 06:11:11.169602 TxDqDly_Margin_A0==98 ps 10
582 06:11:11.174653 RxClkDly_Margin_A1==88 ps 9
583 06:11:11.175156 TxDqDly_Margin_A1==98 ps 10
584 06:11:11.175606 TrainedVREFDQ_A0==74
585 06:11:11.180428 TrainedVREFDQ_A1==74
586 06:11:11.180917 VrefDac_Margin_A0==25
587 06:11:11.181360 DeviceVref_Margin_A0==40
588 06:11:11.185924 VrefDac_Margin_A1==25
589 06:11:11.186397 DeviceVref_Margin_A1==40
590 06:11:11.186839
591 06:11:11.187281
592 06:11:11.191395 channel==1
593 06:11:11.191878 RxClkDly_Margin_A0==88 ps 9
594 06:11:11.192358 TxDqDly_Margin_A0==88 ps 9
595 06:11:11.197013 RxClkDly_Margin_A1==88 ps 9
596 06:11:11.197486 TxDqDly_Margin_A1==88 ps 9
597 06:11:11.202626 TrainedVREFDQ_A0==77
598 06:11:11.203104 TrainedVREFDQ_A1==77
599 06:11:11.203546 VrefDac_Margin_A0==23
600 06:11:11.208269 DeviceVref_Margin_A0==37
601 06:11:11.208740 VrefDac_Margin_A1==24
602 06:11:11.213916 DeviceVref_Margin_A1==37
603 06:11:11.214393
604 06:11:11.214835 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 06:11:11.215279
606 06:11:11.247342 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 06:11:11.247973 2D training succeed
608 06:11:11.252956 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 06:11:11.258563 auto size-- 65535DDR cs0 size: 2048MB
610 06:11:11.259045 DDR cs1 size: 2048MB
611 06:11:11.264202 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 06:11:11.264698 cs0 DataBus test pass
613 06:11:11.269902 cs1 DataBus test pass
614 06:11:11.270392 cs0 AddrBus test pass
615 06:11:11.271040 cs1 AddrBus test pass
616 06:11:11.271506
617 06:11:11.275390 100bdlr_step_size ps== 420
618 06:11:11.275892 result report
619 06:11:11.280973 boot times 0Enable ddr reg access
620 06:11:11.286095 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 06:11:11.299638 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 06:11:11.873306 0.0;M3 CHK:0;cm4_sp_mode 0
623 06:11:11.874000 MVN_1=0x00000000
624 06:11:11.878873 MVN_2=0x00000000
625 06:11:11.884637 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 06:11:11.885143 OPS=0x10
627 06:11:11.885593 ring efuse init
628 06:11:11.886030 chipver efuse init
629 06:11:11.890124 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 06:11:11.895894 [0.018961 Inits done]
631 06:11:11.896420 secure task start!
632 06:11:11.896856 high task start!
633 06:11:11.900395 low task start!
634 06:11:11.900860 run into bl31
635 06:11:11.906988 NOTICE: BL31: v1.3(release):4fc40b1
636 06:11:11.914883 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 06:11:11.915462 NOTICE: BL31: G12A normal boot!
638 06:11:11.941673 NOTICE: BL31: BL33 decompress pass
639 06:11:11.945852 ERROR: Error initializing runtime service opteed_fast
640 06:11:13.178894
641 06:11:13.179551
642 06:11:13.187402 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 06:11:13.187911
644 06:11:13.188394 Model: Libre Computer AML-A311D-CC Alta
645 06:11:13.395832 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 06:11:13.419215 DRAM: 2 GiB (effective 3.8 GiB)
647 06:11:13.562065 Core: 408 devices, 31 uclasses, devicetree: separate
648 06:11:13.568085 WDT: Not starting watchdog@f0d0
649 06:11:13.600394 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 06:11:13.612725 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 06:11:13.617617 ** Bad device specification mmc 0 **
652 06:11:13.628072 Card did not respond to voltage select! : -110
653 06:11:13.635657 ** Bad device specification mmc 0 **
654 06:11:13.636175 Couldn't find partition mmc 0
655 06:11:13.644087 Card did not respond to voltage select! : -110
656 06:11:13.649555 ** Bad device specification mmc 0 **
657 06:11:13.650036 Couldn't find partition mmc 0
658 06:11:13.654599 Error: could not access storage.
659 06:11:13.997191 Net: eth0: ethernet@ff3f0000
660 06:11:13.997847 starting USB...
661 06:11:14.248949 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 06:11:14.249600 Starting the controller
663 06:11:14.255895 USB XHCI 1.10
664 06:11:15.967196 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 06:11:15.967852 bl2_stage_init 0x01
666 06:11:15.968369 bl2_stage_init 0x81
667 06:11:15.972803 hw id: 0x0000 - pwm id 0x01
668 06:11:15.973303 bl2_stage_init 0xc1
669 06:11:15.973750 bl2_stage_init 0x02
670 06:11:15.974193
671 06:11:15.978413 L0:00000000
672 06:11:15.978896 L1:20000703
673 06:11:15.979344 L2:00008067
674 06:11:15.979781 L3:14000000
675 06:11:15.984087 B2:00402000
676 06:11:15.984574 B1:e0f83180
677 06:11:15.985015
678 06:11:15.985458 TE: 58124
679 06:11:15.986046
680 06:11:15.989678 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 06:11:15.990164
682 06:11:15.990606 Board ID = 1
683 06:11:15.995202 Set A53 clk to 24M
684 06:11:15.995711 Set A73 clk to 24M
685 06:11:15.996192 Set clk81 to 24M
686 06:11:16.000774 A53 clk: 1200 MHz
687 06:11:16.001282 A73 clk: 1200 MHz
688 06:11:16.001720 CLK81: 166.6M
689 06:11:16.002160 smccc: 00012a92
690 06:11:16.006294 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 06:11:16.011963 board id: 1
692 06:11:16.017866 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 06:11:16.028741 fw parse done
694 06:11:16.034562 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 06:11:16.077038 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 06:11:16.087929 PIEI prepare done
697 06:11:16.088476 fastboot data load
698 06:11:16.088930 fastboot data verify
699 06:11:16.093622 verify result: 266
700 06:11:16.099160 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 06:11:16.099666 LPDDR4 probe
702 06:11:16.100140 ddr clk to 1584MHz
703 06:11:16.107193 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 06:11:16.144498
705 06:11:16.145047 dmc_version 0001
706 06:11:16.151101 Check phy result
707 06:11:16.156976 INFO : End of CA training
708 06:11:16.157488 INFO : End of initialization
709 06:11:16.162603 INFO : Training has run successfully!
710 06:11:16.163112 Check phy result
711 06:11:16.168234 INFO : End of initialization
712 06:11:16.168742 INFO : End of read enable training
713 06:11:16.171437 INFO : End of fine write leveling
714 06:11:16.177027 INFO : End of Write leveling coarse delay
715 06:11:16.182726 INFO : Training has run successfully!
716 06:11:16.183294 Check phy result
717 06:11:16.183751 INFO : End of initialization
718 06:11:16.188352 INFO : End of read dq deskew training
719 06:11:16.191746 INFO : End of MPR read delay center optimization
720 06:11:16.197334 INFO : End of write delay center optimization
721 06:11:16.202936 INFO : End of read delay center optimization
722 06:11:16.203451 INFO : End of max read latency training
723 06:11:16.208470 INFO : Training has run successfully!
724 06:11:16.208987 1D training succeed
725 06:11:16.216793 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 06:11:16.264280 Check phy result
727 06:11:16.264813 INFO : End of initialization
728 06:11:16.286114 INFO : End of 2D read delay Voltage center optimization
729 06:11:16.305400 INFO : End of 2D read delay Voltage center optimization
730 06:11:16.357420 INFO : End of 2D write delay Voltage center optimization
731 06:11:16.406974 INFO : End of 2D write delay Voltage center optimization
732 06:11:16.412301 INFO : Training has run successfully!
733 06:11:16.412844
734 06:11:16.413296 channel==0
735 06:11:16.417888 RxClkDly_Margin_A0==88 ps 9
736 06:11:16.418431 TxDqDly_Margin_A0==98 ps 10
737 06:11:16.421274 RxClkDly_Margin_A1==88 ps 9
738 06:11:16.421823 TxDqDly_Margin_A1==98 ps 10
739 06:11:16.426797 TrainedVREFDQ_A0==74
740 06:11:16.427341 TrainedVREFDQ_A1==74
741 06:11:16.432422 VrefDac_Margin_A0==25
742 06:11:16.432969 DeviceVref_Margin_A0==40
743 06:11:16.433412 VrefDac_Margin_A1==25
744 06:11:16.438032 DeviceVref_Margin_A1==40
745 06:11:16.438594
746 06:11:16.439044
747 06:11:16.439483 channel==1
748 06:11:16.439917 RxClkDly_Margin_A0==88 ps 9
749 06:11:16.443601 TxDqDly_Margin_A0==88 ps 9
750 06:11:16.444188 RxClkDly_Margin_A1==88 ps 9
751 06:11:16.449248 TxDqDly_Margin_A1==88 ps 9
752 06:11:16.449802 TrainedVREFDQ_A0==76
753 06:11:16.450250 TrainedVREFDQ_A1==77
754 06:11:16.454804 VrefDac_Margin_A0==23
755 06:11:16.455345 DeviceVref_Margin_A0==38
756 06:11:16.460324 VrefDac_Margin_A1==24
757 06:11:16.460873 DeviceVref_Margin_A1==37
758 06:11:16.461314
759 06:11:16.466020 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 06:11:16.466568
761 06:11:16.493918 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 06:11:16.499514 2D training succeed
763 06:11:16.505104 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 06:11:16.505655 auto size-- 65535DDR cs0 size: 2048MB
765 06:11:16.510706 DDR cs1 size: 2048MB
766 06:11:16.511248 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 06:11:16.516289 cs0 DataBus test pass
768 06:11:16.516840 cs1 DataBus test pass
769 06:11:16.517281 cs0 AddrBus test pass
770 06:11:16.521905 cs1 AddrBus test pass
771 06:11:16.522451
772 06:11:16.522895 100bdlr_step_size ps== 420
773 06:11:16.523344 result report
774 06:11:16.527472 boot times 0Enable ddr reg access
775 06:11:16.535086 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 06:11:16.548490 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 06:11:17.122138 0.0;M3 CHK:0;cm4_sp_mode 0
778 06:11:17.122774 MVN_1=0x00000000
779 06:11:17.127740 MVN_2=0x00000000
780 06:11:17.133493 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 06:11:17.134034 OPS=0x10
782 06:11:17.134484 ring efuse init
783 06:11:17.134915 chipver efuse init
784 06:11:17.138994 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 06:11:17.144704 [0.018961 Inits done]
786 06:11:17.145228 secure task start!
787 06:11:17.145665 high task start!
788 06:11:17.149179 low task start!
789 06:11:17.149704 run into bl31
790 06:11:17.155840 NOTICE: BL31: v1.3(release):4fc40b1
791 06:11:17.163626 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 06:11:17.164197 NOTICE: BL31: G12A normal boot!
793 06:11:17.188953 NOTICE: BL31: BL33 decompress pass
794 06:11:17.193998 ERROR: Error initializing runtime service opteed_fast
795 06:11:18.427502
796 06:11:18.427885
797 06:11:18.435711 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 06:11:18.436053
799 06:11:18.436294 Model: Libre Computer AML-A311D-CC Alta
800 06:11:18.644312 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 06:11:18.667715 DRAM: 2 GiB (effective 3.8 GiB)
802 06:11:18.810735 Core: 408 devices, 31 uclasses, devicetree: separate
803 06:11:18.816196 WDT: Not starting watchdog@f0d0
804 06:11:18.848925 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 06:11:18.861355 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 06:11:18.866292 ** Bad device specification mmc 0 **
807 06:11:18.876637 Card did not respond to voltage select! : -110
808 06:11:18.884292 ** Bad device specification mmc 0 **
809 06:11:18.884675 Couldn't find partition mmc 0
810 06:11:18.892656 Card did not respond to voltage select! : -110
811 06:11:18.898168 ** Bad device specification mmc 0 **
812 06:11:18.898549 Couldn't find partition mmc 0
813 06:11:18.903232 Error: could not access storage.
814 06:11:19.245680 Net: eth0: ethernet@ff3f0000
815 06:11:19.246275 starting USB...
816 06:11:19.497459 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 06:11:19.497890 Starting the controller
818 06:11:19.504400 USB XHCI 1.10
819 06:11:21.667323 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 06:11:21.668038 bl2_stage_init 0x01
821 06:11:21.668540 bl2_stage_init 0x81
822 06:11:21.672859 hw id: 0x0000 - pwm id 0x01
823 06:11:21.673412 bl2_stage_init 0xc1
824 06:11:21.673884 bl2_stage_init 0x02
825 06:11:21.674344
826 06:11:21.678557 L0:00000000
827 06:11:21.679094 L1:20000703
828 06:11:21.679558 L2:00008067
829 06:11:21.680049 L3:14000000
830 06:11:21.681297 B2:00402000
831 06:11:21.681827 B1:e0f83180
832 06:11:21.682295
833 06:11:21.682751 TE: 58124
834 06:11:21.683212
835 06:11:21.692403 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 06:11:21.692954
837 06:11:21.693420 Board ID = 1
838 06:11:21.693873 Set A53 clk to 24M
839 06:11:21.694316 Set A73 clk to 24M
840 06:11:21.698050 Set clk81 to 24M
841 06:11:21.698586 A53 clk: 1200 MHz
842 06:11:21.699049 A73 clk: 1200 MHz
843 06:11:21.703572 CLK81: 166.6M
844 06:11:21.704136 smccc: 00012a92
845 06:11:21.709200 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 06:11:21.709741 board id: 1
847 06:11:21.717994 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 06:11:21.728479 fw parse done
849 06:11:21.734498 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 06:11:21.777038 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 06:11:21.788081 PIEI prepare done
852 06:11:21.788628 fastboot data load
853 06:11:21.789098 fastboot data verify
854 06:11:21.793635 verify result: 266
855 06:11:21.799284 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 06:11:21.799819 LPDDR4 probe
857 06:11:21.800325 ddr clk to 1584MHz
858 06:11:21.807186 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 06:11:21.844657
860 06:11:21.845206 dmc_version 0001
861 06:11:21.851174 Check phy result
862 06:11:21.857118 INFO : End of CA training
863 06:11:21.857653 INFO : End of initialization
864 06:11:21.862655 INFO : Training has run successfully!
865 06:11:21.863188 Check phy result
866 06:11:21.868319 INFO : End of initialization
867 06:11:21.868859 INFO : End of read enable training
868 06:11:21.871541 INFO : End of fine write leveling
869 06:11:21.877093 INFO : End of Write leveling coarse delay
870 06:11:21.882686 INFO : Training has run successfully!
871 06:11:21.883222 Check phy result
872 06:11:21.883689 INFO : End of initialization
873 06:11:21.888333 INFO : End of read dq deskew training
874 06:11:21.891741 INFO : End of MPR read delay center optimization
875 06:11:21.897253 INFO : End of write delay center optimization
876 06:11:21.902848 INFO : End of read delay center optimization
877 06:11:21.903384 INFO : End of max read latency training
878 06:11:21.908543 INFO : Training has run successfully!
879 06:11:21.909079 1D training succeed
880 06:11:21.916648 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 06:11:21.964261 Check phy result
882 06:11:21.964812 INFO : End of initialization
883 06:11:21.986641 INFO : End of 2D read delay Voltage center optimization
884 06:11:22.005889 INFO : End of 2D read delay Voltage center optimization
885 06:11:22.057838 INFO : End of 2D write delay Voltage center optimization
886 06:11:22.107088 INFO : End of 2D write delay Voltage center optimization
887 06:11:22.112593 INFO : Training has run successfully!
888 06:11:22.113137
889 06:11:22.113604 channel==0
890 06:11:22.118215 RxClkDly_Margin_A0==88 ps 9
891 06:11:22.118757 TxDqDly_Margin_A0==98 ps 10
892 06:11:22.123812 RxClkDly_Margin_A1==88 ps 9
893 06:11:22.124378 TxDqDly_Margin_A1==98 ps 10
894 06:11:22.124868 TrainedVREFDQ_A0==74
895 06:11:22.129427 TrainedVREFDQ_A1==74
896 06:11:22.129994 VrefDac_Margin_A0==25
897 06:11:22.130462 DeviceVref_Margin_A0==40
898 06:11:22.135046 VrefDac_Margin_A1==24
899 06:11:22.135596 DeviceVref_Margin_A1==40
900 06:11:22.136069
901 06:11:22.136513
902 06:11:22.140584 channel==1
903 06:11:22.141108 RxClkDly_Margin_A0==88 ps 9
904 06:11:22.141545 TxDqDly_Margin_A0==98 ps 10
905 06:11:22.146329 RxClkDly_Margin_A1==88 ps 9
906 06:11:22.146850 TxDqDly_Margin_A1==88 ps 9
907 06:11:22.151805 TrainedVREFDQ_A0==77
908 06:11:22.152363 TrainedVREFDQ_A1==77
909 06:11:22.152804 VrefDac_Margin_A0==23
910 06:11:22.157358 DeviceVref_Margin_A0==37
911 06:11:22.157874 VrefDac_Margin_A1==24
912 06:11:22.162930 DeviceVref_Margin_A1==37
913 06:11:22.163467
914 06:11:22.163905 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 06:11:22.164382
916 06:11:22.196499 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
917 06:11:22.197090 2D training succeed
918 06:11:22.202169 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 06:11:22.207781 auto size-- 65535DDR cs0 size: 2048MB
920 06:11:22.208348 DDR cs1 size: 2048MB
921 06:11:22.213335 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 06:11:22.213856 cs0 DataBus test pass
923 06:11:22.218952 cs1 DataBus test pass
924 06:11:22.219472 cs0 AddrBus test pass
925 06:11:22.219910 cs1 AddrBus test pass
926 06:11:22.220375
927 06:11:22.224544 100bdlr_step_size ps== 420
928 06:11:22.225075 result report
929 06:11:22.230217 boot times 0Enable ddr reg access
930 06:11:22.234524 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 06:11:22.248843 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 06:11:22.820798 0.0;M3 CHK:0;cm4_sp_mode 0
933 06:11:22.821467 MVN_1=0x00000000
934 06:11:22.826323 MVN_2=0x00000000
935 06:11:22.832080 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 06:11:22.832625 OPS=0x10
937 06:11:22.833091 ring efuse init
938 06:11:22.833542 chipver efuse init
939 06:11:22.837731 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 06:11:22.843303 [0.018960 Inits done]
941 06:11:22.843842 secure task start!
942 06:11:22.844548 high task start!
943 06:11:22.847841 low task start!
944 06:11:22.848348 run into bl31
945 06:11:22.854459 NOTICE: BL31: v1.3(release):4fc40b1
946 06:11:22.862184 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 06:11:22.862653 NOTICE: BL31: G12A normal boot!
948 06:11:22.887561 NOTICE: BL31: BL33 decompress pass
949 06:11:22.893257 ERROR: Error initializing runtime service opteed_fast
950 06:11:24.126153
951 06:11:24.126761
952 06:11:24.134697 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 06:11:24.135177
954 06:11:24.135604 Model: Libre Computer AML-A311D-CC Alta
955 06:11:24.343046 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 06:11:24.366355 DRAM: 2 GiB (effective 3.8 GiB)
957 06:11:24.509406 Core: 408 devices, 31 uclasses, devicetree: separate
958 06:11:24.515244 WDT: Not starting watchdog@f0d0
959 06:11:24.547492 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 06:11:24.559975 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 06:11:24.564927 ** Bad device specification mmc 0 **
962 06:11:24.575273 Card did not respond to voltage select! : -110
963 06:11:24.582903 ** Bad device specification mmc 0 **
964 06:11:24.583379 Couldn't find partition mmc 0
965 06:11:24.591240 Card did not respond to voltage select! : -110
966 06:11:24.596782 ** Bad device specification mmc 0 **
967 06:11:24.597253 Couldn't find partition mmc 0
968 06:11:24.601818 Error: could not access storage.
969 06:11:24.944313 Net: eth0: ethernet@ff3f0000
970 06:11:24.944828 starting USB...
971 06:11:25.196066 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 06:11:25.196576 Starting the controller
973 06:11:25.203053 USB XHCI 1.10
974 06:11:27.067109 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
975 06:11:27.067922 bl2_stage_init 0x81
976 06:11:27.072526 hw id: 0x0000 - pwm id 0x01
977 06:11:27.073014 bl2_stage_init 0xc1
978 06:11:27.073434 bl2_stage_init 0x02
979 06:11:27.073841
980 06:11:27.078163 L0:00000000
981 06:11:27.078619 L1:20000703
982 06:11:27.079031 L2:00008067
983 06:11:27.079436 L3:14000000
984 06:11:27.079837 B2:00402000
985 06:11:27.081029 B1:e0f83180
986 06:11:27.081480
987 06:11:27.081895 TE: 58150
988 06:11:27.082303
989 06:11:27.092142 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 06:11:27.092598
991 06:11:27.093011 Board ID = 1
992 06:11:27.093416 Set A53 clk to 24M
993 06:11:27.093817 Set A73 clk to 24M
994 06:11:27.097736 Set clk81 to 24M
995 06:11:27.098183 A53 clk: 1200 MHz
996 06:11:27.098590 A73 clk: 1200 MHz
997 06:11:27.103298 CLK81: 166.6M
998 06:11:27.103746 smccc: 00012aac
999 06:11:27.109026 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 06:11:27.109476 board id: 1
1001 06:11:27.117349 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 06:11:27.128188 fw parse done
1003 06:11:27.134165 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 06:11:27.176170 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 06:11:27.187665 PIEI prepare done
1006 06:11:27.189407 fastboot data load
1007 06:11:27.189880 fastboot data verify
1008 06:11:27.193387 verify result: 266
1009 06:11:27.199153 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 06:11:27.199653 LPDDR4 probe
1011 06:11:27.200081 ddr clk to 1584MHz
1012 06:11:27.206875 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 06:11:27.244233
1014 06:11:27.244621 dmc_version 0001
1015 06:11:27.251026 Check phy result
1016 06:11:27.256823 INFO : End of CA training
1017 06:11:27.257356 INFO : End of initialization
1018 06:11:27.262438 INFO : Training has run successfully!
1019 06:11:27.262985 Check phy result
1020 06:11:27.268056 INFO : End of initialization
1021 06:11:27.268608 INFO : End of read enable training
1022 06:11:27.273621 INFO : End of fine write leveling
1023 06:11:27.279554 INFO : End of Write leveling coarse delay
1024 06:11:27.280130 INFO : Training has run successfully!
1025 06:11:27.280587 Check phy result
1026 06:11:27.285033 INFO : End of initialization
1027 06:11:27.285569 INFO : End of read dq deskew training
1028 06:11:27.290596 INFO : End of MPR read delay center optimization
1029 06:11:27.296115 INFO : End of write delay center optimization
1030 06:11:27.301857 INFO : End of read delay center optimization
1031 06:11:27.302438 INFO : End of max read latency training
1032 06:11:27.307409 INFO : Training has run successfully!
1033 06:11:27.308004 1D training succeed
1034 06:11:27.316719 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 06:11:27.364260 Check phy result
1036 06:11:27.364913 INFO : End of initialization
1037 06:11:27.385720 INFO : End of 2D read delay Voltage center optimization
1038 06:11:27.405098 INFO : End of 2D read delay Voltage center optimization
1039 06:11:27.457130 INFO : End of 2D write delay Voltage center optimization
1040 06:11:27.506567 INFO : End of 2D write delay Voltage center optimization
1041 06:11:27.511920 INFO : Training has run successfully!
1042 06:11:27.512472
1043 06:11:27.512926 channel==0
1044 06:11:27.517546 RxClkDly_Margin_A0==88 ps 9
1045 06:11:27.518085 TxDqDly_Margin_A0==98 ps 10
1046 06:11:27.523145 RxClkDly_Margin_A1==78 ps 8
1047 06:11:27.523660 TxDqDly_Margin_A1==88 ps 9
1048 06:11:27.524172 TrainedVREFDQ_A0==74
1049 06:11:27.528725 TrainedVREFDQ_A1==74
1050 06:11:27.529235 VrefDac_Margin_A0==25
1051 06:11:27.529697 DeviceVref_Margin_A0==40
1052 06:11:27.534628 VrefDac_Margin_A1==25
1053 06:11:27.535135 DeviceVref_Margin_A1==40
1054 06:11:27.535593
1055 06:11:27.536078
1056 06:11:27.536541 channel==1
1057 06:11:27.540066 RxClkDly_Margin_A0==88 ps 9
1058 06:11:27.540667 TxDqDly_Margin_A0==98 ps 10
1059 06:11:27.545540 RxClkDly_Margin_A1==88 ps 9
1060 06:11:27.546100 TxDqDly_Margin_A1==98 ps 10
1061 06:11:27.551199 TrainedVREFDQ_A0==77
1062 06:11:27.551725 TrainedVREFDQ_A1==77
1063 06:11:27.552091 VrefDac_Margin_A0==23
1064 06:11:27.556669 DeviceVref_Margin_A0==37
1065 06:11:27.556933 VrefDac_Margin_A1==24
1066 06:11:27.562368 DeviceVref_Margin_A1==37
1067 06:11:27.562884
1068 06:11:27.563346 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 06:11:27.563798
1070 06:11:27.595953 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000019 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1071 06:11:27.596565 2D training succeed
1072 06:11:27.601660 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 06:11:27.607218 auto size-- 65535DDR cs0 size: 2048MB
1074 06:11:27.607793 DDR cs1 size: 2048MB
1075 06:11:27.612796 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 06:11:27.613310 cs0 DataBus test pass
1077 06:11:27.618379 cs1 DataBus test pass
1078 06:11:27.618879 cs0 AddrBus test pass
1079 06:11:27.619337 cs1 AddrBus test pass
1080 06:11:27.619784
1081 06:11:27.623965 100bdlr_step_size ps== 420
1082 06:11:27.624527 result report
1083 06:11:27.629586 boot times 0Enable ddr reg access
1084 06:11:27.634872 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 06:11:27.648259 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 06:11:28.222108 0.0;M3 CHK:0;cm4_sp_mode 0
1087 06:11:28.222767 MVN_1=0x00000000
1088 06:11:28.227628 MVN_2=0x00000000
1089 06:11:28.233316 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 06:11:28.233894 OPS=0x10
1091 06:11:28.234373 ring efuse init
1092 06:11:28.234832 chipver efuse init
1093 06:11:28.241432 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 06:11:28.241989 [0.018960 Inits done]
1095 06:11:28.248201 secure task start!
1096 06:11:28.248770 high task start!
1097 06:11:28.249242 low task start!
1098 06:11:28.249696 run into bl31
1099 06:11:28.255748 NOTICE: BL31: v1.3(release):4fc40b1
1100 06:11:28.263489 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 06:11:28.264077 NOTICE: BL31: G12A normal boot!
1102 06:11:28.289441 NOTICE: BL31: BL33 decompress pass
1103 06:11:28.295007 ERROR: Error initializing runtime service opteed_fast
1104 06:11:29.528121
1105 06:11:29.528828
1106 06:11:29.536538 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 06:11:29.537111
1108 06:11:29.537590 Model: Libre Computer AML-A311D-CC Alta
1109 06:11:29.744839 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 06:11:29.768456 DRAM: 2 GiB (effective 3.8 GiB)
1111 06:11:29.911270 Core: 408 devices, 31 uclasses, devicetree: separate
1112 06:11:29.917065 WDT: Not starting watchdog@f0d0
1113 06:11:29.949494 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 06:11:29.961837 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 06:11:29.966805 ** Bad device specification mmc 0 **
1116 06:11:29.977199 Card did not respond to voltage select! : -110
1117 06:11:29.984753 ** Bad device specification mmc 0 **
1118 06:11:29.985156 Couldn't find partition mmc 0
1119 06:11:29.993135 Card did not respond to voltage select! : -110
1120 06:11:29.998681 ** Bad device specification mmc 0 **
1121 06:11:29.999228 Couldn't find partition mmc 0
1122 06:11:30.003763 Error: could not access storage.
1123 06:11:30.348246 Net: eth0: ethernet@ff3f0000
1124 06:11:30.348967 starting USB...
1125 06:11:30.599197 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 06:11:30.599903 Starting the controller
1127 06:11:30.606232 USB XHCI 1.10
1128 06:11:32.159944 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 06:11:32.167896 scanning usb for storage devices... 0 Storage Device(s) found
1131 06:11:32.219889 Hit any key to stop autoboot: 1
1132 06:11:32.220874 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1133 06:11:32.221510 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1134 06:11:32.222017 Setting prompt string to ['=>']
1135 06:11:32.222544 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1136 06:11:32.235848 0
1137 06:11:32.236910 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 06:11:32.237444 Sending with 10 millisecond of delay
1140 06:11:33.373801 => setenv autoload no
1141 06:11:33.384765 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1142 06:11:33.390373 setenv autoload no
1143 06:11:33.391231 Sending with 10 millisecond of delay
1145 06:11:35.188425 => setenv initrd_high 0xffffffff
1146 06:11:35.199273 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1147 06:11:35.200342 setenv initrd_high 0xffffffff
1148 06:11:35.201129 Sending with 10 millisecond of delay
1150 06:11:36.817499 => setenv fdt_high 0xffffffff
1151 06:11:36.828343 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1152 06:11:36.829262 setenv fdt_high 0xffffffff
1153 06:11:36.830032 Sending with 10 millisecond of delay
1155 06:11:37.121975 => dhcp
1156 06:11:37.132801 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1157 06:11:37.133771 dhcp
1158 06:11:37.134267 Speed: 1000, full duplex
1159 06:11:37.134730 BOOTP broadcast 1
1160 06:11:37.380824 BOOTP broadcast 2
1161 06:11:37.397494 DHCP client bound to address 192.168.6.33 (264 ms)
1162 06:11:37.398667 Sending with 10 millisecond of delay
1164 06:11:39.077442 => setenv serverip 192.168.6.2
1165 06:11:39.088512 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1166 06:11:39.089753 setenv serverip 192.168.6.2
1167 06:11:39.090702 Sending with 10 millisecond of delay
1169 06:11:42.818122 => tftpboot 0x01080000 796671/tftp-deploy-kmrholan/kernel/uImage
1170 06:11:42.829151 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1171 06:11:42.830315 tftpboot 0x01080000 796671/tftp-deploy-kmrholan/kernel/uImage
1172 06:11:42.830893 Speed: 1000, full duplex
1173 06:11:42.831426 Using ethernet@ff3f0000 device
1174 06:11:42.832320 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1175 06:11:42.837690 Filename '796671/tftp-deploy-kmrholan/kernel/uImage'.
1176 06:11:42.841655 Load address: 0x1080000
1177 06:11:44.296176 Loading: *################# UDP wrong checksum 000000ff 00006aae
1178 06:11:44.317157 UDP wrong checksum 000000ff 0000ffa0
1179 06:11:44.576150 ### UDP wrong checksum 000000ff 0000520c
1180 06:11:44.597292 UDP wrong checksum 000000ff 0000eefe
1181 06:11:47.201666 ############################## 43.6 MiB
1182 06:11:47.202320 10 MiB/s
1183 06:11:47.202780 done
1184 06:11:47.205853 Bytes transferred = 45713984 (2b98a40 hex)
1185 06:11:47.206637 Sending with 10 millisecond of delay
1187 06:11:51.894534 => tftpboot 0x08000000 796671/tftp-deploy-kmrholan/ramdisk/ramdisk.cpio.gz.uboot
1188 06:11:51.905312 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
1189 06:11:51.906184 tftpboot 0x08000000 796671/tftp-deploy-kmrholan/ramdisk/ramdisk.cpio.gz.uboot
1190 06:11:51.906611 Speed: 1000, full duplex
1191 06:11:51.907012 Using ethernet@ff3f0000 device
1192 06:11:51.907964 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1193 06:11:51.916535 Filename '796671/tftp-deploy-kmrholan/ramdisk/ramdisk.cpio.gz.uboot'.
1194 06:11:51.916978 Load address: 0x8000000
1195 06:11:54.445537 Loading: *################################################# UDP wrong checksum 00000005 00007fd3
1196 06:11:59.444210 T UDP wrong checksum 00000005 00007fd3
1197 06:12:09.447022 T T UDP wrong checksum 00000005 00007fd3
1198 06:12:22.031313 T T UDP wrong checksum 000000ff 0000854d
1199 06:12:22.042906 UDP wrong checksum 000000ff 00000a40
1200 06:12:29.448943 T UDP wrong checksum 00000005 00007fd3
1201 06:12:49.456112 T T T T
1202 06:12:49.456796 Retry count exceeded; starting again
1204 06:12:49.458355 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1207 06:12:49.460542 end: 2.4 uboot-commands (duration 00:01:55) [common]
1209 06:12:49.462098 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1211 06:12:49.463210 end: 2 uboot-action (duration 00:01:55) [common]
1213 06:12:49.464927 Cleaning after the job
1214 06:12:49.465528 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/ramdisk
1215 06:12:49.466898 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/kernel
1216 06:12:49.497974 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/dtb
1217 06:12:49.499583 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/nfsrootfs
1218 06:12:49.541228 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796671/tftp-deploy-kmrholan/modules
1219 06:12:49.545429 start: 4.1 power-off (timeout 00:00:30) [common]
1220 06:12:49.546003 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1221 06:12:49.587840 >> OK - accepted request
1222 06:12:49.589778 Returned 0 in 0 seconds
1223 06:12:49.690538 end: 4.1 power-off (duration 00:00:00) [common]
1225 06:12:49.691580 start: 4.2 read-feedback (timeout 00:10:00) [common]
1226 06:12:49.692306 Listened to connection for namespace 'common' for up to 1s
1227 06:12:50.693244 Finalising connection for namespace 'common'
1228 06:12:50.694014 Disconnecting from shell: Finalise
1229 06:12:50.694596 =>
1230 06:12:50.795662 end: 4.2 read-feedback (duration 00:00:01) [common]
1231 06:12:50.796409 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796671
1232 06:12:53.917813 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796671
1233 06:12:53.918403 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.