Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:00:55.252885 lava-dispatcher, installed at version: 2024.01
2 06:00:55.253708 start: 0 validate
3 06:00:55.254266 Start time: 2024-10-03 06:00:55.254232+00:00 (UTC)
4 06:00:55.254822 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:00:55.255391 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 06:00:55.293632 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:00:55.294342 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:00:55.325228 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:00:55.325907 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:00:55.360874 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:00:55.361406 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:00:55.395701 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 06:00:55.396245 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241003%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 06:00:55.437090 validate duration: 0.18
16 06:00:55.438007 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:00:55.438371 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:00:55.438723 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:00:55.439354 Not decompressing ramdisk as can be used compressed.
20 06:00:55.439873 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 06:00:55.440189 saving as /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/ramdisk/initrd.cpio.gz
22 06:00:55.440471 total size: 5628140 (5 MB)
23 06:00:55.475360 progress 0 % (0 MB)
24 06:00:55.479740 progress 5 % (0 MB)
25 06:00:55.483932 progress 10 % (0 MB)
26 06:00:55.487581 progress 15 % (0 MB)
27 06:00:55.491648 progress 20 % (1 MB)
28 06:00:55.495277 progress 25 % (1 MB)
29 06:00:55.499279 progress 30 % (1 MB)
30 06:00:55.503361 progress 35 % (1 MB)
31 06:00:55.506985 progress 40 % (2 MB)
32 06:00:55.510979 progress 45 % (2 MB)
33 06:00:55.514592 progress 50 % (2 MB)
34 06:00:55.518668 progress 55 % (2 MB)
35 06:00:55.522662 progress 60 % (3 MB)
36 06:00:55.526225 progress 65 % (3 MB)
37 06:00:55.530296 progress 70 % (3 MB)
38 06:00:55.533880 progress 75 % (4 MB)
39 06:00:55.537798 progress 80 % (4 MB)
40 06:00:55.541430 progress 85 % (4 MB)
41 06:00:55.545342 progress 90 % (4 MB)
42 06:00:55.548987 progress 95 % (5 MB)
43 06:00:55.552320 progress 100 % (5 MB)
44 06:00:55.553001 5 MB downloaded in 0.11 s (47.70 MB/s)
45 06:00:55.553572 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:00:55.554501 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:00:55.554811 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:00:55.555095 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:00:55.555590 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig/gcc-12/kernel/Image
51 06:00:55.555850 saving as /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/kernel/Image
52 06:00:55.556103 total size: 45713920 (43 MB)
53 06:00:55.556332 No compression specified
54 06:00:55.587971 progress 0 % (0 MB)
55 06:00:55.616441 progress 5 % (2 MB)
56 06:00:55.644853 progress 10 % (4 MB)
57 06:00:55.673476 progress 15 % (6 MB)
58 06:00:55.701521 progress 20 % (8 MB)
59 06:00:55.729379 progress 25 % (10 MB)
60 06:00:55.757706 progress 30 % (13 MB)
61 06:00:55.786003 progress 35 % (15 MB)
62 06:00:55.814299 progress 40 % (17 MB)
63 06:00:55.842064 progress 45 % (19 MB)
64 06:00:55.870366 progress 50 % (21 MB)
65 06:00:55.899019 progress 55 % (24 MB)
66 06:00:55.926413 progress 60 % (26 MB)
67 06:00:55.953358 progress 65 % (28 MB)
68 06:00:55.980891 progress 70 % (30 MB)
69 06:00:56.008346 progress 75 % (32 MB)
70 06:00:56.035772 progress 80 % (34 MB)
71 06:00:56.062831 progress 85 % (37 MB)
72 06:00:56.090857 progress 90 % (39 MB)
73 06:00:56.118762 progress 95 % (41 MB)
74 06:00:56.146054 progress 100 % (43 MB)
75 06:00:56.146602 43 MB downloaded in 0.59 s (73.83 MB/s)
76 06:00:56.147087 end: 1.2.1 http-download (duration 00:00:01) [common]
78 06:00:56.147922 end: 1.2 download-retry (duration 00:00:01) [common]
79 06:00:56.148243 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:00:56.148519 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:00:56.149008 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 06:00:56.149258 saving as /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/dtb/meson-g12b-a311d-libretech-cc.dtb
83 06:00:56.149468 total size: 54703 (0 MB)
84 06:00:56.149678 No compression specified
85 06:00:56.189878 progress 59 % (0 MB)
86 06:00:56.190741 progress 100 % (0 MB)
87 06:00:56.191315 0 MB downloaded in 0.04 s (1.25 MB/s)
88 06:00:56.191813 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:00:56.192726 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:00:56.193006 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:00:56.193291 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:00:56.193779 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 06:00:56.194037 saving as /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/nfsrootfs/full.rootfs.tar
95 06:00:56.194251 total size: 474398908 (452 MB)
96 06:00:56.194471 Using unxz to decompress xz
97 06:00:56.231069 progress 0 % (0 MB)
98 06:00:57.390379 progress 5 % (22 MB)
99 06:00:58.874747 progress 10 % (45 MB)
100 06:00:59.358958 progress 15 % (67 MB)
101 06:01:00.290714 progress 20 % (90 MB)
102 06:01:00.906664 progress 25 % (113 MB)
103 06:01:01.272356 progress 30 % (135 MB)
104 06:01:01.959663 progress 35 % (158 MB)
105 06:01:02.913282 progress 40 % (181 MB)
106 06:01:03.724145 progress 45 % (203 MB)
107 06:01:04.293083 progress 50 % (226 MB)
108 06:01:04.931349 progress 55 % (248 MB)
109 06:01:06.117178 progress 60 % (271 MB)
110 06:01:07.524009 progress 65 % (294 MB)
111 06:01:09.213504 progress 70 % (316 MB)
112 06:01:12.328996 progress 75 % (339 MB)
113 06:01:14.790407 progress 80 % (361 MB)
114 06:01:17.738193 progress 85 % (384 MB)
115 06:01:21.030348 progress 90 % (407 MB)
116 06:01:24.242795 progress 95 % (429 MB)
117 06:01:27.447097 progress 100 % (452 MB)
118 06:01:27.461033 452 MB downloaded in 31.27 s (14.47 MB/s)
119 06:01:27.461742 end: 1.4.1 http-download (duration 00:00:31) [common]
121 06:01:27.463264 end: 1.4 download-retry (duration 00:00:31) [common]
122 06:01:27.463581 start: 1.5 download-retry (timeout 00:09:28) [common]
123 06:01:27.463851 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 06:01:27.466290 downloading http://storage.kernelci.org/next/master/next-20241003/arm64/defconfig/gcc-12/modules.tar.xz
125 06:01:27.467624 saving as /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/modules/modules.tar
126 06:01:27.467844 total size: 11627692 (11 MB)
127 06:01:27.468094 Using unxz to decompress xz
128 06:01:27.526413 progress 0 % (0 MB)
129 06:01:27.596968 progress 5 % (0 MB)
130 06:01:27.675195 progress 10 % (1 MB)
131 06:01:27.761914 progress 15 % (1 MB)
132 06:01:27.838894 progress 20 % (2 MB)
133 06:01:27.921798 progress 25 % (2 MB)
134 06:01:28.001817 progress 30 % (3 MB)
135 06:01:28.081697 progress 35 % (3 MB)
136 06:01:28.155829 progress 40 % (4 MB)
137 06:01:28.233009 progress 45 % (5 MB)
138 06:01:28.310654 progress 50 % (5 MB)
139 06:01:28.387340 progress 55 % (6 MB)
140 06:01:28.467154 progress 60 % (6 MB)
141 06:01:28.552756 progress 65 % (7 MB)
142 06:01:28.634237 progress 70 % (7 MB)
143 06:01:28.732462 progress 75 % (8 MB)
144 06:01:28.822884 progress 80 % (8 MB)
145 06:01:28.904387 progress 85 % (9 MB)
146 06:01:28.980152 progress 90 % (10 MB)
147 06:01:29.056410 progress 95 % (10 MB)
148 06:01:29.128780 progress 100 % (11 MB)
149 06:01:29.142329 11 MB downloaded in 1.67 s (6.62 MB/s)
150 06:01:29.143475 end: 1.5.1 http-download (duration 00:00:02) [common]
152 06:01:29.145334 end: 1.5 download-retry (duration 00:00:02) [common]
153 06:01:29.145904 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 06:01:29.146475 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 06:01:44.874001 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/796638/extract-nfsrootfs-pubf2htr
156 06:01:44.874595 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 06:01:44.874883 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 06:01:44.875482 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq
159 06:01:44.875915 makedir: /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin
160 06:01:44.876294 makedir: /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/tests
161 06:01:44.876636 makedir: /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/results
162 06:01:44.876972 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-add-keys
163 06:01:44.877496 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-add-sources
164 06:01:44.878009 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-background-process-start
165 06:01:44.878510 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-background-process-stop
166 06:01:44.879051 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-common-functions
167 06:01:44.879554 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-echo-ipv4
168 06:01:44.880083 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-install-packages
169 06:01:44.880620 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-installed-packages
170 06:01:44.881113 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-os-build
171 06:01:44.881596 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-probe-channel
172 06:01:44.882120 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-probe-ip
173 06:01:44.882627 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-target-ip
174 06:01:44.883105 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-target-mac
175 06:01:44.883595 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-target-storage
176 06:01:44.884117 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-test-case
177 06:01:44.884620 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-test-event
178 06:01:44.885100 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-test-feedback
179 06:01:44.885663 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-test-raise
180 06:01:44.886152 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-test-reference
181 06:01:44.886635 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-test-runner
182 06:01:44.887115 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-test-set
183 06:01:44.887580 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-test-shell
184 06:01:44.888094 Updating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-install-packages (oe)
185 06:01:44.888650 Updating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/bin/lava-installed-packages (oe)
186 06:01:44.889098 Creating /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/environment
187 06:01:44.889469 LAVA metadata
188 06:01:44.889725 - LAVA_JOB_ID=796638
189 06:01:44.889940 - LAVA_DISPATCHER_IP=192.168.6.2
190 06:01:44.890298 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 06:01:44.891275 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 06:01:44.891587 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 06:01:44.891797 skipped lava-vland-overlay
194 06:01:44.892064 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 06:01:44.892328 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 06:01:44.892547 skipped lava-multinode-overlay
197 06:01:44.892787 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 06:01:44.893035 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 06:01:44.893289 Loading test definitions
200 06:01:44.893566 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 06:01:44.893787 Using /lava-796638 at stage 0
202 06:01:44.895050 uuid=796638_1.6.2.4.1 testdef=None
203 06:01:44.895362 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 06:01:44.895624 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 06:01:44.897433 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 06:01:44.898227 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 06:01:44.900468 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 06:01:44.901303 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 06:01:44.903393 runner path: /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 796638_1.6.2.4.1
212 06:01:44.903970 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 06:01:44.904748 Creating lava-test-runner.conf files
215 06:01:44.904947 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796638/lava-overlay-rbjzq2lq/lava-796638/0 for stage 0
216 06:01:44.905294 - 0_v4l2-decoder-conformance-h265
217 06:01:44.905636 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 06:01:44.905906 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 06:01:44.927679 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 06:01:44.928096 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 06:01:44.928388 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 06:01:44.928696 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 06:01:44.929000 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 06:01:45.583008 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 06:01:45.583487 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 06:01:45.583740 extracting modules file /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796638/extract-nfsrootfs-pubf2htr
227 06:01:47.207863 extracting modules file /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796638/extract-overlay-ramdisk-s4jrmsel/ramdisk
228 06:01:48.632808 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 06:01:48.633300 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 06:01:48.633582 [common] Applying overlay to NFS
231 06:01:48.633796 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796638/compress-overlay-sm7e34ha/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796638/extract-nfsrootfs-pubf2htr
232 06:01:48.663548 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 06:01:48.664012 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 06:01:48.664298 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 06:01:48.664531 Converting downloaded kernel to a uImage
236 06:01:48.664839 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/kernel/Image /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/kernel/uImage
237 06:01:49.141309 output: Image Name:
238 06:01:49.141719 output: Created: Thu Oct 3 06:01:48 2024
239 06:01:49.141929 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 06:01:49.142205 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 06:01:49.142412 output: Load Address: 01080000
242 06:01:49.142611 output: Entry Point: 01080000
243 06:01:49.142810 output:
244 06:01:49.143146 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 06:01:49.143455 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 06:01:49.143733 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 06:01:49.144019 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 06:01:49.144296 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 06:01:49.144550 Building ramdisk /var/lib/lava/dispatcher/tmp/796638/extract-overlay-ramdisk-s4jrmsel/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796638/extract-overlay-ramdisk-s4jrmsel/ramdisk
250 06:01:51.306852 >> 166933 blocks
251 06:01:59.158454 Adding RAMdisk u-boot header.
252 06:01:59.158900 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796638/extract-overlay-ramdisk-s4jrmsel/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796638/extract-overlay-ramdisk-s4jrmsel/ramdisk.cpio.gz.uboot
253 06:01:59.408730 output: Image Name:
254 06:01:59.409154 output: Created: Thu Oct 3 06:01:59 2024
255 06:01:59.409710 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 06:01:59.410191 output: Data Size: 23439199 Bytes = 22889.84 KiB = 22.35 MiB
257 06:01:59.410645 output: Load Address: 00000000
258 06:01:59.411091 output: Entry Point: 00000000
259 06:01:59.411534 output:
260 06:01:59.412734 rename /var/lib/lava/dispatcher/tmp/796638/extract-overlay-ramdisk-s4jrmsel/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/ramdisk/ramdisk.cpio.gz.uboot
261 06:01:59.413537 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 06:01:59.414155 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 06:01:59.414751 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 06:01:59.415263 No LXC device requested
265 06:01:59.415825 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 06:01:59.416447 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 06:01:59.417015 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 06:01:59.417476 Checking files for TFTP limit of 4294967296 bytes.
269 06:01:59.420525 end: 1 tftp-deploy (duration 00:01:04) [common]
270 06:01:59.421187 start: 2 uboot-action (timeout 00:05:00) [common]
271 06:01:59.421785 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 06:01:59.422342 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 06:01:59.422906 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 06:01:59.423495 Using kernel file from prepare-kernel: 796638/tftp-deploy-vi3robbr/kernel/uImage
275 06:01:59.424221 substitutions:
276 06:01:59.424687 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 06:01:59.425133 - {DTB_ADDR}: 0x01070000
278 06:01:59.425575 - {DTB}: 796638/tftp-deploy-vi3robbr/dtb/meson-g12b-a311d-libretech-cc.dtb
279 06:01:59.426022 - {INITRD}: 796638/tftp-deploy-vi3robbr/ramdisk/ramdisk.cpio.gz.uboot
280 06:01:59.426463 - {KERNEL_ADDR}: 0x01080000
281 06:01:59.426934 - {KERNEL}: 796638/tftp-deploy-vi3robbr/kernel/uImage
282 06:01:59.427402 - {LAVA_MAC}: None
283 06:01:59.427899 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/796638/extract-nfsrootfs-pubf2htr
284 06:01:59.428382 - {NFS_SERVER_IP}: 192.168.6.2
285 06:01:59.428825 - {PRESEED_CONFIG}: None
286 06:01:59.429261 - {PRESEED_LOCAL}: None
287 06:01:59.429694 - {RAMDISK_ADDR}: 0x08000000
288 06:01:59.430123 - {RAMDISK}: 796638/tftp-deploy-vi3robbr/ramdisk/ramdisk.cpio.gz.uboot
289 06:01:59.430557 - {ROOT_PART}: None
290 06:01:59.430989 - {ROOT}: None
291 06:01:59.431418 - {SERVER_IP}: 192.168.6.2
292 06:01:59.431852 - {TEE_ADDR}: 0x83000000
293 06:01:59.432307 - {TEE}: None
294 06:01:59.432742 Parsed boot commands:
295 06:01:59.433161 - setenv autoload no
296 06:01:59.433591 - setenv initrd_high 0xffffffff
297 06:01:59.434023 - setenv fdt_high 0xffffffff
298 06:01:59.434450 - dhcp
299 06:01:59.434878 - setenv serverip 192.168.6.2
300 06:01:59.435308 - tftpboot 0x01080000 796638/tftp-deploy-vi3robbr/kernel/uImage
301 06:01:59.435736 - tftpboot 0x08000000 796638/tftp-deploy-vi3robbr/ramdisk/ramdisk.cpio.gz.uboot
302 06:01:59.436199 - tftpboot 0x01070000 796638/tftp-deploy-vi3robbr/dtb/meson-g12b-a311d-libretech-cc.dtb
303 06:01:59.436634 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/796638/extract-nfsrootfs-pubf2htr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 06:01:59.437081 - bootm 0x01080000 0x08000000 0x01070000
305 06:01:59.437654 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 06:01:59.439314 start: 2.3 connect-device (timeout 00:05:00) [common]
308 06:01:59.439787 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 06:01:59.455582 Setting prompt string to ['lava-test: # ']
310 06:01:59.457223 end: 2.3 connect-device (duration 00:00:00) [common]
311 06:01:59.457898 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 06:01:59.458518 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 06:01:59.459422 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 06:01:59.460789 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 06:01:59.497674 >> OK - accepted request
316 06:01:59.499932 Returned 0 in 0 seconds
317 06:01:59.601310 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 06:01:59.603172 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 06:01:59.603822 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 06:01:59.604454 Setting prompt string to ['Hit any key to stop autoboot']
322 06:01:59.604980 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 06:01:59.606695 Trying 192.168.56.21...
324 06:01:59.607232 Connected to conserv1.
325 06:01:59.607715 Escape character is '^]'.
326 06:01:59.608223
327 06:01:59.608702 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 06:01:59.609187
329 06:02:10.613687 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 06:02:10.614135 bl2_stage_init 0x01
331 06:02:10.614362 bl2_stage_init 0x81
332 06:02:10.619175 hw id: 0x0000 - pwm id 0x01
333 06:02:10.619526 bl2_stage_init 0xc1
334 06:02:10.619740 bl2_stage_init 0x02
335 06:02:10.619944
336 06:02:10.624797 L0:00000000
337 06:02:10.625160 L1:20000703
338 06:02:10.625381 L2:00008067
339 06:02:10.625588 L3:14000000
340 06:02:10.630338 B2:00402000
341 06:02:10.630674 B1:e0f83180
342 06:02:10.630894
343 06:02:10.631270 TE: 58159
344 06:02:10.631711
345 06:02:10.636198 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 06:02:10.636758
347 06:02:10.637197 Board ID = 1
348 06:02:10.641729 Set A53 clk to 24M
349 06:02:10.642274 Set A73 clk to 24M
350 06:02:10.642715 Set clk81 to 24M
351 06:02:10.647241 A53 clk: 1200 MHz
352 06:02:10.647786 A73 clk: 1200 MHz
353 06:02:10.648273 CLK81: 166.6M
354 06:02:10.648717 smccc: 00012ab5
355 06:02:10.652888 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 06:02:10.658568 board id: 1
357 06:02:10.664405 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 06:02:10.674966 fw parse done
359 06:02:10.681112 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 06:02:10.723353 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 06:02:10.734244 PIEI prepare done
362 06:02:10.734648 fastboot data load
363 06:02:10.734880 fastboot data verify
364 06:02:10.739825 verify result: 266
365 06:02:10.745408 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 06:02:10.745742 LPDDR4 probe
367 06:02:10.745969 ddr clk to 1584MHz
368 06:02:10.753377 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 06:02:10.790711
370 06:02:10.791168 dmc_version 0001
371 06:02:10.797382 Check phy result
372 06:02:10.803284 INFO : End of CA training
373 06:02:10.803727 INFO : End of initialization
374 06:02:10.808825 INFO : Training has run successfully!
375 06:02:10.809207 Check phy result
376 06:02:10.814462 INFO : End of initialization
377 06:02:10.814878 INFO : End of read enable training
378 06:02:10.820054 INFO : End of fine write leveling
379 06:02:10.825704 INFO : End of Write leveling coarse delay
380 06:02:10.826098 INFO : Training has run successfully!
381 06:02:10.826330 Check phy result
382 06:02:10.831280 INFO : End of initialization
383 06:02:10.831717 INFO : End of read dq deskew training
384 06:02:10.836834 INFO : End of MPR read delay center optimization
385 06:02:10.842414 INFO : End of write delay center optimization
386 06:02:10.848072 INFO : End of read delay center optimization
387 06:02:10.848545 INFO : End of max read latency training
388 06:02:10.853631 INFO : Training has run successfully!
389 06:02:10.854014 1D training succeed
390 06:02:10.862895 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 06:02:10.910417 Check phy result
392 06:02:10.910859 INFO : End of initialization
393 06:02:10.932251 INFO : End of 2D read delay Voltage center optimization
394 06:02:10.951647 INFO : End of 2D read delay Voltage center optimization
395 06:02:11.003736 INFO : End of 2D write delay Voltage center optimization
396 06:02:11.053086 INFO : End of 2D write delay Voltage center optimization
397 06:02:11.058895 INFO : Training has run successfully!
398 06:02:11.059474
399 06:02:11.059750 channel==0
400 06:02:11.064265 RxClkDly_Margin_A0==88 ps 9
401 06:02:11.064650 TxDqDly_Margin_A0==98 ps 10
402 06:02:11.070130 RxClkDly_Margin_A1==88 ps 9
403 06:02:11.070567 TxDqDly_Margin_A1==88 ps 9
404 06:02:11.070855 TrainedVREFDQ_A0==74
405 06:02:11.075426 TrainedVREFDQ_A1==74
406 06:02:11.075921 VrefDac_Margin_A0==25
407 06:02:11.076398 DeviceVref_Margin_A0==40
408 06:02:11.081006 VrefDac_Margin_A1==25
409 06:02:11.081508 DeviceVref_Margin_A1==40
410 06:02:11.081943
411 06:02:11.082375
412 06:02:11.082808 channel==1
413 06:02:11.086592 RxClkDly_Margin_A0==88 ps 9
414 06:02:11.087088 TxDqDly_Margin_A0==98 ps 10
415 06:02:11.092231 RxClkDly_Margin_A1==88 ps 9
416 06:02:11.092737 TxDqDly_Margin_A1==88 ps 9
417 06:02:11.099081 TrainedVREFDQ_A0==77
418 06:02:11.099560 TrainedVREFDQ_A1==77
419 06:02:11.100024 VrefDac_Margin_A0==23
420 06:02:11.103455 DeviceVref_Margin_A0==37
421 06:02:11.103825 VrefDac_Margin_A1==24
422 06:02:11.108993 DeviceVref_Margin_A1==37
423 06:02:11.109425
424 06:02:11.109662 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 06:02:11.109866
426 06:02:11.142567 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 06:02:11.143029 2D training succeed
428 06:02:11.148188 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 06:02:11.153776 auto size-- 65535DDR cs0 size: 2048MB
430 06:02:11.154134 DDR cs1 size: 2048MB
431 06:02:11.159385 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 06:02:11.159746 cs0 DataBus test pass
433 06:02:11.165189 cs1 DataBus test pass
434 06:02:11.165789 cs0 AddrBus test pass
435 06:02:11.166225 cs1 AddrBus test pass
436 06:02:11.166792
437 06:02:11.170719 100bdlr_step_size ps== 420
438 06:02:11.171260 result report
439 06:02:11.177138 boot times 0Enable ddr reg access
440 06:02:11.181454 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 06:02:11.194952 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 06:02:11.768784 0.0;M3 CHK:0;cm4_sp_mode 0
443 06:02:11.769456 MVN_1=0x00000000
444 06:02:11.774152 MVN_2=0x00000000
445 06:02:11.779864 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 06:02:11.780433 OPS=0x10
447 06:02:11.780875 ring efuse init
448 06:02:11.781311 chipver efuse init
449 06:02:11.788183 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 06:02:11.788756 [0.018961 Inits done]
451 06:02:11.789193 secure task start!
452 06:02:11.795658 high task start!
453 06:02:11.796235 low task start!
454 06:02:11.796687 run into bl31
455 06:02:11.802350 NOTICE: BL31: v1.3(release):4fc40b1
456 06:02:11.810232 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 06:02:11.810773 NOTICE: BL31: G12A normal boot!
458 06:02:11.835341 NOTICE: BL31: BL33 decompress pass
459 06:02:11.841012 ERROR: Error initializing runtime service opteed_fast
460 06:02:13.073962
461 06:02:13.074603
462 06:02:13.082275 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 06:02:13.082789
464 06:02:13.083244 Model: Libre Computer AML-A311D-CC Alta
465 06:02:13.290502 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 06:02:13.314202 DRAM: 2 GiB (effective 3.8 GiB)
467 06:02:13.457165 Core: 408 devices, 31 uclasses, devicetree: separate
468 06:02:13.463050 WDT: Not starting watchdog@f0d0
469 06:02:13.495259 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 06:02:13.507716 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 06:02:13.511757 ** Bad device specification mmc 0 **
472 06:02:13.523060 Card did not respond to voltage select! : -110
473 06:02:13.530581 ** Bad device specification mmc 0 **
474 06:02:13.531120 Couldn't find partition mmc 0
475 06:02:13.539054 Card did not respond to voltage select! : -110
476 06:02:13.544582 ** Bad device specification mmc 0 **
477 06:02:13.545116 Couldn't find partition mmc 0
478 06:02:13.549441 Error: could not access storage.
479 06:02:14.813848 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 06:02:14.814228 bl2_stage_init 0x01
481 06:02:14.814447 bl2_stage_init 0x81
482 06:02:14.819387 hw id: 0x0000 - pwm id 0x01
483 06:02:14.819671 bl2_stage_init 0xc1
484 06:02:14.819883 bl2_stage_init 0x02
485 06:02:14.820131
486 06:02:14.824994 L0:00000000
487 06:02:14.825294 L1:20000703
488 06:02:14.825509 L2:00008067
489 06:02:14.825715 L3:14000000
490 06:02:14.827872 B2:00402000
491 06:02:14.828157 B1:e0f83180
492 06:02:14.828369
493 06:02:14.828574 TE: 58150
494 06:02:14.828775
495 06:02:14.839056 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 06:02:14.839357
497 06:02:14.839576 Board ID = 1
498 06:02:14.839780 Set A53 clk to 24M
499 06:02:14.840005 Set A73 clk to 24M
500 06:02:14.844694 Set clk81 to 24M
501 06:02:14.844968 A53 clk: 1200 MHz
502 06:02:14.845177 A73 clk: 1200 MHz
503 06:02:14.850280 CLK81: 166.6M
504 06:02:14.850560 smccc: 00012aac
505 06:02:14.855944 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 06:02:14.856469 board id: 1
507 06:02:14.863718 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 06:02:14.875154 fw parse done
509 06:02:14.880197 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 06:02:14.923027 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 06:02:14.934644 PIEI prepare done
512 06:02:14.934975 fastboot data load
513 06:02:14.935201 fastboot data verify
514 06:02:14.940303 verify result: 266
515 06:02:14.945894 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 06:02:14.946193 LPDDR4 probe
517 06:02:14.946409 ddr clk to 1584MHz
518 06:02:14.953062 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 06:02:14.990307
520 06:02:14.990688 dmc_version 0001
521 06:02:14.997086 Check phy result
522 06:02:15.003717 INFO : End of CA training
523 06:02:15.004084 INFO : End of initialization
524 06:02:15.009297 INFO : Training has run successfully!
525 06:02:15.009608 Check phy result
526 06:02:15.014875 INFO : End of initialization
527 06:02:15.015185 INFO : End of read enable training
528 06:02:15.018238 INFO : End of fine write leveling
529 06:02:15.023716 INFO : End of Write leveling coarse delay
530 06:02:15.029370 INFO : Training has run successfully!
531 06:02:15.029692 Check phy result
532 06:02:15.029908 INFO : End of initialization
533 06:02:15.035338 INFO : End of read dq deskew training
534 06:02:15.040596 INFO : End of MPR read delay center optimization
535 06:02:15.040974 INFO : End of write delay center optimization
536 06:02:15.046209 INFO : End of read delay center optimization
537 06:02:15.051802 INFO : End of max read latency training
538 06:02:15.052193 INFO : Training has run successfully!
539 06:02:15.057416 1D training succeed
540 06:02:15.062326 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 06:02:15.110901 Check phy result
542 06:02:15.111248 INFO : End of initialization
543 06:02:15.131879 INFO : End of 2D read delay Voltage center optimization
544 06:02:15.152306 INFO : End of 2D read delay Voltage center optimization
545 06:02:15.203553 INFO : End of 2D write delay Voltage center optimization
546 06:02:15.253737 INFO : End of 2D write delay Voltage center optimization
547 06:02:15.259277 INFO : Training has run successfully!
548 06:02:15.259552
549 06:02:15.259772 channel==0
550 06:02:15.264922 RxClkDly_Margin_A0==88 ps 9
551 06:02:15.265211 TxDqDly_Margin_A0==98 ps 10
552 06:02:15.270490 RxClkDly_Margin_A1==88 ps 9
553 06:02:15.270768 TxDqDly_Margin_A1==98 ps 10
554 06:02:15.270988 TrainedVREFDQ_A0==74
555 06:02:15.276215 TrainedVREFDQ_A1==74
556 06:02:15.276508 VrefDac_Margin_A0==25
557 06:02:15.276723 DeviceVref_Margin_A0==40
558 06:02:15.281657 VrefDac_Margin_A1==25
559 06:02:15.281932 DeviceVref_Margin_A1==40
560 06:02:15.282147
561 06:02:15.282355
562 06:02:15.287219 channel==1
563 06:02:15.287484 RxClkDly_Margin_A0==98 ps 10
564 06:02:15.287696 TxDqDly_Margin_A0==88 ps 9
565 06:02:15.292824 RxClkDly_Margin_A1==88 ps 9
566 06:02:15.293097 TxDqDly_Margin_A1==88 ps 9
567 06:02:15.298404 TrainedVREFDQ_A0==76
568 06:02:15.298667 TrainedVREFDQ_A1==77
569 06:02:15.298882 VrefDac_Margin_A0==22
570 06:02:15.304079 DeviceVref_Margin_A0==38
571 06:02:15.304343 VrefDac_Margin_A1==24
572 06:02:15.309619 DeviceVref_Margin_A1==37
573 06:02:15.309879
574 06:02:15.310091 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 06:02:15.310298
576 06:02:15.343228 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 06:02:15.343554 2D training succeed
578 06:02:15.348818 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 06:02:15.354434 auto size-- 65535DDR cs0 size: 2048MB
580 06:02:15.354707 DDR cs1 size: 2048MB
581 06:02:15.360106 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 06:02:15.360368 cs0 DataBus test pass
583 06:02:15.365616 cs1 DataBus test pass
584 06:02:15.365880 cs0 AddrBus test pass
585 06:02:15.366092 cs1 AddrBus test pass
586 06:02:15.366299
587 06:02:15.371207 100bdlr_step_size ps== 420
588 06:02:15.371484 result report
589 06:02:15.376803 boot times 0Enable ddr reg access
590 06:02:15.381797 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 06:02:15.395155 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 06:02:15.967818 0.0;M3 CHK:0;cm4_sp_mode 0
593 06:02:15.968221 MVN_1=0x00000000
594 06:02:15.973214 MVN_2=0x00000000
595 06:02:15.979016 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 06:02:15.979274 OPS=0x10
597 06:02:15.979489 ring efuse init
598 06:02:15.979704 chipver efuse init
599 06:02:15.984474 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 06:02:15.990241 [0.018961 Inits done]
601 06:02:15.990495 secure task start!
602 06:02:15.990707 high task start!
603 06:02:15.994952 low task start!
604 06:02:15.995197 run into bl31
605 06:02:16.001316 NOTICE: BL31: v1.3(release):4fc40b1
606 06:02:16.009230 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 06:02:16.009492 NOTICE: BL31: G12A normal boot!
608 06:02:16.034469 NOTICE: BL31: BL33 decompress pass
609 06:02:16.040102 ERROR: Error initializing runtime service opteed_fast
610 06:02:17.273048
611 06:02:17.273451
612 06:02:17.280703 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 06:02:17.280985
614 06:02:17.281202 Model: Libre Computer AML-A311D-CC Alta
615 06:02:17.489985 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 06:02:17.512568 DRAM: 2 GiB (effective 3.8 GiB)
617 06:02:17.656269 Core: 408 devices, 31 uclasses, devicetree: separate
618 06:02:17.661205 WDT: Not starting watchdog@f0d0
619 06:02:17.694478 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 06:02:17.706909 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 06:02:17.711756 ** Bad device specification mmc 0 **
622 06:02:17.722149 Card did not respond to voltage select! : -110
623 06:02:17.729734 ** Bad device specification mmc 0 **
624 06:02:17.729983 Couldn't find partition mmc 0
625 06:02:17.738143 Card did not respond to voltage select! : -110
626 06:02:17.743661 ** Bad device specification mmc 0 **
627 06:02:17.743903 Couldn't find partition mmc 0
628 06:02:17.747758 Error: could not access storage.
629 06:02:18.091033 Net: eth0: ethernet@ff3f0000
630 06:02:18.091434 starting USB...
631 06:02:18.342993 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 06:02:18.343387 Starting the controller
633 06:02:18.348983 USB XHCI 1.10
634 06:02:19.934029 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 06:02:19.934470 bl2_stage_init 0x01
636 06:02:19.934710 bl2_stage_init 0x81
637 06:02:19.939470 hw id: 0x0000 - pwm id 0x01
638 06:02:19.939774 bl2_stage_init 0xc1
639 06:02:19.940041 bl2_stage_init 0x02
640 06:02:19.940272
641 06:02:19.945111 L0:00000000
642 06:02:19.945439 L1:20000703
643 06:02:19.945669 L2:00008067
644 06:02:19.945890 L3:14000000
645 06:02:19.950782 B2:00402000
646 06:02:19.951127 B1:e0f83180
647 06:02:19.951355
648 06:02:19.951569 TE: 58159
649 06:02:19.951782
650 06:02:19.956335 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 06:02:19.956659
652 06:02:19.956895 Board ID = 1
653 06:02:19.961843 Set A53 clk to 24M
654 06:02:19.962166 Set A73 clk to 24M
655 06:02:19.962394 Set clk81 to 24M
656 06:02:19.967494 A53 clk: 1200 MHz
657 06:02:19.967805 A73 clk: 1200 MHz
658 06:02:19.968065 CLK81: 166.6M
659 06:02:19.968295 smccc: 00012ab5
660 06:02:19.973099 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 06:02:19.978762 board id: 1
662 06:02:19.984593 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 06:02:19.995579 fw parse done
664 06:02:20.000401 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 06:02:20.043790 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 06:02:20.054615 PIEI prepare done
667 06:02:20.054952 fastboot data load
668 06:02:20.055184 fastboot data verify
669 06:02:20.060236 verify result: 266
670 06:02:20.065860 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 06:02:20.066170 LPDDR4 probe
672 06:02:20.066402 ddr clk to 1584MHz
673 06:02:20.073839 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 06:02:20.111111
675 06:02:20.111517 dmc_version 0001
676 06:02:20.117832 Check phy result
677 06:02:20.123652 INFO : End of CA training
678 06:02:20.123974 INFO : End of initialization
679 06:02:20.129244 INFO : Training has run successfully!
680 06:02:20.129553 Check phy result
681 06:02:20.134853 INFO : End of initialization
682 06:02:20.135192 INFO : End of read enable training
683 06:02:20.140434 INFO : End of fine write leveling
684 06:02:20.146043 INFO : End of Write leveling coarse delay
685 06:02:20.146358 INFO : Training has run successfully!
686 06:02:20.146590 Check phy result
687 06:02:20.151650 INFO : End of initialization
688 06:02:20.151972 INFO : End of read dq deskew training
689 06:02:20.157219 INFO : End of MPR read delay center optimization
690 06:02:20.162816 INFO : End of write delay center optimization
691 06:02:20.168428 INFO : End of read delay center optimization
692 06:02:20.168736 INFO : End of max read latency training
693 06:02:20.174016 INFO : Training has run successfully!
694 06:02:20.174323 1D training succeed
695 06:02:20.183231 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 06:02:20.230913 Check phy result
697 06:02:20.231318 INFO : End of initialization
698 06:02:20.253439 INFO : End of 2D read delay Voltage center optimization
699 06:02:20.272880 INFO : End of 2D read delay Voltage center optimization
700 06:02:20.324987 INFO : End of 2D write delay Voltage center optimization
701 06:02:20.374339 INFO : End of 2D write delay Voltage center optimization
702 06:02:20.379856 INFO : Training has run successfully!
703 06:02:20.380200
704 06:02:20.380439 channel==0
705 06:02:20.385412 RxClkDly_Margin_A0==88 ps 9
706 06:02:20.385744 TxDqDly_Margin_A0==98 ps 10
707 06:02:20.391055 RxClkDly_Margin_A1==88 ps 9
708 06:02:20.391388 TxDqDly_Margin_A1==98 ps 10
709 06:02:20.391628 TrainedVREFDQ_A0==74
710 06:02:20.396653 TrainedVREFDQ_A1==75
711 06:02:20.396984 VrefDac_Margin_A0==25
712 06:02:20.397217 DeviceVref_Margin_A0==40
713 06:02:20.402225 VrefDac_Margin_A1==24
714 06:02:20.402538 DeviceVref_Margin_A1==39
715 06:02:20.402773
716 06:02:20.402995
717 06:02:20.407867 channel==1
718 06:02:20.408204 RxClkDly_Margin_A0==88 ps 9
719 06:02:20.408435 TxDqDly_Margin_A0==88 ps 9
720 06:02:20.413437 RxClkDly_Margin_A1==88 ps 9
721 06:02:20.413742 TxDqDly_Margin_A1==88 ps 9
722 06:02:20.419023 TrainedVREFDQ_A0==77
723 06:02:20.419329 TrainedVREFDQ_A1==77
724 06:02:20.419563 VrefDac_Margin_A0==23
725 06:02:20.424652 DeviceVref_Margin_A0==37
726 06:02:20.424971 VrefDac_Margin_A1==24
727 06:02:20.430264 DeviceVref_Margin_A1==37
728 06:02:20.430601
729 06:02:20.430833 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 06:02:20.431059
731 06:02:20.463969 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000019 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 06:02:20.464398 2D training succeed
733 06:02:20.469472 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 06:02:20.475078 auto size-- 65535DDR cs0 size: 2048MB
735 06:02:20.475436 DDR cs1 size: 2048MB
736 06:02:20.480656 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 06:02:20.481013 cs0 DataBus test pass
738 06:02:20.486450 cs1 DataBus test pass
739 06:02:20.487068 cs0 AddrBus test pass
740 06:02:20.487521 cs1 AddrBus test pass
741 06:02:20.487959
742 06:02:20.491942 100bdlr_step_size ps== 420
743 06:02:20.492488 result report
744 06:02:20.497454 boot times 0Enable ddr reg access
745 06:02:20.502678 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 06:02:20.516228 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 06:02:21.089098 0.0;M3 CHK:0;cm4_sp_mode 0
748 06:02:21.089774 MVN_1=0x00000000
749 06:02:21.094585 MVN_2=0x00000000
750 06:02:21.100375 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 06:02:21.100866 OPS=0x10
752 06:02:21.101309 ring efuse init
753 06:02:21.101762 chipver efuse init
754 06:02:21.105983 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 06:02:21.111598 [0.018961 Inits done]
756 06:02:21.112142 secure task start!
757 06:02:21.112586 high task start!
758 06:02:21.116164 low task start!
759 06:02:21.116632 run into bl31
760 06:02:21.122819 NOTICE: BL31: v1.3(release):4fc40b1
761 06:02:21.130680 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 06:02:21.131264 NOTICE: BL31: G12A normal boot!
763 06:02:21.156601 NOTICE: BL31: BL33 decompress pass
764 06:02:21.162245 ERROR: Error initializing runtime service opteed_fast
765 06:02:22.395087
766 06:02:22.395800
767 06:02:22.403527 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 06:02:22.404176
769 06:02:22.404673 Model: Libre Computer AML-A311D-CC Alta
770 06:02:22.612148 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 06:02:22.635536 DRAM: 2 GiB (effective 3.8 GiB)
772 06:02:22.778430 Core: 408 devices, 31 uclasses, devicetree: separate
773 06:02:22.784284 WDT: Not starting watchdog@f0d0
774 06:02:22.816620 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 06:02:22.829023 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 06:02:22.833953 ** Bad device specification mmc 0 **
777 06:02:22.844315 Card did not respond to voltage select! : -110
778 06:02:22.851920 ** Bad device specification mmc 0 **
779 06:02:22.852444 Couldn't find partition mmc 0
780 06:02:22.860272 Card did not respond to voltage select! : -110
781 06:02:22.865746 ** Bad device specification mmc 0 **
782 06:02:22.866242 Couldn't find partition mmc 0
783 06:02:22.870806 Error: could not access storage.
784 06:02:23.214439 Net: eth0: ethernet@ff3f0000
785 06:02:23.215104 starting USB...
786 06:02:23.466272 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 06:02:23.466945 Starting the controller
788 06:02:23.473146 USB XHCI 1.10
789 06:02:25.635767 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 06:02:25.636510 bl2_stage_init 0x01
791 06:02:25.636965 bl2_stage_init 0x81
792 06:02:25.641870 hw id: 0x0000 - pwm id 0x01
793 06:02:25.642442 bl2_stage_init 0xc1
794 06:02:25.642891 bl2_stage_init 0x02
795 06:02:25.643330
796 06:02:25.646825 L0:00000000
797 06:02:25.647316 L1:20000703
798 06:02:25.647751 L2:00008067
799 06:02:25.648219 L3:14000000
800 06:02:25.652366 B2:00402000
801 06:02:25.652849 B1:e0f83180
802 06:02:25.653285
803 06:02:25.653722 TE: 58124
804 06:02:25.654157
805 06:02:25.657948 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 06:02:25.658443
807 06:02:25.658878 Board ID = 1
808 06:02:25.663602 Set A53 clk to 24M
809 06:02:25.664111 Set A73 clk to 24M
810 06:02:25.664545 Set clk81 to 24M
811 06:02:25.669221 A53 clk: 1200 MHz
812 06:02:25.669703 A73 clk: 1200 MHz
813 06:02:25.670135 CLK81: 166.6M
814 06:02:25.670562 smccc: 00012a92
815 06:02:25.674709 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 06:02:25.680483 board id: 1
817 06:02:25.686231 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 06:02:25.696861 fw parse done
819 06:02:25.702757 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 06:02:25.745454 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 06:02:25.756294 PIEI prepare done
822 06:02:25.756665 fastboot data load
823 06:02:25.756871 fastboot data verify
824 06:02:25.761993 verify result: 266
825 06:02:25.767649 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 06:02:25.768197 LPDDR4 probe
827 06:02:25.768638 ddr clk to 1584MHz
828 06:02:25.775578 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 06:02:25.812928
830 06:02:25.813341 dmc_version 0001
831 06:02:25.819564 Check phy result
832 06:02:25.825661 INFO : End of CA training
833 06:02:25.826135 INFO : End of initialization
834 06:02:25.830965 INFO : Training has run successfully!
835 06:02:25.831303 Check phy result
836 06:02:25.836680 INFO : End of initialization
837 06:02:25.837031 INFO : End of read enable training
838 06:02:25.842093 INFO : End of fine write leveling
839 06:02:25.848131 INFO : End of Write leveling coarse delay
840 06:02:25.848479 INFO : Training has run successfully!
841 06:02:25.848697 Check phy result
842 06:02:25.853384 INFO : End of initialization
843 06:02:25.853753 INFO : End of read dq deskew training
844 06:02:25.859014 INFO : End of MPR read delay center optimization
845 06:02:25.864591 INFO : End of write delay center optimization
846 06:02:25.870185 INFO : End of read delay center optimization
847 06:02:25.870520 INFO : End of max read latency training
848 06:02:25.875782 INFO : Training has run successfully!
849 06:02:25.876150 1D training succeed
850 06:02:25.884996 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 06:02:25.932634 Check phy result
852 06:02:25.933042 INFO : End of initialization
853 06:02:25.955075 INFO : End of 2D read delay Voltage center optimization
854 06:02:25.976190 INFO : End of 2D read delay Voltage center optimization
855 06:02:26.027405 INFO : End of 2D write delay Voltage center optimization
856 06:02:26.076839 INFO : End of 2D write delay Voltage center optimization
857 06:02:26.082343 INFO : Training has run successfully!
858 06:02:26.082670
859 06:02:26.082910 channel==0
860 06:02:26.087964 RxClkDly_Margin_A0==88 ps 9
861 06:02:26.088327 TxDqDly_Margin_A0==98 ps 10
862 06:02:26.091246 RxClkDly_Margin_A1==88 ps 9
863 06:02:26.091551 TxDqDly_Margin_A1==98 ps 10
864 06:02:26.097056 TrainedVREFDQ_A0==74
865 06:02:26.097384 TrainedVREFDQ_A1==74
866 06:02:26.102483 VrefDac_Margin_A0==24
867 06:02:26.102803 DeviceVref_Margin_A0==40
868 06:02:26.103041 VrefDac_Margin_A1==24
869 06:02:26.108252 DeviceVref_Margin_A1==40
870 06:02:26.108824
871 06:02:26.109270
872 06:02:26.109706 channel==1
873 06:02:26.110140 RxClkDly_Margin_A0==98 ps 10
874 06:02:26.113641 TxDqDly_Margin_A0==98 ps 10
875 06:02:26.114142 RxClkDly_Margin_A1==88 ps 9
876 06:02:26.119179 TxDqDly_Margin_A1==88 ps 9
877 06:02:26.119739 TrainedVREFDQ_A0==77
878 06:02:26.120377 TrainedVREFDQ_A1==77
879 06:02:26.124915 VrefDac_Margin_A0==22
880 06:02:26.125489 DeviceVref_Margin_A0==37
881 06:02:26.130414 VrefDac_Margin_A1==24
882 06:02:26.130976 DeviceVref_Margin_A1==37
883 06:02:26.131416
884 06:02:26.135944 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 06:02:26.136480
886 06:02:26.164007 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 06:02:26.169539 2D training succeed
888 06:02:26.175570 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 06:02:26.176116 auto size-- 65535DDR cs0 size: 2048MB
890 06:02:26.180790 DDR cs1 size: 2048MB
891 06:02:26.181282 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 06:02:26.186328 cs0 DataBus test pass
893 06:02:26.186801 cs1 DataBus test pass
894 06:02:26.187236 cs0 AddrBus test pass
895 06:02:26.191962 cs1 AddrBus test pass
896 06:02:26.192458
897 06:02:26.192895 100bdlr_step_size ps== 420
898 06:02:26.193334 result report
899 06:02:26.197562 boot times 0Enable ddr reg access
900 06:02:26.205257 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 06:02:26.218792 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 06:02:26.792372 0.0;M3 CHK:0;cm4_sp_mode 0
903 06:02:26.793058 MVN_1=0x00000000
904 06:02:26.797804 MVN_2=0x00000000
905 06:02:26.803550 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 06:02:26.804151 OPS=0x10
907 06:02:26.804651 ring efuse init
908 06:02:26.805124 chipver efuse init
909 06:02:26.809188 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 06:02:26.814783 [0.018960 Inits done]
911 06:02:26.815327 secure task start!
912 06:02:26.815789 high task start!
913 06:02:26.819320 low task start!
914 06:02:26.819874 run into bl31
915 06:02:26.826054 NOTICE: BL31: v1.3(release):4fc40b1
916 06:02:26.833852 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 06:02:26.834479 NOTICE: BL31: G12A normal boot!
918 06:02:26.859193 NOTICE: BL31: BL33 decompress pass
919 06:02:26.864839 ERROR: Error initializing runtime service opteed_fast
920 06:02:28.097754
921 06:02:28.098185
922 06:02:28.106147 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 06:02:28.106538
924 06:02:28.106761 Model: Libre Computer AML-A311D-CC Alta
925 06:02:28.314687 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 06:02:28.337979 DRAM: 2 GiB (effective 3.8 GiB)
927 06:02:28.481046 Core: 408 devices, 31 uclasses, devicetree: separate
928 06:02:28.486770 WDT: Not starting watchdog@f0d0
929 06:02:28.519065 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 06:02:28.531475 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 06:02:28.536420 ** Bad device specification mmc 0 **
932 06:02:28.546806 Card did not respond to voltage select! : -110
933 06:02:28.554413 ** Bad device specification mmc 0 **
934 06:02:28.554893 Couldn't find partition mmc 0
935 06:02:28.562796 Card did not respond to voltage select! : -110
936 06:02:28.568298 ** Bad device specification mmc 0 **
937 06:02:28.568769 Couldn't find partition mmc 0
938 06:02:28.573350 Error: could not access storage.
939 06:02:28.916064 Net: eth0: ethernet@ff3f0000
940 06:02:28.916680 starting USB...
941 06:02:29.168753 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 06:02:29.169361 Starting the controller
943 06:02:29.175625 USB XHCI 1.10
944 06:02:30.732749 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 06:02:30.740988 scanning usb for storage devices... 0 Storage Device(s) found
947 06:02:30.792571 Hit any key to stop autoboot: 1
948 06:02:30.793476 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
949 06:02:30.794092 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
950 06:02:30.794590 Setting prompt string to ['=>']
951 06:02:30.795093 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
952 06:02:30.808485 0
953 06:02:30.809402 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 06:02:30.809930 Sending with 10 millisecond of delay
956 06:02:31.944871 => setenv autoload no
957 06:02:31.955709 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 06:02:31.961094 setenv autoload no
959 06:02:31.961863 Sending with 10 millisecond of delay
961 06:02:33.758993 => setenv initrd_high 0xffffffff
962 06:02:33.769869 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
963 06:02:33.770821 setenv initrd_high 0xffffffff
964 06:02:33.771608 Sending with 10 millisecond of delay
966 06:02:35.388133 => setenv fdt_high 0xffffffff
967 06:02:35.398949 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
968 06:02:45.241724 setenv fdt_high 0xffffffff
969 06:02:45.242583 Sending with 10 millisecond of delay
971 06:02:45.534910 => dhcp
972 06:02:45.545547 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
973 06:02:45.546192 dhcp
974 06:02:45.546430 Speed: 1000, full duplex
975 06:02:45.546642 BOOTP broadcast 1
976 06:02:45.553649 DHCP client bound to address 192.168.6.33 (9 ms)
977 06:02:45.554264 Sending with 10 millisecond of delay
979 06:02:47.232432 => setenv serverip 192.168.6.2
980 06:02:47.243683 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
981 06:02:47.245089 setenv serverip 192.168.6.2
982 06:02:47.246198 Sending with 10 millisecond of delay
984 06:02:50.974254 => tftpboot 0x01080000 796638/tftp-deploy-vi3robbr/kernel/uImage
985 06:02:50.985041 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:08)
986 06:02:50.985868 tftpboot 0x01080000 796638/tftp-deploy-vi3robbr/kernel/uImage
987 06:02:50.986328 Speed: 1000, full duplex
988 06:02:50.986729 Using ethernet@ff3f0000 device
989 06:02:50.987586 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
990 06:02:50.993348 Filename '796638/tftp-deploy-vi3robbr/kernel/uImage'.
991 06:02:50.997171 Load address: 0x1080000
992 06:02:54.788719 Loading: *################################################## 43.6 MiB
993 06:02:54.789788 11.5 MiB/s
994 06:02:54.790131 done
995 06:02:54.792854 Bytes transferred = 45713984 (2b98a40 hex)
996 06:02:54.793804 Sending with 10 millisecond of delay
998 06:02:59.484388 => tftpboot 0x08000000 796638/tftp-deploy-vi3robbr/ramdisk/ramdisk.cpio.gz.uboot
999 06:02:59.495415 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
1000 06:02:59.496554 tftpboot 0x08000000 796638/tftp-deploy-vi3robbr/ramdisk/ramdisk.cpio.gz.uboot
1001 06:02:59.497135 Speed: 1000, full duplex
1002 06:02:59.497660 Using ethernet@ff3f0000 device
1003 06:02:59.498315 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1004 06:02:59.509203 Filename '796638/tftp-deploy-vi3robbr/ramdisk/ramdisk.cpio.gz.uboot'.
1005 06:02:59.509831 Load address: 0x8000000
1006 06:03:02.186478 Loading: *################################################# UDP wrong checksum 00000005 00000d8d
1007 06:03:07.187690 T UDP wrong checksum 00000005 00000d8d
1008 06:03:17.190042 T T UDP wrong checksum 00000005 00000d8d
1009 06:03:19.856045 UDP wrong checksum 000000ff 0000c1e5
1010 06:03:19.862478 UDP wrong checksum 000000ff 000058d8
1011 06:03:35.474633 T T T UDP wrong checksum 000000ff 000020d4
1012 06:03:35.481044 UDP wrong checksum 000000ff 0000b3c6
1013 06:03:37.194803 T UDP wrong checksum 00000005 00000d8d
1014 06:03:44.305277 T UDP wrong checksum 000000ff 00004005
1015 06:03:44.338529 UDP wrong checksum 000000ff 0000c6f7
1016 06:03:57.199730 T T
1017 06:03:57.200439 Retry count exceeded; starting again
1019 06:03:57.201997 end: 2.4.3 bootloader-commands (duration 00:01:26) [common]
1022 06:03:57.204127 end: 2.4 uboot-commands (duration 00:01:58) [common]
1024 06:03:57.205711 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1026 06:03:57.206851 end: 2 uboot-action (duration 00:01:58) [common]
1028 06:03:57.208555 Cleaning after the job
1029 06:03:57.209156 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/ramdisk
1030 06:03:57.210502 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/kernel
1031 06:03:57.246837 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/dtb
1032 06:03:57.248326 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/nfsrootfs
1033 06:03:57.303058 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796638/tftp-deploy-vi3robbr/modules
1034 06:03:57.309122 start: 4.1 power-off (timeout 00:00:30) [common]
1035 06:03:57.309754 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1036 06:03:57.342905 >> OK - accepted request
1037 06:03:57.345035 Returned 0 in 0 seconds
1038 06:03:57.446089 end: 4.1 power-off (duration 00:00:00) [common]
1040 06:03:57.447102 start: 4.2 read-feedback (timeout 00:10:00) [common]
1041 06:03:57.447772 Listened to connection for namespace 'common' for up to 1s
1042 06:03:58.448779 Finalising connection for namespace 'common'
1043 06:03:58.449517 Disconnecting from shell: Finalise
1044 06:03:58.450026 =>
1045 06:03:58.551130 end: 4.2 read-feedback (duration 00:00:01) [common]
1046 06:03:58.551897 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796638
1047 06:04:01.381723 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796638
1048 06:04:01.382321 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.