Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 07:55:17.739112 lava-dispatcher, installed at version: 2023.08
2 07:55:17.739413 start: 0 validate
3 07:55:17.739604 Start time: 2024-10-04 07:55:17.739593+00:00 (UTC)
4 07:55:17.739839 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 07:55:18.285582 Validating that http://storage.kernelci.org/next/master/next-20241004/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 07:55:18.399945 Validating that http://storage.kernelci.org/next/master/next-20241004/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 07:55:18.513935 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 07:55:18.641313 Validating that http://storage.kernelci.org/next/master/next-20241004/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 07:55:18.759637 validate duration: 1.02
11 07:55:18.760421 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 07:55:18.760754 start: 1.1 download-retry (timeout 00:10:00) [common]
13 07:55:18.761066 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 07:55:18.761540 Not decompressing ramdisk as can be used compressed.
15 07:55:18.761836 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 07:55:18.762075 saving as /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/ramdisk/initrd.cpio.gz
17 07:55:18.762318 total size: 4775763 (4 MB)
18 07:55:18.991082 progress 0 % (0 MB)
19 07:55:19.327538 progress 5 % (0 MB)
20 07:55:19.438794 progress 10 % (0 MB)
21 07:55:19.587724 progress 15 % (0 MB)
22 07:55:19.665226 progress 20 % (0 MB)
23 07:55:19.706313 progress 25 % (1 MB)
24 07:55:19.712474 progress 30 % (1 MB)
25 07:55:19.774553 progress 35 % (1 MB)
26 07:55:19.796345 progress 40 % (1 MB)
27 07:55:19.884948 progress 45 % (2 MB)
28 07:55:19.905730 progress 50 % (2 MB)
29 07:55:19.996302 progress 55 % (2 MB)
30 07:55:20.017551 progress 60 % (2 MB)
31 07:55:20.102947 progress 65 % (2 MB)
32 07:55:20.128462 progress 70 % (3 MB)
33 07:55:20.155633 progress 75 % (3 MB)
34 07:55:20.235338 progress 80 % (3 MB)
35 07:55:20.261796 progress 85 % (3 MB)
36 07:55:20.344147 progress 90 % (4 MB)
37 07:55:20.370288 progress 95 % (4 MB)
38 07:55:20.448785 progress 100 % (4 MB)
39 07:55:20.449525 4 MB downloaded in 1.69 s (2.70 MB/s)
40 07:55:20.449986 end: 1.1.1 http-download (duration 00:00:02) [common]
42 07:55:20.450775 end: 1.1 download-retry (duration 00:00:02) [common]
43 07:55:20.451055 start: 1.2 download-retry (timeout 00:09:58) [common]
44 07:55:20.451323 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 07:55:20.451719 downloading http://storage.kernelci.org/next/master/next-20241004/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 07:55:20.451935 saving as /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/kernel/zImage
47 07:55:20.452142 total size: 11465216 (10 MB)
48 07:55:20.452375 No compression specified
49 07:55:20.570923 progress 0 % (0 MB)
50 07:55:20.912757 progress 5 % (0 MB)
51 07:55:21.137729 progress 10 % (1 MB)
52 07:55:21.261456 progress 15 % (1 MB)
53 07:55:21.486189 progress 20 % (2 MB)
54 07:55:21.794572 progress 25 % (2 MB)
55 07:55:22.015146 progress 30 % (3 MB)
56 07:55:22.239457 progress 35 % (3 MB)
57 07:55:22.380098 progress 40 % (4 MB)
58 07:55:22.807577 progress 45 % (4 MB)
59 07:55:22.934514 progress 50 % (5 MB)
60 07:55:23.259023 progress 55 % (6 MB)
61 07:55:23.497122 progress 60 % (6 MB)
62 07:55:23.814524 progress 65 % (7 MB)
63 07:55:24.053254 progress 70 % (7 MB)
64 07:55:24.357099 progress 75 % (8 MB)
65 07:55:24.599609 progress 80 % (8 MB)
66 07:55:24.834088 progress 85 % (9 MB)
67 07:55:25.067014 progress 90 % (9 MB)
68 07:55:25.367586 progress 95 % (10 MB)
69 07:55:25.605377 progress 100 % (10 MB)
70 07:55:25.606286 10 MB downloaded in 5.15 s (2.12 MB/s)
71 07:55:25.606731 end: 1.2.1 http-download (duration 00:00:05) [common]
73 07:55:25.607550 end: 1.2 download-retry (duration 00:00:05) [common]
74 07:55:25.607845 start: 1.3 download-retry (timeout 00:09:53) [common]
75 07:55:25.608127 start: 1.3.1 http-download (timeout 00:09:53) [common]
76 07:55:25.608544 downloading http://storage.kernelci.org/next/master/next-20241004/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 07:55:25.608773 saving as /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/dtb/am335x-boneblack.dtb
78 07:55:25.608990 total size: 70568 (0 MB)
79 07:55:25.609208 No compression specified
80 07:55:25.725335 progress 46 % (0 MB)
81 07:55:25.728160 progress 92 % (0 MB)
82 07:55:25.729159 progress 100 % (0 MB)
83 07:55:25.729551 0 MB downloaded in 0.12 s (0.56 MB/s)
84 07:55:25.729951 end: 1.3.1 http-download (duration 00:00:00) [common]
86 07:55:25.730738 end: 1.3 download-retry (duration 00:00:00) [common]
87 07:55:25.731017 start: 1.4 download-retry (timeout 00:09:53) [common]
88 07:55:25.731301 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 07:55:25.731657 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 07:55:25.731883 saving as /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/nfsrootfs/full.rootfs.tar
91 07:55:25.732096 total size: 117747780 (112 MB)
92 07:55:25.732341 Using unxz to decompress xz
93 07:55:25.850941 progress 0 % (0 MB)
94 07:55:28.869515 progress 5 % (5 MB)
95 07:55:31.437999 progress 10 % (11 MB)
96 07:55:34.326930 progress 15 % (16 MB)
97 07:55:36.989746 progress 20 % (22 MB)
98 07:55:39.915758 progress 25 % (28 MB)
99 07:55:42.475801 progress 30 % (33 MB)
100 07:55:44.979607 progress 35 % (39 MB)
101 07:55:47.249564 progress 40 % (44 MB)
102 07:55:49.039063 progress 45 % (50 MB)
103 07:55:50.383700 progress 50 % (56 MB)
104 07:55:51.478022 progress 55 % (61 MB)
105 07:55:52.848192 progress 60 % (67 MB)
106 07:55:54.474606 progress 65 % (73 MB)
107 07:55:55.958841 progress 70 % (78 MB)
108 07:55:57.494034 progress 75 % (84 MB)
109 07:55:58.961496 progress 80 % (89 MB)
110 07:56:00.770631 progress 85 % (95 MB)
111 07:56:03.996111 progress 90 % (101 MB)
112 07:56:07.122339 progress 95 % (106 MB)
113 07:56:11.415504 progress 100 % (112 MB)
114 07:56:11.419315 112 MB downloaded in 45.69 s (2.46 MB/s)
115 07:56:11.419744 end: 1.4.1 http-download (duration 00:00:46) [common]
117 07:56:11.420563 end: 1.4 download-retry (duration 00:00:46) [common]
118 07:56:11.420844 start: 1.5 download-retry (timeout 00:09:07) [common]
119 07:56:11.421120 start: 1.5.1 http-download (timeout 00:09:07) [common]
120 07:56:11.421503 downloading http://storage.kernelci.org/next/master/next-20241004/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 07:56:11.421725 saving as /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/modules/modules.tar
122 07:56:11.421933 total size: 6615468 (6 MB)
123 07:56:11.422145 Using unxz to decompress xz
124 07:56:11.540760 progress 0 % (0 MB)
125 07:56:11.771263 progress 5 % (0 MB)
126 07:56:12.337598 progress 10 % (0 MB)
127 07:56:12.678779 progress 15 % (0 MB)
128 07:56:13.024845 progress 20 % (1 MB)
129 07:56:13.358662 progress 25 % (1 MB)
130 07:56:13.688859 progress 30 % (1 MB)
131 07:56:14.011365 progress 35 % (2 MB)
132 07:56:14.251727 progress 40 % (2 MB)
133 07:56:14.573104 progress 45 % (2 MB)
134 07:56:14.830267 progress 50 % (3 MB)
135 07:56:15.142539 progress 55 % (3 MB)
136 07:56:15.471874 progress 60 % (3 MB)
137 07:56:15.701797 progress 65 % (4 MB)
138 07:56:16.033239 progress 70 % (4 MB)
139 07:56:16.264807 progress 75 % (4 MB)
140 07:56:16.601033 progress 80 % (5 MB)
141 07:56:16.831130 progress 85 % (5 MB)
142 07:56:17.159915 progress 90 % (5 MB)
143 07:56:17.389546 progress 95 % (6 MB)
144 07:56:17.719315 progress 100 % (6 MB)
145 07:56:17.725482 6 MB downloaded in 6.30 s (1.00 MB/s)
146 07:56:17.725969 end: 1.5.1 http-download (duration 00:00:06) [common]
148 07:56:17.726769 end: 1.5 download-retry (duration 00:00:06) [common]
149 07:56:17.727053 start: 1.6 prepare-tftp-overlay (timeout 00:09:01) [common]
150 07:56:17.727334 start: 1.6.1 extract-nfsrootfs (timeout 00:09:01) [common]
151 07:56:23.272416 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1201675/extract-nfsrootfs-wrs5zboo
152 07:56:23.272718 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 07:56:23.272867 start: 1.6.2 lava-overlay (timeout 00:08:55) [common]
154 07:56:23.273164 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9
155 07:56:23.273344 makedir: /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin
156 07:56:23.273496 makedir: /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/tests
157 07:56:23.273646 makedir: /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/results
158 07:56:23.273807 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-add-keys
159 07:56:23.274031 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-add-sources
160 07:56:23.274210 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-background-process-start
161 07:56:23.274393 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-background-process-stop
162 07:56:23.274597 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-common-functions
163 07:56:23.274778 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-echo-ipv4
164 07:56:23.274951 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-install-packages
165 07:56:23.275122 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-installed-packages
166 07:56:23.275292 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-os-build
167 07:56:23.275464 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-probe-channel
168 07:56:23.275635 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-probe-ip
169 07:56:23.275810 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-target-ip
170 07:56:23.275983 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-target-mac
171 07:56:23.276155 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-target-storage
172 07:56:23.276469 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-test-case
173 07:56:23.276640 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-test-event
174 07:56:23.276809 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-test-feedback
175 07:56:23.276978 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-test-raise
176 07:56:23.277147 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-test-reference
177 07:56:23.277317 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-test-runner
178 07:56:23.277487 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-test-set
179 07:56:23.277656 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-test-shell
180 07:56:23.277828 Updating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-add-keys (debian)
181 07:56:23.278052 Updating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-add-sources (debian)
182 07:56:23.278246 Updating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-install-packages (debian)
183 07:56:23.278439 Updating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-installed-packages (debian)
184 07:56:23.278630 Updating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/bin/lava-os-build (debian)
185 07:56:23.278800 Creating /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/environment
186 07:56:23.278930 LAVA metadata
187 07:56:23.279031 - LAVA_JOB_ID=1201675
188 07:56:23.279128 - LAVA_DISPATCHER_IP=192.168.11.5
189 07:56:23.279271 start: 1.6.2.1 ssh-authorize (timeout 00:08:55) [common]
190 07:56:23.279598 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 07:56:23.279731 start: 1.6.2.2 lava-vland-overlay (timeout 00:08:55) [common]
192 07:56:23.279849 skipped lava-vland-overlay
193 07:56:23.279962 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 07:56:23.280082 start: 1.6.2.3 lava-multinode-overlay (timeout 00:08:55) [common]
195 07:56:23.280185 skipped lava-multinode-overlay
196 07:56:23.280315 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 07:56:23.280431 start: 1.6.2.4 test-definition (timeout 00:08:55) [common]
198 07:56:23.280533 Loading test definitions
199 07:56:23.280656 start: 1.6.2.4.1 inline-repo-action (timeout 00:08:55) [common]
200 07:56:23.280756 Using /lava-1201675 at stage 0
201 07:56:23.281160 uuid=1201675_1.6.2.4.1 testdef=None
202 07:56:23.281285 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 07:56:23.281404 start: 1.6.2.4.2 test-overlay (timeout 00:08:55) [common]
204 07:56:23.282013 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 07:56:23.282342 start: 1.6.2.4.3 test-install-overlay (timeout 00:08:55) [common]
207 07:56:23.283113 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 07:56:23.283456 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:08:55) [common]
210 07:56:23.284317 runner path: /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/0/tests/0_timesync-off test_uuid 1201675_1.6.2.4.1
211 07:56:23.284528 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 07:56:23.284883 start: 1.6.2.4.5 git-repo-action (timeout 00:08:55) [common]
214 07:56:23.284985 Using /lava-1201675 at stage 0
215 07:56:23.285125 Fetching tests from https://github.com/kernelci/test-definitions.git
216 07:56:23.285229 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/0/tests/1_kselftest-dt'
217 07:56:28.216586 Running '/usr/bin/git checkout kernelci.org
218 07:56:28.468583 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 07:56:28.469775 uuid=1201675_1.6.2.4.5 testdef=None
220 07:56:28.470081 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 07:56:28.470783 start: 1.6.2.4.6 test-overlay (timeout 00:08:50) [common]
223 07:56:28.473149 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 07:56:28.473940 start: 1.6.2.4.7 test-install-overlay (timeout 00:08:50) [common]
226 07:56:28.485164 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 07:56:28.485642 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:08:50) [common]
229 07:56:28.526660 runner path: /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/0/tests/1_kselftest-dt test_uuid 1201675_1.6.2.4.5
230 07:56:28.526951 BOARD='beaglebone-black'
231 07:56:28.527179 BRANCH='next'
232 07:56:28.527400 SKIPFILE='/dev/null'
233 07:56:28.527641 SKIP_INSTALL='True'
234 07:56:28.527852 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241004/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 07:56:28.528064 TST_CASENAME=''
236 07:56:28.528297 TST_CMDFILES='dt'
237 07:56:28.528770 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 07:56:28.529509 Creating lava-test-runner.conf files
240 07:56:28.529724 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1201675/lava-overlay-gt005vr9/lava-1201675/0 for stage 0
241 07:56:28.530019 - 0_timesync-off
242 07:56:28.530247 - 1_kselftest-dt
243 07:56:28.530571 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 07:56:28.530853 start: 1.6.2.5 compress-overlay (timeout 00:08:50) [common]
245 07:56:37.007620 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 07:56:37.007831 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:42) [common]
247 07:56:37.007976 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 07:56:37.008130 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 07:56:37.008298 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:42) [common]
250 07:56:37.134422 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 07:56:37.134714 start: 1.6.4 extract-modules (timeout 00:08:42) [common]
252 07:56:37.134877 extracting modules file /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1201675/extract-nfsrootfs-wrs5zboo
253 07:56:37.438393 extracting modules file /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1201675/extract-overlay-ramdisk-xmfq1wge/ramdisk
254 07:56:37.748058 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 07:56:37.748339 start: 1.6.5 apply-overlay-tftp (timeout 00:08:41) [common]
256 07:56:37.748475 [common] Applying overlay to NFS
257 07:56:37.748581 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1201675/compress-overlay-1eff__ex/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1201675/extract-nfsrootfs-wrs5zboo
258 07:56:38.933145 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 07:56:38.933356 start: 1.6.6 prepare-kernel (timeout 00:08:40) [common]
260 07:56:38.933481 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:40) [common]
261 07:56:38.933609 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 07:56:38.933725 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 07:56:38.933844 start: 1.6.7 configure-preseed-file (timeout 00:08:40) [common]
264 07:56:38.933958 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 07:56:38.934074 start: 1.6.8 compress-ramdisk (timeout 00:08:40) [common]
266 07:56:38.934175 Building ramdisk /var/lib/lava/dispatcher/tmp/1201675/extract-overlay-ramdisk-xmfq1wge/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1201675/extract-overlay-ramdisk-xmfq1wge/ramdisk
267 07:56:39.245592 >> 74954 blocks
268 07:56:41.177564 Adding RAMdisk u-boot header.
269 07:56:41.177847 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1201675/extract-overlay-ramdisk-xmfq1wge/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1201675/extract-overlay-ramdisk-xmfq1wge/ramdisk.cpio.gz.uboot
270 07:56:41.330523 output: Image Name:
271 07:56:41.330872 output: Created: Fri Oct 4 07:56:41 2024
272 07:56:41.331063 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 07:56:41.331262 output: Data Size: 14796203 Bytes = 14449.42 KiB = 14.11 MiB
274 07:56:41.331453 output: Load Address: 00000000
275 07:56:41.331642 output: Entry Point: 00000000
276 07:56:41.331832 output:
277 07:56:41.332171 rename /var/lib/lava/dispatcher/tmp/1201675/extract-overlay-ramdisk-xmfq1wge/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/ramdisk/ramdisk.cpio.gz.uboot
278 07:56:41.332530 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 07:56:41.332818 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
280 07:56:41.333095 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:37) [common]
281 07:56:41.333307 No LXC device requested
282 07:56:41.333574 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 07:56:41.333842 start: 1.8 deploy-device-env (timeout 00:08:37) [common]
284 07:56:41.334102 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 07:56:41.334312 Checking files for TFTP limit of 4294967296 bytes.
286 07:56:41.335572 end: 1 tftp-deploy (duration 00:01:23) [common]
287 07:56:41.335851 start: 2 uboot-action (timeout 00:05:00) [common]
288 07:56:41.336132 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 07:56:41.336411 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 07:56:41.336681 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 07:56:41.337080 substitutions:
292 07:56:41.337288 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 07:56:41.337505 - {DTB_ADDR}: 0x88000000
294 07:56:41.337715 - {DTB}: 1201675/tftp-deploy-7td0yafb/dtb/am335x-boneblack.dtb
295 07:56:41.337926 - {INITRD}: 1201675/tftp-deploy-7td0yafb/ramdisk/ramdisk.cpio.gz.uboot
296 07:56:41.338139 - {KERNEL_ADDR}: 0x82000000
297 07:56:41.338350 - {KERNEL}: 1201675/tftp-deploy-7td0yafb/kernel/zImage
298 07:56:41.338560 - {LAVA_MAC}: None
299 07:56:41.338779 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1201675/extract-nfsrootfs-wrs5zboo
300 07:56:41.338989 - {NFS_SERVER_IP}: 192.168.11.5
301 07:56:41.339195 - {PRESEED_CONFIG}: None
302 07:56:41.339400 - {PRESEED_LOCAL}: None
303 07:56:41.339605 - {RAMDISK_ADDR}: 0x83000000
304 07:56:41.339809 - {RAMDISK}: 1201675/tftp-deploy-7td0yafb/ramdisk/ramdisk.cpio.gz.uboot
305 07:56:41.340014 - {ROOT_PART}: None
306 07:56:41.340229 - {ROOT}: None
307 07:56:41.340435 - {SERVER_IP}: 192.168.11.5
308 07:56:41.340637 - {TEE_ADDR}: 0x83000000
309 07:56:41.340840 - {TEE}: None
310 07:56:41.341042 Parsed boot commands:
311 07:56:41.341241 - setenv autoload no
312 07:56:41.341444 - setenv initrd_high 0xffffffff
313 07:56:41.341645 - setenv fdt_high 0xffffffff
314 07:56:41.341845 - dhcp
315 07:56:41.342046 - setenv serverip 192.168.11.5
316 07:56:41.342246 - tftp 0x82000000 1201675/tftp-deploy-7td0yafb/kernel/zImage
317 07:56:41.342450 - tftp 0x83000000 1201675/tftp-deploy-7td0yafb/ramdisk/ramdisk.cpio.gz.uboot
318 07:56:41.342639 - setenv initrd_size ${filesize}
319 07:56:41.342824 - tftp 0x88000000 1201675/tftp-deploy-7td0yafb/dtb/am335x-boneblack.dtb
320 07:56:41.343010 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1201675/extract-nfsrootfs-wrs5zboo,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 07:56:41.343204 - bootz 0x82000000 0x83000000 0x88000000
322 07:56:41.343447 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 07:56:41.344133 start: 2.3 connect-device (timeout 00:05:00) [common]
325 07:56:41.344347 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 07:56:41.703979 Setting prompt string to ['lava-test: # ']
327 07:56:41.704481 end: 2.3 connect-device (duration 00:00:00) [common]
328 07:56:41.704653 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 07:56:41.704822 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 07:56:41.705005 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 07:56:41.705327 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 07:56:42.070810 Returned 0 in 0 seconds
333 07:56:42.171665 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 07:56:42.172590 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 07:56:42.172912 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 07:56:42.173192 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 07:56:42.173436 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 07:56:42.174167 Trying 127.0.0.1...
340 07:56:42.174399 Connected to 127.0.0.1.
341 07:56:42.174609 Escape character is '^]'.
342 07:56:47.081003
343 07:56:47.084539 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 07:56:47.141180 Trying to boot from MMC2
345 07:56:47.189572 Loading Environment from EXT4... Card did not respond to voltage select!
346 07:56:47.256913
347 07:56:47.257237
348 07:56:47.262537 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 07:56:47.262775
350 07:56:47.267423 CPU : AM335X-GP rev 2.1
351 07:56:47.321395 I2C: ready
352 07:56:47.321675 DRAM: 512 MiB
353 07:56:47.376022 No match for driver 'omap_hsmmc'
354 07:56:47.381753 No match for driver 'omap_hsmmc'
355 07:56:47.382036 Some drivers were not found
356 07:56:47.387908 Reset Source: Power-on reset has occurred.
357 07:56:47.388188 RTC 32KCLK Source: External.
358 07:56:47.395434 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 07:56:47.408818 Loading Environment from EXT4... Card did not respond to voltage select!
360 07:56:47.473261 Board: BeagleBone Black
361 07:56:47.477042 <ethaddr> not set. Validating first E-fuse MAC
362 07:56:47.533783 BeagleBone Black:
363 07:56:47.534080 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 07:56:47.539330 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 07:56:47.545331 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 07:56:47.545580 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 07:56:47.550264 Net: eth0: MII MODE
368 07:56:47.559663 cpsw, usb_ether
369 07:56:47.559885 Press SPACE to abort autoboot in 2 seconds
370 07:56:47.610607 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 07:56:47.610998 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 07:56:47.611285 Setting prompt string to ['=> ']
373 07:56:47.611541 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 07:56:47.614724 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 07:56:47.615018 Sending with 10 millisecond of delay
377 07:56:48.749604 => setenv autoload no
378 07:56:48.760133 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 07:56:48.762559 setenv autoload no
380 07:56:48.763031 Sending with 10 millisecond of delay
382 07:56:50.559908 => setenv initrd_high 0xffffffff
383 07:56:50.570402 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 07:56:50.570880 setenv initrd_high 0xffffffff
385 07:56:50.571328 Sending with 10 millisecond of delay
387 07:56:52.187696 => setenv fdt_high 0xffffffff
388 07:56:52.198199 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 07:56:52.198657 setenv fdt_high 0xffffffff
390 07:56:52.199103 Sending with 10 millisecond of delay
392 07:56:52.490557 => dhcp
393 07:56:52.500887 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 07:56:52.501231 dhcp
395 07:56:52.501411 link up on port 0, speed 100, full duplex
396 07:56:52.501605 BOOTP broadcast 1
397 07:56:52.509231 DHCP client bound to address 192.168.11.7 (4 ms)
398 07:56:52.509655 Sending with 10 millisecond of delay
400 07:56:54.246295 => setenv serverip 192.168.11.5
401 07:56:54.256777 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 07:56:54.257252 setenv serverip 192.168.11.5
403 07:56:54.257701 Sending with 10 millisecond of delay
405 07:56:57.800438 => tftp 0x82000000 1201675/tftp-deploy-7td0yafb/kernel/zImage
406 07:56:57.810915 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 07:56:57.811408 tftp 0x82000000 1201675/tftp-deploy-7td0yafb/kernel/zImage
408 07:56:57.811656 link up on port 0, speed 100, full duplex
409 07:56:57.811891 Using cpsw device
410 07:56:57.815389 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
411 07:56:57.820842 Filename '1201675/tftp-deploy-7td0yafb/kernel/zImage'.
412 07:56:57.920005 Load address: 0x82000000
413 07:56:58.009263 Loading: *#################################################################
414 07:56:58.184256 #################################################################
415 07:56:58.360476 #################################################################
416 07:56:58.557956 #################################################################
417 07:56:58.719704 #################################################################
418 07:56:58.899492 #################################################################
419 07:56:59.072185 #################################################################
420 07:56:59.268922 #################################################################
421 07:56:59.438665 #################################################################
422 07:56:59.609172 #################################################################
423 07:56:59.777116 #################################################################
424 07:56:59.951421 #################################################################
425 07:56:59.951743 ##
426 07:56:59.951967 5.1 MiB/s
427 07:56:59.952187 done
428 07:56:59.954497 Bytes transferred = 11465216 (aef200 hex)
429 07:56:59.955023 Sending with 10 millisecond of delay
431 07:57:04.461766 => tftp 0x83000000 1201675/tftp-deploy-7td0yafb/ramdisk/ramdisk.cpio.gz.uboot
432 07:57:04.472255 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
433 07:57:04.472748 tftp 0x83000000 1201675/tftp-deploy-7td0yafb/ramdisk/ramdisk.cpio.gz.uboot
434 07:57:04.473000 link up on port 0, speed 100, full duplex
435 07:57:04.473236 Using cpsw device
436 07:57:04.476591 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
437 07:57:04.536655 Filename '1201675/tftp-deploy-7td0yafb/ramdisk/ramdisk.cpio.gz.uboot'.
438 07:57:04.536954 Load address: 0x83000000
439 07:57:04.662548 Loading: *#################################################################
440 07:57:04.836176 #################################################################
441 07:57:05.010578 #################################################################
442 07:57:05.185179 #################################################################
443 07:57:05.359819 #################################################################
444 07:57:05.555719 #################################################################
445 07:57:05.730078 #################################################################
446 07:57:05.897818 #################################################################
447 07:57:06.072530 #################################################################
448 07:57:06.247530 #################################################################
449 07:57:06.445276 #################################################################
450 07:57:06.619752 #################################################################
451 07:57:06.788310 #################################################################
452 07:57:06.964185 #################################################################
453 07:57:07.140285 #################################################################
454 07:57:07.229063 #################################
455 07:57:07.229322 5.2 MiB/s
456 07:57:07.229548 done
457 07:57:07.232951 Bytes transferred = 14796267 (e1c5eb hex)
458 07:57:07.233490 Sending with 10 millisecond of delay
460 07:57:09.090609 => setenv initrd_size ${filesize}
461 07:57:09.101108 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
462 07:57:09.101569 setenv initrd_size ${filesize}
463 07:57:09.102017 Sending with 10 millisecond of delay
465 07:57:13.307790 => tftp 0x88000000 1201675/tftp-deploy-7td0yafb/dtb/am335x-boneblack.dtb
466 07:57:13.318273 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
467 07:57:13.318728 tftp 0x88000000 1201675/tftp-deploy-7td0yafb/dtb/am335x-boneblack.dtb
468 07:57:13.318955 link up on port 0, speed 100, full duplex
469 07:57:13.319168 Using cpsw device
470 07:57:13.322600 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
471 07:57:13.347092 Filename '1201675/tftp-deploy-7td0yafb/dtb/am335x-boneblack.dtb'.
472 07:57:13.347395 Load address: 0x88000000
473 07:57:13.347617 Loading: *#####
474 07:57:13.347832 4.8 MiB/s
475 07:57:13.353946 done
476 07:57:13.354212 Bytes transferred = 70568 (113a8 hex)
477 07:57:13.354650 Sending with 10 millisecond of delay
479 07:57:26.653412 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1201675/extract-nfsrootfs-wrs5zboo,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 07:57:26.663923 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
481 07:57:26.664402 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1201675/extract-nfsrootfs-wrs5zboo,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
482 07:57:26.664860 Sending with 10 millisecond of delay
484 07:57:29.003859 => bootz 0x82000000 0x83000000 0x88000000
485 07:57:29.014386 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
486 07:57:29.014708 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
487 07:57:29.015247 bootz 0x82000000 0x83000000 0x88000000
488 07:57:29.015487 ## Loading init Ramdisk from Legacy Image at 83000000 ...
489 07:57:29.015947 Image Name:
490 07:57:29.016172 Created: 2024-10-04 7:56:41 UTC
491 07:57:29.021579 Image Type: ARM Linux RAMDisk Image (uncompressed)
492 07:57:29.027182 Data Size: 14796203 Bytes = 14.1 MiB
493 07:57:29.027450 Load Address: 00000000
494 07:57:29.034383 Entry Point: 00000000
495 07:57:29.171742 Verifying Checksum ... OK
496 07:57:29.172017 ## Flattened Device Tree blob at 88000000
497 07:57:29.178348 Booting using the fdt blob at 0x88000000
498 07:57:29.183274 Using Device Tree in place at 88000000, end 880143a7
499 07:57:29.190928
500 07:57:29.191206 Starting kernel ...
501 07:57:29.191427
502 07:57:29.191962 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
503 07:57:29.192274 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
504 07:57:29.192525 Setting prompt string to ['Linux version [0-9]']
505 07:57:29.192769 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
506 07:57:29.193014 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
507 07:57:30.041393 [ 0.000000] Booting Linux on physical CPU 0x0
508 07:57:30.047284 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
509 07:57:30.047588 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
510 07:57:30.047842 Setting prompt string to []
511 07:57:30.048102 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
512 07:57:30.048375 Using line separator: #'\n'#
513 07:57:30.048596 No login prompt set.
514 07:57:30.048819 Parsing kernel messages
515 07:57:30.049024 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
516 07:57:30.049410 [login-action] Waiting for messages, (timeout 00:04:11)
517 07:57:30.064043 [ 0.000000] Linux version 6.12.0-rc1-next-20241004 (KernelCI@build-j332012-arm-gcc-12-multi-v7-defconfig-z5qc8) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Oct 4 06:50:11 UTC 2024
518 07:57:30.069792 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 07:57:30.081295 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 07:57:30.086917 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 07:57:30.092668 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 07:57:30.098417 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 07:57:30.105047 [ 0.000000] Memory policy: Data cache writeback
524 07:57:30.105322 [ 0.000000] efi: UEFI not found.
525 07:57:30.111840 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 07:57:30.117562 [ 0.000000] Zone ranges:
527 07:57:30.123296 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 07:57:30.129046 [ 0.000000] Normal empty
529 07:57:30.129322 [ 0.000000] HighMem empty
530 07:57:30.134689 [ 0.000000] Movable zone start for each node
531 07:57:30.134965 [ 0.000000] Early memory node ranges
532 07:57:30.146313 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 07:57:30.151508 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 07:57:30.176833 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 07:57:30.182495 [ 0.000000] AM335X ES2.1 (sgx neon)
536 07:57:30.194191 [ 0.000000] percpu: Embedded 17 pages/cpu s40908 r8192 d20532 u69632
537 07:57:30.211884 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1201675/extract-nfsrootfs-wrs5zboo,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 07:57:30.223289 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 07:57:30.229015 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 07:57:30.234762 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 07:57:30.244972 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 07:57:30.274139 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 07:57:30.280139 <6>[ 0.000000] trace event string verifier disabled
544 07:57:30.280435 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 07:57:30.285763 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 07:57:30.297259 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 07:57:30.302991 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 07:57:30.310312 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 07:57:30.325437 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 07:57:30.342513 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 07:57:30.349311 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 07:57:30.440885 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 07:57:30.452385 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 07:57:30.459129 <6>[ 0.008334] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 07:57:30.472192 <6>[ 0.019134] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 07:57:30.479530 <6>[ 0.033918] Console: colour dummy device 80x30
557 07:57:30.485562 Matched prompt #6: WARNING:
558 07:57:30.485876 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 07:57:30.491008 <3>[ 0.038816] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 07:57:30.496756 <3>[ 0.045886] This ensures that you still see kernel messages. Please
561 07:57:30.499950 <3>[ 0.052613] update your kernel commandline.
562 07:57:30.540632 <6>[ 0.057226] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 07:57:30.546378 <6>[ 0.096137] CPU: Testing write buffer coherency: ok
564 07:57:30.552383 <6>[ 0.101507] CPU0: Spectre v2: using BPIALL workaround
565 07:57:30.552652 <6>[ 0.106969] pid_max: default: 32768 minimum: 301
566 07:57:30.563875 <6>[ 0.112164] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 07:57:30.570746 <6>[ 0.119986] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 07:57:30.577889 <6>[ 0.129362] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 07:57:30.586249 <6>[ 0.136362] Setting up static identity map for 0x80300000 - 0x803000ac
570 07:57:30.592125 <6>[ 0.146004] rcu: Hierarchical SRCU implementation.
571 07:57:30.599709 <6>[ 0.151288] rcu: Max phase no-delay instances is 1000.
572 07:57:30.608312 <6>[ 0.162408] EFI services will not be available.
573 07:57:30.614128 <6>[ 0.167694] smp: Bringing up secondary CPUs ...
574 07:57:30.619750 <6>[ 0.172742] smp: Brought up 1 node, 1 CPU
575 07:57:30.625624 <6>[ 0.177141] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 07:57:30.631517 <6>[ 0.183911] CPU: All CPU(s) started in SVC mode.
577 07:57:30.651798 <6>[ 0.189095] Memory: 405984K/522240K available (16384K kernel code, 2547K rwdata, 6792K rodata, 2048K init, 430K bss, 49060K reserved, 65536K cma-reserved, 0K highmem)
578 07:57:30.652045 <6>[ 0.205395] devtmpfs: initialized
579 07:57:30.674381 <6>[ 0.222726] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 07:57:30.685868 <6>[ 0.231306] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 07:57:30.691795 <6>[ 0.241764] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 07:57:30.702566 <6>[ 0.254081] pinctrl core: initialized pinctrl subsystem
583 07:57:30.711934 <6>[ 0.264738] DMI not present or invalid.
584 07:57:30.720257 <6>[ 0.270605] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 07:57:30.729684 <6>[ 0.279576] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 07:57:30.744725 <6>[ 0.291060] thermal_sys: Registered thermal governor 'step_wise'
587 07:57:30.745003 <6>[ 0.291223] cpuidle: using governor menu
588 07:57:30.772287 <6>[ 0.326693] No ATAGs?
589 07:57:30.778489 <6>[ 0.329336] hw-breakpoint: debug architecture 0x4 unsupported.
590 07:57:30.788694 <6>[ 0.341409] Serial: AMBA PL011 UART driver
591 07:57:30.821143 <6>[ 0.375468] iommu: Default domain type: Translated
592 07:57:30.830308 <6>[ 0.380820] iommu: DMA domain TLB invalidation policy: strict mode
593 07:57:30.856724 <5>[ 0.410347] SCSI subsystem initialized
594 07:57:30.862499 <6>[ 0.415243] usbcore: registered new interface driver usbfs
595 07:57:30.868323 <6>[ 0.421296] usbcore: registered new interface driver hub
596 07:57:30.875048 <6>[ 0.427078] usbcore: registered new device driver usb
597 07:57:30.880740 <6>[ 0.433628] pps_core: LinuxPPS API ver. 1 registered
598 07:57:30.892363 <6>[ 0.439018] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 07:57:30.899403 <6>[ 0.448747] PTP clock support registered
600 07:57:30.899630 <6>[ 0.453210] EDAC MC: Ver: 3.0.0
601 07:57:30.949061 <6>[ 0.500923] scmi_core: SCMI protocol bus registered
602 07:57:30.964651 <6>[ 0.518320] vgaarb: loaded
603 07:57:30.970606 <6>[ 0.522170] clocksource: Switched to clocksource dmtimer
604 07:57:31.004642 <6>[ 0.558697] NET: Registered PF_INET protocol family
605 07:57:31.017192 <6>[ 0.564409] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 07:57:31.022925 <6>[ 0.573249] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 07:57:31.034371 <6>[ 0.582174] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 07:57:31.040162 <6>[ 0.590415] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 07:57:31.051714 <6>[ 0.598697] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 07:57:31.057565 <6>[ 0.606415] TCP: Hash tables configured (established 4096 bind 4096)
611 07:57:31.063340 <6>[ 0.613333] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 07:57:31.069190 <6>[ 0.620340] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 07:57:31.076734 <6>[ 0.627953] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 07:57:31.162819 <6>[ 0.711602] RPC: Registered named UNIX socket transport module.
615 07:57:31.163101 <6>[ 0.718037] RPC: Registered udp transport module.
616 07:57:31.168576 <6>[ 0.723160] RPC: Registered tcp transport module.
617 07:57:31.174313 <6>[ 0.728264] RPC: Registered tcp-with-tls transport module.
618 07:57:31.187353 <6>[ 0.734193] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 07:57:31.187616 <6>[ 0.741101] PCI: CLS 0 bytes, default 64
620 07:57:31.194518 <5>[ 0.746904] Initialise system trusted keyrings
621 07:57:31.215614 <6>[ 0.767023] Trying to unpack rootfs image as initramfs...
622 07:57:31.294618 <6>[ 0.842802] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 07:57:31.299214 <6>[ 0.850298] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 07:57:31.338864 <5>[ 0.893264] NFS: Registering the id_resolver key type
625 07:57:31.344554 <5>[ 0.898857] Key type id_resolver registered
626 07:57:31.350412 <5>[ 0.903530] Key type id_legacy registered
627 07:57:31.356164 <6>[ 0.907972] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 07:57:31.365698 <6>[ 0.915169] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 07:57:31.438377 <5>[ 0.992888] Key type asymmetric registered
630 07:57:31.444336 <5>[ 0.997411] Asymmetric key parser 'x509' registered
631 07:57:31.455797 <6>[ 1.002941] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 07:57:31.456053 <6>[ 1.010830] io scheduler mq-deadline registered
633 07:57:31.461551 <6>[ 1.015808] io scheduler kyber registered
634 07:57:31.467222 <6>[ 1.020260] io scheduler bfq registered
635 07:57:31.589081 <6>[ 1.139790] ledtrig-cpu: registered to indicate activity on CPUs
636 07:57:31.903649 <6>[ 1.454115] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 07:57:31.933684 <6>[ 1.487614] msm_serial: driver initialized
638 07:57:31.939455 <6>[ 1.492653] SuperH (H)SCI(F) driver initialized
639 07:57:31.945425 <6>[ 1.497772] STMicroelectronics ASC driver initialized
640 07:57:31.948627 <6>[ 1.503464] STM32 USART driver initialized
641 07:57:32.065731 <6>[ 1.619632] brd: module loaded
642 07:57:32.105223 <6>[ 1.659060] loop: module loaded
643 07:57:32.156831 <6>[ 1.710250] CAN device driver interface
644 07:57:32.163377 <6>[ 1.715581] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 07:57:32.169120 <6>[ 1.722662] e1000e: Intel(R) PRO/1000 Network Driver
646 07:57:32.174993 <6>[ 1.728048] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 07:57:32.180776 <6>[ 1.734506] igb: Intel(R) Gigabit Ethernet Network Driver
648 07:57:32.188924 <6>[ 1.740331] igb: Copyright (c) 2007-2014 Intel Corporation.
649 07:57:32.200894 <6>[ 1.749563] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 07:57:32.206518 <6>[ 1.755720] usbcore: registered new interface driver pegasus
651 07:57:32.212443 <6>[ 1.761844] usbcore: registered new interface driver asix
652 07:57:32.218138 <6>[ 1.767738] usbcore: registered new interface driver ax88179_178a
653 07:57:32.223914 <6>[ 1.774342] usbcore: registered new interface driver cdc_ether
654 07:57:32.229762 <6>[ 1.780639] usbcore: registered new interface driver smsc75xx
655 07:57:32.235506 <6>[ 1.786892] usbcore: registered new interface driver smsc95xx
656 07:57:32.241295 <6>[ 1.793125] usbcore: registered new interface driver net1080
657 07:57:32.247130 <6>[ 1.799242] usbcore: registered new interface driver cdc_subset
658 07:57:32.252757 <6>[ 1.805651] usbcore: registered new interface driver zaurus
659 07:57:32.260428 <6>[ 1.811692] usbcore: registered new interface driver cdc_ncm
660 07:57:32.270381 <6>[ 1.821180] usbcore: registered new interface driver usb-storage
661 07:57:32.551619 <6>[ 2.104251] i2c_dev: i2c /dev entries driver
662 07:57:32.612557 <5>[ 2.158919] cpuidle: enable-method property 'ti,am3352' found operations
663 07:57:32.618429 <6>[ 2.168606] sdhci: Secure Digital Host Controller Interface driver
664 07:57:32.625887 <6>[ 2.175376] sdhci: Copyright(c) Pierre Ossman
665 07:57:32.633283 <6>[ 2.181852] Synopsys Designware Multimedia Card Interface Driver
666 07:57:32.638690 <6>[ 2.189926] sdhci-pltfm: SDHCI platform and OF driver helper
667 07:57:32.766532 <6>[ 2.313678] usbcore: registered new interface driver usbhid
668 07:57:32.766802 <6>[ 2.319719] usbhid: USB HID core driver
669 07:57:32.817198 <6>[ 2.369186] NET: Registered PF_INET6 protocol family
670 07:57:32.859148 <6>[ 2.413706] Segment Routing with IPv6
671 07:57:32.865103 <6>[ 2.417857] In-situ OAM (IOAM) with IPv6
672 07:57:32.871721 <6>[ 2.422359] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 07:57:32.877489 <6>[ 2.429626] NET: Registered PF_PACKET protocol family
674 07:57:32.883344 <6>[ 2.435179] can: controller area network core
675 07:57:32.889096 <6>[ 2.440003] NET: Registered PF_CAN protocol family
676 07:57:32.889356 <6>[ 2.445252] can: raw protocol
677 07:57:32.894859 <6>[ 2.448580] can: broadcast manager protocol
678 07:57:32.901487 <6>[ 2.453210] can: netlink gateway - max_hops=1
679 07:57:32.907618 <5>[ 2.458724] Key type dns_resolver registered
680 07:57:32.913865 <6>[ 2.463792] ThumbEE CPU extension supported.
681 07:57:32.914115 <5>[ 2.468479] Registering SWP/SWPB emulation handler
682 07:57:32.923955 <3>[ 2.474182] omap_voltage_late_init: Voltage driver support not added
683 07:57:33.110881 <5>[ 2.662836] Loading compiled-in X.509 certificates
684 07:57:33.239398 <6>[ 2.780934] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 07:57:33.246575 <6>[ 2.797629] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 07:57:33.272954 <3>[ 2.821449] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 07:57:33.473959 <3>[ 3.022354] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 07:57:33.680385 <6>[ 3.233124] OMAP GPIO hardware version 0.1
689 07:57:33.701138 <6>[ 3.251830] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 07:57:33.783700 <4>[ 3.334199] at24 2-0054: supply vcc not found, using dummy regulator
691 07:57:33.819370 <4>[ 3.369878] at24 2-0055: supply vcc not found, using dummy regulator
692 07:57:33.856807 <4>[ 3.407349] at24 2-0056: supply vcc not found, using dummy regulator
693 07:57:33.895507 <4>[ 3.445959] at24 2-0057: supply vcc not found, using dummy regulator
694 07:57:33.934183 <6>[ 3.485370] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 07:57:34.011886 <3>[ 3.559258] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 07:57:34.036543 <6>[ 3.580145] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 07:57:34.058772 <4>[ 3.606569] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 07:57:34.066418 <4>[ 3.615698] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 07:57:34.162374 <6>[ 3.712978] omap_rng 48310000.rng: Random Number Generator ver. 20
700 07:57:34.185835 <5>[ 3.739403] random: crng init done
701 07:57:34.245903 <6>[ 3.800290] Freeing initrd memory: 14452K
702 07:57:34.255791 <6>[ 3.804984] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 07:57:34.306369 <6>[ 3.854636] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 07:57:34.312110 <6>[ 3.864965] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 07:57:34.323861 <6>[ 3.872320] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 07:57:34.329744 <6>[ 3.879776] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 07:57:34.341233 <6>[ 3.887900] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 07:57:34.348604 <6>[ 3.899532] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
709 07:57:34.361784 <5>[ 3.908568] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 07:57:34.389611 <3>[ 3.938468] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 07:57:34.395410 <6>[ 3.947056] edma 49000000.dma: TI EDMA DMA engine driver
712 07:57:34.466803 <3>[ 4.014898] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 07:57:34.481534 <6>[ 4.029271] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 07:57:34.494423 <3>[ 4.046386] l3-aon-clkctrl:0000:0: failed to disable
715 07:57:34.544485 <6>[ 4.093304] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 07:57:34.550225 <6>[ 4.102773] printk: legacy console [ttyS0] enabled
717 07:57:34.555850 <6>[ 4.102773] printk: legacy console [ttyS0] enabled
718 07:57:34.561600 <6>[ 4.113101] printk: legacy bootconsole [omap8250] disabled
719 07:57:34.567439 <6>[ 4.113101] printk: legacy bootconsole [omap8250] disabled
720 07:57:34.605230 <4>[ 4.152935] tps65217-pmic: Failed to locate of_node [id: -1]
721 07:57:34.608804 <4>[ 4.160341] tps65217-bl: Failed to locate of_node [id: -1]
722 07:57:34.625264 <6>[ 4.179998] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 07:57:34.643600 <6>[ 4.186963] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 07:57:34.655368 <6>[ 4.200670] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 07:57:34.661024 <6>[ 4.212561] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 07:57:34.683245 <6>[ 4.232369] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 07:57:34.689100 <6>[ 4.241425] sdhci-omap 48060000.mmc: Got CD GPIO
728 07:57:34.697155 <4>[ 4.246593] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 07:57:34.711593 <4>[ 4.260102] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 07:57:34.718095 <4>[ 4.268743] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 07:57:34.727894 <4>[ 4.277437] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 07:57:34.826287 <6>[ 4.376441] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 07:57:34.869775 <6>[ 4.419107] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 07:57:34.919217 <6>[ 4.466760] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 07:57:34.925890 <6>[ 4.476449] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 07:57:34.990979 <6>[ 4.542434] mmc1: new high speed MMC card at address 0001
737 07:57:34.998502 <6>[ 4.551164] mmcblk1: mmc1:0001 M62704 3.56 GiB
738 07:57:35.009398 <6>[ 4.561894] mmcblk1: p1
739 07:57:35.014746 <6>[ 4.566973] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
740 07:57:35.025378 <6>[ 4.577562] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
741 07:57:35.041639 <6>[ 4.588156] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 07:57:35.056038 <6>[ 4.606894] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
743 07:57:38.174270 <6>[ 7.723206] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
744 07:57:38.247664 <5>[ 7.762181] Sending DHCP requests ., OK
745 07:57:38.258971 <6>[ 7.806612] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.7
746 07:57:38.259251 <6>[ 7.814844] IP-Config: Complete:
747 07:57:38.270212 <6>[ 7.818384] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.7, mask=255.255.255.0, gw=192.168.11.1
748 07:57:38.275960 <6>[ 7.828979] host=192.168.11.7, domain=usen.ad.jp, nis-domain=(none)
749 07:57:38.288227 <6>[ 7.836070] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
750 07:57:38.288499 <6>[ 7.836104] nameserver0=192.168.11.1
751 07:57:38.294338 <6>[ 7.848378] clk: Disabling unused clocks
752 07:57:38.301103 <6>[ 7.853134] PM: genpd: Disabling unused power domains
753 07:57:38.320573 <6>[ 7.871833] Freeing unused kernel image (initmem) memory: 2048K
754 07:57:38.328246 <6>[ 7.881666] Run /init as init process
755 07:57:38.353039 Loading, please wait...
756 07:57:38.428842 Starting systemd-udevd version 252.22-1~deb12u1
757 07:57:41.727656 <4>[ 11.275299] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
758 07:57:41.865393 <4>[ 11.413056] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
759 07:57:42.042354 <6>[ 11.595558] tda998x 0-0070: found TDA19988
760 07:57:42.056371 <6>[ 11.611503] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
761 07:57:42.067388 <6>[ 11.617407] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
762 07:57:42.367909 <6>[ 11.921583] hub 1-0:1.0: USB hub found
763 07:57:42.443590 <6>[ 11.996965] hub 1-0:1.0: 1 port detected
764 07:57:45.317021 Begin: Loading essential drivers ... done.
765 07:57:45.323412 Begin: Running /scripts/init-premount ... done.
766 07:57:45.334761 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
767 07:57:45.340275 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
768 07:57:45.344565 Device /sys/class/net/eth0 found
769 07:57:45.344830 done.
770 07:57:45.422198 Begin: Waiting up to 180 secs for any network device to become available ... done.
771 07:57:45.492760 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
772 07:57:45.493031 IP-Config: eth0 guessed broadcast address 192.168.11.255
773 07:57:45.498381 IP-Config: eth0 complete (dhcp from 192.168.11.1):
774 07:57:45.509508 address: 192.168.11.7 broadcast: 192.168.11.255 netmask: 255.255.255.0
775 07:57:45.515130 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
776 07:57:45.520756 domain : usen.ad.jp
777 07:57:45.525703 rootserver: 192.168.11.1 rootpath:
778 07:57:45.525978 filename :
779 07:57:45.603760 done.
780 07:57:45.614790 Begin: Running /scripts/nfs-bottom ... done.
781 07:57:45.678487 Begin: Running /scripts/init-bottom ... done.
782 07:57:47.112646 <30>[ 16.663483] systemd[1]: System time before build time, advancing clock.
783 07:57:47.304105 <30>[ 16.828876] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
784 07:57:47.312961 <30>[ 16.865728] systemd[1]: Detected architecture arm.
785 07:57:47.325456
786 07:57:47.325697 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
787 07:57:47.325919
788 07:57:47.351198 <30>[ 16.902718] systemd[1]: Hostname set to <debian-bookworm-armhf>.
789 07:57:49.591016 <30>[ 19.141424] systemd[1]: Queued start job for default target graphical.target.
790 07:57:49.608301 <30>[ 19.156445] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
791 07:57:49.615760 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
792 07:57:49.636331 <30>[ 19.185061] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
793 07:57:49.644749 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
794 07:57:49.667062 <30>[ 19.215613] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
795 07:57:49.675329 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
796 07:57:49.695309 <30>[ 19.244175] systemd[1]: Created slice user.slice - User and Session Slice.
797 07:57:49.702031 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
798 07:57:49.730587 <30>[ 19.273580] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
799 07:57:49.736643 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
800 07:57:49.754459 <30>[ 19.303337] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
801 07:57:49.763364 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
802 07:57:49.795443 <30>[ 19.333337] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
803 07:57:49.801957 <30>[ 19.353882] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
804 07:57:49.810373 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
805 07:57:49.833573 <30>[ 19.382645] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
806 07:57:49.841748 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
807 07:57:49.864234 <30>[ 19.412982] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
808 07:57:49.872618 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
809 07:57:49.897212 <30>[ 19.444439] systemd[1]: Reached target paths.target - Path Units.
810 07:57:49.902249 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
811 07:57:49.923567 <30>[ 19.472730] systemd[1]: Reached target remote-fs.target - Remote File Systems.
812 07:57:49.930886 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
813 07:57:49.953598 <30>[ 19.502685] systemd[1]: Reached target slices.target - Slice Units.
814 07:57:49.958988 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
815 07:57:49.984082 <30>[ 19.533056] systemd[1]: Reached target swap.target - Swaps.
816 07:57:49.987989 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
817 07:57:50.014245 <30>[ 19.563012] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
818 07:57:50.023022 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
819 07:57:50.044962 <30>[ 19.593716] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
820 07:57:50.053243 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
821 07:57:50.134567 <30>[ 19.678504] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
822 07:57:50.147227 <30>[ 19.695946] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
823 07:57:50.155621 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
824 07:57:50.175718 <30>[ 19.724089] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
825 07:57:50.183107 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
826 07:57:50.207205 <30>[ 19.755863] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
827 07:57:50.215362 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
828 07:57:50.238826 <30>[ 19.787404] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
829 07:57:50.244467 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
830 07:57:50.277822 <30>[ 19.825594] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
831 07:57:50.285237 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
832 07:57:50.310797 <30>[ 19.853768] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
833 07:57:50.327362 <30>[ 19.870263] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
834 07:57:50.373693 <30>[ 19.922767] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
835 07:57:50.381131 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
836 07:57:50.410228 <30>[ 19.959927] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
837 07:57:50.442584 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
838 07:57:50.544802 <30>[ 20.093345] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
839 07:57:50.567373 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
840 07:57:50.630218 <30>[ 20.179532] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
841 07:57:50.654610 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
842 07:57:50.704601 <30>[ 20.254138] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
843 07:57:50.724091 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
844 07:57:50.783501 <30>[ 20.333631] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
845 07:57:50.804244 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
846 07:57:50.871263 <30>[ 20.420093] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
847 07:57:50.912037 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
848 07:57:50.964764 <30>[ 20.514690] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
849 07:57:50.983543 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
850 07:57:51.025739 <30>[ 20.575718] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
851 07:57:51.053334 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
852 07:57:51.081014 <28>[ 20.624401] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
853 07:57:51.089675 <28>[ 20.638644] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
854 07:57:51.133271 <30>[ 20.683617] systemd[1]: Starting systemd-journald.service - Journal Service...
855 07:57:51.153384 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
856 07:57:51.226645 <30>[ 20.776257] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
857 07:57:51.242739 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
858 07:57:51.281578 <30>[ 20.831464] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
859 07:57:51.333734 Starting [0;1;39msystemd-network-g… units from Kernel command line...
860 07:57:51.397088 <30>[ 20.945583] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
861 07:57:51.443638 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
862 07:57:51.516620 <30>[ 21.065857] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
863 07:57:51.558618 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
864 07:57:51.644621 <30>[ 21.194736] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
865 07:57:51.693618 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
866 07:57:51.714564 <30>[ 21.264442] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
867 07:57:51.739315 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
868 07:57:51.768622 <30>[ 21.317357] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
869 07:57:51.799077 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
870 07:57:51.937315 <30>[ 21.487936] systemd[1]: modprobe@configfs.service: Deactivated successfully.
871 07:57:51.974458 <30>[ 21.523937] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
872 07:57:52.003599 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
873 07:57:52.024789 <30>[ 21.573951] systemd[1]: Started systemd-journald.service - Journal Service.
874 07:57:52.031548 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
875 07:57:52.076812 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
876 07:57:52.109047 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
877 07:57:52.139620 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
878 07:57:52.174796 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
879 07:57:52.204920 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
880 07:57:52.226187 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
881 07:57:52.253556 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
882 07:57:52.276064 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
883 07:57:52.298108 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
884 07:57:52.363328 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
885 07:57:52.406575 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
886 07:57:52.485578 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
887 07:57:52.566446 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
888 07:57:52.656220 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
889 07:57:52.765075 <46>[ 22.315006] systemd-journald[162]: Received client request to flush runtime journal.
890 07:57:52.779547 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
891 07:57:52.946019 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
892 07:57:53.746782 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
893 07:57:53.806278 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
894 07:57:53.875565 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
895 07:57:54.555387 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
896 07:57:54.715762 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
897 07:57:54.735486 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
898 07:57:54.754447 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
899 07:57:54.813704 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
900 07:57:54.861913 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
901 07:57:55.798593 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
902 07:57:55.865715 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
903 07:57:56.290121 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
904 07:57:56.427165 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
905 07:57:56.486729 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
906 07:57:58.064983 <5>[ 27.615329] cfg80211: Loading compiled-in X.509 certificates for regulatory database
907 07:57:58.355757 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
908 07:57:58.796947 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
909 07:57:59.688115 <5>[ 29.240562] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
910 07:57:59.699849 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
911 07:57:59.757704 <5>[ 29.305919] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
912 07:57:59.763449 <4>[ 29.315508] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
913 07:57:59.771223 <6>[ 29.324622] cfg80211: failed to load regulatory.db
914 07:58:01.177714 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
915 07:58:01.222551 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
916 07:58:01.616654 <46>[ 31.157117] systemd-journald[162]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
917 07:58:01.829030 <46>[ 31.372539] systemd-journald[162]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
918 07:58:10.267536 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
919 07:58:10.299488 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
920 07:58:10.325110 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
921 07:58:10.345245 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
922 07:58:10.413084 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
923 07:58:10.456276 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
924 07:58:10.498341 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
925 07:58:10.585152 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
926 07:58:10.641589 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
927 07:58:10.669097 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
928 07:58:10.710718 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
929 07:58:10.737618 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
930 07:58:10.779334 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
931 07:58:10.823081 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
932 07:58:10.863896 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
933 07:58:10.893831 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
934 07:58:10.924445 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
935 07:58:10.953201 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
936 07:58:10.974951 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
937 07:58:10.995986 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
938 07:58:11.033701 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
939 07:58:11.056985 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
940 07:58:11.085984 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
941 07:58:11.153241 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
942 07:58:11.206928 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
943 07:58:11.309824 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
944 07:58:11.385398 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
945 07:58:11.457836 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
946 07:58:11.485504 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
947 07:58:11.498026 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
948 07:58:11.744036 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
949 07:58:11.794146 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
950 07:58:11.852994 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
951 07:58:11.873396 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
952 07:58:11.894946 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
953 07:58:12.106095 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
954 07:58:12.438633 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
955 07:58:12.494077 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
956 07:58:12.519010 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
957 07:58:12.587678 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
958 07:58:12.760110 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
959 07:58:12.893076
960 07:58:12.893355 Debian GNU/Linux 1worm-armhf login: root (automatic login)
961 07:58:12.896403
962 07:58:13.202193 Linux debian-bookworm-armhf 6.12.0-rc1-next-20241004 #1 SMP Fri Oct 4 06:50:11 UTC 2024 armv7l
963 07:58:13.202546
964 07:58:13.207766 The programs included with the Debian GNU/Linux system are free software;
965 07:58:13.213395 the exact distribution terms for each program are described in the
966 07:58:13.218903 individual files in /usr/share/doc/*/copyright.
967 07:58:13.219202
968 07:58:13.224480 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
969 07:58:13.228148 permitted by applicable law.
970 07:58:17.929886 Unable to match end of the kernel message
972 07:58:17.930664 Setting prompt string to ['/ #']
973 07:58:17.930961 end: 2.4.4.1 login-action (duration 00:00:48) [common]
975 07:58:17.931640 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
976 07:58:17.931929 start: 2.4.5 expect-shell-connection (timeout 00:03:23) [common]
977 07:58:17.932178 Setting prompt string to ['/ #']
978 07:58:17.932421 Forcing a shell prompt, looking for ['/ #']
980 07:58:17.982967 / #
981 07:58:17.983338 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
982 07:58:17.983592 Waiting using forced prompt support (timeout 00:02:30)
983 07:58:17.987769
984 07:58:17.994290 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
985 07:58:17.994625 start: 2.4.6 export-device-env (timeout 00:03:23) [common]
986 07:58:17.994882 Sending with 10 millisecond of delay
988 07:58:23.043530 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1201675/extract-nfsrootfs-wrs5zboo'
989 07:58:23.054119 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1201675/extract-nfsrootfs-wrs5zboo'
990 07:58:23.055285 Sending with 10 millisecond of delay
992 07:58:25.213602 / # export NFS_SERVER_IP='192.168.11.5'
993 07:58:25.224223 export NFS_SERVER_IP='192.168.11.5'
994 07:58:25.225315 end: 2.4.6 export-device-env (duration 00:00:07) [common]
995 07:58:25.225663 end: 2.4 uboot-commands (duration 00:01:44) [common]
996 07:58:25.225974 end: 2 uboot-action (duration 00:01:44) [common]
997 07:58:25.226276 start: 3 lava-test-retry (timeout 00:06:54) [common]
998 07:58:25.226581 start: 3.1 lava-test-shell (timeout 00:06:54) [common]
999 07:58:25.226829 Using namespace: common
1001 07:58:25.327505 / # #
1002 07:58:25.327941 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1003 07:58:25.332313 #
1004 07:58:25.338583 Using /lava-1201675
1006 07:58:25.439313 / # export SHELL=/bin/bash
1007 07:58:25.445652 export SHELL=/bin/bash
1009 07:58:25.560505 / # . /lava-1201675/environment
1010 07:58:25.565332 . /lava-1201675/environment
1012 07:58:25.681010 / # /lava-1201675/bin/lava-test-runner /lava-1201675/0
1013 07:58:25.681391 Test shell timeout: 10s (minimum of the action and connection timeout)
1014 07:58:25.685692 /lava-1201675/bin/lava-test-runner /lava-1201675/0
1015 07:58:26.079067 + export TESTRUN_ID=0_timesync-off
1016 07:58:26.087105 + TESTRUN_ID=0_timesync-off
1017 07:58:26.087397 + cd /lava-1201675/0/tests/0_timesync-off
1018 07:58:26.087626 ++ cat uuid
1019 07:58:26.102778 + UUID=1201675_1.6.2.4.1
1020 07:58:26.103056 + set +x
1021 07:58:26.108420 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1201675_1.6.2.4.1>
1022 07:58:26.108879 Received signal: <STARTRUN> 0_timesync-off 1201675_1.6.2.4.1
1023 07:58:26.109119 Starting test lava.0_timesync-off (1201675_1.6.2.4.1)
1024 07:58:26.109391 Skipping test definition patterns.
1025 07:58:26.111588 + systemctl stop systemd-timesyncd
1026 07:58:26.407029 + set +x
1027 07:58:26.407615 Received signal: <ENDRUN> 0_timesync-off 1201675_1.6.2.4.1
1028 07:58:26.407899 Ending use of test pattern.
1029 07:58:26.408123 Ending test lava.0_timesync-off (1201675_1.6.2.4.1), duration 0.30
1031 07:58:26.410093 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1201675_1.6.2.4.1>
1032 07:58:26.584825 + export TESTRUN_ID=1_kselftest-dt
1033 07:58:26.592813 + TESTRUN_ID=1_kselftest-dt
1034 07:58:26.593059 + cd /lava-1201675/0/tests/1_kselftest-dt
1035 07:58:26.593287 ++ cat uuid
1036 07:58:26.621327 + UUID=1201675_1.6.2.4.5
1037 07:58:26.621635 + set +x
1038 07:58:26.626769 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1201675_1.6.2.4.5>
1039 07:58:26.627006 + cd ./automated/linux/kselftest/
1040 07:58:26.627446 Received signal: <STARTRUN> 1_kselftest-dt 1201675_1.6.2.4.5
1041 07:58:26.627692 Starting test lava.1_kselftest-dt (1201675_1.6.2.4.5)
1042 07:58:26.627969 Skipping test definition patterns.
1043 07:58:26.653262 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241004/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1044 07:58:26.761768 INFO: install_deps skipped
1045 07:58:27.332148 --2024-10-04 07:58:27-- http://storage.kernelci.org/next/master/next-20241004/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1046 07:58:27.361668 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1047 07:58:27.476348 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1048 07:58:27.590439 HTTP request sent, awaiting response... 200 OK
1049 07:58:27.590717 Length: 3815132 (3.6M) [application/octet-stream]
1050 07:58:27.596009 Saving to: 'kselftest_armhf.tar.gz'
1051 07:58:27.596305
1052 07:58:29.233709 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 1%[ ] 49.92K 224KB/s kselftest_armhf.tar 5%[> ] 218.67K 486KB/s kselftest_armhf.tar 19%[==> ] 708.48K 966KB/s kselftest_armhf.tar 32%[=====> ] 1.18M 1.21MB/s kselftest_armhf.tar 60%[===========> ] 2.19M 1.87MB/s kselftest_armhf.tar 78%[==============> ] 2.86M 2.08MB/s kselftest_armhf.tar 97%[==================> ] 3.54M 2.24MB/s kselftest_armhf.tar 100%[===================>] 3.64M 2.22MB/s in 1.6s
1053 07:58:29.234096
1054 07:58:29.831391 2024-10-04 07:58:29 (2.22 MB/s) - 'kselftest_armhf.tar.gz' saved [3815132/3815132]
1055 07:58:29.831730
1056 07:58:52.103876 skiplist:
1057 07:58:52.104250 ========================================
1058 07:58:52.109475 ========================================
1059 07:58:52.217809 dt:test_unprobed_devices.sh
1060 07:58:52.252615 ============== Tests to run ===============
1061 07:58:52.260041 dt:test_unprobed_devices.sh
1062 07:58:52.263972 ===========End Tests to run ===============
1063 07:58:52.273843 shardfile-dt pass
1064 07:58:52.499978 <12>[ 82.055980] kselftest: Running tests in dt
1065 07:58:52.527881 TAP version 13
1066 07:58:52.551272 1..1
1067 07:58:52.605271 # timeout set to 45
1068 07:58:52.605544 # selftests: dt: test_unprobed_devices.sh
1069 07:58:53.429912 # TAP version 13
1070 07:59:18.727298 # 1..257
1071 07:59:18.900075 # ok 1 / # SKIP
1072 07:59:18.927633 # ok 2 /clk_mcasp0
1073 07:59:18.995159 # ok 3 /clk_mcasp0_fixed # SKIP
1074 07:59:19.071870 # ok 4 /cpus/cpu@0 # SKIP
1075 07:59:19.144408 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1076 07:59:19.162790 # ok 6 /fixedregulator0
1077 07:59:19.187799 # ok 7 /leds
1078 07:59:19.204287 # ok 8 /ocp
1079 07:59:19.229526 # ok 9 /ocp/interconnect@44c00000
1080 07:59:19.254615 # ok 10 /ocp/interconnect@44c00000/segment@0
1081 07:59:19.281187 # ok 11 /ocp/interconnect@44c00000/segment@100000
1082 07:59:19.305779 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1083 07:59:19.377328 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1084 07:59:19.396797 # ok 14 /ocp/interconnect@44c00000/segment@200000
1085 07:59:19.425832 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1086 07:59:19.529399 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1087 07:59:19.603488 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1088 07:59:19.679113 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1089 07:59:19.755503 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1090 07:59:19.829237 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1091 07:59:19.900766 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1092 07:59:19.972761 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1093 07:59:20.045855 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1094 07:59:20.124405 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1095 07:59:20.193624 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1096 07:59:20.266473 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1097 07:59:20.345118 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1098 07:59:20.419232 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1099 07:59:20.488471 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1100 07:59:20.561089 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1101 07:59:20.635087 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1102 07:59:20.707943 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1103 07:59:20.782711 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1104 07:59:20.855100 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1105 07:59:20.934576 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1106 07:59:21.002956 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1107 07:59:21.077087 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1108 07:59:21.155785 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1109 07:59:21.229693 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1110 07:59:21.304475 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1111 07:59:21.378705 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1112 07:59:21.450197 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1113 07:59:21.522661 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1114 07:59:21.596452 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1115 07:59:21.672406 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1116 07:59:21.743559 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1117 07:59:21.817615 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1118 07:59:21.895445 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1119 07:59:21.965061 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1120 07:59:22.039101 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1121 07:59:22.113537 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1122 07:59:22.187409 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1123 07:59:22.266292 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1124 07:59:22.340775 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1125 07:59:22.411433 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1126 07:59:22.485680 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1127 07:59:22.559207 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1128 07:59:22.632362 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1129 07:59:22.705726 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1130 07:59:22.785345 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1131 07:59:22.854582 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1132 07:59:22.928424 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1133 07:59:23.003760 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1134 07:59:23.077948 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1135 07:59:23.154185 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1136 07:59:23.228742 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1137 07:59:23.303812 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1138 07:59:23.376924 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1139 07:59:23.450425 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1140 07:59:23.524585 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1141 07:59:23.598098 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1142 07:59:23.678626 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1143 07:59:23.749950 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1144 07:59:23.826479 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1145 07:59:23.895992 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1146 07:59:23.969673 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1147 07:59:24.043587 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1148 07:59:24.119732 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1149 07:59:24.191717 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1150 07:59:24.264922 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1151 07:59:24.338599 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1152 07:59:24.416806 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1153 07:59:24.488857 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1154 07:59:24.561888 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1155 07:59:24.632162 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1156 07:59:24.705632 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1157 07:59:24.785412 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1158 07:59:24.853501 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1159 07:59:24.929038 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1160 07:59:25.003871 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1161 07:59:25.075620 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1162 07:59:25.152741 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1163 07:59:25.225408 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1164 07:59:25.299573 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1165 07:59:25.320775 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1166 07:59:25.344972 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1167 07:59:25.373871 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1168 07:59:25.397479 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1169 07:59:25.426125 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1170 07:59:25.443703 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1171 07:59:25.468477 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1172 07:59:25.491145 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1173 07:59:25.600748 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1174 07:59:25.628268 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1175 07:59:25.656374 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1176 07:59:25.678102 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1177 07:59:25.784865 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1178 07:59:25.862361 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1179 07:59:25.934460 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1180 07:59:26.008925 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1181 07:59:26.083078 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1182 07:59:26.156833 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1183 07:59:26.232413 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1184 07:59:26.309424 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1185 07:59:26.379969 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1186 07:59:26.456091 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1187 07:59:26.530058 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1188 07:59:26.607648 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1189 07:59:26.680026 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1190 07:59:26.753581 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1191 07:59:26.828425 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1192 07:59:26.904661 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1193 07:59:26.924660 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1194 07:59:26.997517 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1195 07:59:27.073228 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1196 07:59:27.147929 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1197 07:59:27.168416 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1198 07:59:27.239762 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1199 07:59:27.263537 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1200 07:59:27.343730 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1201 07:59:27.365558 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1202 07:59:27.387262 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1203 07:59:27.409819 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1204 07:59:27.437367 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1205 07:59:27.462151 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1206 07:59:27.487027 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1207 07:59:27.514657 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1208 07:59:27.590449 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1209 07:59:27.613332 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1210 07:59:27.633279 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1211 07:59:27.708776 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1212 07:59:27.781277 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1213 07:59:27.799648 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1214 07:59:27.902444 # not ok 144 /ocp/interconnect@47c00000
1215 07:59:27.979667 # not ok 145 /ocp/interconnect@47c00000/segment@0
1216 07:59:28.000652 # ok 146 /ocp/interconnect@48000000
1217 07:59:28.024526 # ok 147 /ocp/interconnect@48000000/segment@0
1218 07:59:28.045384 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1219 07:59:28.069467 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1220 07:59:28.092931 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1221 07:59:28.121265 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1222 07:59:28.144647 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1223 07:59:28.166882 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1224 07:59:28.187915 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1225 07:59:28.260446 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1226 07:59:28.333746 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1227 07:59:28.361000 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1228 07:59:28.381016 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1229 07:59:28.403379 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1230 07:59:28.433161 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1231 07:59:28.455644 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1232 07:59:28.476870 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1233 07:59:28.498655 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1234 07:59:28.526940 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1235 07:59:28.549378 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1236 07:59:28.569890 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1237 07:59:28.593484 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1238 07:59:28.617452 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1239 07:59:28.640868 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1240 07:59:28.666564 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1241 07:59:28.689156 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1242 07:59:28.713870 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1243 07:59:28.741269 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1244 07:59:28.766312 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1245 07:59:28.784703 # ok 175 /ocp/interconnect@48000000/segment@100000
1246 07:59:28.808867 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1247 07:59:28.833184 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1248 07:59:28.908370 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1249 07:59:28.988677 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1250 07:59:29.058802 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1251 07:59:29.136284 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1252 07:59:29.208832 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1253 07:59:29.286728 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1254 07:59:29.353915 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1255 07:59:29.429555 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1256 07:59:29.449915 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1257 07:59:29.473455 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1258 07:59:29.501566 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1259 07:59:29.521233 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1260 07:59:29.544499 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1261 07:59:29.569867 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1262 07:59:29.596384 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1263 07:59:29.618217 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1264 07:59:29.641563 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1265 07:59:29.665198 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1266 07:59:29.688917 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1267 07:59:29.713443 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1268 07:59:29.734297 # ok 198 /ocp/interconnect@48000000/segment@200000
1269 07:59:29.759414 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1270 07:59:29.833070 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1271 07:59:29.859294 # ok 201 /ocp/interconnect@48000000/segment@300000
1272 07:59:29.884272 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1273 07:59:29.906386 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1274 07:59:29.929285 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1275 07:59:29.952187 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1276 07:59:29.975896 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1277 07:59:30.004137 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1278 07:59:30.077388 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1279 07:59:30.093324 # ok 209 /ocp/interconnect@4a000000
1280 07:59:30.120128 # ok 210 /ocp/interconnect@4a000000/segment@0
1281 07:59:30.145517 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1282 07:59:30.166050 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1283 07:59:30.196015 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1284 07:59:30.216118 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1285 07:59:30.288648 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1286 07:59:30.397255 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1287 07:59:30.476138 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1288 07:59:30.583160 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1289 07:59:30.652747 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1290 07:59:30.726118 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1291 07:59:30.827550 # not ok 221 /ocp/interconnect@4b140000
1292 07:59:30.904631 # not ok 222 /ocp/interconnect@4b140000/segment@0
1293 07:59:30.973768 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1294 07:59:31.000164 # ok 224 /ocp/target-module@40300000
1295 07:59:31.023540 # ok 225 /ocp/target-module@40300000/sram@0
1296 07:59:31.096185 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1297 07:59:31.172649 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1298 07:59:31.192499 # ok 228 /ocp/target-module@47400000
1299 07:59:31.213122 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1300 07:59:31.240383 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1301 07:59:31.259119 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1302 07:59:31.284329 # ok 232 /ocp/target-module@47400000/usb@1400
1303 07:59:31.304993 # ok 233 /ocp/target-module@47400000/usb@1800
1304 07:59:31.331143 # ok 234 /ocp/target-module@47810000
1305 07:59:31.353381 # ok 235 /ocp/target-module@49000000
1306 07:59:31.373867 # ok 236 /ocp/target-module@49000000/dma@0
1307 07:59:31.395648 # ok 237 /ocp/target-module@49800000
1308 07:59:31.423115 # ok 238 /ocp/target-module@49800000/dma@0
1309 07:59:31.443528 # ok 239 /ocp/target-module@49900000
1310 07:59:31.469496 # ok 240 /ocp/target-module@49900000/dma@0
1311 07:59:31.492287 # ok 241 /ocp/target-module@49a00000
1312 07:59:31.511238 # ok 242 /ocp/target-module@49a00000/dma@0
1313 07:59:31.538111 # ok 243 /ocp/target-module@4c000000
1314 07:59:31.610482 # not ok 244 /ocp/target-module@4c000000/emif@0
1315 07:59:31.632144 # ok 245 /ocp/target-module@50000000
1316 07:59:31.650485 # ok 246 /ocp/target-module@53100000
1317 07:59:31.724978 # not ok 247 /ocp/target-module@53100000/sham@0
1318 07:59:31.750861 # ok 248 /ocp/target-module@53500000
1319 07:59:31.824248 # not ok 249 /ocp/target-module@53500000/aes@0
1320 07:59:31.842383 # ok 250 /ocp/target-module@56000000
1321 07:59:31.954485 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1322 07:59:32.020430 # ok 252 /opp-table # SKIP
1323 07:59:32.092393 # ok 253 /soc # SKIP
1324 07:59:32.113793 # ok 254 /sound
1325 07:59:32.138664 # ok 255 /target-module@4b000000
1326 07:59:32.164840 # ok 256 /target-module@4b000000/target-module@140000
1327 07:59:32.184693 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1328 07:59:32.193073 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1329 07:59:32.201346 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1330 07:59:34.402993 dt_test_unprobed_devices_sh_ skip
1331 07:59:34.408597 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1332 07:59:34.414177 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1333 07:59:34.414446 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1334 07:59:34.419818 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1335 07:59:34.425301 dt_test_unprobed_devices_sh_fixedregulator0 pass
1336 07:59:34.430940 dt_test_unprobed_devices_sh_leds pass
1337 07:59:34.431210 dt_test_unprobed_devices_sh_ocp pass
1338 07:59:34.436583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1339 07:59:34.442176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1340 07:59:34.447797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1341 07:59:34.459183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1342 07:59:34.464681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1343 07:59:34.470250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1344 07:59:34.481369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1345 07:59:34.486990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1346 07:59:34.498159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1347 07:59:34.509373 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1348 07:59:34.520659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1349 07:59:34.526299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1350 07:59:34.537522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1351 07:59:34.548655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1352 07:59:34.559871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1353 07:59:34.570993 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1354 07:59:34.576660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1355 07:59:34.587867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1356 07:59:34.598994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1357 07:59:34.610261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1358 07:59:34.621367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1359 07:59:34.627015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1360 07:59:34.638134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1361 07:59:34.649366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1362 07:59:34.660652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1363 07:59:34.666116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1364 07:59:34.677366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1365 07:59:34.688529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1366 07:59:34.699736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1367 07:59:34.710986 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1368 07:59:34.716529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1369 07:59:34.727738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1370 07:59:34.738897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1371 07:59:34.750150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1372 07:59:34.761236 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1373 07:59:34.772526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1374 07:59:34.783733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1375 07:59:34.794886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1376 07:59:34.806172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1377 07:59:34.817296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1378 07:59:34.828543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1379 07:59:34.839669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1380 07:59:34.850920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1381 07:59:34.862043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1382 07:59:34.873292 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1383 07:59:34.884541 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1384 07:59:34.895667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1385 07:59:34.906915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1386 07:59:34.918164 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1387 07:59:34.929415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1388 07:59:34.940540 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1389 07:59:34.951915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1390 07:59:34.963038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1391 07:59:34.974287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1392 07:59:34.985538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1393 07:59:34.996665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1394 07:59:35.002287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1395 07:59:35.013536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1396 07:59:35.024664 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1397 07:59:35.035909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1398 07:59:35.047033 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1399 07:59:35.058284 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1400 07:59:35.069410 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1401 07:59:35.080660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1402 07:59:35.091913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1403 07:59:35.103035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1404 07:59:35.114285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1405 07:59:35.125407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1406 07:59:35.136657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1407 07:59:35.147906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1408 07:59:35.159029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1409 07:59:35.170158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1410 07:59:35.181405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1411 07:59:35.192533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1412 07:59:35.198156 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1413 07:59:35.209409 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1414 07:59:35.220531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1415 07:59:35.231906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1416 07:59:35.243028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1417 07:59:35.248654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1418 07:59:35.265531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1419 07:59:35.276656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1420 07:59:35.282278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1421 07:59:35.299229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1422 07:59:35.310403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1423 07:59:35.321571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1424 07:59:35.327148 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1425 07:59:35.338454 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1426 07:59:35.349555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1427 07:59:35.355165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1428 07:59:35.366400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1429 07:59:35.377539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1430 07:59:35.383151 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1431 07:59:35.394401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1432 07:59:35.399898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1433 07:59:35.411149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1434 07:59:35.422274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1435 07:59:35.433563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1436 07:59:35.444700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1437 07:59:35.455897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1438 07:59:35.467183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1439 07:59:35.478297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1440 07:59:35.489519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1441 07:59:35.500659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1442 07:59:35.511891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1443 07:59:35.523018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1444 07:59:35.534266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1445 07:59:35.550978 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1446 07:59:35.562242 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1447 07:59:35.573366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1448 07:59:35.584634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1449 07:59:35.595883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1450 07:59:35.612635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1451 07:59:35.623886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1452 07:59:35.635013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1453 07:59:35.646149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1454 07:59:35.651761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1455 07:59:35.663029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1456 07:59:35.674167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1457 07:59:35.679756 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1458 07:59:35.691008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1459 07:59:35.696510 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1460 07:59:35.707784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1461 07:59:35.713386 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1462 07:59:35.724502 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1463 07:59:35.730133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1464 07:59:35.741287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1465 07:59:35.746905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1466 07:59:35.758168 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1467 07:59:35.769268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1468 07:59:35.780500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1469 07:59:35.791630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1470 07:59:35.802875 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1471 07:59:35.808506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1472 07:59:35.819608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1473 07:59:35.825201 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1474 07:59:35.830820 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1475 07:59:35.836467 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1476 07:59:35.842030 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1477 07:59:35.847591 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1478 07:59:35.858897 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1479 07:59:35.864403 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1480 07:59:35.870026 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1481 07:59:35.881270 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1482 07:59:35.886900 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1483 07:59:35.897942 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1484 07:59:35.903590 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1485 07:59:35.914844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1486 07:59:35.920334 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1487 07:59:35.931562 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1488 07:59:35.937070 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1489 07:59:35.948378 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1490 07:59:35.954001 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1491 07:59:35.965124 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1492 07:59:35.970750 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1493 07:59:35.981997 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1494 07:59:35.987519 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1495 07:59:35.993129 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1496 07:59:36.004273 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1497 07:59:36.009877 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1498 07:59:36.021124 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1499 07:59:36.026748 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1500 07:59:36.037888 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1501 07:59:36.043516 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1502 07:59:36.054742 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1503 07:59:36.060268 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1504 07:59:36.065893 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1505 07:59:36.077121 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1506 07:59:36.082643 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1507 07:59:36.093888 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1508 07:59:36.104995 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1509 07:59:36.116266 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1510 07:59:36.127493 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1511 07:59:36.138615 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1512 07:59:36.149866 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1513 07:59:36.161009 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1514 07:59:36.172278 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1515 07:59:36.177869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1516 07:59:36.188989 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1517 07:59:36.194616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1518 07:59:36.205864 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1519 07:59:36.211367 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1520 07:59:36.222695 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1521 07:59:36.228242 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1522 07:59:36.239333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1523 07:59:36.245017 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1524 07:59:36.256253 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1525 07:59:36.261859 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1526 07:59:36.272989 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1527 07:59:36.278630 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1528 07:59:36.289879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1529 07:59:36.295365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1530 07:59:36.301002 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1531 07:59:36.312158 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1532 07:59:36.317786 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1533 07:59:36.328898 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1534 07:59:36.334619 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1535 07:59:36.345817 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1536 07:59:36.351320 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1537 07:59:36.362607 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1538 07:59:36.368230 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1539 07:59:36.373825 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1540 07:59:36.379326 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1541 07:59:36.390598 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1542 07:59:36.401820 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1543 07:59:36.407355 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1544 07:59:36.412970 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1545 07:59:36.424209 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1546 07:59:36.435315 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1547 07:59:36.446572 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1548 07:59:36.457925 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1549 07:59:36.463464 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1550 07:59:36.469226 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1551 07:59:36.475025 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1552 07:59:36.480576 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1553 07:59:36.486073 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1554 07:59:36.491697 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1555 07:59:36.502959 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1556 07:59:36.508530 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1557 07:59:36.514077 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1558 07:59:36.519746 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1559 07:59:36.525366 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1560 07:59:36.536617 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1561 07:59:36.542248 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1562 07:59:36.547853 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1563 07:59:36.553371 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1564 07:59:36.558994 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1565 07:59:36.564621 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1566 07:59:36.570260 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1567 07:59:36.575875 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1568 07:59:36.581374 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1569 07:59:36.586979 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1570 07:59:36.592622 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1571 07:59:36.598242 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1572 07:59:36.603866 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1573 07:59:36.609370 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1574 07:59:36.615025 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1575 07:59:36.620620 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1576 07:59:36.626244 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1577 07:59:36.631867 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1578 07:59:36.637369 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1579 07:59:36.642993 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1580 07:59:36.648617 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1581 07:59:36.648896 dt_test_unprobed_devices_sh_opp-table skip
1582 07:59:36.654273 dt_test_unprobed_devices_sh_soc skip
1583 07:59:36.659866 dt_test_unprobed_devices_sh_sound pass
1584 07:59:36.665497 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1585 07:59:36.670986 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1586 07:59:36.676720 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1587 07:59:36.682253 dt_test_unprobed_devices_sh fail
1588 07:59:36.682528 + ../../utils/send-to-lava.sh ./output/result.txt
1589 07:59:36.689159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1590 07:59:36.689710 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1592 07:59:36.698333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1593 07:59:36.698816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1595 07:59:36.792243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1596 07:59:36.792724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1598 07:59:36.884721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1599 07:59:36.885209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1601 07:59:36.980591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1602 07:59:36.981080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1604 07:59:37.080103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1605 07:59:37.080612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1607 07:59:37.176956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1608 07:59:37.177441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1610 07:59:37.274439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1611 07:59:37.274928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1613 07:59:37.373061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1614 07:59:37.373546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1616 07:59:37.472068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1617 07:59:37.472706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1619 07:59:37.569414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1620 07:59:37.569981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1622 07:59:37.666931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1623 07:59:37.667414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1625 07:59:37.766870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1626 07:59:37.767347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1628 07:59:37.862225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1629 07:59:37.862701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1631 07:59:37.957838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1632 07:59:37.958338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1634 07:59:38.058636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1635 07:59:38.059111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1637 07:59:38.153455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1638 07:59:38.153933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1640 07:59:38.251632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1641 07:59:38.252150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1643 07:59:38.351930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1644 07:59:38.352428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1646 07:59:38.450013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1647 07:59:38.450545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1649 07:59:38.541952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1650 07:59:38.542521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1652 07:59:38.641641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1653 07:59:38.642165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1655 07:59:38.739013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1656 07:59:38.739499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1658 07:59:38.836007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1659 07:59:38.836512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1661 07:59:38.933791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1662 07:59:38.934278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1664 07:59:39.031285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1665 07:59:39.031757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1667 07:59:39.123983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1668 07:59:39.124481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1670 07:59:39.220085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1671 07:59:39.220587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1673 07:59:39.315991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1674 07:59:39.316498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1676 07:59:39.410809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1677 07:59:39.411285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1679 07:59:39.509818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1680 07:59:39.510362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1682 07:59:39.608550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1683 07:59:39.609024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1685 07:59:39.704023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1686 07:59:39.704533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1688 07:59:39.802554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1689 07:59:39.803030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1691 07:59:39.899433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1692 07:59:39.899906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1694 07:59:39.995108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1695 07:59:39.995591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1697 07:59:40.091970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1698 07:59:40.092474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1700 07:59:40.188838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1701 07:59:40.189319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1703 07:59:40.284883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1704 07:59:40.285365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1706 07:59:40.383860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1707 07:59:40.384341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1709 07:59:40.481413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1710 07:59:40.481905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1712 07:59:40.576911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1713 07:59:40.577473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1715 07:59:40.676645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1716 07:59:40.677129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1718 07:59:40.777151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1719 07:59:40.777639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1721 07:59:40.875542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1722 07:59:40.876025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1724 07:59:40.973146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1725 07:59:40.973628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1727 07:59:41.070391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1728 07:59:41.070914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1730 07:59:41.167000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1731 07:59:41.167497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1733 07:59:41.266331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1734 07:59:41.266807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1736 07:59:41.362800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1737 07:59:41.363259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1739 07:59:41.461571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1740 07:59:41.462049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1742 07:59:41.558221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1743 07:59:41.558784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1745 07:59:41.657121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1746 07:59:41.657620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1748 07:59:41.756328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1749 07:59:41.756803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1751 07:59:41.857276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1752 07:59:41.857760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1754 07:59:41.956816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1755 07:59:41.957298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1757 07:59:42.056168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1758 07:59:42.056673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1760 07:59:42.153805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1761 07:59:42.154286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1763 07:59:42.251807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1764 07:59:42.252279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1766 07:59:42.347288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1767 07:59:42.347763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1769 07:59:42.440166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1770 07:59:42.440653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1772 07:59:42.535147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1773 07:59:42.535682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1775 07:59:42.631478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1776 07:59:42.631962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1778 07:59:42.731235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1779 07:59:42.731715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1781 07:59:42.832505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1782 07:59:42.832978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1784 07:59:42.933020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1785 07:59:42.933489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1787 07:59:43.032935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1788 07:59:43.033415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1790 07:59:43.133190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1791 07:59:43.133671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1793 07:59:43.231998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1794 07:59:43.232490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1796 07:59:43.330643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1797 07:59:43.331131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1799 07:59:43.427249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1800 07:59:43.427695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1802 07:59:43.526271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1803 07:59:43.526810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1805 07:59:43.624632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1806 07:59:43.625087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1808 07:59:43.724747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1809 07:59:43.725257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1811 07:59:43.825992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1812 07:59:43.826494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1814 07:59:43.924998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1815 07:59:43.925504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1817 07:59:44.023901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1818 07:59:44.024390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1820 07:59:44.122678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1821 07:59:44.123166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1823 07:59:44.220320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1824 07:59:44.220790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1826 07:59:44.318846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1827 07:59:44.319332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1829 07:59:44.416856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1830 07:59:44.417360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1832 07:59:44.515757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1833 07:59:44.516334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1835 07:59:44.610286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1836 07:59:44.610771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1838 07:59:44.707051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1839 07:59:44.707565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1841 07:59:44.804137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1842 07:59:44.804636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1844 07:59:44.902752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1845 07:59:44.903223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1847 07:59:45.004284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1848 07:59:45.004766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1850 07:59:45.103958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1851 07:59:45.104474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1853 07:59:45.204539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1854 07:59:45.205023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1856 07:59:45.304752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1857 07:59:45.305238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1859 07:59:45.403884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1860 07:59:45.404365 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1862 07:59:45.500617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1863 07:59:45.501095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1865 07:59:45.601860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1866 07:59:45.602403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1868 07:59:45.698365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1869 07:59:45.698836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1871 07:59:45.795744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1872 07:59:45.796244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1874 07:59:45.891219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1875 07:59:45.891698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1877 07:59:45.993895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1878 07:59:45.994388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1880 07:59:46.093977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1881 07:59:46.094477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1883 07:59:46.191614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1884 07:59:46.192086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1886 07:59:46.290945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1887 07:59:46.291396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1889 07:59:46.391715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1890 07:59:46.392194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1892 07:59:46.504830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1893 07:59:46.505310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1895 07:59:46.609311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1896 07:59:46.609861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1898 07:59:46.711819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1899 07:59:46.712255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1901 07:59:46.814239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1902 07:59:46.814729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1904 07:59:46.914608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1905 07:59:46.915132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1907 07:59:47.014232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1908 07:59:47.014726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1910 07:59:47.115830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1911 07:59:47.116318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1913 07:59:47.218731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1914 07:59:47.219222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1916 07:59:47.316224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1917 07:59:47.316740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1919 07:59:47.413551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1920 07:59:47.414034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1922 07:59:47.509815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1923 07:59:47.510309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1925 07:59:47.607694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1926 07:59:47.608268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1928 07:59:47.706836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1929 07:59:47.707341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1931 07:59:47.805546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1932 07:59:47.806082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1934 07:59:47.904008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1935 07:59:47.904520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1937 07:59:48.004063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1938 07:59:48.004574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1940 07:59:48.102098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1941 07:59:48.102576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1943 07:59:48.199006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1944 07:59:48.199499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1946 07:59:48.295110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1947 07:59:48.295582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1949 07:59:48.392239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1951 07:59:48.395462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1952 07:59:48.492217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1954 07:59:48.495494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1955 07:59:48.586596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1957 07:59:48.589611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1958 07:59:48.679833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1959 07:59:48.680341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1961 07:59:48.779639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1962 07:59:48.780140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1964 07:59:48.875783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1965 07:59:48.876267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1967 07:59:48.977725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1968 07:59:48.978235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1970 07:59:49.075030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1971 07:59:49.075532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1973 07:59:49.176229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1974 07:59:49.176731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1976 07:59:49.275731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1977 07:59:49.276252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1979 07:59:49.377457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1980 07:59:49.377958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1982 07:59:49.474827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1983 07:59:49.475336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1985 07:59:49.576149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1986 07:59:49.576730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1988 07:59:49.674419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1989 07:59:49.674908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1991 07:59:49.773599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1992 07:59:49.774076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1994 07:59:49.870576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1995 07:59:49.871061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1997 07:59:49.974121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1998 07:59:49.974609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2000 07:59:50.075094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2001 07:59:50.075569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2003 07:59:50.170577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2004 07:59:50.171053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2006 07:59:50.267328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2007 07:59:50.267787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2009 07:59:50.366345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2010 07:59:50.366819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2012 07:59:50.463904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2013 07:59:50.464391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2015 07:59:50.561561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2016 07:59:50.562125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2018 07:59:50.658853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2019 07:59:50.659335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2021 07:59:50.756721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2022 07:59:50.757214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2024 07:59:50.860850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2025 07:59:50.861329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2027 07:59:50.960098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2028 07:59:50.960597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2030 07:59:51.059710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2031 07:59:51.060192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2033 07:59:51.160432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2034 07:59:51.160913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2036 07:59:51.260563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2037 07:59:51.261043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2039 07:59:51.361928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2040 07:59:51.362411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2042 07:59:51.461752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2043 07:59:51.462235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2045 07:59:51.561793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2046 07:59:51.562378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2048 07:59:51.661010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2049 07:59:51.661487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2051 07:59:51.759985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2052 07:59:51.760478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2054 07:59:51.859007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2055 07:59:51.859483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2057 07:59:51.954436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2058 07:59:51.954913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2060 07:59:52.046214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2061 07:59:52.046680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2063 07:59:52.143591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2064 07:59:52.144091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2066 07:59:52.243944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2067 07:59:52.244456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2069 07:59:52.343632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2070 07:59:52.344144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2072 07:59:52.441443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2073 07:59:52.441935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2075 07:59:52.542721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2076 07:59:52.543349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2078 07:59:52.642160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2079 07:59:52.642759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2081 07:59:52.742652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2082 07:59:52.743153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2084 07:59:52.841918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2085 07:59:52.842413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2087 07:59:52.941963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2088 07:59:52.942453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2090 07:59:53.043776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2091 07:59:53.044271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2093 07:59:53.142765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2094 07:59:53.143278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2096 07:59:53.240475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2097 07:59:53.240964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2099 07:59:53.339343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2100 07:59:53.339804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2102 07:59:53.436359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2103 07:59:53.436814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2105 07:59:53.533974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2106 07:59:53.534430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2108 07:59:53.630138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2109 07:59:53.630715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2111 07:59:53.728699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2112 07:59:53.729189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2114 07:59:53.821626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2115 07:59:53.822132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2117 07:59:53.924386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2118 07:59:53.924882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2120 07:59:54.023368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2121 07:59:54.023862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2123 07:59:54.124384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2124 07:59:54.124910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2126 07:59:54.223645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2127 07:59:54.224147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2129 07:59:54.322479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2130 07:59:54.322977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2132 07:59:54.423309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2133 07:59:54.423804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2135 07:59:54.519343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2136 07:59:54.519863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2138 07:59:54.616451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2139 07:59:54.617020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2141 07:59:54.715973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2142 07:59:54.716484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2144 07:59:54.815553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2145 07:59:54.816054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2147 07:59:54.912963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2148 07:59:54.913470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2150 07:59:55.012572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2151 07:59:55.013053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2153 07:59:55.110558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2154 07:59:55.111048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2156 07:59:55.212148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2157 07:59:55.212647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2159 07:59:55.306772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2160 07:59:55.307240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2162 07:59:55.403914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2163 07:59:55.404429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2165 07:59:55.499603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2166 07:59:55.500090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2168 07:59:55.599796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2169 07:59:55.600363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2171 07:59:55.698128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2172 07:59:55.698608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2174 07:59:55.796494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2175 07:59:55.796965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2177 07:59:55.895879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2178 07:59:55.896356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2180 07:59:55.994642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2181 07:59:55.995121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2183 07:59:56.091954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2184 07:59:56.092423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2186 07:59:56.190115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2187 07:59:56.190590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2189 07:59:56.289236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2190 07:59:56.289710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2192 07:59:56.384248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2193 07:59:56.384694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2195 07:59:56.482373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2196 07:59:56.482816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2198 07:59:56.582423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2199 07:59:56.582998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2201 07:59:56.678513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2202 07:59:56.679044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2204 07:59:56.772653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2205 07:59:56.773146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2207 07:59:56.869826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2208 07:59:56.870337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2210 07:59:56.962564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2211 07:59:56.963021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2213 07:59:57.056924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2214 07:59:57.057403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2216 07:59:57.148850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2217 07:59:57.149291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2219 07:59:57.247689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2220 07:59:57.248143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2222 07:59:57.349933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2223 07:59:57.350374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2225 07:59:57.449552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2226 07:59:57.450043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2228 07:59:57.551160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2229 07:59:57.551652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2231 07:59:57.647420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2232 07:59:57.647973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2234 07:59:57.748775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2235 07:59:57.749246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2237 07:59:57.849648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2238 07:59:57.850138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2240 07:59:57.951143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2241 07:59:57.951639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2243 07:59:58.049604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2244 07:59:58.050104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2246 07:59:58.144429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2247 07:59:58.144948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2249 07:59:58.243729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2250 07:59:58.244249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2252 07:59:58.336438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2253 07:59:58.336930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2255 07:59:58.436386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2256 07:59:58.436876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2258 07:59:58.532828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2259 07:59:58.533314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2261 07:59:58.631601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2262 07:59:58.632156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2264 07:59:58.731197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2265 07:59:58.731684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2267 07:59:58.828571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2268 07:59:58.829058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2270 07:59:58.928972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2272 07:59:58.931983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2273 07:59:59.029187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2274 07:59:59.029673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2276 07:59:59.130223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2277 07:59:59.130717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2279 07:59:59.229217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2280 07:59:59.229705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2282 07:59:59.327030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2283 07:59:59.327516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2285 07:59:59.426422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2286 07:59:59.426912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2288 07:59:59.527169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2289 07:59:59.527679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2291 07:59:59.628544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2292 07:59:59.629088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2294 07:59:59.725800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2295 07:59:59.726279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2297 07:59:59.823563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2298 07:59:59.824049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2300 07:59:59.917775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2301 07:59:59.918263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2303 08:00:00.016121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2304 08:00:00.016684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2306 08:00:00.112429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2307 08:00:00.112900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2309 08:00:00.211511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2310 08:00:00.211966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2312 08:00:00.309680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2313 08:00:00.310160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2315 08:00:00.411310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2316 08:00:00.411791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2318 08:00:00.510616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2319 08:00:00.511087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2321 08:00:00.608449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2322 08:00:00.609007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2324 08:00:00.705211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2325 08:00:00.705692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2327 08:00:00.801101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2328 08:00:00.801581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2330 08:00:00.898064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2331 08:00:00.898562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2333 08:00:00.996437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2334 08:00:00.996919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2336 08:00:01.099677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2337 08:00:01.100158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2339 08:00:01.197052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2340 08:00:01.197540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2342 08:00:01.294180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2343 08:00:01.294661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2345 08:00:01.389208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2346 08:00:01.389695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2348 08:00:01.486807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2349 08:00:01.487290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2351 08:00:01.579437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2352 08:00:01.580024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2354 08:00:01.674679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2355 08:00:01.675202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2357 08:00:01.771600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2358 08:00:01.772080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2360 08:00:01.867207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2361 08:00:01.867688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2363 08:00:01.955522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2364 08:00:01.955809 + set +x
2365 08:00:01.956267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2367 08:00:01.959845 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1201675_1.6.2.4.5>
2368 08:00:01.960318 Received signal: <ENDRUN> 1_kselftest-dt 1201675_1.6.2.4.5
2369 08:00:01.960616 Ending use of test pattern.
2370 08:00:01.960839 Ending test lava.1_kselftest-dt (1201675_1.6.2.4.5), duration 95.33
2372 08:00:01.967211 <LAVA_TEST_RUNNER EXIT>
2373 08:00:01.967688 ok: lava_test_shell seems to have completed
2374 08:00:01.973333 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2375 08:00:01.974387 end: 3.1 lava-test-shell (duration 00:01:37) [common]
2376 08:00:01.974679 end: 3 lava-test-retry (duration 00:01:37) [common]
2377 08:00:01.974969 start: 4 finalize (timeout 00:05:17) [common]
2378 08:00:01.975260 start: 4.1 power-off (timeout 00:00:30) [common]
2379 08:00:01.975632 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2380 08:00:02.341084 Returned 0 in 0 seconds
2381 08:00:02.441984 end: 4.1 power-off (duration 00:00:00) [common]
2383 08:00:02.442995 start: 4.2 read-feedback (timeout 00:05:16) [common]
2384 08:00:02.443665 Listened to connection for namespace 'common' for up to 1s
2385 08:00:02.444254 Listened to connection for namespace 'common' for up to 1s
2386 08:00:03.444402 Finalising connection for namespace 'common'
2387 08:00:03.444845 Disconnecting from shell: Finalise
2388 08:00:03.445159 / #
2389 08:00:03.545748 end: 4.2 read-feedback (duration 00:00:01) [common]
2390 08:00:03.546164 end: 4 finalize (duration 00:00:02) [common]
2391 08:00:03.546561 Cleaning after the job
2392 08:00:03.546911 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/ramdisk
2393 08:00:03.550565 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/kernel
2394 08:00:03.553533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/dtb
2395 08:00:03.554044 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/nfsrootfs
2396 08:00:03.608039 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1201675/tftp-deploy-7td0yafb/modules
2397 08:00:03.611566 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1201675
2398 08:00:04.257748 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1201675
2399 08:00:04.258033 Job finished correctly