Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:22:51.914209 lava-dispatcher, installed at version: 2024.01
2 09:22:51.915009 start: 0 validate
3 09:22:51.915496 Start time: 2024-10-08 09:22:51.915466+00:00 (UTC)
4 09:22:51.916081 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:22:51.916693 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 09:22:51.952237 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:22:51.952808 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241008%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:22:51.980727 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:22:51.981353 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241008%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:22:52.009972 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:22:52.010817 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241008%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 09:22:52.046275 validate duration: 0.13
14 09:22:52.047185 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:22:52.047532 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:22:52.047876 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:22:52.048540 Not decompressing ramdisk as can be used compressed.
18 09:22:52.049029 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 09:22:52.049289 saving as /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/ramdisk/rootfs.cpio.gz
20 09:22:52.049547 total size: 47897469 (45 MB)
21 09:22:52.084758 progress 0 % (0 MB)
22 09:22:52.117851 progress 5 % (2 MB)
23 09:22:52.149269 progress 10 % (4 MB)
24 09:22:52.180066 progress 15 % (6 MB)
25 09:22:52.211434 progress 20 % (9 MB)
26 09:22:52.243160 progress 25 % (11 MB)
27 09:22:52.274831 progress 30 % (13 MB)
28 09:22:52.308371 progress 35 % (16 MB)
29 09:22:52.344917 progress 40 % (18 MB)
30 09:22:52.375823 progress 45 % (20 MB)
31 09:22:52.407044 progress 50 % (22 MB)
32 09:22:52.438428 progress 55 % (25 MB)
33 09:22:52.470635 progress 60 % (27 MB)
34 09:22:52.502083 progress 65 % (29 MB)
35 09:22:52.533855 progress 70 % (32 MB)
36 09:22:52.565024 progress 75 % (34 MB)
37 09:22:52.595913 progress 80 % (36 MB)
38 09:22:52.627134 progress 85 % (38 MB)
39 09:22:52.658025 progress 90 % (41 MB)
40 09:22:52.688930 progress 95 % (43 MB)
41 09:22:52.719683 progress 100 % (45 MB)
42 09:22:52.720464 45 MB downloaded in 0.67 s (68.09 MB/s)
43 09:22:52.721027 end: 1.1.1 http-download (duration 00:00:01) [common]
45 09:22:52.721926 end: 1.1 download-retry (duration 00:00:01) [common]
46 09:22:52.722233 start: 1.2 download-retry (timeout 00:09:59) [common]
47 09:22:52.722518 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 09:22:52.723009 downloading http://storage.kernelci.org/next/master/next-20241008/arm64/defconfig/gcc-12/kernel/Image
49 09:22:52.723261 saving as /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/kernel/Image
50 09:22:52.723475 total size: 45713920 (43 MB)
51 09:22:52.723691 No compression specified
52 09:22:52.763218 progress 0 % (0 MB)
53 09:22:52.792857 progress 5 % (2 MB)
54 09:22:52.822297 progress 10 % (4 MB)
55 09:22:52.851816 progress 15 % (6 MB)
56 09:22:52.881229 progress 20 % (8 MB)
57 09:22:52.910259 progress 25 % (10 MB)
58 09:22:52.939574 progress 30 % (13 MB)
59 09:22:52.968749 progress 35 % (15 MB)
60 09:22:52.998377 progress 40 % (17 MB)
61 09:22:53.027531 progress 45 % (19 MB)
62 09:22:53.056827 progress 50 % (21 MB)
63 09:22:53.086237 progress 55 % (24 MB)
64 09:22:53.116026 progress 60 % (26 MB)
65 09:22:53.144964 progress 65 % (28 MB)
66 09:22:53.174544 progress 70 % (30 MB)
67 09:22:53.204366 progress 75 % (32 MB)
68 09:22:53.233975 progress 80 % (34 MB)
69 09:22:53.262922 progress 85 % (37 MB)
70 09:22:53.292450 progress 90 % (39 MB)
71 09:22:53.322065 progress 95 % (41 MB)
72 09:22:53.350936 progress 100 % (43 MB)
73 09:22:53.351454 43 MB downloaded in 0.63 s (69.42 MB/s)
74 09:22:53.351923 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:22:53.352821 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:22:53.353105 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:22:53.353371 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:22:53.353803 downloading http://storage.kernelci.org/next/master/next-20241008/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 09:22:53.354046 saving as /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/dtb/meson-g12b-a311d-libretech-cc.dtb
81 09:22:53.354252 total size: 54703 (0 MB)
82 09:22:53.354460 No compression specified
83 09:22:53.389082 progress 59 % (0 MB)
84 09:22:53.390177 progress 100 % (0 MB)
85 09:22:53.390746 0 MB downloaded in 0.04 s (1.43 MB/s)
86 09:22:53.391232 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:22:53.392193 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:22:53.392498 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:22:53.392784 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:22:53.393271 downloading http://storage.kernelci.org/next/master/next-20241008/arm64/defconfig/gcc-12/modules.tar.xz
92 09:22:53.393525 saving as /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/modules/modules.tar
93 09:22:53.393742 total size: 11607224 (11 MB)
94 09:22:53.393960 Using unxz to decompress xz
95 09:22:53.428228 progress 0 % (0 MB)
96 09:22:53.497824 progress 5 % (0 MB)
97 09:22:53.572337 progress 10 % (1 MB)
98 09:22:53.653032 progress 15 % (1 MB)
99 09:22:53.729650 progress 20 % (2 MB)
100 09:22:53.808275 progress 25 % (2 MB)
101 09:22:53.890842 progress 30 % (3 MB)
102 09:22:53.973770 progress 35 % (3 MB)
103 09:22:54.076511 progress 40 % (4 MB)
104 09:22:54.165935 progress 45 % (5 MB)
105 09:22:54.248792 progress 50 % (5 MB)
106 09:22:54.328972 progress 55 % (6 MB)
107 09:22:54.410694 progress 60 % (6 MB)
108 09:22:54.495440 progress 65 % (7 MB)
109 09:22:54.572393 progress 70 % (7 MB)
110 09:22:54.654391 progress 75 % (8 MB)
111 09:22:54.736684 progress 80 % (8 MB)
112 09:22:54.816383 progress 85 % (9 MB)
113 09:22:54.884510 progress 90 % (9 MB)
114 09:22:54.982798 progress 95 % (10 MB)
115 09:22:55.080145 progress 100 % (11 MB)
116 09:22:55.091431 11 MB downloaded in 1.70 s (6.52 MB/s)
117 09:22:55.092061 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:22:55.093816 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:22:55.094387 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 09:22:55.094955 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 09:22:55.095489 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:22:55.096061 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 09:22:55.097398 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi
125 09:22:55.098341 makedir: /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin
126 09:22:55.099035 makedir: /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/tests
127 09:22:55.099702 makedir: /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/results
128 09:22:55.100585 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-add-keys
129 09:22:55.101672 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-add-sources
130 09:22:55.102678 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-background-process-start
131 09:22:55.103696 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-background-process-stop
132 09:22:55.104802 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-common-functions
133 09:22:55.105802 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-echo-ipv4
134 09:22:55.106779 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-install-packages
135 09:22:55.107748 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-installed-packages
136 09:22:55.108752 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-os-build
137 09:22:55.109720 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-probe-channel
138 09:22:55.110688 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-probe-ip
139 09:22:55.111654 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-target-ip
140 09:22:55.112669 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-target-mac
141 09:22:55.113634 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-target-storage
142 09:22:55.114617 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-test-case
143 09:22:55.115586 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-test-event
144 09:22:55.116598 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-test-feedback
145 09:22:55.117566 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-test-raise
146 09:22:55.118546 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-test-reference
147 09:22:55.119557 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-test-runner
148 09:22:55.120577 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-test-set
149 09:22:55.121566 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-test-shell
150 09:22:55.122549 Updating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-install-packages (oe)
151 09:22:55.123599 Updating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/bin/lava-installed-packages (oe)
152 09:22:55.124548 Creating /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/environment
153 09:22:55.125332 LAVA metadata
154 09:22:55.125859 - LAVA_JOB_ID=819488
155 09:22:55.126329 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:22:55.127077 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 09:22:55.128995 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:22:55.129588 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 09:22:55.129998 skipped lava-vland-overlay
160 09:22:55.130482 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:22:55.130982 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 09:22:55.131405 skipped lava-multinode-overlay
163 09:22:55.131883 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:22:55.132420 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 09:22:55.132895 Loading test definitions
166 09:22:55.133433 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 09:22:55.133867 Using /lava-819488 at stage 0
168 09:22:55.136027 uuid=819488_1.5.2.4.1 testdef=None
169 09:22:55.136356 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:22:55.136627 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 09:22:55.138380 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:22:55.139188 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 09:22:55.141386 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:22:55.142251 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 09:22:55.144444 runner path: /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/0/tests/0_igt-gpu-panfrost test_uuid 819488_1.5.2.4.1
178 09:22:55.145055 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:22:55.145867 Creating lava-test-runner.conf files
181 09:22:55.146078 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/819488/lava-overlay-k14h8yhi/lava-819488/0 for stage 0
182 09:22:55.146422 - 0_igt-gpu-panfrost
183 09:22:55.146777 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:22:55.147060 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 09:22:55.170862 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:22:55.171297 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 09:22:55.171563 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:22:55.171831 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:22:55.172121 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 09:23:02.771333 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:08) [common]
191 09:23:02.771791 start: 1.5.4 extract-modules (timeout 00:09:49) [common]
192 09:23:02.772100 extracting modules file /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/819488/extract-overlay-ramdisk-ejaa_jc8/ramdisk
193 09:23:04.217372 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 09:23:04.217832 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 09:23:04.218110 [common] Applying overlay /var/lib/lava/dispatcher/tmp/819488/compress-overlay-v66ofluj/overlay-1.5.2.5.tar.gz to ramdisk
196 09:23:04.218322 [common] Applying overlay /var/lib/lava/dispatcher/tmp/819488/compress-overlay-v66ofluj/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/819488/extract-overlay-ramdisk-ejaa_jc8/ramdisk
197 09:23:04.248623 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:23:04.249055 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 09:23:04.249324 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 09:23:04.249552 Converting downloaded kernel to a uImage
201 09:23:04.249854 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/kernel/Image /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/kernel/uImage
202 09:23:04.729454 output: Image Name:
203 09:23:04.729867 output: Created: Tue Oct 8 09:23:04 2024
204 09:23:04.730075 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:23:04.730277 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 09:23:04.730477 output: Load Address: 01080000
207 09:23:04.730675 output: Entry Point: 01080000
208 09:23:04.730873 output:
209 09:23:04.731201 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 09:23:04.731466 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 09:23:04.731732 start: 1.5.7 configure-preseed-file (timeout 00:09:47) [common]
212 09:23:04.732013 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:23:04.732285 start: 1.5.8 compress-ramdisk (timeout 00:09:47) [common]
214 09:23:04.732540 Building ramdisk /var/lib/lava/dispatcher/tmp/819488/extract-overlay-ramdisk-ejaa_jc8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/819488/extract-overlay-ramdisk-ejaa_jc8/ramdisk
215 09:23:11.253539 >> 502549 blocks
216 09:23:32.109646 Adding RAMdisk u-boot header.
217 09:23:32.110061 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/819488/extract-overlay-ramdisk-ejaa_jc8/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/819488/extract-overlay-ramdisk-ejaa_jc8/ramdisk.cpio.gz.uboot
218 09:23:32.776742 output: Image Name:
219 09:23:32.777158 output: Created: Tue Oct 8 09:23:32 2024
220 09:23:32.777369 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:23:32.777572 output: Data Size: 65735623 Bytes = 64194.94 KiB = 62.69 MiB
222 09:23:32.777770 output: Load Address: 00000000
223 09:23:32.777967 output: Entry Point: 00000000
224 09:23:32.778162 output:
225 09:23:32.778744 rename /var/lib/lava/dispatcher/tmp/819488/extract-overlay-ramdisk-ejaa_jc8/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/ramdisk/ramdisk.cpio.gz.uboot
226 09:23:32.779154 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 09:23:32.779435 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 09:23:32.779703 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 09:23:32.779944 No LXC device requested
230 09:23:32.780498 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:23:32.781054 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 09:23:32.781591 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:23:32.782032 Checking files for TFTP limit of 4294967296 bytes.
234 09:23:32.784971 end: 1 tftp-deploy (duration 00:00:41) [common]
235 09:23:32.785601 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:23:32.786171 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:23:32.786717 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:23:32.787266 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:23:32.787843 Using kernel file from prepare-kernel: 819488/tftp-deploy-7rs145vw/kernel/uImage
240 09:23:32.788574 substitutions:
241 09:23:32.789030 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:23:32.789475 - {DTB_ADDR}: 0x01070000
243 09:23:32.789937 - {DTB}: 819488/tftp-deploy-7rs145vw/dtb/meson-g12b-a311d-libretech-cc.dtb
244 09:23:32.790396 - {INITRD}: 819488/tftp-deploy-7rs145vw/ramdisk/ramdisk.cpio.gz.uboot
245 09:23:32.790840 - {KERNEL_ADDR}: 0x01080000
246 09:23:32.791075 - {KERNEL}: 819488/tftp-deploy-7rs145vw/kernel/uImage
247 09:23:32.791299 - {LAVA_MAC}: None
248 09:23:32.791536 - {PRESEED_CONFIG}: None
249 09:23:32.791770 - {PRESEED_LOCAL}: None
250 09:23:32.792023 - {RAMDISK_ADDR}: 0x08000000
251 09:23:32.792494 - {RAMDISK}: 819488/tftp-deploy-7rs145vw/ramdisk/ramdisk.cpio.gz.uboot
252 09:23:32.792941 - {ROOT_PART}: None
253 09:23:32.793371 - {ROOT}: None
254 09:23:32.793804 - {SERVER_IP}: 192.168.6.2
255 09:23:32.794241 - {TEE_ADDR}: 0x83000000
256 09:23:32.794671 - {TEE}: None
257 09:23:32.795100 Parsed boot commands:
258 09:23:32.795517 - setenv autoload no
259 09:23:32.795944 - setenv initrd_high 0xffffffff
260 09:23:32.796402 - setenv fdt_high 0xffffffff
261 09:23:32.796831 - dhcp
262 09:23:32.797260 - setenv serverip 192.168.6.2
263 09:23:32.797756 - tftpboot 0x01080000 819488/tftp-deploy-7rs145vw/kernel/uImage
264 09:23:32.798210 - tftpboot 0x08000000 819488/tftp-deploy-7rs145vw/ramdisk/ramdisk.cpio.gz.uboot
265 09:23:32.798640 - tftpboot 0x01070000 819488/tftp-deploy-7rs145vw/dtb/meson-g12b-a311d-libretech-cc.dtb
266 09:23:32.799073 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:23:32.799505 - bootm 0x01080000 0x08000000 0x01070000
268 09:23:32.800095 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:23:32.801755 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:23:32.802248 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 09:23:32.818595 Setting prompt string to ['lava-test: # ']
273 09:23:32.820255 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:23:32.820916 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:23:32.821500 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:23:32.822282 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:23:32.823590 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 09:23:32.860856 >> OK - accepted request
279 09:23:32.862890 Returned 0 in 0 seconds
280 09:23:32.963680 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:23:32.964712 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:23:32.965053 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:23:32.965329 Setting prompt string to ['Hit any key to stop autoboot']
285 09:23:32.965560 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:23:32.966494 Trying 192.168.56.21...
287 09:23:32.966746 Connected to conserv1.
288 09:23:32.966959 Escape character is '^]'.
289 09:23:32.967166
290 09:23:32.967386 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 09:23:32.967600
292 09:23:44.483696 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 09:23:44.484164 bl2_stage_init 0x01
294 09:23:44.484398 bl2_stage_init 0x81
295 09:23:44.489135 hw id: 0x0000 - pwm id 0x01
296 09:23:44.489483 bl2_stage_init 0xc1
297 09:23:44.489702 bl2_stage_init 0x02
298 09:23:44.489912
299 09:23:44.494765 L0:00000000
300 09:23:44.495085 L1:20000703
301 09:23:44.495295 L2:00008067
302 09:23:44.495497 L3:14000000
303 09:23:44.500363 B2:00402000
304 09:23:44.500656 B1:e0f83180
305 09:23:44.500864
306 09:23:44.501066 TE: 58167
307 09:23:44.501267
308 09:23:44.506214 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 09:23:44.506578
310 09:23:44.506798 Board ID = 1
311 09:23:44.511485 Set A53 clk to 24M
312 09:23:44.511805 Set A73 clk to 24M
313 09:23:44.512036 Set clk81 to 24M
314 09:23:44.517070 A53 clk: 1200 MHz
315 09:23:44.517395 A73 clk: 1200 MHz
316 09:23:44.517601 CLK81: 166.6M
317 09:23:44.517802 smccc: 00012abe
318 09:23:44.522630 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 09:23:44.528281 board id: 1
320 09:23:44.534115 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:23:44.544800 fw parse done
322 09:23:44.549891 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:23:44.592679 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:23:44.604318 PIEI prepare done
325 09:23:44.604656 fastboot data load
326 09:23:44.604863 fastboot data verify
327 09:23:44.609944 verify result: 266
328 09:23:44.615523 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 09:23:44.615840 LPDDR4 probe
330 09:23:44.616114 ddr clk to 1584MHz
331 09:23:44.622461 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:23:44.660092
333 09:23:44.660500 dmc_version 0001
334 09:23:44.666608 Check phy result
335 09:23:44.673265 INFO : End of CA training
336 09:23:44.673607 INFO : End of initialization
337 09:23:44.678857 INFO : Training has run successfully!
338 09:23:44.679213 Check phy result
339 09:23:44.684497 INFO : End of initialization
340 09:23:44.684841 INFO : End of read enable training
341 09:23:44.690087 INFO : End of fine write leveling
342 09:23:44.695648 INFO : End of Write leveling coarse delay
343 09:23:44.696032 INFO : Training has run successfully!
344 09:23:44.696251 Check phy result
345 09:23:44.701269 INFO : End of initialization
346 09:23:44.701609 INFO : End of read dq deskew training
347 09:23:44.706931 INFO : End of MPR read delay center optimization
348 09:23:44.712488 INFO : End of write delay center optimization
349 09:23:44.718089 INFO : End of read delay center optimization
350 09:23:44.718435 INFO : End of max read latency training
351 09:23:44.723654 INFO : Training has run successfully!
352 09:23:44.724037 1D training succeed
353 09:23:44.732505 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:23:45.023072 Check phy result
355 09:23:45.024104 INFO : End of initialization
356 09:23:45.024365 INFO : End of 2D read delay Voltage center optimization
357 09:23:45.024877 INFO : End of 2D read delay Voltage center optimization
358 09:23:45.025116 INFO : End of 2D write delay Voltage center optimization
359 09:23:45.025326 INFO : End of 2D write delay Voltage center optimization
360 09:23:45.025535 INFO : Training has run successfully!
361 09:23:45.025735
362 09:23:45.025938 channel==0
363 09:23:45.026137 RxClkDly_Margin_A0==88 ps 9
364 09:23:45.026337 TxDqDly_Margin_A0==98 ps 10
365 09:23:45.026538 RxClkDly_Margin_A1==88 ps 9
366 09:23:45.026736 TxDqDly_Margin_A1==88 ps 9
367 09:23:45.026936 TrainedVREFDQ_A0==74
368 09:23:45.027137 TrainedVREFDQ_A1==74
369 09:23:45.027339 VrefDac_Margin_A0==25
370 09:23:45.027672 DeviceVref_Margin_A0==40
371 09:23:45.027875 VrefDac_Margin_A1==25
372 09:23:45.028110 DeviceVref_Margin_A1==40
373 09:23:45.028313
374 09:23:45.028516
375 09:23:45.028719 channel==1
376 09:23:45.028920 RxClkDly_Margin_A0==98 ps 10
377 09:23:45.029119 TxDqDly_Margin_A0==98 ps 10
378 09:23:45.029321 RxClkDly_Margin_A1==98 ps 10
379 09:23:45.029521 TxDqDly_Margin_A1==88 ps 9
380 09:23:45.029721 TrainedVREFDQ_A0==77
381 09:23:45.029924 TrainedVREFDQ_A1==77
382 09:23:45.030126 VrefDac_Margin_A0==22
383 09:23:45.030324 DeviceVref_Margin_A0==37
384 09:23:45.030523 VrefDac_Margin_A1==22
385 09:23:45.030719 DeviceVref_Margin_A1==37
386 09:23:45.030915
387 09:23:45.031113 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:23:45.031310
389 09:23:45.031507 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 09:23:45.031753 2D training succeed
391 09:23:45.031956 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:23:45.032182 auto size-- 65535DDR cs0 size: 2048MB
393 09:23:45.032443 DDR cs1 size: 2048MB
394 09:23:45.032651 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:23:45.033303 cs0 DataBus test pass
396 09:23:45.033570 cs1 DataBus test pass
397 09:23:45.033773 cs0 AddrBus test pass
398 09:23:45.038881 cs1 AddrBus test pass
399 09:23:45.039179
400 09:23:45.039386 100bdlr_step_size ps== 420
401 09:23:45.039592 result report
402 09:23:45.044471 boot times 0Enable ddr reg access
403 09:23:45.051648 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:23:45.065503 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 09:23:45.639433 0.0;M3 CHK:0;cm4_sp_mode 0
406 09:23:45.639868 MVN_1=0x00000000
407 09:23:45.645068 MVN_2=0x00000000
408 09:23:45.650759 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 09:23:45.651120 OPS=0x10
410 09:23:45.651346 ring efuse init
411 09:23:45.651565 chipver efuse init
412 09:23:45.659009 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 09:23:45.659568 [0.018961 Inits done]
414 09:23:45.665996 secure task start!
415 09:23:45.666529 high task start!
416 09:23:45.666975 low task start!
417 09:23:45.667413 run into bl31
418 09:23:45.673798 NOTICE: BL31: v1.3(release):4fc40b1
419 09:23:45.680370 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 09:23:45.680909 NOTICE: BL31: G12A normal boot!
421 09:23:45.706489 NOTICE: BL31: BL33 decompress pass
422 09:23:45.712125 ERROR: Error initializing runtime service opteed_fast
423 09:23:46.944978
424 09:23:46.945425
425 09:23:46.953487 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 09:23:46.953880
427 09:23:46.954097 Model: Libre Computer AML-A311D-CC Alta
428 09:23:47.161920 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 09:23:47.185319 DRAM: 2 GiB (effective 3.8 GiB)
430 09:23:47.328289 Core: 408 devices, 31 uclasses, devicetree: separate
431 09:23:47.333533 WDT: Not starting watchdog@f0d0
432 09:23:47.366462 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 09:23:47.378804 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 09:23:47.383837 ** Bad device specification mmc 0 **
435 09:23:47.394151 Card did not respond to voltage select! : -110
436 09:23:47.401767 ** Bad device specification mmc 0 **
437 09:23:47.402140 Couldn't find partition mmc 0
438 09:23:47.410023 Card did not respond to voltage select! : -110
439 09:23:47.415600 ** Bad device specification mmc 0 **
440 09:23:47.415941 Couldn't find partition mmc 0
441 09:23:47.420618 Error: could not access storage.
442 09:23:48.684111 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 09:23:48.684529 bl2_stage_init 0x01
444 09:23:48.684779 bl2_stage_init 0x81
445 09:23:48.689623 hw id: 0x0000 - pwm id 0x01
446 09:23:48.689958 bl2_stage_init 0xc1
447 09:23:48.690261 bl2_stage_init 0x02
448 09:23:48.690507
449 09:23:48.695266 L0:00000000
450 09:23:48.695646 L1:20000703
451 09:23:48.695892 L2:00008067
452 09:23:48.696153 L3:14000000
453 09:23:48.700838 B2:00402000
454 09:23:48.701151 B1:e0f83180
455 09:23:48.701451
456 09:23:48.701705 TE: 58124
457 09:23:48.701933
458 09:23:48.706548 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 09:23:48.706856
460 09:23:48.707091 Board ID = 1
461 09:23:48.712057 Set A53 clk to 24M
462 09:23:48.712381 Set A73 clk to 24M
463 09:23:48.712617 Set clk81 to 24M
464 09:23:48.717562 A53 clk: 1200 MHz
465 09:23:48.717855 A73 clk: 1200 MHz
466 09:23:48.718091 CLK81: 166.6M
467 09:23:48.718323 smccc: 00012a92
468 09:23:48.723164 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 09:23:48.728742 board id: 1
470 09:23:48.734674 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 09:23:48.745344 fw parse done
472 09:23:48.750579 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 09:23:48.793945 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 09:23:48.804836 PIEI prepare done
475 09:23:48.805191 fastboot data load
476 09:23:48.805428 fastboot data verify
477 09:23:48.810457 verify result: 266
478 09:23:48.816008 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 09:23:48.816320 LPDDR4 probe
480 09:23:48.816557 ddr clk to 1584MHz
481 09:23:48.824296 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 09:23:48.861261
483 09:23:48.861679 dmc_version 0001
484 09:23:48.867041 Check phy result
485 09:23:48.873848 INFO : End of CA training
486 09:23:48.874402 INFO : End of initialization
487 09:23:48.879437 INFO : Training has run successfully!
488 09:23:48.880013 Check phy result
489 09:23:48.885019 INFO : End of initialization
490 09:23:48.885597 INFO : End of read enable training
491 09:23:48.890579 INFO : End of fine write leveling
492 09:23:48.896165 INFO : End of Write leveling coarse delay
493 09:23:48.896620 INFO : Training has run successfully!
494 09:23:48.897021 Check phy result
495 09:23:48.901784 INFO : End of initialization
496 09:23:48.902216 INFO : End of read dq deskew training
497 09:23:48.907427 INFO : End of MPR read delay center optimization
498 09:23:48.912947 INFO : End of write delay center optimization
499 09:23:48.918573 INFO : End of read delay center optimization
500 09:23:48.919016 INFO : End of max read latency training
501 09:23:48.924181 INFO : Training has run successfully!
502 09:23:48.924622 1D training succeed
503 09:23:48.933411 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 09:23:48.981004 Check phy result
505 09:23:48.981540 INFO : End of initialization
506 09:23:49.002606 INFO : End of 2D read delay Voltage center optimization
507 09:23:49.021979 INFO : End of 2D read delay Voltage center optimization
508 09:23:49.074717 INFO : End of 2D write delay Voltage center optimization
509 09:23:49.123915 INFO : End of 2D write delay Voltage center optimization
510 09:23:49.129641 INFO : Training has run successfully!
511 09:23:49.130125
512 09:23:49.130533 channel==0
513 09:23:49.135189 RxClkDly_Margin_A0==88 ps 9
514 09:23:49.135642 TxDqDly_Margin_A0==98 ps 10
515 09:23:49.140732 RxClkDly_Margin_A1==88 ps 9
516 09:23:49.141226 TxDqDly_Margin_A1==88 ps 9
517 09:23:49.141827 TrainedVREFDQ_A0==74
518 09:23:49.146248 TrainedVREFDQ_A1==74
519 09:23:49.146704 VrefDac_Margin_A0==25
520 09:23:49.147100 DeviceVref_Margin_A0==40
521 09:23:49.151904 VrefDac_Margin_A1==25
522 09:23:49.152372 DeviceVref_Margin_A1==40
523 09:23:49.152768
524 09:23:49.153160
525 09:23:49.153551 channel==1
526 09:23:49.157536 RxClkDly_Margin_A0==98 ps 10
527 09:23:49.157978 TxDqDly_Margin_A0==98 ps 10
528 09:23:49.163185 RxClkDly_Margin_A1==98 ps 10
529 09:23:49.163692 TxDqDly_Margin_A1==88 ps 9
530 09:23:49.168808 TrainedVREFDQ_A0==77
531 09:23:49.169374 TrainedVREFDQ_A1==77
532 09:23:49.169783 VrefDac_Margin_A0==22
533 09:23:49.174243 DeviceVref_Margin_A0==37
534 09:23:49.174685 VrefDac_Margin_A1==22
535 09:23:49.179822 DeviceVref_Margin_A1==37
536 09:23:49.180289
537 09:23:49.180690 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 09:23:49.181079
539 09:23:49.213522 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 09:23:49.214127 2D training succeed
541 09:23:49.219186 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 09:23:49.224617 auto size-- 65535DDR cs0 size: 2048MB
543 09:23:49.225063 DDR cs1 size: 2048MB
544 09:23:49.230222 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 09:23:49.230664 cs0 DataBus test pass
546 09:23:49.235818 cs1 DataBus test pass
547 09:23:49.236307 cs0 AddrBus test pass
548 09:23:49.236702 cs1 AddrBus test pass
549 09:23:49.237090
550 09:23:49.241391 100bdlr_step_size ps== 420
551 09:23:49.241844 result report
552 09:23:49.247008 boot times 0Enable ddr reg access
553 09:23:49.251841 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 09:23:49.265827 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 09:23:49.837927 0.0;M3 CHK:0;cm4_sp_mode 0
556 09:23:49.838362 MVN_1=0x00000000
557 09:23:49.843292 MVN_2=0x00000000
558 09:23:49.849017 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 09:23:49.849335 OPS=0x10
560 09:23:49.849547 ring efuse init
561 09:23:49.849753 chipver efuse init
562 09:23:49.854641 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 09:23:49.860213 [0.018961 Inits done]
564 09:23:49.860547 secure task start!
565 09:23:49.860763 high task start!
566 09:23:49.864784 low task start!
567 09:23:49.865092 run into bl31
568 09:23:49.871487 NOTICE: BL31: v1.3(release):4fc40b1
569 09:23:49.879340 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 09:23:49.879732 NOTICE: BL31: G12A normal boot!
571 09:23:49.904660 NOTICE: BL31: BL33 decompress pass
572 09:23:49.909343 ERROR: Error initializing runtime service opteed_fast
573 09:23:51.143214
574 09:23:51.143630
575 09:23:51.151402 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 09:23:51.151702
577 09:23:51.151911 Model: Libre Computer AML-A311D-CC Alta
578 09:23:51.360041 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 09:23:51.383373 DRAM: 2 GiB (effective 3.8 GiB)
580 09:23:51.526372 Core: 408 devices, 31 uclasses, devicetree: separate
581 09:23:51.532248 WDT: Not starting watchdog@f0d0
582 09:23:51.564508 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 09:23:51.576995 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 09:23:51.581926 ** Bad device specification mmc 0 **
585 09:23:51.592282 Card did not respond to voltage select! : -110
586 09:23:51.599940 ** Bad device specification mmc 0 **
587 09:23:51.600227 Couldn't find partition mmc 0
588 09:23:51.608283 Card did not respond to voltage select! : -110
589 09:23:51.613770 ** Bad device specification mmc 0 **
590 09:23:51.614037 Couldn't find partition mmc 0
591 09:23:51.618854 Error: could not access storage.
592 09:23:51.961366 Net: eth0: ethernet@ff3f0000
593 09:23:51.961912 starting USB...
594 09:23:52.213146 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 09:23:52.213532 Starting the controller
596 09:23:52.220162 USB XHCI 1.10
597 09:23:53.935540 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 09:23:53.936201 bl2_stage_init 0x01
599 09:23:53.936628 bl2_stage_init 0x81
600 09:23:53.941126 hw id: 0x0000 - pwm id 0x01
601 09:23:53.941574 bl2_stage_init 0xc1
602 09:23:53.941986 bl2_stage_init 0x02
603 09:23:53.942388
604 09:23:53.946784 L0:00000000
605 09:23:53.947223 L1:20000703
606 09:23:53.947632 L2:00008067
607 09:23:53.948062 L3:14000000
608 09:23:53.952329 B2:00402000
609 09:23:53.952762 B1:e0f83180
610 09:23:53.953163
611 09:23:53.953562 TE: 58124
612 09:23:53.953959
613 09:23:53.957945 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 09:23:53.958396
615 09:23:53.958801 Board ID = 1
616 09:23:53.963538 Set A53 clk to 24M
617 09:23:53.963999 Set A73 clk to 24M
618 09:23:53.964409 Set clk81 to 24M
619 09:23:53.969139 A53 clk: 1200 MHz
620 09:23:53.969577 A73 clk: 1200 MHz
621 09:23:53.969979 CLK81: 166.6M
622 09:23:53.970371 smccc: 00012a92
623 09:23:53.974768 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 09:23:53.980425 board id: 1
625 09:23:53.986184 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 09:23:53.996844 fw parse done
627 09:23:54.002806 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 09:23:54.046421 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 09:23:54.056372 PIEI prepare done
630 09:23:54.056818 fastboot data load
631 09:23:54.057231 fastboot data verify
632 09:23:54.062056 verify result: 266
633 09:23:54.067602 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 09:23:54.068267 LPDDR4 probe
635 09:23:54.068745 ddr clk to 1584MHz
636 09:23:54.076383 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 09:23:54.112924
638 09:23:54.113436 dmc_version 0001
639 09:23:54.119576 Check phy result
640 09:23:54.125451 INFO : End of CA training
641 09:23:54.125901 INFO : End of initialization
642 09:23:54.131036 INFO : Training has run successfully!
643 09:23:54.131486 Check phy result
644 09:23:54.136641 INFO : End of initialization
645 09:23:54.137092 INFO : End of read enable training
646 09:23:54.142266 INFO : End of fine write leveling
647 09:23:54.147824 INFO : End of Write leveling coarse delay
648 09:23:54.148301 INFO : Training has run successfully!
649 09:23:54.148698 Check phy result
650 09:23:54.153471 INFO : End of initialization
651 09:23:54.153926 INFO : End of read dq deskew training
652 09:23:54.159169 INFO : End of MPR read delay center optimization
653 09:23:54.164635 INFO : End of write delay center optimization
654 09:23:54.170254 INFO : End of read delay center optimization
655 09:23:54.170705 INFO : End of max read latency training
656 09:23:54.175851 INFO : Training has run successfully!
657 09:23:54.176355 1D training succeed
658 09:23:54.185030 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 09:23:54.232818 Check phy result
660 09:23:54.233294 INFO : End of initialization
661 09:23:54.254440 INFO : End of 2D read delay Voltage center optimization
662 09:23:54.273664 INFO : End of 2D read delay Voltage center optimization
663 09:23:54.325543 INFO : End of 2D write delay Voltage center optimization
664 09:23:54.374814 INFO : End of 2D write delay Voltage center optimization
665 09:23:54.380398 INFO : Training has run successfully!
666 09:23:54.380862
667 09:23:54.381258 channel==0
668 09:23:54.385941 RxClkDly_Margin_A0==88 ps 9
669 09:23:54.386397 TxDqDly_Margin_A0==98 ps 10
670 09:23:54.389261 RxClkDly_Margin_A1==88 ps 9
671 09:23:54.389710 TxDqDly_Margin_A1==88 ps 9
672 09:23:54.394747 TrainedVREFDQ_A0==74
673 09:23:54.395200 TrainedVREFDQ_A1==74
674 09:23:54.395596 VrefDac_Margin_A0==25
675 09:23:54.400363 DeviceVref_Margin_A0==40
676 09:23:54.400813 VrefDac_Margin_A1==25
677 09:23:54.405923 DeviceVref_Margin_A1==40
678 09:23:54.406370
679 09:23:54.406760
680 09:23:54.407149 channel==1
681 09:23:54.407532 RxClkDly_Margin_A0==88 ps 9
682 09:23:54.411606 TxDqDly_Margin_A0==88 ps 9
683 09:23:54.411869 RxClkDly_Margin_A1==88 ps 9
684 09:23:54.417201 TxDqDly_Margin_A1==88 ps 9
685 09:23:54.417666 TrainedVREFDQ_A0==77
686 09:23:54.418080 TrainedVREFDQ_A1==77
687 09:23:54.422725 VrefDac_Margin_A0==23
688 09:23:54.423183 DeviceVref_Margin_A0==37
689 09:23:54.428407 VrefDac_Margin_A1==24
690 09:23:54.428955 DeviceVref_Margin_A1==37
691 09:23:54.429375
692 09:23:54.433937 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 09:23:54.434404
694 09:23:54.461898 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000017 00000017 00000019 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
695 09:23:54.467534 2D training succeed
696 09:23:54.473131 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 09:23:54.473600 auto size-- 65535DDR cs0 size: 2048MB
698 09:23:54.478731 DDR cs1 size: 2048MB
699 09:23:54.479192 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 09:23:54.484304 cs0 DataBus test pass
701 09:23:54.484762 cs1 DataBus test pass
702 09:23:54.485169 cs0 AddrBus test pass
703 09:23:54.489924 cs1 AddrBus test pass
704 09:23:54.490394
705 09:23:54.490804 100bdlr_step_size ps== 420
706 09:23:54.491211 result report
707 09:23:54.495551 boot times 0Enable ddr reg access
708 09:23:54.503000 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 09:23:54.516512 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 09:23:55.088794 0.0;M3 CHK:0;cm4_sp_mode 0
711 09:23:55.089279 MVN_1=0x00000000
712 09:23:55.094227 MVN_2=0x00000000
713 09:23:55.100379 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 09:23:55.101516 OPS=0x10
715 09:23:55.102404 ring efuse init
716 09:23:55.103191 chipver efuse init
717 09:23:55.108193 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 09:23:55.109254 [0.018961 Inits done]
719 09:23:55.110036 secure task start!
720 09:23:55.115821 high task start!
721 09:23:55.116894 low task start!
722 09:23:55.117685 run into bl31
723 09:23:55.122139 NOTICE: BL31: v1.3(release):4fc40b1
724 09:23:55.130290 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 09:23:55.131230 NOTICE: BL31: G12A normal boot!
726 09:23:55.155355 NOTICE: BL31: BL33 decompress pass
727 09:23:55.161118 ERROR: Error initializing runtime service opteed_fast
728 09:23:56.394070
729 09:23:56.394796
730 09:23:56.402291 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 09:23:56.402927
732 09:23:56.403480 Model: Libre Computer AML-A311D-CC Alta
733 09:23:56.610882 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 09:23:56.634214 DRAM: 2 GiB (effective 3.8 GiB)
735 09:23:56.777352 Core: 408 devices, 31 uclasses, devicetree: separate
736 09:23:56.783000 WDT: Not starting watchdog@f0d0
737 09:23:56.815260 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 09:23:56.827786 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 09:23:56.832779 ** Bad device specification mmc 0 **
740 09:23:56.842996 Card did not respond to voltage select! : -110
741 09:23:56.850956 ** Bad device specification mmc 0 **
742 09:23:56.851545 Couldn't find partition mmc 0
743 09:23:56.859005 Card did not respond to voltage select! : -110
744 09:23:56.864601 ** Bad device specification mmc 0 **
745 09:23:56.864884 Couldn't find partition mmc 0
746 09:23:56.869823 Error: could not access storage.
747 09:23:57.212289 Net: eth0: ethernet@ff3f0000
748 09:23:57.212743 starting USB...
749 09:23:57.464078 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 09:23:57.464538 Starting the controller
751 09:23:57.470947 USB XHCI 1.10
752 09:23:59.634099 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 09:23:59.634495 bl2_stage_init 0x01
754 09:23:59.634717 bl2_stage_init 0x81
755 09:23:59.639756 hw id: 0x0000 - pwm id 0x01
756 09:23:59.640201 bl2_stage_init 0xc1
757 09:23:59.640521 bl2_stage_init 0x02
758 09:23:59.640829
759 09:23:59.645418 L0:00000000
760 09:23:59.645738 L1:20000703
761 09:23:59.645943 L2:00008067
762 09:23:59.646156 L3:14000000
763 09:23:59.648294 B2:00402000
764 09:23:59.648571 B1:e0f83180
765 09:23:59.648775
766 09:23:59.648976 TE: 58167
767 09:23:59.649172
768 09:23:59.659464 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 09:23:59.659788
770 09:23:59.660248 Board ID = 1
771 09:23:59.660570 Set A53 clk to 24M
772 09:23:59.660794 Set A73 clk to 24M
773 09:23:59.665024 Set clk81 to 24M
774 09:23:59.665371 A53 clk: 1200 MHz
775 09:23:59.665577 A73 clk: 1200 MHz
776 09:23:59.670767 CLK81: 166.6M
777 09:23:59.671043 smccc: 00012abd
778 09:23:59.676332 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 09:23:59.676621 board id: 1
780 09:23:59.685124 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 09:23:59.695391 fw parse done
782 09:23:59.701424 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 09:23:59.743964 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 09:23:59.754926 PIEI prepare done
785 09:23:59.755227 fastboot data load
786 09:23:59.755441 fastboot data verify
787 09:23:59.760541 verify result: 266
788 09:23:59.766154 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 09:23:59.766466 LPDDR4 probe
790 09:23:59.766686 ddr clk to 1584MHz
791 09:23:59.774209 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 09:23:59.811473
793 09:23:59.811855 dmc_version 0001
794 09:23:59.818153 Check phy result
795 09:23:59.824054 INFO : End of CA training
796 09:23:59.824378 INFO : End of initialization
797 09:23:59.829602 INFO : Training has run successfully!
798 09:23:59.829894 Check phy result
799 09:23:59.835214 INFO : End of initialization
800 09:23:59.835616 INFO : End of read enable training
801 09:23:59.840773 INFO : End of fine write leveling
802 09:23:59.846485 INFO : End of Write leveling coarse delay
803 09:23:59.846812 INFO : Training has run successfully!
804 09:23:59.847063 Check phy result
805 09:23:59.852025 INFO : End of initialization
806 09:23:59.852358 INFO : End of read dq deskew training
807 09:23:59.857590 INFO : End of MPR read delay center optimization
808 09:23:59.863175 INFO : End of write delay center optimization
809 09:23:59.868843 INFO : End of read delay center optimization
810 09:23:59.869424 INFO : End of max read latency training
811 09:23:59.874438 INFO : Training has run successfully!
812 09:23:59.874987 1D training succeed
813 09:23:59.883642 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 09:23:59.931293 Check phy result
815 09:23:59.931894 INFO : End of initialization
816 09:23:59.952957 INFO : End of 2D read delay Voltage center optimization
817 09:23:59.973209 INFO : End of 2D read delay Voltage center optimization
818 09:24:00.025252 INFO : End of 2D write delay Voltage center optimization
819 09:24:00.074601 INFO : End of 2D write delay Voltage center optimization
820 09:24:00.080166 INFO : Training has run successfully!
821 09:24:00.080736
822 09:24:00.081189 channel==0
823 09:24:00.085776 RxClkDly_Margin_A0==88 ps 9
824 09:24:00.086367 TxDqDly_Margin_A0==98 ps 10
825 09:24:00.091354 RxClkDly_Margin_A1==88 ps 9
826 09:24:00.091938 TxDqDly_Margin_A1==88 ps 9
827 09:24:00.092462 TrainedVREFDQ_A0==74
828 09:24:00.096964 TrainedVREFDQ_A1==74
829 09:24:00.097526 VrefDac_Margin_A0==25
830 09:24:00.097963 DeviceVref_Margin_A0==40
831 09:24:00.102605 VrefDac_Margin_A1==25
832 09:24:00.103179 DeviceVref_Margin_A1==40
833 09:24:00.103611
834 09:24:00.104086
835 09:24:00.104554 channel==1
836 09:24:00.108266 RxClkDly_Margin_A0==98 ps 10
837 09:24:00.108832 TxDqDly_Margin_A0==98 ps 10
838 09:24:00.113750 RxClkDly_Margin_A1==98 ps 10
839 09:24:00.114290 TxDqDly_Margin_A1==88 ps 9
840 09:24:00.119388 TrainedVREFDQ_A0==77
841 09:24:00.119956 TrainedVREFDQ_A1==77
842 09:24:00.120475 VrefDac_Margin_A0==22
843 09:24:00.124972 DeviceVref_Margin_A0==37
844 09:24:00.125526 VrefDac_Margin_A1==22
845 09:24:00.130547 DeviceVref_Margin_A1==37
846 09:24:00.131087
847 09:24:00.131525 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 09:24:00.131972
849 09:24:00.164207 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
850 09:24:00.164815 2D training succeed
851 09:24:00.169799 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 09:24:00.175348 auto size-- 65535DDR cs0 size: 2048MB
853 09:24:00.175894 DDR cs1 size: 2048MB
854 09:24:00.180973 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 09:24:00.181564 cs0 DataBus test pass
856 09:24:00.186608 cs1 DataBus test pass
857 09:24:00.187202 cs0 AddrBus test pass
858 09:24:00.187640 cs1 AddrBus test pass
859 09:24:00.188117
860 09:24:00.192232 100bdlr_step_size ps== 420
861 09:24:00.192833 result report
862 09:24:00.197828 boot times 0Enable ddr reg access
863 09:24:00.203230 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 09:24:00.215691 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 09:24:00.790141 0.0;M3 CHK:0;cm4_sp_mode 0
866 09:24:00.790561 MVN_1=0x00000000
867 09:24:00.795669 MVN_2=0x00000000
868 09:24:00.801433 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 09:24:00.801762 OPS=0x10
870 09:24:00.801987 ring efuse init
871 09:24:00.802198 chipver efuse init
872 09:24:00.807059 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 09:24:00.812632 [0.018960 Inits done]
874 09:24:00.812975 secure task start!
875 09:24:00.813200 high task start!
876 09:24:00.817192 low task start!
877 09:24:00.817527 run into bl31
878 09:24:00.823877 NOTICE: BL31: v1.3(release):4fc40b1
879 09:24:00.831620 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 09:24:00.831975 NOTICE: BL31: G12A normal boot!
881 09:24:00.857048 NOTICE: BL31: BL33 decompress pass
882 09:24:00.862646 ERROR: Error initializing runtime service opteed_fast
883 09:24:02.095601
884 09:24:02.096081
885 09:24:02.103101 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 09:24:02.103510
887 09:24:02.103796 Model: Libre Computer AML-A311D-CC Alta
888 09:24:02.312448 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 09:24:02.335763 DRAM: 2 GiB (effective 3.8 GiB)
890 09:24:02.478901 Core: 408 devices, 31 uclasses, devicetree: separate
891 09:24:02.484601 WDT: Not starting watchdog@f0d0
892 09:24:02.516947 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 09:24:02.529414 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 09:24:02.534257 ** Bad device specification mmc 0 **
895 09:24:02.544666 Card did not respond to voltage select! : -110
896 09:24:02.552010 ** Bad device specification mmc 0 **
897 09:24:02.552395 Couldn't find partition mmc 0
898 09:24:02.560639 Card did not respond to voltage select! : -110
899 09:24:02.566135 ** Bad device specification mmc 0 **
900 09:24:02.566497 Couldn't find partition mmc 0
901 09:24:02.571116 Error: could not access storage.
902 09:24:02.914248 Net: eth0: ethernet@ff3f0000
903 09:24:02.914877 starting USB...
904 09:24:03.166637 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 09:24:03.167066 Starting the controller
906 09:24:03.172668 USB XHCI 1.10
907 09:24:05.034335 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 09:24:05.035478 bl2_stage_init 0x01
909 09:24:05.036414 bl2_stage_init 0x81
910 09:24:05.039762 hw id: 0x0000 - pwm id 0x01
911 09:24:05.040777 bl2_stage_init 0xc1
912 09:24:05.041596 bl2_stage_init 0x02
913 09:24:05.042463
914 09:24:05.045417 L0:00000000
915 09:24:05.046311 L1:20000703
916 09:24:05.047148 L2:00008067
917 09:24:05.048019 L3:14000000
918 09:24:05.049310 B2:00402000
919 09:24:05.049805 B1:e0f83180
920 09:24:05.050263
921 09:24:05.050715 TE: 58167
922 09:24:05.051162
923 09:24:05.059477 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 09:24:05.060090
925 09:24:05.060590 Board ID = 1
926 09:24:05.061065 Set A53 clk to 24M
927 09:24:05.061538 Set A73 clk to 24M
928 09:24:05.065072 Set clk81 to 24M
929 09:24:05.065605 A53 clk: 1200 MHz
930 09:24:05.066079 A73 clk: 1200 MHz
931 09:24:05.068614 CLK81: 166.6M
932 09:24:05.069136 smccc: 00012abd
933 09:24:05.074197 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 09:24:05.079950 board id: 1
935 09:24:05.084129 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 09:24:05.095276 fw parse done
937 09:24:05.100253 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 09:24:05.143580 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 09:24:05.155158 PIEI prepare done
940 09:24:05.155524 fastboot data load
941 09:24:05.155745 fastboot data verify
942 09:24:05.160481 verify result: 266
943 09:24:05.166175 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 09:24:05.166772 LPDDR4 probe
945 09:24:05.167231 ddr clk to 1584MHz
946 09:24:05.173511 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 09:24:05.210486
948 09:24:05.210866 dmc_version 0001
949 09:24:05.218563 Check phy result
950 09:24:05.224177 INFO : End of CA training
951 09:24:05.225176 INFO : End of initialization
952 09:24:05.229659 INFO : Training has run successfully!
953 09:24:05.230639 Check phy result
954 09:24:05.235268 INFO : End of initialization
955 09:24:05.236399 INFO : End of read enable training
956 09:24:05.240853 INFO : End of fine write leveling
957 09:24:05.246396 INFO : End of Write leveling coarse delay
958 09:24:05.246995 INFO : Training has run successfully!
959 09:24:05.247501 Check phy result
960 09:24:05.251853 INFO : End of initialization
961 09:24:05.252366 INFO : End of read dq deskew training
962 09:24:05.257673 INFO : End of MPR read delay center optimization
963 09:24:05.263305 INFO : End of write delay center optimization
964 09:24:05.268897 INFO : End of read delay center optimization
965 09:24:05.269860 INFO : End of max read latency training
966 09:24:05.274508 INFO : Training has run successfully!
967 09:24:05.275415 1D training succeed
968 09:24:05.282627 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 09:24:05.331284 Check phy result
970 09:24:05.331968 INFO : End of initialization
971 09:24:05.352332 INFO : End of 2D read delay Voltage center optimization
972 09:24:05.372368 INFO : End of 2D read delay Voltage center optimization
973 09:24:05.424681 INFO : End of 2D write delay Voltage center optimization
974 09:24:05.474431 INFO : End of 2D write delay Voltage center optimization
975 09:24:05.480095 INFO : Training has run successfully!
976 09:24:05.480711
977 09:24:05.481197 channel==0
978 09:24:05.485661 RxClkDly_Margin_A0==88 ps 9
979 09:24:05.486248 TxDqDly_Margin_A0==98 ps 10
980 09:24:05.491576 RxClkDly_Margin_A1==88 ps 9
981 09:24:05.492219 TxDqDly_Margin_A1==98 ps 10
982 09:24:05.492711 TrainedVREFDQ_A0==74
983 09:24:05.496889 TrainedVREFDQ_A1==74
984 09:24:05.497461 VrefDac_Margin_A0==25
985 09:24:05.497934 DeviceVref_Margin_A0==40
986 09:24:05.502355 VrefDac_Margin_A1==25
987 09:24:05.502688 DeviceVref_Margin_A1==40
988 09:24:05.502934
989 09:24:05.503178
990 09:24:05.507878 channel==1
991 09:24:05.508236 RxClkDly_Margin_A0==98 ps 10
992 09:24:05.508488 TxDqDly_Margin_A0==98 ps 10
993 09:24:05.513503 RxClkDly_Margin_A1==98 ps 10
994 09:24:05.513844 TxDqDly_Margin_A1==88 ps 9
995 09:24:05.519166 TrainedVREFDQ_A0==77
996 09:24:05.519541 TrainedVREFDQ_A1==77
997 09:24:05.519762 VrefDac_Margin_A0==22
998 09:24:05.524800 DeviceVref_Margin_A0==37
999 09:24:05.525176 VrefDac_Margin_A1==22
1000 09:24:05.530301 DeviceVref_Margin_A1==37
1001 09:24:05.530617
1002 09:24:05.530846 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 09:24:05.535907
1004 09:24:05.563962 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 09:24:05.564631 2D training succeed
1006 09:24:05.569646 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 09:24:05.575139 auto size-- 65535DDR cs0 size: 2048MB
1008 09:24:05.575475 DDR cs1 size: 2048MB
1009 09:24:05.580809 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 09:24:05.581327 cs0 DataBus test pass
1011 09:24:05.586385 cs1 DataBus test pass
1012 09:24:05.586885 cs0 AddrBus test pass
1013 09:24:05.587139 cs1 AddrBus test pass
1014 09:24:05.587342
1015 09:24:05.592029 100bdlr_step_size ps== 420
1016 09:24:05.592543 result report
1017 09:24:05.597546 boot times 0Enable ddr reg access
1018 09:24:05.602444 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 09:24:05.615681 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 09:24:06.189590 0.0;M3 CHK:0;cm4_sp_mode 0
1021 09:24:06.190024 MVN_1=0x00000000
1022 09:24:06.195070 MVN_2=0x00000000
1023 09:24:06.200823 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 09:24:06.201325 OPS=0x10
1025 09:24:06.201784 ring efuse init
1026 09:24:06.202229 chipver efuse init
1027 09:24:06.206431 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 09:24:06.212077 [0.018960 Inits done]
1029 09:24:06.212582 secure task start!
1030 09:24:06.213036 high task start!
1031 09:24:06.215769 low task start!
1032 09:24:06.216311 run into bl31
1033 09:24:06.223260 NOTICE: BL31: v1.3(release):4fc40b1
1034 09:24:06.230144 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 09:24:06.230648 NOTICE: BL31: G12A normal boot!
1036 09:24:06.256442 NOTICE: BL31: BL33 decompress pass
1037 09:24:06.261499 ERROR: Error initializing runtime service opteed_fast
1038 09:24:07.495087
1039 09:24:07.495756
1040 09:24:07.502859 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 09:24:07.503371
1042 09:24:07.503831 Model: Libre Computer AML-A311D-CC Alta
1043 09:24:07.710845 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 09:24:07.734237 DRAM: 2 GiB (effective 3.8 GiB)
1045 09:24:07.878189 Core: 408 devices, 31 uclasses, devicetree: separate
1046 09:24:07.883788 WDT: Not starting watchdog@f0d0
1047 09:24:07.916408 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 09:24:07.928790 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 09:24:07.932947 ** Bad device specification mmc 0 **
1050 09:24:07.944107 Card did not respond to voltage select! : -110
1051 09:24:07.950868 ** Bad device specification mmc 0 **
1052 09:24:07.951363 Couldn't find partition mmc 0
1053 09:24:07.960118 Card did not respond to voltage select! : -110
1054 09:24:07.965621 ** Bad device specification mmc 0 **
1055 09:24:07.966116 Couldn't find partition mmc 0
1056 09:24:07.970745 Error: could not access storage.
1057 09:24:08.312633 Net: eth0: ethernet@ff3f0000
1058 09:24:08.313257 starting USB...
1059 09:24:08.564931 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 09:24:08.565528 Starting the controller
1061 09:24:08.570947 USB XHCI 1.10
1062 09:24:10.129225 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 09:24:10.136615 scanning usb for storage devices... 0 Storage Device(s) found
1065 09:24:10.188315 Hit any key to stop autoboot: 1
1066 09:24:10.189180 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1067 09:24:10.189861 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1068 09:24:10.190365 Setting prompt string to ['=>']
1069 09:24:10.190875 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1070 09:24:10.196387 0
1071 09:24:10.197296 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 09:24:10.197826 Sending with 10 millisecond of delay
1074 09:24:11.332698 => setenv autoload no
1075 09:24:11.343516 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 09:24:11.348885 setenv autoload no
1077 09:24:11.349678 Sending with 10 millisecond of delay
1079 09:24:13.146565 => setenv initrd_high 0xffffffff
1080 09:24:13.157323 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1081 09:24:13.157812 setenv initrd_high 0xffffffff
1082 09:24:13.158252 Sending with 10 millisecond of delay
1084 09:24:14.774404 => setenv fdt_high 0xffffffff
1085 09:24:14.785133 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 09:24:14.785863 setenv fdt_high 0xffffffff
1087 09:24:14.786480 Sending with 10 millisecond of delay
1089 09:24:15.078095 => dhcp
1090 09:24:15.088651 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1091 09:24:15.089150 dhcp
1092 09:24:15.089405 Speed: 1000, full duplex
1093 09:24:15.089634 BOOTP broadcast 1
1094 09:24:15.335662 BOOTP broadcast 2
1095 09:24:15.837375 BOOTP broadcast 3
1096 09:24:15.849337 DHCP client bound to address 192.168.6.33 (761 ms)
1097 09:24:15.850163 Sending with 10 millisecond of delay
1099 09:24:17.527158 => setenv serverip 192.168.6.2
1100 09:24:17.537977 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1101 09:24:17.538901 setenv serverip 192.168.6.2
1102 09:24:17.539653 Sending with 10 millisecond of delay
1104 09:24:21.265796 => tftpboot 0x01080000 819488/tftp-deploy-7rs145vw/kernel/uImage
1105 09:24:21.277729 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1106 09:24:21.278694 tftpboot 0x01080000 819488/tftp-deploy-7rs145vw/kernel/uImage
1107 09:24:21.279180 Speed: 1000, full duplex
1108 09:24:21.279642 Using ethernet@ff3f0000 device
1109 09:24:21.280505 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1110 09:24:21.285985 Filename '819488/tftp-deploy-7rs145vw/kernel/uImage'.
1111 09:24:21.289899 Load address: 0x1080000
1112 09:24:24.761921 Loading: *################################################## 43.6 MiB
1113 09:24:24.762321 12.5 MiB/s
1114 09:24:24.762535 done
1115 09:24:24.766269 Bytes transferred = 45713984 (2b98a40 hex)
1116 09:24:24.766869 Sending with 10 millisecond of delay
1118 09:24:29.455209 => tftpboot 0x08000000 819488/tftp-deploy-7rs145vw/ramdisk/ramdisk.cpio.gz.uboot
1119 09:24:29.466114 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
1120 09:24:29.466802 tftpboot 0x08000000 819488/tftp-deploy-7rs145vw/ramdisk/ramdisk.cpio.gz.uboot
1121 09:24:29.467057 Speed: 1000, full duplex
1122 09:24:29.467269 Using ethernet@ff3f0000 device
1123 09:24:29.471720 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1124 09:24:29.481481 Filename '819488/tftp-deploy-7rs145vw/ramdisk/ramdisk.cpio.gz.uboot'.
1125 09:24:29.482137 Load address: 0x8000000
1126 09:24:39.502744 Loading: *T ################################# UDP wrong checksum 000000ff 0000ffa7
1127 09:24:39.599651 UDP wrong checksum 000000ff 0000959a
1128 09:24:45.882966 T ########### UDP wrong checksum 000000ff 00004c26
1129 09:24:45.903640 # UDP wrong checksum 000000ff 0000e918
1130 09:24:46.447424 #### UDP wrong checksum 0000000f 0000090e
1131 09:24:51.448082 T UDP wrong checksum 0000000f 0000090e
1132 09:24:54.950792 UDP wrong checksum 000000ff 0000a135
1133 09:24:54.959343 UDP wrong checksum 000000ff 00003528
1134 09:25:01.449641 T T UDP wrong checksum 0000000f 0000090e
1135 09:25:21.453845 T T T T UDP wrong checksum 0000000f 0000090e
1136 09:25:31.457080 T
1137 09:25:31.457505 Retry count exceeded; starting again
1139 09:25:31.459202 end: 2.4.3 bootloader-commands (duration 00:01:21) [common]
1142 09:25:31.461371 end: 2.4 uboot-commands (duration 00:01:59) [common]
1144 09:25:31.462825 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1146 09:25:31.464031 end: 2 uboot-action (duration 00:01:59) [common]
1148 09:25:31.465712 Cleaning after the job
1149 09:25:31.466323 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/ramdisk
1150 09:25:31.467698 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/kernel
1151 09:25:31.497845 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/dtb
1152 09:25:31.499320 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/819488/tftp-deploy-7rs145vw/modules
1153 09:25:31.506885 start: 4.1 power-off (timeout 00:00:30) [common]
1154 09:25:31.508070 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1155 09:25:31.544419 >> OK - accepted request
1156 09:25:31.546498 Returned 0 in 0 seconds
1157 09:25:31.647777 end: 4.1 power-off (duration 00:00:00) [common]
1159 09:25:31.649783 start: 4.2 read-feedback (timeout 00:10:00) [common]
1160 09:25:31.651129 Listened to connection for namespace 'common' for up to 1s
1161 09:25:32.651800 Finalising connection for namespace 'common'
1162 09:25:32.652350 Disconnecting from shell: Finalise
1163 09:25:32.652665 =>
1164 09:25:32.753513 end: 4.2 read-feedback (duration 00:00:01) [common]
1165 09:25:32.754060 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/819488
1166 09:25:33.916241 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/819488
1167 09:25:33.916920 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.