Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:18:17.338015 lava-dispatcher, installed at version: 2024.01
2 07:18:17.338822 start: 0 validate
3 07:18:17.339295 Start time: 2024-10-10 07:18:17.339266+00:00 (UTC)
4 07:18:17.339963 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:18:17.340523 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:18:17.387381 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:18:17.387959 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241010%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 07:18:17.419689 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:18:17.420328 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241010%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 07:18:17.452013 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:18:17.452468 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:18:17.487390 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:18:17.487839 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241010%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
14 07:18:17.530999 validate duration: 0.19
16 07:18:17.532540 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:18:17.533177 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:18:17.533748 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:18:17.534715 Not decompressing ramdisk as can be used compressed.
20 07:18:17.535482 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 07:18:17.536005 saving as /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/ramdisk/initrd.cpio.gz
22 07:18:17.536538 total size: 5628182 (5 MB)
23 07:18:17.583505 progress 0 % (0 MB)
24 07:18:17.589162 progress 5 % (0 MB)
25 07:18:17.597116 progress 10 % (0 MB)
26 07:18:17.604258 progress 15 % (0 MB)
27 07:18:17.612228 progress 20 % (1 MB)
28 07:18:17.617866 progress 25 % (1 MB)
29 07:18:17.622127 progress 30 % (1 MB)
30 07:18:17.626375 progress 35 % (1 MB)
31 07:18:17.630130 progress 40 % (2 MB)
32 07:18:17.634300 progress 45 % (2 MB)
33 07:18:17.638020 progress 50 % (2 MB)
34 07:18:17.642263 progress 55 % (2 MB)
35 07:18:17.646393 progress 60 % (3 MB)
36 07:18:17.650104 progress 65 % (3 MB)
37 07:18:17.654256 progress 70 % (3 MB)
38 07:18:17.658196 progress 75 % (4 MB)
39 07:18:17.662367 progress 80 % (4 MB)
40 07:18:17.666136 progress 85 % (4 MB)
41 07:18:17.670220 progress 90 % (4 MB)
42 07:18:17.674398 progress 95 % (5 MB)
43 07:18:17.677939 progress 100 % (5 MB)
44 07:18:17.678621 5 MB downloaded in 0.14 s (37.78 MB/s)
45 07:18:17.679193 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:18:17.680150 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:18:17.680453 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:18:17.680738 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:18:17.681233 downloading http://storage.kernelci.org/next/master/next-20241010/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
51 07:18:17.681474 saving as /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/kernel/Image
52 07:18:17.681703 total size: 46066176 (43 MB)
53 07:18:17.681918 No compression specified
54 07:18:17.720124 progress 0 % (0 MB)
55 07:18:17.754740 progress 5 % (2 MB)
56 07:18:17.788842 progress 10 % (4 MB)
57 07:18:17.822300 progress 15 % (6 MB)
58 07:18:17.857224 progress 20 % (8 MB)
59 07:18:17.890928 progress 25 % (11 MB)
60 07:18:17.924922 progress 30 % (13 MB)
61 07:18:17.959463 progress 35 % (15 MB)
62 07:18:17.993879 progress 40 % (17 MB)
63 07:18:18.028402 progress 45 % (19 MB)
64 07:18:18.062627 progress 50 % (21 MB)
65 07:18:18.098266 progress 55 % (24 MB)
66 07:18:18.133382 progress 60 % (26 MB)
67 07:18:18.165234 progress 65 % (28 MB)
68 07:18:18.194194 progress 70 % (30 MB)
69 07:18:18.221951 progress 75 % (32 MB)
70 07:18:18.250534 progress 80 % (35 MB)
71 07:18:18.279493 progress 85 % (37 MB)
72 07:18:18.309968 progress 90 % (39 MB)
73 07:18:18.339151 progress 95 % (41 MB)
74 07:18:18.367775 progress 100 % (43 MB)
75 07:18:18.368588 43 MB downloaded in 0.69 s (63.96 MB/s)
76 07:18:18.369092 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:18:18.369938 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:18:18.370221 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:18:18.370493 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:18:18.370951 downloading http://storage.kernelci.org/next/master/next-20241010/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 07:18:18.371232 saving as /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 07:18:18.371442 total size: 53209 (0 MB)
84 07:18:18.371655 No compression specified
85 07:18:18.408828 progress 61 % (0 MB)
86 07:18:18.409683 progress 100 % (0 MB)
87 07:18:18.410268 0 MB downloaded in 0.04 s (1.31 MB/s)
88 07:18:18.410767 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:18:18.411623 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:18:18.411914 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:18:18.412232 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:18:18.412742 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 07:18:18.413016 saving as /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/nfsrootfs/full.rootfs.tar
95 07:18:18.413238 total size: 107552908 (102 MB)
96 07:18:18.413473 Using unxz to decompress xz
97 07:18:18.447395 progress 0 % (0 MB)
98 07:18:19.092128 progress 5 % (5 MB)
99 07:18:19.820060 progress 10 % (10 MB)
100 07:18:20.540912 progress 15 % (15 MB)
101 07:18:21.371723 progress 20 % (20 MB)
102 07:18:21.941226 progress 25 % (25 MB)
103 07:18:22.562787 progress 30 % (30 MB)
104 07:18:23.307315 progress 35 % (35 MB)
105 07:18:23.655337 progress 40 % (41 MB)
106 07:18:24.080100 progress 45 % (46 MB)
107 07:18:24.781212 progress 50 % (51 MB)
108 07:18:25.476813 progress 55 % (56 MB)
109 07:18:26.229737 progress 60 % (61 MB)
110 07:18:26.982834 progress 65 % (66 MB)
111 07:18:27.714508 progress 70 % (71 MB)
112 07:18:28.579360 progress 75 % (76 MB)
113 07:18:29.277389 progress 80 % (82 MB)
114 07:18:29.980931 progress 85 % (87 MB)
115 07:18:30.709013 progress 90 % (92 MB)
116 07:18:31.413461 progress 95 % (97 MB)
117 07:18:32.144418 progress 100 % (102 MB)
118 07:18:32.156179 102 MB downloaded in 13.74 s (7.46 MB/s)
119 07:18:32.157038 end: 1.4.1 http-download (duration 00:00:14) [common]
121 07:18:32.158645 end: 1.4 download-retry (duration 00:00:14) [common]
122 07:18:32.159164 start: 1.5 download-retry (timeout 00:09:45) [common]
123 07:18:32.159675 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 07:18:32.160510 downloading http://storage.kernelci.org/next/master/next-20241010/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
125 07:18:32.160979 saving as /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/modules/modules.tar
126 07:18:32.161380 total size: 11623480 (11 MB)
127 07:18:32.161790 Using unxz to decompress xz
128 07:18:32.207484 progress 0 % (0 MB)
129 07:18:32.269631 progress 5 % (0 MB)
130 07:18:32.348282 progress 10 % (1 MB)
131 07:18:32.435580 progress 15 % (1 MB)
132 07:18:32.526779 progress 20 % (2 MB)
133 07:18:32.610051 progress 25 % (2 MB)
134 07:18:32.687586 progress 30 % (3 MB)
135 07:18:32.771200 progress 35 % (3 MB)
136 07:18:32.847425 progress 40 % (4 MB)
137 07:18:32.934713 progress 45 % (5 MB)
138 07:18:33.017691 progress 50 % (5 MB)
139 07:18:33.100819 progress 55 % (6 MB)
140 07:18:33.180299 progress 60 % (6 MB)
141 07:18:33.256565 progress 65 % (7 MB)
142 07:18:33.336659 progress 70 % (7 MB)
143 07:18:33.414373 progress 75 % (8 MB)
144 07:18:33.486771 progress 80 % (8 MB)
145 07:18:33.570363 progress 85 % (9 MB)
146 07:18:33.654250 progress 90 % (10 MB)
147 07:18:33.729759 progress 95 % (10 MB)
148 07:18:33.809530 progress 100 % (11 MB)
149 07:18:33.823755 11 MB downloaded in 1.66 s (6.67 MB/s)
150 07:18:33.824690 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:18:33.826290 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:18:33.826809 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 07:18:33.827319 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 07:18:43.869930 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/831780/extract-nfsrootfs-o3f84vtm
156 07:18:43.870642 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 07:18:43.870997 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 07:18:43.871790 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk
159 07:18:43.872463 makedir: /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin
160 07:18:43.872928 makedir: /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/tests
161 07:18:43.873339 makedir: /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/results
162 07:18:43.873742 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-add-keys
163 07:18:43.874395 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-add-sources
164 07:18:43.875015 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-background-process-start
165 07:18:43.875882 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-background-process-stop
166 07:18:43.876825 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-common-functions
167 07:18:43.877528 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-echo-ipv4
168 07:18:43.878178 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-install-packages
169 07:18:43.878799 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-installed-packages
170 07:18:43.879435 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-os-build
171 07:18:43.880059 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-probe-channel
172 07:18:43.880665 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-probe-ip
173 07:18:43.881256 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-target-ip
174 07:18:43.881847 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-target-mac
175 07:18:43.882568 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-target-storage
176 07:18:43.883270 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-test-case
177 07:18:43.883920 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-test-event
178 07:18:43.884583 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-test-feedback
179 07:18:43.885189 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-test-raise
180 07:18:43.885821 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-test-reference
181 07:18:43.886419 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-test-runner
182 07:18:43.887047 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-test-set
183 07:18:43.887636 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-test-shell
184 07:18:43.888322 Updating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-install-packages (oe)
185 07:18:43.889002 Updating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/bin/lava-installed-packages (oe)
186 07:18:43.889554 Creating /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/environment
187 07:18:43.890036 LAVA metadata
188 07:18:43.890356 - LAVA_JOB_ID=831780
189 07:18:43.890662 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:18:43.891135 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 07:18:43.892548 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:18:43.892975 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 07:18:43.893259 skipped lava-vland-overlay
194 07:18:43.893568 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:18:43.894091 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 07:18:43.894388 skipped lava-multinode-overlay
197 07:18:43.894722 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:18:43.895043 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 07:18:43.895356 Loading test definitions
200 07:18:43.895704 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 07:18:43.895969 Using /lava-831780 at stage 0
202 07:18:43.897633 uuid=831780_1.6.2.4.1 testdef=None
203 07:18:43.898014 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:18:43.898339 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 07:18:43.900600 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:18:43.901563 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 07:18:43.904516 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:18:43.905521 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 07:18:43.908395 runner path: /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/0/tests/0_dmesg test_uuid 831780_1.6.2.4.1
212 07:18:43.909179 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:18:43.910147 Creating lava-test-runner.conf files
215 07:18:43.910395 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/831780/lava-overlay-z_d_rjzk/lava-831780/0 for stage 0
216 07:18:43.910882 - 0_dmesg
217 07:18:43.911338 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:18:43.911722 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 07:18:43.941425 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:18:43.941972 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 07:18:43.942307 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:18:43.942675 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:18:43.943050 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 07:18:44.576647 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:18:44.577116 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 07:18:44.577364 extracting modules file /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/modules/modules.tar to /var/lib/lava/dispatcher/tmp/831780/extract-nfsrootfs-o3f84vtm
227 07:18:46.057433 extracting modules file /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/modules/modules.tar to /var/lib/lava/dispatcher/tmp/831780/extract-overlay-ramdisk-oqv5wzuy/ramdisk
228 07:18:47.464458 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:18:47.464927 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 07:18:47.465213 [common] Applying overlay to NFS
231 07:18:47.465428 [common] Applying overlay /var/lib/lava/dispatcher/tmp/831780/compress-overlay-6z0q8uom/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/831780/extract-nfsrootfs-o3f84vtm
232 07:18:47.494911 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:18:47.495330 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 07:18:47.495602 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 07:18:47.495829 Converting downloaded kernel to a uImage
236 07:18:47.496161 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/kernel/Image /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/kernel/uImage
237 07:18:47.992904 output: Image Name:
238 07:18:47.993329 output: Created: Thu Oct 10 07:18:47 2024
239 07:18:47.993537 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:18:47.993741 output: Data Size: 46066176 Bytes = 44986.50 KiB = 43.93 MiB
241 07:18:47.993941 output: Load Address: 01080000
242 07:18:47.994139 output: Entry Point: 01080000
243 07:18:47.994335 output:
244 07:18:47.994670 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 07:18:47.994936 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 07:18:47.995203 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 07:18:47.995456 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:18:47.995714 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 07:18:47.996009 Building ramdisk /var/lib/lava/dispatcher/tmp/831780/extract-overlay-ramdisk-oqv5wzuy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/831780/extract-overlay-ramdisk-oqv5wzuy/ramdisk
250 07:18:50.380585 >> 167077 blocks
251 07:18:58.685949 Adding RAMdisk u-boot header.
252 07:18:58.686494 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/831780/extract-overlay-ramdisk-oqv5wzuy/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/831780/extract-overlay-ramdisk-oqv5wzuy/ramdisk.cpio.gz.uboot
253 07:18:58.938779 output: Image Name:
254 07:18:58.939203 output: Created: Thu Oct 10 07:18:58 2024
255 07:18:58.939418 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:18:58.939625 output: Data Size: 23430613 Bytes = 22881.46 KiB = 22.35 MiB
257 07:18:58.939826 output: Load Address: 00000000
258 07:18:58.940097 output: Entry Point: 00000000
259 07:18:58.940499 output:
260 07:18:58.941638 rename /var/lib/lava/dispatcher/tmp/831780/extract-overlay-ramdisk-oqv5wzuy/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/ramdisk/ramdisk.cpio.gz.uboot
261 07:18:58.942354 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 07:18:58.942901 end: 1.6 prepare-tftp-overlay (duration 00:00:25) [common]
263 07:18:58.943464 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
264 07:18:58.943919 No LXC device requested
265 07:18:58.944451 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:18:58.944961 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
267 07:18:58.945454 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:18:58.945862 Checking files for TFTP limit of 4294967296 bytes.
269 07:18:58.948556 end: 1 tftp-deploy (duration 00:00:41) [common]
270 07:18:58.949133 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:18:58.949655 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:18:58.950147 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:18:58.950646 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:18:58.951170 Using kernel file from prepare-kernel: 831780/tftp-deploy-vilhxska/kernel/uImage
275 07:18:58.951791 substitutions:
276 07:18:58.952225 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:18:58.952628 - {DTB_ADDR}: 0x01070000
278 07:18:58.953023 - {DTB}: 831780/tftp-deploy-vilhxska/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 07:18:58.953420 - {INITRD}: 831780/tftp-deploy-vilhxska/ramdisk/ramdisk.cpio.gz.uboot
280 07:18:58.953813 - {KERNEL_ADDR}: 0x01080000
281 07:18:58.954207 - {KERNEL}: 831780/tftp-deploy-vilhxska/kernel/uImage
282 07:18:58.954600 - {LAVA_MAC}: None
283 07:18:58.955027 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/831780/extract-nfsrootfs-o3f84vtm
284 07:18:58.955421 - {NFS_SERVER_IP}: 192.168.6.2
285 07:18:58.955810 - {PRESEED_CONFIG}: None
286 07:18:58.956141 - {PRESEED_LOCAL}: None
287 07:18:58.956338 - {RAMDISK_ADDR}: 0x08000000
288 07:18:58.956532 - {RAMDISK}: 831780/tftp-deploy-vilhxska/ramdisk/ramdisk.cpio.gz.uboot
289 07:18:58.956726 - {ROOT_PART}: None
290 07:18:58.956920 - {ROOT}: None
291 07:18:58.957117 - {SERVER_IP}: 192.168.6.2
292 07:18:58.957311 - {TEE_ADDR}: 0x83000000
293 07:18:58.957503 - {TEE}: None
294 07:18:58.957697 Parsed boot commands:
295 07:18:58.957887 - setenv autoload no
296 07:18:58.958080 - setenv initrd_high 0xffffffff
297 07:18:58.958273 - setenv fdt_high 0xffffffff
298 07:18:58.958465 - dhcp
299 07:18:58.958658 - setenv serverip 192.168.6.2
300 07:18:58.958850 - tftpboot 0x01080000 831780/tftp-deploy-vilhxska/kernel/uImage
301 07:18:58.959043 - tftpboot 0x08000000 831780/tftp-deploy-vilhxska/ramdisk/ramdisk.cpio.gz.uboot
302 07:18:58.959236 - tftpboot 0x01070000 831780/tftp-deploy-vilhxska/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 07:18:58.959428 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/831780/extract-nfsrootfs-o3f84vtm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:18:58.959628 - bootm 0x01080000 0x08000000 0x01070000
305 07:18:58.959883 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:18:58.961287 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:18:58.961699 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 07:18:58.976805 Setting prompt string to ['lava-test: # ']
310 07:18:58.978306 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:18:58.978890 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:18:58.979428 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:18:58.980009 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:18:58.981121 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 07:18:59.017920 >> OK - accepted request
316 07:18:59.020104 Returned 0 in 0 seconds
317 07:18:59.121029 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:18:59.122719 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:18:59.123278 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:18:59.123781 Setting prompt string to ['Hit any key to stop autoboot']
322 07:18:59.124375 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:18:59.125933 Trying 192.168.56.21...
324 07:18:59.126416 Connected to conserv1.
325 07:18:59.126836 Escape character is '^]'.
326 07:18:59.127252
327 07:18:59.127672 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 07:18:59.128136
329 07:19:07.519379 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 07:19:07.519825 bl2_stage_init 0x01
331 07:19:07.520098 bl2_stage_init 0x81
332 07:19:07.525119 hw id: 0x0000 - pwm id 0x01
333 07:19:07.525430 bl2_stage_init 0xc1
334 07:19:07.525655 bl2_stage_init 0x02
335 07:19:07.525867
336 07:19:07.530560 L0:00000000
337 07:19:07.530951 L1:00000703
338 07:19:07.531272 L2:00008067
339 07:19:07.531593 L3:15000000
340 07:19:07.531914 S1:00000000
341 07:19:07.536170 B2:20282000
342 07:19:07.536552 B1:a0f83180
343 07:19:07.536877
344 07:19:07.537113 TE: 68153
345 07:19:07.537322
346 07:19:07.541770 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 07:19:07.542169
348 07:19:07.547316 Board ID = 1
349 07:19:07.547707 Set cpu clk to 24M
350 07:19:07.548045 Set clk81 to 24M
351 07:19:07.553108 Use GP1_pll as DSU clk.
352 07:19:07.553384 DSU clk: 1200 Mhz
353 07:19:07.553595 CPU clk: 1200 MHz
354 07:19:07.553798 Set clk81 to 166.6M
355 07:19:07.564198 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 07:19:07.564507 board id: 1
357 07:19:07.570635 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:19:07.581216 fw parse done
359 07:19:07.586620 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:19:07.629049 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:19:07.640799 PIEI prepare done
362 07:19:07.641133 fastboot data load
363 07:19:07.641346 fastboot data verify
364 07:19:07.646318 verify result: 266
365 07:19:07.652086 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 07:19:07.652362 LPDDR4 probe
367 07:19:07.652566 ddr clk to 1584MHz
368 07:19:07.659021 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:19:07.696316
370 07:19:07.696673 dmc_version 0001
371 07:19:07.703432 Check phy result
372 07:19:07.709832 INFO : End of CA training
373 07:19:07.710125 INFO : End of initialization
374 07:19:07.715339 INFO : Training has run successfully!
375 07:19:07.715620 Check phy result
376 07:19:07.721062 INFO : End of initialization
377 07:19:07.721346 INFO : End of read enable training
378 07:19:07.724340 INFO : End of fine write leveling
379 07:19:07.729894 INFO : End of Write leveling coarse delay
380 07:19:07.735518 INFO : Training has run successfully!
381 07:19:07.735799 Check phy result
382 07:19:07.736054 INFO : End of initialization
383 07:19:07.741071 INFO : End of read dq deskew training
384 07:19:07.746717 INFO : End of MPR read delay center optimization
385 07:19:07.746995 INFO : End of write delay center optimization
386 07:19:07.752284 INFO : End of read delay center optimization
387 07:19:07.757874 INFO : End of max read latency training
388 07:19:07.758187 INFO : Training has run successfully!
389 07:19:07.763519 1D training succeed
390 07:19:07.769292 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:19:07.817068 Check phy result
392 07:19:07.817495 INFO : End of initialization
393 07:19:07.838676 INFO : End of 2D read delay Voltage center optimization
394 07:19:07.857680 INFO : End of 2D read delay Voltage center optimization
395 07:19:07.909803 INFO : End of 2D write delay Voltage center optimization
396 07:19:07.959643 INFO : End of 2D write delay Voltage center optimization
397 07:19:07.965119 INFO : Training has run successfully!
398 07:19:07.965401
399 07:19:07.965616 channel==0
400 07:19:07.970736 RxClkDly_Margin_A0==78 ps 8
401 07:19:07.971024 TxDqDly_Margin_A0==88 ps 9
402 07:19:07.976445 RxClkDly_Margin_A1==88 ps 9
403 07:19:07.976725 TxDqDly_Margin_A1==88 ps 9
404 07:19:07.976941 TrainedVREFDQ_A0==74
405 07:19:07.981991 TrainedVREFDQ_A1==75
406 07:19:07.982277 VrefDac_Margin_A0==24
407 07:19:07.982487 DeviceVref_Margin_A0==40
408 07:19:07.987521 VrefDac_Margin_A1==23
409 07:19:07.987799 DeviceVref_Margin_A1==39
410 07:19:07.988033
411 07:19:07.988248
412 07:19:07.988454 channel==1
413 07:19:07.993214 RxClkDly_Margin_A0==78 ps 8
414 07:19:07.993494 TxDqDly_Margin_A0==88 ps 9
415 07:19:07.998773 RxClkDly_Margin_A1==78 ps 8
416 07:19:07.999061 TxDqDly_Margin_A1==88 ps 9
417 07:19:08.004356 TrainedVREFDQ_A0==75
418 07:19:08.004640 TrainedVREFDQ_A1==77
419 07:19:08.004848 VrefDac_Margin_A0==22
420 07:19:08.009959 DeviceVref_Margin_A0==39
421 07:19:08.010240 VrefDac_Margin_A1==22
422 07:19:08.010448 DeviceVref_Margin_A1==37
423 07:19:08.015518
424 07:19:08.015798 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:19:08.016036
426 07:19:08.049101 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
427 07:19:08.049515 2D training succeed
428 07:19:08.054653 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:19:08.060319 auto size-- 65535DDR cs0 size: 2048MB
430 07:19:08.060606 DDR cs1 size: 2048MB
431 07:19:08.065868 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:19:08.066153 cs0 DataBus test pass
433 07:19:08.071432 cs1 DataBus test pass
434 07:19:08.071713 cs0 AddrBus test pass
435 07:19:08.071921 cs1 AddrBus test pass
436 07:19:08.072162
437 07:19:08.077164 100bdlr_step_size ps== 478
438 07:19:08.077457 result report
439 07:19:08.082659 boot times 0Enable ddr reg access
440 07:19:08.086747 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:19:08.101056 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 07:19:08.755886 bl2z: ptr: 05129330, size: 00001e40
443 07:19:08.764190 0.0;M3 CHK:0;cm4_sp_mode 0
444 07:19:08.764504 MVN_1=0x00000000
445 07:19:08.764713 MVN_2=0x00000000
446 07:19:08.775603 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 07:19:08.775919 OPS=0x04
448 07:19:08.776162 ring efuse init
449 07:19:08.781220 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 07:19:08.781494 [0.017319 Inits done]
451 07:19:08.781703 secure task start!
452 07:19:08.787671 high task start!
453 07:19:08.787935 low task start!
454 07:19:08.788165 run into bl31
455 07:19:08.797215 NOTICE: BL31: v1.3(release):4fc40b1
456 07:19:08.804757 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 07:19:08.805051 NOTICE: BL31: G12A normal boot!
458 07:19:08.820515 NOTICE: BL31: BL33 decompress pass
459 07:19:08.826119 ERROR: Error initializing runtime service opteed_fast
460 07:19:11.569693 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 07:19:11.570544 bl2_stage_init 0x01
462 07:19:11.571133 bl2_stage_init 0x81
463 07:19:11.575429 hw id: 0x0000 - pwm id 0x01
464 07:19:11.576183 bl2_stage_init 0xc1
465 07:19:11.576747 bl2_stage_init 0x02
466 07:19:11.577296
467 07:19:11.580928 L0:00000000
468 07:19:11.581617 L1:00000703
469 07:19:11.582147 L2:00008067
470 07:19:11.582656 L3:15000000
471 07:19:11.583196 S1:00000000
472 07:19:11.584106 B2:20282000
473 07:19:11.584650 B1:a0f83180
474 07:19:11.588862
475 07:19:11.589383 TE: 68719
476 07:19:11.589802
477 07:19:11.594425 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 07:19:11.594919
479 07:19:11.595321 Board ID = 1
480 07:19:11.595714 Set cpu clk to 24M
481 07:19:11.600060 Set clk81 to 24M
482 07:19:11.600548 Use GP1_pll as DSU clk.
483 07:19:11.600948 DSU clk: 1200 Mhz
484 07:19:11.605631 CPU clk: 1200 MHz
485 07:19:11.606118 Set clk81 to 166.6M
486 07:19:11.611227 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 07:19:11.611722 board id: 1
488 07:19:11.619911 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 07:19:11.631849 fw parse done
490 07:19:11.637258 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 07:19:11.680932 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 07:19:11.692002 PIEI prepare done
493 07:19:11.692323 fastboot data load
494 07:19:11.692531 fastboot data verify
495 07:19:11.697551 verify result: 266
496 07:19:11.703134 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 07:19:11.703515 LPDDR4 probe
498 07:19:11.703787 ddr clk to 1584MHz
499 07:19:11.710222 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
500 07:19:11.748459
501 07:19:11.749012 dmc_version 0001
502 07:19:11.755148 Check phy result
503 07:19:11.761879 INFO : End of CA training
504 07:19:11.762475 INFO : End of initialization
505 07:19:11.767508 INFO : Training has run successfully!
506 07:19:11.768033 Check phy result
507 07:19:11.773023 INFO : End of initialization
508 07:19:11.773512 INFO : End of read enable training
509 07:19:11.778672 INFO : End of fine write leveling
510 07:19:11.784282 INFO : End of Write leveling coarse delay
511 07:19:11.784786 INFO : Training has run successfully!
512 07:19:11.785251 Check phy result
513 07:19:11.789835 INFO : End of initialization
514 07:19:11.790357 INFO : End of read dq deskew training
515 07:19:11.795513 INFO : End of MPR read delay center optimization
516 07:19:11.801071 INFO : End of write delay center optimization
517 07:19:11.806629 INFO : End of read delay center optimization
518 07:19:11.807123 INFO : End of max read latency training
519 07:19:11.812275 INFO : Training has run successfully!
520 07:19:11.812766 1D training succeed
521 07:19:11.820487 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
522 07:19:11.869431 Check phy result
523 07:19:11.869968 INFO : End of initialization
524 07:19:11.897042 INFO : End of 2D read delay Voltage center optimization
525 07:19:11.920498 INFO : End of 2D read delay Voltage center optimization
526 07:19:11.977094 INFO : End of 2D write delay Voltage center optimization
527 07:19:12.032070 INFO : End of 2D write delay Voltage center optimization
528 07:19:12.037567 INFO : Training has run successfully!
529 07:19:12.038078
530 07:19:12.038543 channel==0
531 07:19:12.043088 RxClkDly_Margin_A0==78 ps 8
532 07:19:12.043579 TxDqDly_Margin_A0==98 ps 10
533 07:19:12.048739 RxClkDly_Margin_A1==69 ps 7
534 07:19:12.049355 TxDqDly_Margin_A1==98 ps 10
535 07:19:12.049834 TrainedVREFDQ_A0==74
536 07:19:12.054356 TrainedVREFDQ_A1==75
537 07:19:12.054921 VrefDac_Margin_A0==23
538 07:19:12.055374 DeviceVref_Margin_A0==40
539 07:19:12.059898 VrefDac_Margin_A1==22
540 07:19:12.060421 DeviceVref_Margin_A1==39
541 07:19:12.060864
542 07:19:12.061305
543 07:19:12.065576 channel==1
544 07:19:12.066054 RxClkDly_Margin_A0==88 ps 9
545 07:19:12.066494 TxDqDly_Margin_A0==98 ps 10
546 07:19:12.071062 RxClkDly_Margin_A1==78 ps 8
547 07:19:12.071535 TxDqDly_Margin_A1==88 ps 9
548 07:19:12.076684 TrainedVREFDQ_A0==78
549 07:19:12.077171 TrainedVREFDQ_A1==78
550 07:19:12.077609 VrefDac_Margin_A0==22
551 07:19:12.082304 DeviceVref_Margin_A0==36
552 07:19:12.082780 VrefDac_Margin_A1==22
553 07:19:12.087879 DeviceVref_Margin_A1==36
554 07:19:12.088382
555 07:19:12.088825 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
556 07:19:12.089262
557 07:19:12.121620 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000060
558 07:19:12.122233 2D training succeed
559 07:19:12.127111 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
560 07:19:12.132689 auto size-- 65535DDR cs0 size: 2048MB
561 07:19:12.133167 DDR cs1 size: 2048MB
562 07:19:12.138365 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
563 07:19:12.138883 cs0 DataBus test pass
564 07:19:12.143867 cs1 DataBus test pass
565 07:19:12.144556 cs0 AddrBus test pass
566 07:19:12.145053 cs1 AddrBus test pass
567 07:19:12.145505
568 07:19:12.149578 100bdlr_step_size ps== 471
569 07:19:12.150087 result report
570 07:19:12.155067 boot times 0Enable ddr reg access
571 07:19:12.160126 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
572 07:19:12.173297 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
573 07:19:12.833003 bl2z: ptr: 05129330, size: 00001e40
574 07:19:12.842219 0.0;M3 CHK:0;cm4_sp_mode 0
575 07:19:12.842831 MVN_1=0x00000000
576 07:19:12.843302 MVN_2=0x00000000
577 07:19:12.854240 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
578 07:19:12.854845 OPS=0x04
579 07:19:12.855327 ring efuse init
580 07:19:12.859283 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
581 07:19:12.859857 [0.017354 Inits done]
582 07:19:12.860370 secure task start!
583 07:19:12.866490 high task start!
584 07:19:12.867052 low task start!
585 07:19:12.868451 run into bl31
586 07:19:12.876786 NOTICE: BL31: v1.3(release):4fc40b1
587 07:19:12.883819 NOTICE: BL31: Built : 15:57:33, May 22 2019
588 07:19:12.884459 NOTICE: BL31: G12A normal boot!
589 07:19:12.898794 NOTICE: BL31: BL33 decompress pass
590 07:19:12.903546 ERROR: Error initializing runtime service opteed_fast
591 07:19:14.273345 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
592 07:19:14.273863 bl2_stage_init 0x01
593 07:19:14.274173 bl2_stage_init 0x81
594 07:19:14.278994 hw id: 0x0000 - pwm id 0x01
595 07:19:14.279343 bl2_stage_init 0xc1
596 07:19:14.284652 bl2_stage_init 0x02
597 07:19:14.285107
598 07:19:14.285514 L0:00000000
599 07:19:14.285801 L1:00000703
600 07:19:14.286080 L2:00008067
601 07:19:14.286347 L3:15000000
602 07:19:14.290207 S1:00000000
603 07:19:14.290498 B2:20282000
604 07:19:14.290719 B1:a0f83180
605 07:19:14.290940
606 07:19:14.291161 TE: 72757
607 07:19:14.291383
608 07:19:14.296149 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
609 07:19:14.296477
610 07:19:14.301488 Board ID = 1
611 07:19:14.301791 Set cpu clk to 24M
612 07:19:14.302017 Set clk81 to 24M
613 07:19:14.305090 Use GP1_pll as DSU clk.
614 07:19:14.305428 DSU clk: 1200 Mhz
615 07:19:14.311073 CPU clk: 1200 MHz
616 07:19:14.311427 Set clk81 to 166.6M
617 07:19:14.316285 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
618 07:19:14.316629 board id: 1
619 07:19:14.325257 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
620 07:19:14.336253 fw parse done
621 07:19:14.342271 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
622 07:19:14.385258 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
623 07:19:14.396568 PIEI prepare done
624 07:19:14.397261 fastboot data load
625 07:19:14.397823 fastboot data verify
626 07:19:14.402153 verify result: 266
627 07:19:14.407729 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
628 07:19:14.408432 LPDDR4 probe
629 07:19:14.408981 ddr clk to 1584MHz
630 07:19:14.415771 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
631 07:19:14.453852
632 07:19:14.454640 dmc_version 0001
633 07:19:14.460643 Check phy result
634 07:19:14.466655 INFO : End of CA training
635 07:19:14.467232 INFO : End of initialization
636 07:19:14.472192 INFO : Training has run successfully!
637 07:19:14.472867 Check phy result
638 07:19:14.477801 INFO : End of initialization
639 07:19:14.478468 INFO : End of read enable training
640 07:19:14.483352 INFO : End of fine write leveling
641 07:19:14.488944 INFO : End of Write leveling coarse delay
642 07:19:14.489578 INFO : Training has run successfully!
643 07:19:14.490138 Check phy result
644 07:19:14.494517 INFO : End of initialization
645 07:19:14.495027 INFO : End of read dq deskew training
646 07:19:14.500115 INFO : End of MPR read delay center optimization
647 07:19:14.505779 INFO : End of write delay center optimization
648 07:19:14.511371 INFO : End of read delay center optimization
649 07:19:14.511913 INFO : End of max read latency training
650 07:19:14.516844 INFO : Training has run successfully!
651 07:19:14.517345 1D training succeed
652 07:19:14.526153 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
653 07:19:14.574335 Check phy result
654 07:19:14.574937 INFO : End of initialization
655 07:19:14.601704 INFO : End of 2D read delay Voltage center optimization
656 07:19:14.625073 INFO : End of 2D read delay Voltage center optimization
657 07:19:14.681873 INFO : End of 2D write delay Voltage center optimization
658 07:19:14.736370 INFO : End of 2D write delay Voltage center optimization
659 07:19:14.741855 INFO : Training has run successfully!
660 07:19:14.742389
661 07:19:14.742855 channel==0
662 07:19:14.747432 RxClkDly_Margin_A0==78 ps 8
663 07:19:14.747976 TxDqDly_Margin_A0==98 ps 10
664 07:19:14.753022 RxClkDly_Margin_A1==78 ps 8
665 07:19:14.753552 TxDqDly_Margin_A1==88 ps 9
666 07:19:14.754011 TrainedVREFDQ_A0==76
667 07:19:14.758615 TrainedVREFDQ_A1==74
668 07:19:14.759142 VrefDac_Margin_A0==23
669 07:19:14.759600 DeviceVref_Margin_A0==38
670 07:19:14.764225 VrefDac_Margin_A1==22
671 07:19:14.764738 DeviceVref_Margin_A1==40
672 07:19:14.765199
673 07:19:14.765658
674 07:19:14.766104 channel==1
675 07:19:14.769826 RxClkDly_Margin_A0==78 ps 8
676 07:19:14.770332 TxDqDly_Margin_A0==98 ps 10
677 07:19:14.775440 RxClkDly_Margin_A1==78 ps 8
678 07:19:14.775964 TxDqDly_Margin_A1==88 ps 9
679 07:19:14.781019 TrainedVREFDQ_A0==78
680 07:19:14.781544 TrainedVREFDQ_A1==78
681 07:19:14.782004 VrefDac_Margin_A0==22
682 07:19:14.786646 DeviceVref_Margin_A0==36
683 07:19:14.787154 VrefDac_Margin_A1==22
684 07:19:14.792268 DeviceVref_Margin_A1==36
685 07:19:14.792782
686 07:19:14.793242 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
687 07:19:14.793692
688 07:19:14.825837 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
689 07:19:14.826416 2D training succeed
690 07:19:14.831430 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
691 07:19:14.837053 auto size-- 65535DDR cs0 size: 2048MB
692 07:19:14.837550 DDR cs1 size: 2048MB
693 07:19:14.842644 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
694 07:19:14.843131 cs0 DataBus test pass
695 07:19:14.848267 cs1 DataBus test pass
696 07:19:14.848758 cs0 AddrBus test pass
697 07:19:14.849208 cs1 AddrBus test pass
698 07:19:14.849645
699 07:19:14.853842 100bdlr_step_size ps== 471
700 07:19:14.854344 result report
701 07:19:14.859427 boot times 0Enable ddr reg access
702 07:19:14.864597 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
703 07:19:14.878442 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
704 07:19:15.537919 bl2z: ptr: 05129330, size: 00001e40
705 07:19:15.546149 0.0;M3 CHK:0;cm4_sp_mode 0
706 07:19:15.546474 MVN_1=0x00000000
707 07:19:15.546685 MVN_2=0x00000000
708 07:19:15.557634 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
709 07:19:15.558193 OPS=0x04
710 07:19:15.558544 ring efuse init
711 07:19:15.563290 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
712 07:19:15.563723 [0.017355 Inits done]
713 07:19:15.563961 secure task start!
714 07:19:15.570532 high task start!
715 07:19:15.570844 low task start!
716 07:19:15.571054 run into bl31
717 07:19:15.579133 NOTICE: BL31: v1.3(release):4fc40b1
718 07:19:15.586939 NOTICE: BL31: Built : 15:57:33, May 22 2019
719 07:19:15.587381 NOTICE: BL31: G12A normal boot!
720 07:19:15.602603 NOTICE: BL31: BL33 decompress pass
721 07:19:15.608274 ERROR: Error initializing runtime service opteed_fast
722 07:19:16.402392
723 07:19:16.402859
724 07:19:16.407810 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
725 07:19:16.408343
726 07:19:16.410397 Model: Libre Computer AML-S905D3-CC Solitude
727 07:19:16.557239 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
728 07:19:16.572651 DRAM: 2 GiB (effective 3.8 GiB)
729 07:19:16.674639 Core: 406 devices, 33 uclasses, devicetree: separate
730 07:19:16.679482 WDT: Not starting watchdog@f0d0
731 07:19:16.705536 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
732 07:19:16.717779 Loading Environment from FAT... Card did not respond to voltage select! : -110
733 07:19:16.721853 ** Bad device specification mmc 0 **
734 07:19:16.732877 Card did not respond to voltage select! : -110
735 07:19:16.739487 ** Bad device specification mmc 0 **
736 07:19:16.740017 Couldn't find partition mmc 0
737 07:19:16.748877 Card did not respond to voltage select! : -110
738 07:19:16.754415 ** Bad device specification mmc 0 **
739 07:19:16.754953 Couldn't find partition mmc 0
740 07:19:16.758381 Error: could not access storage.
741 07:19:17.054784 Net: eth0: ethernet@ff3f0000
742 07:19:17.055191 starting USB...
743 07:19:17.300402 Bus usb@ff500000: Register 3000140 NbrPorts 3
744 07:19:17.301003 Starting the controller
745 07:19:17.306547 USB XHCI 1.10
746 07:19:18.860813 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
747 07:19:18.869177 scanning usb for storage devices... 0 Storage Device(s) found
749 07:19:18.920472 Hit any key to stop autoboot: 1
750 07:19:18.921620 end: 2.4.2 bootloader-interrupt (duration 00:00:20) [common]
751 07:19:18.922017 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
752 07:19:18.922309 Setting prompt string to ['=>']
753 07:19:18.922596 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
754 07:19:18.935158 0
755 07:19:18.935937 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
757 07:19:19.036819 => setenv autoload no
758 07:19:19.037559 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
759 07:19:19.041788 setenv autoload no
761 07:19:19.142911 => setenv initrd_high 0xffffffff
762 07:19:19.143631 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
763 07:19:19.147846 setenv initrd_high 0xffffffff
765 07:19:19.248970 => setenv fdt_high 0xffffffff
766 07:19:19.249883 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
767 07:19:19.254012 setenv fdt_high 0xffffffff
769 07:19:19.355193 => dhcp
770 07:19:19.356013 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
771 07:19:19.360147 dhcp
772 07:19:20.316116 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
773 07:19:20.316533 Speed: 1000, full duplex
774 07:19:20.316755 BOOTP broadcast 1
775 07:19:20.564476 BOOTP broadcast 2
776 07:19:21.065548 BOOTP broadcast 3
777 07:19:22.066499 BOOTP broadcast 4
778 07:19:24.067573 BOOTP broadcast 5
779 07:19:24.079830 DHCP client bound to address 192.168.6.12 (3763 ms)
781 07:19:24.182510 => setenv serverip 192.168.6.2
782 07:19:24.183635 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
783 07:19:24.188191 setenv serverip 192.168.6.2
785 07:19:24.290722 => tftpboot 0x01080000 831780/tftp-deploy-vilhxska/kernel/uImage
786 07:19:24.291926 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
787 07:19:24.298776 tftpboot 0x01080000 831780/tftp-deploy-vilhxska/kernel/uImage
788 07:19:24.299089 Speed: 1000, full duplex
789 07:19:24.299300 Using ethernet@ff3f0000 device
790 07:19:24.304329 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
791 07:19:24.309710 Filename '831780/tftp-deploy-vilhxska/kernel/uImage'.
792 07:19:24.313581 Load address: 0x1080000
793 07:19:28.647751 Loading: *################################################## 43.9 MiB
794 07:19:28.648232 10.1 MiB/s
795 07:19:28.648475 done
796 07:19:28.652230 Bytes transferred = 46066240 (2beea40 hex)
798 07:19:28.753480 => tftpboot 0x08000000 831780/tftp-deploy-vilhxska/ramdisk/ramdisk.cpio.gz.uboot
799 07:19:28.754039 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:30)
800 07:19:28.760842 tftpboot 0x08000000 831780/tftp-deploy-vilhxska/ramdisk/ramdisk.cpio.gz.uboot
801 07:19:28.761172 Speed: 1000, full duplex
802 07:19:28.761406 Using ethernet@ff3f0000 device
803 07:19:28.766364 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
804 07:19:28.776287 Filename '831780/tftp-deploy-vilhxska/ramdisk/ramdisk.cpio.gz.uboot'.
805 07:19:28.776658 Load address: 0x8000000
806 07:19:33.932643 Loading: *################# UDP wrong checksum 00000005 0000b5ff
807 07:19:35.628347 T ################################ UDP wrong checksum 00000005 0000a7f9
808 07:19:40.629583 T UDP wrong checksum 00000005 0000a7f9
809 07:19:50.631351 T T UDP wrong checksum 00000005 0000a7f9
810 07:19:51.188029 UDP wrong checksum 000000ff 0000a4fd
811 07:19:51.195579 UDP wrong checksum 000000ff 0000fd7f
812 07:20:10.635501 T T T T UDP wrong checksum 00000005 0000a7f9
813 07:20:25.639015 T T
814 07:20:25.639446 Retry count exceeded; starting again
816 07:20:25.642509 end: 2.4.3 bootloader-commands (duration 00:01:07) [common]
819 07:20:25.643472 end: 2.4 uboot-commands (duration 00:01:27) [common]
821 07:20:25.644232 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
823 07:20:25.644817 end: 2 uboot-action (duration 00:01:27) [common]
825 07:20:25.645829 Cleaning after the job
826 07:20:25.646166 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/ramdisk
827 07:20:25.647047 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/kernel
828 07:20:25.669373 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/dtb
829 07:20:25.670919 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/nfsrootfs
830 07:20:25.696828 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/831780/tftp-deploy-vilhxska/modules
831 07:20:25.701561 start: 4.1 power-off (timeout 00:00:30) [common]
832 07:20:25.702240 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
833 07:20:25.736052 >> OK - accepted request
834 07:20:25.738240 Returned 0 in 0 seconds
835 07:20:25.839109 end: 4.1 power-off (duration 00:00:00) [common]
837 07:20:25.840177 start: 4.2 read-feedback (timeout 00:10:00) [common]
838 07:20:25.840842 Listened to connection for namespace 'common' for up to 1s
839 07:20:26.841111 Finalising connection for namespace 'common'
840 07:20:26.841818 Disconnecting from shell: Finalise
841 07:20:26.842326 =>
842 07:20:26.943318 end: 4.2 read-feedback (duration 00:00:01) [common]
843 07:20:26.944047 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/831780
844 07:20:29.161887 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/831780
845 07:20:29.162540 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.