Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:28:32.186983 lava-dispatcher, installed at version: 2024.01
2 08:28:32.187800 start: 0 validate
3 08:28:32.188280 Start time: 2024-10-11 08:28:32.188251+00:00 (UTC)
4 08:28:32.188836 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:28:32.189348 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 08:28:32.223203 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:28:32.223844 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241011%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 08:28:32.256012 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:28:32.256696 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241011%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 08:28:33.304893 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:28:33.308290 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241011%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 08:28:33.347759 validate duration: 1.16
14 08:28:33.348665 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:28:33.349004 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:28:33.349297 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:28:33.350031 Not decompressing ramdisk as can be used compressed.
18 08:28:33.350513 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 08:28:33.350777 saving as /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/ramdisk/rootfs.cpio.gz
20 08:28:33.351083 total size: 8181887 (7 MB)
21 08:28:33.386987 progress 0 % (0 MB)
22 08:28:33.394182 progress 5 % (0 MB)
23 08:28:33.400798 progress 10 % (0 MB)
24 08:28:33.408304 progress 15 % (1 MB)
25 08:28:33.414899 progress 20 % (1 MB)
26 08:28:33.421913 progress 25 % (1 MB)
27 08:28:33.428375 progress 30 % (2 MB)
28 08:28:33.435420 progress 35 % (2 MB)
29 08:28:33.441915 progress 40 % (3 MB)
30 08:28:33.449180 progress 45 % (3 MB)
31 08:28:33.455646 progress 50 % (3 MB)
32 08:28:33.462818 progress 55 % (4 MB)
33 08:28:33.469478 progress 60 % (4 MB)
34 08:28:33.476714 progress 65 % (5 MB)
35 08:28:33.483410 progress 70 % (5 MB)
36 08:28:33.490801 progress 75 % (5 MB)
37 08:28:33.497693 progress 80 % (6 MB)
38 08:28:33.504906 progress 85 % (6 MB)
39 08:28:33.511413 progress 90 % (7 MB)
40 08:28:33.518535 progress 95 % (7 MB)
41 08:28:33.524569 progress 100 % (7 MB)
42 08:28:33.525402 7 MB downloaded in 0.17 s (44.77 MB/s)
43 08:28:33.526106 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:28:33.527230 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:28:33.527607 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:28:33.527954 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:28:33.528599 downloading http://storage.kernelci.org/next/master/next-20241011/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
49 08:28:33.528913 saving as /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/kernel/Image
50 08:28:33.529185 total size: 46066176 (43 MB)
51 08:28:33.529453 No compression specified
52 08:28:33.564976 progress 0 % (0 MB)
53 08:28:33.599413 progress 5 % (2 MB)
54 08:28:33.634751 progress 10 % (4 MB)
55 08:28:33.668997 progress 15 % (6 MB)
56 08:28:33.704160 progress 20 % (8 MB)
57 08:28:33.738458 progress 25 % (11 MB)
58 08:28:33.772788 progress 30 % (13 MB)
59 08:28:33.806556 progress 35 % (15 MB)
60 08:28:33.840609 progress 40 % (17 MB)
61 08:28:33.875431 progress 45 % (19 MB)
62 08:28:33.909598 progress 50 % (21 MB)
63 08:28:33.944108 progress 55 % (24 MB)
64 08:28:33.977821 progress 60 % (26 MB)
65 08:28:34.011961 progress 65 % (28 MB)
66 08:28:34.046253 progress 70 % (30 MB)
67 08:28:34.080526 progress 75 % (32 MB)
68 08:28:34.114672 progress 80 % (35 MB)
69 08:28:34.148620 progress 85 % (37 MB)
70 08:28:34.182609 progress 90 % (39 MB)
71 08:28:34.215838 progress 95 % (41 MB)
72 08:28:34.248921 progress 100 % (43 MB)
73 08:28:34.249865 43 MB downloaded in 0.72 s (60.96 MB/s)
74 08:28:34.250480 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:28:34.251504 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:28:34.251872 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:28:34.252252 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:28:34.252861 downloading http://storage.kernelci.org/next/master/next-20241011/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 08:28:34.253213 saving as /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 08:28:34.253475 total size: 53209 (0 MB)
82 08:28:34.253735 No compression specified
83 08:28:34.293484 progress 61 % (0 MB)
84 08:28:34.294376 progress 100 % (0 MB)
85 08:28:34.294965 0 MB downloaded in 0.04 s (1.22 MB/s)
86 08:28:34.295498 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:28:34.296464 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:28:34.296774 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:28:34.297073 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:28:34.297588 downloading http://storage.kernelci.org/next/master/next-20241011/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
92 08:28:34.297873 saving as /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/modules/modules.tar
93 08:28:34.298102 total size: 11606984 (11 MB)
94 08:28:34.298341 Using unxz to decompress xz
95 08:28:34.333931 progress 0 % (0 MB)
96 08:28:34.405947 progress 5 % (0 MB)
97 08:28:34.483496 progress 10 % (1 MB)
98 08:28:34.571648 progress 15 % (1 MB)
99 08:28:34.650366 progress 20 % (2 MB)
100 08:28:34.728044 progress 25 % (2 MB)
101 08:28:34.808476 progress 30 % (3 MB)
102 08:28:34.881768 progress 35 % (3 MB)
103 08:28:34.963556 progress 40 % (4 MB)
104 08:28:35.049947 progress 45 % (5 MB)
105 08:28:35.132176 progress 50 % (5 MB)
106 08:28:35.211582 progress 55 % (6 MB)
107 08:28:35.293069 progress 60 % (6 MB)
108 08:28:35.378844 progress 65 % (7 MB)
109 08:28:35.458086 progress 70 % (7 MB)
110 08:28:35.540046 progress 75 % (8 MB)
111 08:28:35.623769 progress 80 % (8 MB)
112 08:28:35.704527 progress 85 % (9 MB)
113 08:28:35.773876 progress 90 % (9 MB)
114 08:28:35.873164 progress 95 % (10 MB)
115 08:28:35.988218 progress 100 % (11 MB)
116 08:28:35.999905 11 MB downloaded in 1.70 s (6.50 MB/s)
117 08:28:36.000984 end: 1.4.1 http-download (duration 00:00:02) [common]
119 08:28:36.002755 end: 1.4 download-retry (duration 00:00:02) [common]
120 08:28:36.003330 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 08:28:36.003898 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 08:28:36.004476 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:28:36.005028 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 08:28:36.006079 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga
125 08:28:36.007001 makedir: /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin
126 08:28:36.007700 makedir: /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/tests
127 08:28:36.008439 makedir: /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/results
128 08:28:36.009114 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-add-keys
129 08:28:36.010146 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-add-sources
130 08:28:36.011184 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-background-process-start
131 08:28:36.012308 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-background-process-stop
132 08:28:36.013459 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-common-functions
133 08:28:36.014481 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-echo-ipv4
134 08:28:36.015608 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-install-packages
135 08:28:36.016714 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-installed-packages
136 08:28:36.017711 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-os-build
137 08:28:36.018710 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-probe-channel
138 08:28:36.019728 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-probe-ip
139 08:28:36.021020 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-target-ip
140 08:28:36.022169 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-target-mac
141 08:28:36.023169 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-target-storage
142 08:28:36.024210 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-test-case
143 08:28:36.025262 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-test-event
144 08:28:36.026258 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-test-feedback
145 08:28:36.027239 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-test-raise
146 08:28:36.028443 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-test-reference
147 08:28:36.029503 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-test-runner
148 08:28:36.030539 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-test-set
149 08:28:36.031512 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-test-shell
150 08:28:36.032608 Updating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-install-packages (oe)
151 08:28:36.033675 Updating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/bin/lava-installed-packages (oe)
152 08:28:36.034532 Creating /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/environment
153 08:28:36.035260 LAVA metadata
154 08:28:36.035739 - LAVA_JOB_ID=838544
155 08:28:36.036203 - LAVA_DISPATCHER_IP=192.168.6.2
156 08:28:36.036889 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 08:28:36.038776 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 08:28:36.039371 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 08:28:36.039777 skipped lava-vland-overlay
160 08:28:36.040216 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 08:28:36.040483 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 08:28:36.040707 skipped lava-multinode-overlay
163 08:28:36.040955 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 08:28:36.041225 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 08:28:36.041486 Loading test definitions
166 08:28:36.041772 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 08:28:36.041998 Using /lava-838544 at stage 0
168 08:28:36.043229 uuid=838544_1.5.2.4.1 testdef=None
169 08:28:36.043544 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 08:28:36.043812 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 08:28:36.045697 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 08:28:36.046512 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 08:28:36.048882 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 08:28:36.049726 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 08:28:36.051973 runner path: /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/0/tests/0_dmesg test_uuid 838544_1.5.2.4.1
178 08:28:36.052609 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 08:28:36.053386 Creating lava-test-runner.conf files
181 08:28:36.053590 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/838544/lava-overlay-h_q3fyga/lava-838544/0 for stage 0
182 08:28:36.053943 - 0_dmesg
183 08:28:36.054304 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 08:28:36.054595 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 08:28:36.079173 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 08:28:36.079625 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 08:28:36.079892 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 08:28:36.080192 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 08:28:36.080461 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 08:28:37.059124 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 08:28:37.059853 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 08:28:37.060371 extracting modules file /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/838544/extract-overlay-ramdisk-2iryd26r/ramdisk
193 08:28:38.499171 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 08:28:38.499655 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 08:28:38.499931 [common] Applying overlay /var/lib/lava/dispatcher/tmp/838544/compress-overlay-3rvf3st3/overlay-1.5.2.5.tar.gz to ramdisk
196 08:28:38.500178 [common] Applying overlay /var/lib/lava/dispatcher/tmp/838544/compress-overlay-3rvf3st3/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/838544/extract-overlay-ramdisk-2iryd26r/ramdisk
197 08:28:38.531582 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 08:28:38.532065 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 08:28:38.532342 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 08:28:38.532574 Converting downloaded kernel to a uImage
201 08:28:38.532882 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/kernel/Image /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/kernel/uImage
202 08:28:38.997964 output: Image Name:
203 08:28:38.998369 output: Created: Fri Oct 11 08:28:38 2024
204 08:28:38.998581 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 08:28:38.998787 output: Data Size: 46066176 Bytes = 44986.50 KiB = 43.93 MiB
206 08:28:38.998985 output: Load Address: 01080000
207 08:28:38.999183 output: Entry Point: 01080000
208 08:28:38.999380 output:
209 08:28:38.999711 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 08:28:38.999976 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 08:28:39.000289 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 08:28:39.000542 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 08:28:39.000798 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 08:28:39.001056 Building ramdisk /var/lib/lava/dispatcher/tmp/838544/extract-overlay-ramdisk-2iryd26r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/838544/extract-overlay-ramdisk-2iryd26r/ramdisk
215 08:28:41.829338 >> 181857 blocks
216 08:28:50.994419 Adding RAMdisk u-boot header.
217 08:28:50.994879 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/838544/extract-overlay-ramdisk-2iryd26r/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/838544/extract-overlay-ramdisk-2iryd26r/ramdisk.cpio.gz.uboot
218 08:28:51.281138 output: Image Name:
219 08:28:51.281536 output: Created: Fri Oct 11 08:28:50 2024
220 08:28:51.281744 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 08:28:51.281946 output: Data Size: 26063347 Bytes = 25452.49 KiB = 24.86 MiB
222 08:28:51.282145 output: Load Address: 00000000
223 08:28:51.282340 output: Entry Point: 00000000
224 08:28:51.282532 output:
225 08:28:51.283156 rename /var/lib/lava/dispatcher/tmp/838544/extract-overlay-ramdisk-2iryd26r/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/ramdisk/ramdisk.cpio.gz.uboot
226 08:28:51.283564 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 08:28:51.283846 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 08:28:51.284341 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
229 08:28:51.284845 No LXC device requested
230 08:28:51.285391 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 08:28:51.285943 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
232 08:28:51.286479 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 08:28:51.286928 Checking files for TFTP limit of 4294967296 bytes.
234 08:28:51.289874 end: 1 tftp-deploy (duration 00:00:18) [common]
235 08:28:51.290493 start: 2 uboot-action (timeout 00:05:00) [common]
236 08:28:51.291069 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 08:28:51.291614 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 08:28:51.292192 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 08:28:51.292770 Using kernel file from prepare-kernel: 838544/tftp-deploy-0m30b30y/kernel/uImage
240 08:28:51.293428 substitutions:
241 08:28:51.293872 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 08:28:51.294312 - {DTB_ADDR}: 0x01070000
243 08:28:51.294747 - {DTB}: 838544/tftp-deploy-0m30b30y/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 08:28:51.295180 - {INITRD}: 838544/tftp-deploy-0m30b30y/ramdisk/ramdisk.cpio.gz.uboot
245 08:28:51.295615 - {KERNEL_ADDR}: 0x01080000
246 08:28:51.296076 - {KERNEL}: 838544/tftp-deploy-0m30b30y/kernel/uImage
247 08:28:51.296512 - {LAVA_MAC}: None
248 08:28:51.296984 - {PRESEED_CONFIG}: None
249 08:28:51.297417 - {PRESEED_LOCAL}: None
250 08:28:51.297844 - {RAMDISK_ADDR}: 0x08000000
251 08:28:51.298267 - {RAMDISK}: 838544/tftp-deploy-0m30b30y/ramdisk/ramdisk.cpio.gz.uboot
252 08:28:51.298698 - {ROOT_PART}: None
253 08:28:51.299126 - {ROOT}: None
254 08:28:51.299552 - {SERVER_IP}: 192.168.6.2
255 08:28:51.299999 - {TEE_ADDR}: 0x83000000
256 08:28:51.300433 - {TEE}: None
257 08:28:51.300861 Parsed boot commands:
258 08:28:51.301274 - setenv autoload no
259 08:28:51.301698 - setenv initrd_high 0xffffffff
260 08:28:51.302123 - setenv fdt_high 0xffffffff
261 08:28:51.302542 - dhcp
262 08:28:51.302963 - setenv serverip 192.168.6.2
263 08:28:51.303386 - tftpboot 0x01080000 838544/tftp-deploy-0m30b30y/kernel/uImage
264 08:28:51.303838 - tftpboot 0x08000000 838544/tftp-deploy-0m30b30y/ramdisk/ramdisk.cpio.gz.uboot
265 08:28:51.304428 - tftpboot 0x01070000 838544/tftp-deploy-0m30b30y/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 08:28:51.304978 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 08:28:51.305476 - bootm 0x01080000 0x08000000 0x01070000
268 08:28:51.306152 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 08:28:51.307942 start: 2.3 connect-device (timeout 00:05:00) [common]
271 08:28:51.308480 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 08:28:51.324442 Setting prompt string to ['lava-test: # ']
273 08:28:51.326071 end: 2.3 connect-device (duration 00:00:00) [common]
274 08:28:51.326711 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 08:28:51.327312 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 08:28:51.327895 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 08:28:51.329162 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 08:28:51.364536 >> OK - accepted request
279 08:28:51.366635 Returned 0 in 0 seconds
280 08:28:51.467834 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 08:28:51.469664 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 08:28:51.470270 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 08:28:51.470821 Setting prompt string to ['Hit any key to stop autoboot']
285 08:28:51.471305 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 08:28:51.473030 Trying 192.168.56.21...
287 08:28:51.473556 Connected to conserv1.
288 08:28:51.474013 Escape character is '^]'.
289 08:28:51.474474
290 08:28:51.474935 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 08:28:51.475416
292 08:28:58.651904 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 08:28:58.652387 bl2_stage_init 0x01
294 08:28:58.652636 bl2_stage_init 0x81
295 08:28:58.659930 hw id: 0x0000 - pwm id 0x01
296 08:28:58.660324 bl2_stage_init 0xc1
297 08:28:58.662875 bl2_stage_init 0x02
298 08:28:58.663180
299 08:28:58.663402 L0:00000000
300 08:28:58.663612 L1:00000703
301 08:28:58.663830 L2:00008067
302 08:28:58.664062 L3:15000000
303 08:28:58.668678 S1:00000000
304 08:28:58.668998 B2:20282000
305 08:28:58.669213 B1:a0f83180
306 08:28:58.669422
307 08:28:58.669632 TE: 67544
308 08:28:58.669837
309 08:28:58.674085 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 08:28:58.674373
311 08:28:58.679671 Board ID = 1
312 08:28:58.679969 Set cpu clk to 24M
313 08:28:58.680211 Set clk81 to 24M
314 08:28:58.685242 Use GP1_pll as DSU clk.
315 08:28:58.685544 DSU clk: 1200 Mhz
316 08:28:58.685761 CPU clk: 1200 MHz
317 08:28:58.690833 Set clk81 to 166.6M
318 08:28:58.696463 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 08:28:58.696787 board id: 1
320 08:28:58.703199 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 08:28:58.714344 fw parse done
322 08:28:58.720035 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 08:28:58.762409 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 08:28:58.773999 PIEI prepare done
325 08:28:58.774380 fastboot data load
326 08:28:58.774601 fastboot data verify
327 08:28:58.779558 verify result: 266
328 08:28:58.785182 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 08:28:58.785521 LPDDR4 probe
330 08:28:58.785763 ddr clk to 1584MHz
331 08:28:58.793495 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 08:28:58.830541
333 08:28:58.831213 dmc_version 0001
334 08:28:58.836189 Check phy result
335 08:28:58.843009 INFO : End of CA training
336 08:28:58.843535 INFO : End of initialization
337 08:28:58.849762 INFO : Training has run successfully!
338 08:28:58.850251 Check phy result
339 08:28:58.854193 INFO : End of initialization
340 08:28:58.854712 INFO : End of read enable training
341 08:28:58.859736 INFO : End of fine write leveling
342 08:28:58.865381 INFO : End of Write leveling coarse delay
343 08:28:58.865999 INFO : Training has run successfully!
344 08:28:58.866476 Check phy result
345 08:28:58.871056 INFO : End of initialization
346 08:28:58.871595 INFO : End of read dq deskew training
347 08:28:58.876605 INFO : End of MPR read delay center optimization
348 08:28:58.882135 INFO : End of write delay center optimization
349 08:28:58.887778 INFO : End of read delay center optimization
350 08:28:58.888310 INFO : End of max read latency training
351 08:28:58.893389 INFO : Training has run successfully!
352 08:28:58.893894 1D training succeed
353 08:28:58.902295 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 08:28:58.951073 Check phy result
355 08:28:58.951666 INFO : End of initialization
356 08:28:58.972722 INFO : End of 2D read delay Voltage center optimization
357 08:28:58.991774 INFO : End of 2D read delay Voltage center optimization
358 08:28:59.043359 INFO : End of 2D write delay Voltage center optimization
359 08:28:59.092928 INFO : End of 2D write delay Voltage center optimization
360 08:28:59.098490 INFO : Training has run successfully!
361 08:28:59.099016
362 08:28:59.099477 channel==0
363 08:28:59.104140 RxClkDly_Margin_A0==88 ps 9
364 08:28:59.104646 TxDqDly_Margin_A0==98 ps 10
365 08:28:59.107348 RxClkDly_Margin_A1==88 ps 9
366 08:28:59.107831 TxDqDly_Margin_A1==98 ps 10
367 08:28:59.112982 TrainedVREFDQ_A0==74
368 08:28:59.113509 TrainedVREFDQ_A1==74
369 08:28:59.118474 VrefDac_Margin_A0==24
370 08:28:59.118974 DeviceVref_Margin_A0==40
371 08:28:59.119425 VrefDac_Margin_A1==23
372 08:28:59.124086 DeviceVref_Margin_A1==40
373 08:28:59.124590
374 08:28:59.125042
375 08:28:59.125489 channel==1
376 08:28:59.125928 RxClkDly_Margin_A0==88 ps 9
377 08:28:59.127503 TxDqDly_Margin_A0==88 ps 9
378 08:28:59.133138 RxClkDly_Margin_A1==88 ps 9
379 08:28:59.133657 TxDqDly_Margin_A1==78 ps 8
380 08:28:59.134117 TrainedVREFDQ_A0==77
381 08:28:59.138682 TrainedVREFDQ_A1==75
382 08:28:59.139183 VrefDac_Margin_A0==22
383 08:28:59.144321 DeviceVref_Margin_A0==37
384 08:28:59.144834 VrefDac_Margin_A1==22
385 08:28:59.145299 DeviceVref_Margin_A1==39
386 08:28:59.145747
387 08:28:59.149825 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 08:28:59.150325
389 08:28:59.183466 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000016 00000018 00000016 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 08:28:59.183974 2D training succeed
391 08:28:59.189236 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 08:28:59.194572 auto size-- 65535DDR cs0 size: 2048MB
393 08:28:59.194974 DDR cs1 size: 2048MB
394 08:28:59.200275 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 08:28:59.200666 cs0 DataBus test pass
396 08:28:59.200941 cs1 DataBus test pass
397 08:28:59.205764 cs0 AddrBus test pass
398 08:28:59.206148 cs1 AddrBus test pass
399 08:28:59.206399
400 08:28:59.211363 100bdlr_step_size ps== 464
401 08:28:59.211769 result report
402 08:28:59.212058 boot times 0Enable ddr reg access
403 08:28:59.220274 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 08:28:59.233901 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 08:28:59.889175 bl2z: ptr: 05129330, size: 00001e40
406 08:28:59.896492 0.0;M3 CHK:0;cm4_sp_mode 0
407 08:28:59.896938 MVN_1=0x00000000
408 08:28:59.897184 MVN_2=0x00000000
409 08:28:59.908717 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 08:28:59.909426 OPS=0x04
411 08:28:59.909753 ring efuse init
412 08:28:59.911051 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 08:28:59.916878 [0.017319 Inits done]
414 08:28:59.917370 secure task start!
415 08:28:59.917631 high task start!
416 08:28:59.918016 low task start!
417 08:28:59.920805 run into bl31
418 08:28:59.929762 NOTICE: BL31: v1.3(release):4fc40b1
419 08:28:59.936675 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 08:28:59.937185 NOTICE: BL31: G12A normal boot!
421 08:28:59.953139 NOTICE: BL31: BL33 decompress pass
422 08:28:59.957689 ERROR: Error initializing runtime service opteed_fast
423 08:29:02.703441 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 08:29:02.704150 bl2_stage_init 0x01
425 08:29:02.704633 bl2_stage_init 0x81
426 08:29:02.709052 hw id: 0x0000 - pwm id 0x01
427 08:29:02.709571 bl2_stage_init 0xc1
428 08:29:02.714608 bl2_stage_init 0x02
429 08:29:02.715158
430 08:29:02.715601 L0:00000000
431 08:29:02.716067 L1:00000703
432 08:29:02.716502 L2:00008067
433 08:29:02.716928 L3:15000000
434 08:29:02.720166 S1:00000000
435 08:29:02.720630 B2:20282000
436 08:29:02.721064 B1:a0f83180
437 08:29:02.721489
438 08:29:02.721917 TE: 69408
439 08:29:02.722343
440 08:29:02.725786 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 08:29:02.726250
442 08:29:02.731386 Board ID = 1
443 08:29:02.731846 Set cpu clk to 24M
444 08:29:02.732312 Set clk81 to 24M
445 08:29:02.737015 Use GP1_pll as DSU clk.
446 08:29:02.737493 DSU clk: 1200 Mhz
447 08:29:02.737922 CPU clk: 1200 MHz
448 08:29:02.742561 Set clk81 to 166.6M
449 08:29:02.748161 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 08:29:02.748623 board id: 1
451 08:29:02.754518 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 08:29:02.766020 fw parse done
453 08:29:02.771106 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 08:29:02.813713 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 08:29:02.825623 PIEI prepare done
456 08:29:02.826128 fastboot data load
457 08:29:02.826566 fastboot data verify
458 08:29:02.831218 verify result: 266
459 08:29:02.836776 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 08:29:02.837245 LPDDR4 probe
461 08:29:02.837671 ddr clk to 1584MHz
462 08:29:02.843855 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 08:29:02.881063
464 08:29:02.881574 dmc_version 0001
465 08:29:02.888696 Check phy result
466 08:29:02.894638 INFO : End of CA training
467 08:29:02.895163 INFO : End of initialization
468 08:29:02.900237 INFO : Training has run successfully!
469 08:29:02.900731 Check phy result
470 08:29:02.905759 INFO : End of initialization
471 08:29:02.906236 INFO : End of read enable training
472 08:29:02.911475 INFO : End of fine write leveling
473 08:29:02.916980 INFO : End of Write leveling coarse delay
474 08:29:02.917460 INFO : Training has run successfully!
475 08:29:02.917909 Check phy result
476 08:29:02.922578 INFO : End of initialization
477 08:29:02.923059 INFO : End of read dq deskew training
478 08:29:02.928162 INFO : End of MPR read delay center optimization
479 08:29:02.933770 INFO : End of write delay center optimization
480 08:29:02.939401 INFO : End of read delay center optimization
481 08:29:02.939871 INFO : End of max read latency training
482 08:29:02.944966 INFO : Training has run successfully!
483 08:29:02.945458 1D training succeed
484 08:29:02.953271 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 08:29:03.001490 Check phy result
486 08:29:03.002066 INFO : End of initialization
487 08:29:03.023336 INFO : End of 2D read delay Voltage center optimization
488 08:29:03.042559 INFO : End of 2D read delay Voltage center optimization
489 08:29:03.094312 INFO : End of 2D write delay Voltage center optimization
490 08:29:03.144442 INFO : End of 2D write delay Voltage center optimization
491 08:29:03.149870 INFO : Training has run successfully!
492 08:29:03.150182
493 08:29:03.150395 channel==0
494 08:29:03.155492 RxClkDly_Margin_A0==78 ps 8
495 08:29:03.155785 TxDqDly_Margin_A0==98 ps 10
496 08:29:03.161085 RxClkDly_Margin_A1==88 ps 9
497 08:29:03.161416 TxDqDly_Margin_A1==98 ps 10
498 08:29:03.161633 TrainedVREFDQ_A0==76
499 08:29:03.166678 TrainedVREFDQ_A1==74
500 08:29:03.167124 VrefDac_Margin_A0==23
501 08:29:03.167464 DeviceVref_Margin_A0==38
502 08:29:03.172299 VrefDac_Margin_A1==23
503 08:29:03.172719 DeviceVref_Margin_A1==40
504 08:29:03.172965
505 08:29:03.173173
506 08:29:03.177907 channel==1
507 08:29:03.178310 RxClkDly_Margin_A0==78 ps 8
508 08:29:03.178636 TxDqDly_Margin_A0==78 ps 8
509 08:29:03.183784 RxClkDly_Margin_A1==88 ps 9
510 08:29:03.184426 TxDqDly_Margin_A1==88 ps 9
511 08:29:03.189138 TrainedVREFDQ_A0==75
512 08:29:03.189461 TrainedVREFDQ_A1==75
513 08:29:03.189712 VrefDac_Margin_A0==22
514 08:29:03.194727 DeviceVref_Margin_A0==39
515 08:29:03.195195 VrefDac_Margin_A1==21
516 08:29:03.200345 DeviceVref_Margin_A1==38
517 08:29:03.200986
518 08:29:03.201492 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 08:29:03.201788
520 08:29:03.233912 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000015 00000018 00000016 00000018 00000017 00000017 00000018 00000018 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000061
521 08:29:03.234836 2D training succeed
522 08:29:03.239482 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 08:29:03.245106 auto size-- 65535DDR cs0 size: 2048MB
524 08:29:03.245700 DDR cs1 size: 2048MB
525 08:29:03.250730 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 08:29:03.251240 cs0 DataBus test pass
527 08:29:03.256321 cs1 DataBus test pass
528 08:29:03.256835 cs0 AddrBus test pass
529 08:29:03.257295 cs1 AddrBus test pass
530 08:29:03.257746
531 08:29:03.261899 100bdlr_step_size ps== 478
532 08:29:03.262426 result report
533 08:29:03.267540 boot times 0Enable ddr reg access
534 08:29:03.272014 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 08:29:03.285590 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 08:29:03.942192 bl2z: ptr: 05129330, size: 00001e40
537 08:29:03.950039 0.0;M3 CHK:0;cm4_sp_mode 0
538 08:29:03.950906 MVN_1=0x00000000
539 08:29:03.951187 MVN_2=0x00000000
540 08:29:03.962222 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 08:29:03.962819 OPS=0x04
542 08:29:03.963285 ring efuse init
543 08:29:03.964539 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 08:29:03.970628 [0.017310 Inits done]
545 08:29:03.971217 secure task start!
546 08:29:03.971687 high task start!
547 08:29:03.972176 low task start!
548 08:29:03.974736 run into bl31
549 08:29:03.983311 NOTICE: BL31: v1.3(release):4fc40b1
550 08:29:03.990521 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 08:29:03.991153 NOTICE: BL31: G12A normal boot!
552 08:29:04.006713 NOTICE: BL31: BL33 decompress pass
553 08:29:04.011447 ERROR: Error initializing runtime service opteed_fast
554 08:29:05.402357 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 08:29:05.403011 bl2_stage_init 0x01
556 08:29:05.403481 bl2_stage_init 0x81
557 08:29:05.408114 hw id: 0x0000 - pwm id 0x01
558 08:29:05.408612 bl2_stage_init 0xc1
559 08:29:05.413496 bl2_stage_init 0x02
560 08:29:05.413979
561 08:29:05.414434 L0:00000000
562 08:29:05.414881 L1:00000703
563 08:29:05.415325 L2:00008067
564 08:29:05.415766 L3:15000000
565 08:29:05.418980 S1:00000000
566 08:29:05.419471 B2:20282000
567 08:29:05.419919 B1:a0f83180
568 08:29:05.420401
569 08:29:05.420847 TE: 67896
570 08:29:05.421286
571 08:29:05.424642 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 08:29:05.425133
573 08:29:05.430220 Board ID = 1
574 08:29:05.430702 Set cpu clk to 24M
575 08:29:05.431148 Set clk81 to 24M
576 08:29:05.435921 Use GP1_pll as DSU clk.
577 08:29:05.436438 DSU clk: 1200 Mhz
578 08:29:05.436886 CPU clk: 1200 MHz
579 08:29:05.441435 Set clk81 to 166.6M
580 08:29:05.447066 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 08:29:05.447553 board id: 1
582 08:29:05.453744 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 08:29:05.464890 fw parse done
584 08:29:05.470853 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 08:29:05.512822 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 08:29:05.524444 PIEI prepare done
587 08:29:05.524946 fastboot data load
588 08:29:05.525409 fastboot data verify
589 08:29:05.529975 verify result: 266
590 08:29:05.535616 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 08:29:05.536163 LPDDR4 probe
592 08:29:05.536620 ddr clk to 1584MHz
593 08:29:05.543282 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 08:29:05.579955
595 08:29:05.580531 dmc_version 0001
596 08:29:05.586978 Check phy result
597 08:29:05.593504 INFO : End of CA training
598 08:29:05.593972 INFO : End of initialization
599 08:29:05.599079 INFO : Training has run successfully!
600 08:29:05.599551 Check phy result
601 08:29:05.604695 INFO : End of initialization
602 08:29:05.605163 INFO : End of read enable training
603 08:29:05.610520 INFO : End of fine write leveling
604 08:29:05.615949 INFO : End of Write leveling coarse delay
605 08:29:05.616433 INFO : Training has run successfully!
606 08:29:05.616851 Check phy result
607 08:29:05.621491 INFO : End of initialization
608 08:29:05.621955 INFO : End of read dq deskew training
609 08:29:05.627052 INFO : End of MPR read delay center optimization
610 08:29:05.632703 INFO : End of write delay center optimization
611 08:29:05.638279 INFO : End of read delay center optimization
612 08:29:05.638744 INFO : End of max read latency training
613 08:29:05.643935 INFO : Training has run successfully!
614 08:29:05.644439 1D training succeed
615 08:29:05.652042 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 08:29:05.699961 Check phy result
617 08:29:05.700499 INFO : End of initialization
618 08:29:05.722610 INFO : End of 2D read delay Voltage center optimization
619 08:29:05.741191 INFO : End of 2D read delay Voltage center optimization
620 08:29:05.794170 INFO : End of 2D write delay Voltage center optimization
621 08:29:05.843170 INFO : End of 2D write delay Voltage center optimization
622 08:29:05.848719 INFO : Training has run successfully!
623 08:29:05.849274
624 08:29:05.849740 channel==0
625 08:29:05.854410 RxClkDly_Margin_A0==88 ps 9
626 08:29:05.854954 TxDqDly_Margin_A0==98 ps 10
627 08:29:05.859938 RxClkDly_Margin_A1==88 ps 9
628 08:29:05.860494 TxDqDly_Margin_A1==98 ps 10
629 08:29:05.860942 TrainedVREFDQ_A0==74
630 08:29:05.865558 TrainedVREFDQ_A1==74
631 08:29:05.866087 VrefDac_Margin_A0==24
632 08:29:05.866511 DeviceVref_Margin_A0==40
633 08:29:05.871095 VrefDac_Margin_A1==23
634 08:29:05.871609 DeviceVref_Margin_A1==40
635 08:29:05.872065
636 08:29:05.872370
637 08:29:05.876694 channel==1
638 08:29:05.877224 RxClkDly_Margin_A0==88 ps 9
639 08:29:05.877625 TxDqDly_Margin_A0==88 ps 9
640 08:29:05.882260 RxClkDly_Margin_A1==78 ps 8
641 08:29:05.882696 TxDqDly_Margin_A1==88 ps 9
642 08:29:05.887908 TrainedVREFDQ_A0==75
643 08:29:05.888437 TrainedVREFDQ_A1==75
644 08:29:05.888844 VrefDac_Margin_A0==22
645 08:29:05.893523 DeviceVref_Margin_A0==38
646 08:29:05.893965 VrefDac_Margin_A1==22
647 08:29:05.899098 DeviceVref_Margin_A1==38
648 08:29:05.899529
649 08:29:05.899924 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 08:29:05.900348
651 08:29:05.933149 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000016 00000018 00000016 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 08:29:05.933660 2D training succeed
653 08:29:05.939192 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 08:29:05.943924 auto size-- 65535DDR cs0 size: 2048MB
655 08:29:05.944457 DDR cs1 size: 2048MB
656 08:29:05.949553 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 08:29:05.950029 cs0 DataBus test pass
658 08:29:05.955110 cs1 DataBus test pass
659 08:29:05.955596 cs0 AddrBus test pass
660 08:29:05.956046 cs1 AddrBus test pass
661 08:29:05.956463
662 08:29:05.960683 100bdlr_step_size ps== 478
663 08:29:05.961163 result report
664 08:29:05.966329 boot times 0Enable ddr reg access
665 08:29:05.970903 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 08:29:05.984886 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 08:29:06.640202 bl2z: ptr: 05129330, size: 00001e40
668 08:29:06.646981 0.0;M3 CHK:0;cm4_sp_mode 0
669 08:29:06.647404 MVN_1=0x00000000
670 08:29:06.647659 MVN_2=0x00000000
671 08:29:06.658490 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 08:29:06.658927 OPS=0x04
673 08:29:06.659197 ring efuse init
674 08:29:06.661471 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 08:29:06.666996 [0.017319 Inits done]
676 08:29:06.667295 secure task start!
677 08:29:06.667528 high task start!
678 08:29:06.667739 low task start!
679 08:29:06.671321 run into bl31
680 08:29:06.679944 NOTICE: BL31: v1.3(release):4fc40b1
681 08:29:06.687753 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 08:29:06.688084 NOTICE: BL31: G12A normal boot!
683 08:29:06.703419 NOTICE: BL31: BL33 decompress pass
684 08:29:06.709033 ERROR: Error initializing runtime service opteed_fast
685 08:29:07.504515
686 08:29:07.504909
687 08:29:07.509952 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 08:29:07.510252
689 08:29:07.513334 Model: Libre Computer AML-S905D3-CC Solitude
690 08:29:07.661587 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 08:29:07.675749 DRAM: 2 GiB (effective 3.8 GiB)
692 08:29:07.776715 Core: 406 devices, 33 uclasses, devicetree: separate
693 08:29:07.782439 WDT: Not starting watchdog@f0d0
694 08:29:07.807679 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 08:29:07.820025 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 08:29:07.824847 ** Bad device specification mmc 0 **
697 08:29:07.835013 Card did not respond to voltage select! : -110
698 08:29:07.841747 ** Bad device specification mmc 0 **
699 08:29:07.842055 Couldn't find partition mmc 0
700 08:29:07.850992 Card did not respond to voltage select! : -110
701 08:29:07.856415 ** Bad device specification mmc 0 **
702 08:29:07.856720 Couldn't find partition mmc 0
703 08:29:07.861501 Error: could not access storage.
704 08:29:08.159116 Net: eth0: ethernet@ff3f0000
705 08:29:08.159779 starting USB...
706 08:29:08.403675 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 08:29:08.404396 Starting the controller
708 08:29:08.410619 USB XHCI 1.10
709 08:29:09.965135 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 08:29:09.973349 scanning usb for storage devices... 0 Storage Device(s) found
712 08:29:10.024879 Hit any key to stop autoboot: 1
713 08:29:10.025981 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 08:29:10.026607 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 08:29:10.027091 Setting prompt string to ['=>']
716 08:29:10.027602 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 08:29:10.039349 0
718 08:29:10.040333 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 08:29:10.141626 => setenv autoload no
721 08:29:10.142380 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 08:29:10.147177 setenv autoload no
724 08:29:10.248737 => setenv initrd_high 0xffffffff
725 08:29:10.249512 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 08:29:10.253727 setenv initrd_high 0xffffffff
728 08:29:10.355193 => setenv fdt_high 0xffffffff
729 08:29:10.355921 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 08:29:10.359440 setenv fdt_high 0xffffffff
732 08:29:10.461140 => dhcp
733 08:29:10.462132 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 08:29:10.466151 dhcp
735 08:29:10.971661 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 08:29:10.972375 Speed: 1000, full duplex
737 08:29:10.972891 BOOTP broadcast 1
738 08:29:11.218905 BOOTP broadcast 2
739 08:29:11.719763 BOOTP broadcast 3
740 08:29:12.720543 BOOTP broadcast 4
741 08:29:14.721710 BOOTP broadcast 5
742 08:29:14.766154 DHCP client bound to address 192.168.6.12 (3794 ms)
744 08:29:14.867761 => setenv serverip 192.168.6.2
745 08:29:14.868585 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
746 08:29:14.872314 setenv serverip 192.168.6.2
748 08:29:14.973916 => tftpboot 0x01080000 838544/tftp-deploy-0m30b30y/kernel/uImage
749 08:29:14.974734 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
750 08:29:14.981491 tftpboot 0x01080000 838544/tftp-deploy-0m30b30y/kernel/uImage
751 08:29:14.982074 Speed: 1000, full duplex
752 08:29:14.982525 Using ethernet@ff3f0000 device
753 08:29:14.987014 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 08:29:14.992481 Filename '838544/tftp-deploy-0m30b30y/kernel/uImage'.
755 08:29:14.996422 Load address: 0x1080000
756 08:29:19.130167 Loading: *################################################## 43.9 MiB
757 08:29:19.130817 10.6 MiB/s
758 08:29:19.131274 done
759 08:29:19.134440 Bytes transferred = 46066240 (2beea40 hex)
761 08:29:19.236036 => tftpboot 0x08000000 838544/tftp-deploy-0m30b30y/ramdisk/ramdisk.cpio.gz.uboot
762 08:29:19.236772 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
763 08:29:19.243671 tftpboot 0x08000000 838544/tftp-deploy-0m30b30y/ramdisk/ramdisk.cpio.gz.uboot
764 08:29:19.244232 Speed: 1000, full duplex
765 08:29:19.244678 Using ethernet@ff3f0000 device
766 08:29:19.249184 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
767 08:29:19.259020 Filename '838544/tftp-deploy-0m30b30y/ramdisk/ramdisk.cpio.gz.uboot'.
768 08:29:19.259550 Load address: 0x8000000
769 08:29:19.356416 Loading: *## UDP wrong checksum 000000ff 00000214
770 08:29:19.385827 # UDP wrong checksum 000000ff 00008b06
771 08:29:24.618318 ##################### UDP wrong checksum 000000ff 0000a8a4
772 08:29:24.633681 UDP wrong checksum 000000ff 00002d97
773 08:29:26.754567 T ######################### UDP wrong checksum 00000005 00001ced
774 08:29:31.755796 T UDP wrong checksum 00000005 00001ced
775 08:29:41.757394 T T UDP wrong checksum 00000005 00001ced
776 08:29:58.871097 T T T UDP wrong checksum 000000ff 000018bd
777 08:29:58.900488 UDP wrong checksum 000000ff 00009faf
778 08:30:01.761674 T UDP wrong checksum 00000005 00001ced
779 08:30:16.765267 T T
780 08:30:16.765672 Retry count exceeded; starting again
782 08:30:16.766810 end: 2.4.3 bootloader-commands (duration 00:01:07) [common]
785 08:30:16.767714 end: 2.4 uboot-commands (duration 00:01:25) [common]
787 08:30:16.768434 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
789 08:30:16.768980 end: 2 uboot-action (duration 00:01:25) [common]
791 08:30:16.769820 Cleaning after the job
792 08:30:16.770136 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/ramdisk
793 08:30:16.771066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/kernel
794 08:30:16.798732 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/dtb
795 08:30:16.799651 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/838544/tftp-deploy-0m30b30y/modules
796 08:30:16.819973 start: 4.1 power-off (timeout 00:00:30) [common]
797 08:30:16.820652 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
798 08:30:16.853735 >> OK - accepted request
799 08:30:16.855638 Returned 0 in 0 seconds
800 08:30:16.956507 end: 4.1 power-off (duration 00:00:00) [common]
802 08:30:16.957734 start: 4.2 read-feedback (timeout 00:10:00) [common]
803 08:30:16.958389 Listened to connection for namespace 'common' for up to 1s
804 08:30:17.958646 Finalising connection for namespace 'common'
805 08:30:17.959288 Disconnecting from shell: Finalise
806 08:30:17.959664 =>
807 08:30:18.060629 end: 4.2 read-feedback (duration 00:00:01) [common]
808 08:30:18.061250 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/838544
809 08:30:18.351431 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/838544
810 08:30:18.352025 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.