Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 4
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:29:36.826916 lava-dispatcher, installed at version: 2024.01
2 22:29:36.827871 start: 0 validate
3 22:29:36.828494 Start time: 2024-10-15 22:29:36.828455+00:00 (UTC)
4 22:29:36.829213 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:29:36.829937 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 22:29:36.877082 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:29:36.877731 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241015%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 22:29:36.915403 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:29:36.916098 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241015%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 22:29:37.964308 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:29:37.964793 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241015%2Farm64%2Fdefconfig%2BCONFIG_RANDOMIZE_BASE%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 22:29:38.003821 validate duration: 1.18
14 22:29:38.004704 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:29:38.005025 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:29:38.005324 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:29:38.005929 Not decompressing ramdisk as can be used compressed.
18 22:29:38.006368 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 22:29:38.006634 saving as /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/ramdisk/rootfs.cpio.gz
20 22:29:38.006905 total size: 8181887 (7 MB)
21 22:29:38.041464 progress 0 % (0 MB)
22 22:29:38.052867 progress 5 % (0 MB)
23 22:29:38.063374 progress 10 % (0 MB)
24 22:29:38.071569 progress 15 % (1 MB)
25 22:29:38.076937 progress 20 % (1 MB)
26 22:29:38.082621 progress 25 % (1 MB)
27 22:29:38.088108 progress 30 % (2 MB)
28 22:29:38.093940 progress 35 % (2 MB)
29 22:29:38.099325 progress 40 % (3 MB)
30 22:29:38.105208 progress 45 % (3 MB)
31 22:29:38.110558 progress 50 % (3 MB)
32 22:29:38.116174 progress 55 % (4 MB)
33 22:29:38.121423 progress 60 % (4 MB)
34 22:29:38.127123 progress 65 % (5 MB)
35 22:29:38.133085 progress 70 % (5 MB)
36 22:29:38.138994 progress 75 % (5 MB)
37 22:29:38.144610 progress 80 % (6 MB)
38 22:29:38.150581 progress 85 % (6 MB)
39 22:29:38.156079 progress 90 % (7 MB)
40 22:29:38.161890 progress 95 % (7 MB)
41 22:29:38.166969 progress 100 % (7 MB)
42 22:29:38.167679 7 MB downloaded in 0.16 s (48.54 MB/s)
43 22:29:38.168303 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:29:38.169277 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:29:38.169600 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:29:38.169901 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:29:38.170389 downloading http://storage.kernelci.org/next/master/next-20241015/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/kernel/Image
49 22:29:38.170668 saving as /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/kernel/Image
50 22:29:38.170893 total size: 45781504 (43 MB)
51 22:29:38.171118 No compression specified
52 22:29:38.207159 progress 0 % (0 MB)
53 22:29:38.239269 progress 5 % (2 MB)
54 22:29:38.267336 progress 10 % (4 MB)
55 22:29:38.295420 progress 15 % (6 MB)
56 22:29:38.323526 progress 20 % (8 MB)
57 22:29:38.351611 progress 25 % (10 MB)
58 22:29:38.379653 progress 30 % (13 MB)
59 22:29:38.407271 progress 35 % (15 MB)
60 22:29:38.435551 progress 40 % (17 MB)
61 22:29:38.463626 progress 45 % (19 MB)
62 22:29:38.491971 progress 50 % (21 MB)
63 22:29:38.520186 progress 55 % (24 MB)
64 22:29:38.548311 progress 60 % (26 MB)
65 22:29:38.576572 progress 65 % (28 MB)
66 22:29:38.604235 progress 70 % (30 MB)
67 22:29:38.632512 progress 75 % (32 MB)
68 22:29:38.660540 progress 80 % (34 MB)
69 22:29:38.688530 progress 85 % (37 MB)
70 22:29:38.716891 progress 90 % (39 MB)
71 22:29:38.745065 progress 95 % (41 MB)
72 22:29:38.772805 progress 100 % (43 MB)
73 22:29:38.773373 43 MB downloaded in 0.60 s (72.47 MB/s)
74 22:29:38.773862 end: 1.2.1 http-download (duration 00:00:01) [common]
76 22:29:38.774678 end: 1.2 download-retry (duration 00:00:01) [common]
77 22:29:38.774955 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:29:38.775219 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:29:38.775677 downloading http://storage.kernelci.org/next/master/next-20241015/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 22:29:38.775963 saving as /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 22:29:38.776201 total size: 53209 (0 MB)
82 22:29:38.776412 No compression specified
83 22:29:38.819849 progress 61 % (0 MB)
84 22:29:38.820733 progress 100 % (0 MB)
85 22:29:38.821274 0 MB downloaded in 0.05 s (1.13 MB/s)
86 22:29:38.821738 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:29:38.822553 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:29:38.822817 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:29:38.823080 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:29:38.823536 downloading http://storage.kernelci.org/next/master/next-20241015/arm64/defconfig+CONFIG_RANDOMIZE_BASE=y/gcc-12/modules.tar.xz
92 22:29:38.823787 saving as /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/modules/modules.tar
93 22:29:38.824013 total size: 11623720 (11 MB)
94 22:29:38.824228 Using unxz to decompress xz
95 22:29:38.861592 progress 0 % (0 MB)
96 22:29:38.923703 progress 5 % (0 MB)
97 22:29:39.003765 progress 10 % (1 MB)
98 22:29:39.092728 progress 15 % (1 MB)
99 22:29:39.184489 progress 20 % (2 MB)
100 22:29:39.267774 progress 25 % (2 MB)
101 22:29:39.345992 progress 30 % (3 MB)
102 22:29:39.428786 progress 35 % (3 MB)
103 22:29:39.504946 progress 40 % (4 MB)
104 22:29:39.583185 progress 45 % (5 MB)
105 22:29:39.665882 progress 50 % (5 MB)
106 22:29:39.749287 progress 55 % (6 MB)
107 22:29:39.828686 progress 60 % (6 MB)
108 22:29:39.905037 progress 65 % (7 MB)
109 22:29:39.987381 progress 70 % (7 MB)
110 22:29:40.066894 progress 75 % (8 MB)
111 22:29:40.139897 progress 80 % (8 MB)
112 22:29:40.223711 progress 85 % (9 MB)
113 22:29:40.308154 progress 90 % (10 MB)
114 22:29:40.387394 progress 95 % (10 MB)
115 22:29:40.466467 progress 100 % (11 MB)
116 22:29:40.480661 11 MB downloaded in 1.66 s (6.69 MB/s)
117 22:29:40.481294 end: 1.4.1 http-download (duration 00:00:02) [common]
119 22:29:40.482114 end: 1.4 download-retry (duration 00:00:02) [common]
120 22:29:40.482386 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 22:29:40.482653 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 22:29:40.482900 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:29:40.483152 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 22:29:40.483733 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed
125 22:29:40.484553 makedir: /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin
126 22:29:40.485311 makedir: /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/tests
127 22:29:40.486009 makedir: /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/results
128 22:29:40.486675 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-add-keys
129 22:29:40.487753 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-add-sources
130 22:29:40.488871 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-background-process-start
131 22:29:40.489941 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-background-process-stop
132 22:29:40.491041 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-common-functions
133 22:29:40.492096 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-echo-ipv4
134 22:29:40.493129 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-install-packages
135 22:29:40.494158 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-installed-packages
136 22:29:40.495223 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-os-build
137 22:29:40.496270 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-probe-channel
138 22:29:40.497328 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-probe-ip
139 22:29:40.498355 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-target-ip
140 22:29:40.499391 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-target-mac
141 22:29:40.500428 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-target-storage
142 22:29:40.501455 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-test-case
143 22:29:40.502505 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-test-event
144 22:29:40.503494 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-test-feedback
145 22:29:40.504529 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-test-raise
146 22:29:40.505516 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-test-reference
147 22:29:40.506499 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-test-runner
148 22:29:40.507515 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-test-set
149 22:29:40.508597 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-test-shell
150 22:29:40.509695 Updating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-install-packages (oe)
151 22:29:40.510803 Updating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/bin/lava-installed-packages (oe)
152 22:29:40.511731 Creating /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/environment
153 22:29:40.512593 LAVA metadata
154 22:29:40.513135 - LAVA_JOB_ID=847809
155 22:29:40.513603 - LAVA_DISPATCHER_IP=192.168.6.2
156 22:29:40.514333 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 22:29:40.516395 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 22:29:40.517015 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 22:29:40.517447 skipped lava-vland-overlay
160 22:29:40.517929 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 22:29:40.518430 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 22:29:40.518852 skipped lava-multinode-overlay
163 22:29:40.519329 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 22:29:40.519821 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 22:29:40.520231 Loading test definitions
166 22:29:40.520533 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 22:29:40.520764 Using /lava-847809 at stage 0
168 22:29:40.522126 uuid=847809_1.5.2.4.1 testdef=None
169 22:29:40.522468 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 22:29:40.522740 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 22:29:40.524643 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 22:29:40.525493 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 22:29:40.527818 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 22:29:40.528728 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 22:29:40.530978 runner path: /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/0/tests/0_dmesg test_uuid 847809_1.5.2.4.1
178 22:29:40.531593 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 22:29:40.532430 Creating lava-test-runner.conf files
181 22:29:40.532636 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/847809/lava-overlay-25ulyaed/lava-847809/0 for stage 0
182 22:29:40.533001 - 0_dmesg
183 22:29:40.533367 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 22:29:40.533656 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 22:29:40.558196 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 22:29:40.558648 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 22:29:40.558918 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 22:29:40.559190 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 22:29:40.559457 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 22:29:41.498230 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 22:29:41.498703 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 22:29:41.498951 extracting modules file /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/847809/extract-overlay-ramdisk-ipeayz8p/ramdisk
193 22:29:42.870989 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 22:29:42.871486 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 22:29:42.871772 [common] Applying overlay /var/lib/lava/dispatcher/tmp/847809/compress-overlay-4d8bvxkt/overlay-1.5.2.5.tar.gz to ramdisk
196 22:29:42.872025 [common] Applying overlay /var/lib/lava/dispatcher/tmp/847809/compress-overlay-4d8bvxkt/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/847809/extract-overlay-ramdisk-ipeayz8p/ramdisk
197 22:29:42.903172 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 22:29:42.903640 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 22:29:42.903915 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 22:29:42.904188 Converting downloaded kernel to a uImage
201 22:29:42.904515 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/kernel/Image /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/kernel/uImage
202 22:29:43.394340 output: Image Name:
203 22:29:43.394771 output: Created: Tue Oct 15 22:29:42 2024
204 22:29:43.394983 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 22:29:43.395189 output: Data Size: 45781504 Bytes = 44708.50 KiB = 43.66 MiB
206 22:29:43.395390 output: Load Address: 01080000
207 22:29:43.395588 output: Entry Point: 01080000
208 22:29:43.395786 output:
209 22:29:43.396153 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 22:29:43.396430 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 22:29:43.396697 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 22:29:43.396947 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 22:29:43.397203 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 22:29:43.397459 Building ramdisk /var/lib/lava/dispatcher/tmp/847809/extract-overlay-ramdisk-ipeayz8p/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/847809/extract-overlay-ramdisk-ipeayz8p/ramdisk
215 22:29:46.316387 >> 181753 blocks
216 22:29:54.813827 Adding RAMdisk u-boot header.
217 22:29:54.814268 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/847809/extract-overlay-ramdisk-ipeayz8p/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/847809/extract-overlay-ramdisk-ipeayz8p/ramdisk.cpio.gz.uboot
218 22:29:55.098822 output: Image Name:
219 22:29:55.099242 output: Created: Tue Oct 15 22:29:54 2024
220 22:29:55.099449 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 22:29:55.099653 output: Data Size: 26072884 Bytes = 25461.80 KiB = 24.87 MiB
222 22:29:55.099853 output: Load Address: 00000000
223 22:29:55.100224 output: Entry Point: 00000000
224 22:29:55.100666 output:
225 22:29:55.101865 rename /var/lib/lava/dispatcher/tmp/847809/extract-overlay-ramdisk-ipeayz8p/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/ramdisk/ramdisk.cpio.gz.uboot
226 22:29:55.102626 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 22:29:55.103211 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 22:29:55.103778 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 22:29:55.104311 No LXC device requested
230 22:29:55.104860 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 22:29:55.105413 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 22:29:55.105950 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 22:29:55.106398 Checking files for TFTP limit of 4294967296 bytes.
234 22:29:55.109341 end: 1 tftp-deploy (duration 00:00:17) [common]
235 22:29:55.109990 start: 2 uboot-action (timeout 00:05:00) [common]
236 22:29:55.110560 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 22:29:55.111101 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 22:29:55.111646 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 22:29:55.112255 Using kernel file from prepare-kernel: 847809/tftp-deploy-jblhgcpr/kernel/uImage
240 22:29:55.112936 substitutions:
241 22:29:55.113387 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 22:29:55.113828 - {DTB_ADDR}: 0x01070000
243 22:29:55.114261 - {DTB}: 847809/tftp-deploy-jblhgcpr/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 22:29:55.114698 - {INITRD}: 847809/tftp-deploy-jblhgcpr/ramdisk/ramdisk.cpio.gz.uboot
245 22:29:55.115130 - {KERNEL_ADDR}: 0x01080000
246 22:29:55.115566 - {KERNEL}: 847809/tftp-deploy-jblhgcpr/kernel/uImage
247 22:29:55.116022 - {LAVA_MAC}: None
248 22:29:55.116502 - {PRESEED_CONFIG}: None
249 22:29:55.116939 - {PRESEED_LOCAL}: None
250 22:29:55.117369 - {RAMDISK_ADDR}: 0x08000000
251 22:29:55.117795 - {RAMDISK}: 847809/tftp-deploy-jblhgcpr/ramdisk/ramdisk.cpio.gz.uboot
252 22:29:55.118229 - {ROOT_PART}: None
253 22:29:55.118659 - {ROOT}: None
254 22:29:55.119085 - {SERVER_IP}: 192.168.6.2
255 22:29:55.119517 - {TEE_ADDR}: 0x83000000
256 22:29:55.119943 - {TEE}: None
257 22:29:55.120437 Parsed boot commands:
258 22:29:55.120858 - setenv autoload no
259 22:29:55.121283 - setenv initrd_high 0xffffffff
260 22:29:55.121708 - setenv fdt_high 0xffffffff
261 22:29:55.122132 - dhcp
262 22:29:55.122559 - setenv serverip 192.168.6.2
263 22:29:55.122984 - tftpboot 0x01080000 847809/tftp-deploy-jblhgcpr/kernel/uImage
264 22:29:55.123408 - tftpboot 0x08000000 847809/tftp-deploy-jblhgcpr/ramdisk/ramdisk.cpio.gz.uboot
265 22:29:55.123836 - tftpboot 0x01070000 847809/tftp-deploy-jblhgcpr/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 22:29:55.124301 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 22:29:55.124741 - bootm 0x01080000 0x08000000 0x01070000
268 22:29:55.125287 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 22:29:55.126909 start: 2.3 connect-device (timeout 00:05:00) [common]
271 22:29:55.127390 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 22:29:55.141791 Setting prompt string to ['lava-test: # ']
273 22:29:55.143361 end: 2.3 connect-device (duration 00:00:00) [common]
274 22:29:55.144029 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 22:29:55.144636 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 22:29:55.145196 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 22:29:55.146422 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 22:29:55.182952 >> OK - accepted request
279 22:29:55.185125 Returned 0 in 0 seconds
280 22:29:55.286277 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 22:29:55.288043 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 22:29:55.288680 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 22:29:55.289224 Setting prompt string to ['Hit any key to stop autoboot']
285 22:29:55.289719 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 22:29:55.291441 Trying 192.168.56.21...
287 22:29:55.291954 Connected to conserv1.
288 22:29:55.292469 Escape character is '^]'.
289 22:29:55.292937
290 22:29:55.293404 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 22:29:55.293867
292 22:30:02.781686 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 22:30:02.782121 bl2_stage_init 0x01
294 22:30:02.782354 bl2_stage_init 0x81
295 22:30:02.782577 hw id: 0x0000 - pwm id 0x01
296 22:30:02.782800 bl2_stage_init 0xc1
297 22:30:02.786975 bl2_stage_init 0x02
298 22:30:02.787260
299 22:30:02.787477 L0:00000000
300 22:30:02.787691 L1:00000703
301 22:30:02.787895 L2:00008067
302 22:30:02.788134 L3:15000000
303 22:30:02.792567 S1:00000000
304 22:30:02.792870 B2:20282000
305 22:30:02.793073 B1:a0f83180
306 22:30:02.793280
307 22:30:02.793501 TE: 70932
308 22:30:02.793715
309 22:30:02.803827 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 22:30:02.804149
311 22:30:02.804371 Board ID = 1
312 22:30:02.804580 Set cpu clk to 24M
313 22:30:02.804783 Set clk81 to 24M
314 22:30:02.809349 Use GP1_pll as DSU clk.
315 22:30:02.809613 DSU clk: 1200 Mhz
316 22:30:02.809827 CPU clk: 1200 MHz
317 22:30:02.814949 Set clk81 to 166.6M
318 22:30:02.820526 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 22:30:02.820797 board id: 1
320 22:30:02.827706 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 22:30:02.838644 fw parse done
322 22:30:02.844577 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 22:30:02.887740 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 22:30:02.898885 PIEI prepare done
325 22:30:02.899158 fastboot data load
326 22:30:02.899362 fastboot data verify
327 22:30:02.904373 verify result: 266
328 22:30:02.910025 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 22:30:02.910277 LPDDR4 probe
330 22:30:02.910478 ddr clk to 1584MHz
331 22:30:02.917979 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 22:30:02.955808
333 22:30:02.956158 dmc_version 0001
334 22:30:02.962878 Check phy result
335 22:30:02.968797 INFO : End of CA training
336 22:30:02.969052 INFO : End of initialization
337 22:30:02.974458 INFO : Training has run successfully!
338 22:30:02.974698 Check phy result
339 22:30:02.980021 INFO : End of initialization
340 22:30:02.980506 INFO : End of read enable training
341 22:30:02.985642 INFO : End of fine write leveling
342 22:30:02.991210 INFO : End of Write leveling coarse delay
343 22:30:02.991668 INFO : Training has run successfully!
344 22:30:02.992145 Check phy result
345 22:30:02.996818 INFO : End of initialization
346 22:30:02.997278 INFO : End of read dq deskew training
347 22:30:03.002442 INFO : End of MPR read delay center optimization
348 22:30:03.008042 INFO : End of write delay center optimization
349 22:30:03.013605 INFO : End of read delay center optimization
350 22:30:03.014077 INFO : End of max read latency training
351 22:30:03.019219 INFO : Training has run successfully!
352 22:30:03.019690 1D training succeed
353 22:30:03.028396 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 22:30:03.076761 Check phy result
355 22:30:03.077232 INFO : End of initialization
356 22:30:03.104079 INFO : End of 2D read delay Voltage center optimization
357 22:30:03.128255 INFO : End of 2D read delay Voltage center optimization
358 22:30:03.184989 INFO : End of 2D write delay Voltage center optimization
359 22:30:03.238953 INFO : End of 2D write delay Voltage center optimization
360 22:30:03.244361 INFO : Training has run successfully!
361 22:30:03.244824
362 22:30:03.245259 channel==0
363 22:30:03.249999 RxClkDly_Margin_A0==78 ps 8
364 22:30:03.250453 TxDqDly_Margin_A0==98 ps 10
365 22:30:03.255579 RxClkDly_Margin_A1==88 ps 9
366 22:30:03.256115 TxDqDly_Margin_A1==88 ps 9
367 22:30:03.256558 TrainedVREFDQ_A0==74
368 22:30:03.266972 TrainedVREFDQ_A1==74
369 22:30:03.267435 VrefDac_Margin_A0==23
370 22:30:03.267866 DeviceVref_Margin_A0==40
371 22:30:03.268330 VrefDac_Margin_A1==23
372 22:30:03.268757 DeviceVref_Margin_A1==40
373 22:30:03.269185
374 22:30:03.269612
375 22:30:03.270040 channel==1
376 22:30:03.272466 RxClkDly_Margin_A0==78 ps 8
377 22:30:03.272926 TxDqDly_Margin_A0==98 ps 10
378 22:30:03.279212 RxClkDly_Margin_A1==88 ps 9
379 22:30:03.279708 TxDqDly_Margin_A1==88 ps 9
380 22:30:03.283652 TrainedVREFDQ_A0==78
381 22:30:03.284154 TrainedVREFDQ_A1==75
382 22:30:03.284597 VrefDac_Margin_A0==23
383 22:30:03.289275 DeviceVref_Margin_A0==36
384 22:30:03.289732 VrefDac_Margin_A1==22
385 22:30:03.294865 DeviceVref_Margin_A1==39
386 22:30:03.295318
387 22:30:03.295755 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 22:30:03.296223
389 22:30:03.328402 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000018 00000019 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 22:30:03.328936 2D training succeed
391 22:30:03.334026 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 22:30:03.339688 auto size-- 65535DDR cs0 size: 2048MB
393 22:30:03.340178 DDR cs1 size: 2048MB
394 22:30:03.345210 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 22:30:03.345666 cs0 DataBus test pass
396 22:30:03.350829 cs1 DataBus test pass
397 22:30:03.351284 cs0 AddrBus test pass
398 22:30:03.351713 cs1 AddrBus test pass
399 22:30:03.352173
400 22:30:03.356398 100bdlr_step_size ps== 478
401 22:30:03.356872 result report
402 22:30:03.361962 boot times 0Enable ddr reg access
403 22:30:03.367207 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 22:30:03.381082 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 22:30:04.040260 bl2z: ptr: 05129330, size: 00001e40
406 22:30:04.047509 0.0;M3 CHK:0;cm4_sp_mode 0
407 22:30:04.048054 MVN_1=0x00000000
408 22:30:04.048516 MVN_2=0x00000000
409 22:30:04.059043 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 22:30:04.059526 OPS=0x04
411 22:30:04.059973 ring efuse init
412 22:30:04.064610 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 22:30:04.065093 [0.017354 Inits done]
414 22:30:04.065535 secure task start!
415 22:30:04.072361 high task start!
416 22:30:04.072827 low task start!
417 22:30:04.073271 run into bl31
418 22:30:04.080773 NOTICE: BL31: v1.3(release):4fc40b1
419 22:30:04.088714 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 22:30:04.089197 NOTICE: BL31: G12A normal boot!
421 22:30:04.104191 NOTICE: BL31: BL33 decompress pass
422 22:30:04.109792 ERROR: Error initializing runtime service opteed_fast
423 22:30:06.824935 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 22:30:06.825353 bl2_stage_init 0x01
425 22:30:06.825567 bl2_stage_init 0x81
426 22:30:06.830590 hw id: 0x0000 - pwm id 0x01
427 22:30:06.831148 bl2_stage_init 0xc1
428 22:30:06.836136 bl2_stage_init 0x02
429 22:30:06.836592
430 22:30:06.836995 L0:00000000
431 22:30:06.837386 L1:00000703
432 22:30:06.837774 L2:00008067
433 22:30:06.838160 L3:15000000
434 22:30:06.841678 S1:00000000
435 22:30:06.842107 B2:20282000
436 22:30:06.842498 B1:a0f83180
437 22:30:06.842880
438 22:30:06.843269 TE: 68571
439 22:30:06.843656
440 22:30:06.847244 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 22:30:06.847675
442 22:30:06.852856 Board ID = 1
443 22:30:06.853283 Set cpu clk to 24M
444 22:30:06.853674 Set clk81 to 24M
445 22:30:06.858598 Use GP1_pll as DSU clk.
446 22:30:06.859026 DSU clk: 1200 Mhz
447 22:30:06.859413 CPU clk: 1200 MHz
448 22:30:06.864066 Set clk81 to 166.6M
449 22:30:06.869646 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 22:30:06.870066 board id: 1
451 22:30:06.887754 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 22:30:06.888229 fw parse done
453 22:30:06.893480 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 22:30:06.936219 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 22:30:06.947090 PIEI prepare done
456 22:30:06.947530 fastboot data load
457 22:30:06.947934 fastboot data verify
458 22:30:06.952767 verify result: 266
459 22:30:06.958225 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 22:30:06.958648 LPDDR4 probe
461 22:30:06.959040 ddr clk to 1584MHz
462 22:30:06.966292 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 22:30:07.010330
464 22:30:07.010865 dmc_version 0001
465 22:30:07.011261 Check phy result
466 22:30:07.016043 INFO : End of CA training
467 22:30:07.016507 INFO : End of initialization
468 22:30:07.021615 INFO : Training has run successfully!
469 22:30:07.022067 Check phy result
470 22:30:07.027212 INFO : End of initialization
471 22:30:07.027665 INFO : End of read enable training
472 22:30:07.032826 INFO : End of fine write leveling
473 22:30:07.038372 INFO : End of Write leveling coarse delay
474 22:30:07.038839 INFO : Training has run successfully!
475 22:30:07.039257 Check phy result
476 22:30:07.044019 INFO : End of initialization
477 22:30:07.044481 INFO : End of read dq deskew training
478 22:30:07.055372 INFO : End of MPR read delay center optimization
479 22:30:07.055842 INFO : End of write delay center optimization
480 22:30:07.060842 INFO : End of read delay center optimization
481 22:30:07.061290 INFO : End of max read latency training
482 22:30:07.066419 INFO : Training has run successfully!
483 22:30:07.066860 1D training succeed
484 22:30:07.075529 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 22:30:07.123321 Check phy result
486 22:30:07.123781 INFO : End of initialization
487 22:30:07.145783 INFO : End of 2D read delay Voltage center optimization
488 22:30:07.216841 INFO : End of 2D read delay Voltage center optimization
489 22:30:07.217380 INFO : End of 2D write delay Voltage center optimization
490 22:30:07.265851 INFO : End of 2D write delay Voltage center optimization
491 22:30:07.271377 INFO : Training has run successfully!
492 22:30:07.271833
493 22:30:07.272343 channel==0
494 22:30:07.277003 RxClkDly_Margin_A0==88 ps 9
495 22:30:07.277450 TxDqDly_Margin_A0==98 ps 10
496 22:30:07.282646 RxClkDly_Margin_A1==88 ps 9
497 22:30:07.283096 TxDqDly_Margin_A1==98 ps 10
498 22:30:07.283513 TrainedVREFDQ_A0==76
499 22:30:07.288184 TrainedVREFDQ_A1==74
500 22:30:07.288683 VrefDac_Margin_A0==23
501 22:30:07.289098 DeviceVref_Margin_A0==38
502 22:30:07.293775 VrefDac_Margin_A1==23
503 22:30:07.294223 DeviceVref_Margin_A1==40
504 22:30:07.294635
505 22:30:07.295041
506 22:30:07.299277 channel==1
507 22:30:07.299719 RxClkDly_Margin_A0==88 ps 9
508 22:30:07.300156 TxDqDly_Margin_A0==88 ps 9
509 22:30:07.304893 RxClkDly_Margin_A1==78 ps 8
510 22:30:07.305341 TxDqDly_Margin_A1==88 ps 9
511 22:30:07.310633 TrainedVREFDQ_A0==76
512 22:30:07.311072 TrainedVREFDQ_A1==75
513 22:30:07.311483 VrefDac_Margin_A0==22
514 22:30:07.316229 DeviceVref_Margin_A0==38
515 22:30:07.316735 VrefDac_Margin_A1==20
516 22:30:07.321796 DeviceVref_Margin_A1==39
517 22:30:07.322245
518 22:30:07.322661 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 22:30:07.323072
520 22:30:07.360628 soc_vref_reg_value 0x 00000019 00000018 00000019 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000016 00000017 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000015 00000017 dram_vref_reg_value 0x 00000061
521 22:30:07.361136 2D training succeed
522 22:30:07.361564 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 22:30:07.365991 auto size-- 65535DDR cs0 size: 2048MB
524 22:30:07.366442 DDR cs1 size: 2048MB
525 22:30:07.371590 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 22:30:07.372064 cs0 DataBus test pass
527 22:30:07.377199 cs1 DataBus test pass
528 22:30:07.377644 cs0 AddrBus test pass
529 22:30:07.378052 cs1 AddrBus test pass
530 22:30:07.378447
531 22:30:07.382809 100bdlr_step_size ps== 478
532 22:30:07.383262 result report
533 22:30:07.388378 boot times 0Enable ddr reg access
534 22:30:07.394160 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 22:30:07.408220 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 22:30:08.062880 bl2z: ptr: 05129330, size: 00001e40
537 22:30:08.071351 0.0;M3 CHK:0;cm4_sp_mode 0
538 22:30:08.071833 MVN_1=0x00000000
539 22:30:08.072294 MVN_2=0x00000000
540 22:30:08.082827 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 22:30:08.083291 OPS=0x04
542 22:30:08.083711 ring efuse init
543 22:30:08.088469 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 22:30:08.088931 [0.017310 Inits done]
545 22:30:08.089342 secure task start!
546 22:30:08.096059 high task start!
547 22:30:08.096514 low task start!
548 22:30:08.096923 run into bl31
549 22:30:08.104618 NOTICE: BL31: v1.3(release):4fc40b1
550 22:30:08.112452 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 22:30:08.112905 NOTICE: BL31: G12A normal boot!
552 22:30:08.127933 NOTICE: BL31: BL33 decompress pass
553 22:30:08.133667 ERROR: Error initializing runtime service opteed_fast
554 22:30:09.525921 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 22:30:09.526521 bl2_stage_init 0x01
556 22:30:09.526945 bl2_stage_init 0x81
557 22:30:09.531332 hw id: 0x0000 - pwm id 0x01
558 22:30:09.531780 bl2_stage_init 0xc1
559 22:30:09.536937 bl2_stage_init 0x02
560 22:30:09.537380
561 22:30:09.537794 L0:00000000
562 22:30:09.538196 L1:00000703
563 22:30:09.538593 L2:00008067
564 22:30:09.538993 L3:15000000
565 22:30:09.542503 S1:00000000
566 22:30:09.542941 B2:20282000
567 22:30:09.543347 B1:a0f83180
568 22:30:09.543747
569 22:30:09.544228 TE: 70645
570 22:30:09.544679
571 22:30:09.548154 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 22:30:09.548611
573 22:30:09.553816 Board ID = 1
574 22:30:09.554262 Set cpu clk to 24M
575 22:30:09.554670 Set clk81 to 24M
576 22:30:09.559309 Use GP1_pll as DSU clk.
577 22:30:09.559749 DSU clk: 1200 Mhz
578 22:30:09.560195 CPU clk: 1200 MHz
579 22:30:09.564894 Set clk81 to 166.6M
580 22:30:09.570503 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 22:30:09.570946 board id: 1
582 22:30:09.577764 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 22:30:09.588581 fw parse done
584 22:30:09.594568 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 22:30:09.637771 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 22:30:09.648891 PIEI prepare done
587 22:30:09.649335 fastboot data load
588 22:30:09.649750 fastboot data verify
589 22:30:09.654373 verify result: 266
590 22:30:09.660032 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 22:30:09.660479 LPDDR4 probe
592 22:30:09.660889 ddr clk to 1584MHz
593 22:30:09.667997 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 22:30:09.705847
595 22:30:09.706304 dmc_version 0001
596 22:30:09.712840 Check phy result
597 22:30:09.718883 INFO : End of CA training
598 22:30:09.719320 INFO : End of initialization
599 22:30:09.724368 INFO : Training has run successfully!
600 22:30:09.724812 Check phy result
601 22:30:09.729955 INFO : End of initialization
602 22:30:09.730391 INFO : End of read enable training
603 22:30:09.735509 INFO : End of fine write leveling
604 22:30:09.741124 INFO : End of Write leveling coarse delay
605 22:30:09.741575 INFO : Training has run successfully!
606 22:30:09.741988 Check phy result
607 22:30:09.746691 INFO : End of initialization
608 22:30:09.747134 INFO : End of read dq deskew training
609 22:30:09.752288 INFO : End of MPR read delay center optimization
610 22:30:09.757914 INFO : End of write delay center optimization
611 22:30:09.763514 INFO : End of read delay center optimization
612 22:30:09.763968 INFO : End of max read latency training
613 22:30:09.769108 INFO : Training has run successfully!
614 22:30:09.769548 1D training succeed
615 22:30:09.778319 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 22:30:09.826715 Check phy result
617 22:30:09.827178 INFO : End of initialization
618 22:30:09.854029 INFO : End of 2D read delay Voltage center optimization
619 22:30:09.878287 INFO : End of 2D read delay Voltage center optimization
620 22:30:09.934951 INFO : End of 2D write delay Voltage center optimization
621 22:30:09.988956 INFO : End of 2D write delay Voltage center optimization
622 22:30:09.994447 INFO : Training has run successfully!
623 22:30:09.994893
624 22:30:09.995307 channel==0
625 22:30:10.000074 RxClkDly_Margin_A0==78 ps 8
626 22:30:10.000537 TxDqDly_Margin_A0==88 ps 9
627 22:30:10.005656 RxClkDly_Margin_A1==88 ps 9
628 22:30:10.006107 TxDqDly_Margin_A1==98 ps 10
629 22:30:10.006522 TrainedVREFDQ_A0==74
630 22:30:10.011302 TrainedVREFDQ_A1==74
631 22:30:10.011752 VrefDac_Margin_A0==23
632 22:30:10.012198 DeviceVref_Margin_A0==40
633 22:30:10.016908 VrefDac_Margin_A1==23
634 22:30:10.017362 DeviceVref_Margin_A1==40
635 22:30:10.017769
636 22:30:10.018176
637 22:30:10.018580 channel==1
638 22:30:10.022546 RxClkDly_Margin_A0==78 ps 8
639 22:30:10.023000 TxDqDly_Margin_A0==98 ps 10
640 22:30:10.028105 RxClkDly_Margin_A1==78 ps 8
641 22:30:10.028552 TxDqDly_Margin_A1==88 ps 9
642 22:30:10.033668 TrainedVREFDQ_A0==78
643 22:30:10.034117 TrainedVREFDQ_A1==75
644 22:30:10.034524 VrefDac_Margin_A0==23
645 22:30:10.039264 DeviceVref_Margin_A0==36
646 22:30:10.039709 VrefDac_Margin_A1==20
647 22:30:10.044929 DeviceVref_Margin_A1==39
648 22:30:10.045380
649 22:30:10.045787 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 22:30:10.046207
651 22:30:10.078467 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000016 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 22:30:10.078976 2D training succeed
653 22:30:10.084117 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 22:30:10.089664 auto size-- 65535DDR cs0 size: 2048MB
655 22:30:10.090110 DDR cs1 size: 2048MB
656 22:30:10.095274 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 22:30:10.095715 cs0 DataBus test pass
658 22:30:10.100946 cs1 DataBus test pass
659 22:30:10.101399 cs0 AddrBus test pass
660 22:30:10.101810 cs1 AddrBus test pass
661 22:30:10.102214
662 22:30:10.106471 100bdlr_step_size ps== 485
663 22:30:10.106930 result report
664 22:30:10.112079 boot times 0Enable ddr reg access
665 22:30:10.117269 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 22:30:10.131127 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 22:30:10.790995 bl2z: ptr: 05129330, size: 00001e40
668 22:30:10.800933 0.0;M3 CHK:0;cm4_sp_mode 0
669 22:30:10.801455 MVN_1=0x00000000
670 22:30:10.801868 MVN_2=0x00000000
671 22:30:10.812441 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 22:30:10.812944 OPS=0x04
673 22:30:10.813366 ring efuse init
674 22:30:10.815206 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 22:30:10.825924 [0.017354 Inits done]
676 22:30:10.826372 secure task start!
677 22:30:10.826778 high task start!
678 22:30:10.827180 low task start!
679 22:30:10.827575 run into bl31
680 22:30:10.834390 NOTICE: BL31: v1.3(release):4fc40b1
681 22:30:10.842164 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 22:30:10.842619 NOTICE: BL31: G12A normal boot!
683 22:30:10.857801 NOTICE: BL31: BL33 decompress pass
684 22:30:10.863466 ERROR: Error initializing runtime service opteed_fast
685 22:30:11.659093
686 22:30:11.659702
687 22:30:11.664352 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 22:30:11.664822
689 22:30:11.667817 Model: Libre Computer AML-S905D3-CC Solitude
690 22:30:11.815165 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 22:30:11.830473 DRAM: 2 GiB (effective 3.8 GiB)
692 22:30:11.931549 Core: 406 devices, 33 uclasses, devicetree: separate
693 22:30:11.937275 WDT: Not starting watchdog@f0d0
694 22:30:11.962375 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 22:30:11.974540 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 22:30:11.979592 ** Bad device specification mmc 0 **
697 22:30:11.989478 Card did not respond to voltage select! : -110
698 22:30:11.997264 ** Bad device specification mmc 0 **
699 22:30:11.997713 Couldn't find partition mmc 0
700 22:30:12.005534 Card did not respond to voltage select! : -110
701 22:30:12.010981 ** Bad device specification mmc 0 **
702 22:30:12.011296 Couldn't find partition mmc 0
703 22:30:12.016121 Error: could not access storage.
704 22:30:12.312554 Net: eth0: ethernet@ff3f0000
705 22:30:12.313101 starting USB...
706 22:30:12.557284 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 22:30:12.557704 Starting the controller
708 22:30:12.564231 USB XHCI 1.10
709 22:30:14.118179 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 22:30:14.126442 scanning usb for storage devices... 0 Storage Device(s) found
712 22:30:14.178013 Hit any key to stop autoboot: 1
713 22:30:14.178938 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 22:30:14.179580 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 22:30:14.180114 Setting prompt string to ['=>']
716 22:30:14.180614 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 22:30:14.192578 0
718 22:30:14.193578 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 22:30:14.294896 => setenv autoload no
721 22:30:14.295704 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 22:30:14.300821 setenv autoload no
724 22:30:14.402350 => setenv initrd_high 0xffffffff
725 22:30:14.403313 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 22:30:14.408049 setenv initrd_high 0xffffffff
728 22:30:14.509566 => setenv fdt_high 0xffffffff
729 22:30:14.510530 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 22:30:14.515330 setenv fdt_high 0xffffffff
732 22:30:14.616919 => dhcp
733 22:30:14.617684 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 22:30:14.621691 dhcp
735 22:30:15.416607 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. Connection closed by foreign host.
737 22:30:15.419207 end: 2.4.3 bootloader-commands (duration 00:00:01) [common]
740 22:30:15.421606 end: 2.4 uboot-commands (duration 00:00:20) [common]
742 22:30:15.423336 uboot-action failed: 1 of 1 attempts. 'Connection closed'
744 22:30:15.424713 end: 2 uboot-action (duration 00:00:20) [common]
746 22:30:15.426681 Cleaning after the job
747 22:30:15.427405 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/ramdisk
748 22:30:15.444408 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/kernel
749 22:30:15.488042 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/dtb
750 22:30:15.489131 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/847809/tftp-deploy-jblhgcpr/modules
751 22:30:15.510752 start: 4.1 power-off (timeout 00:00:30) [common]
752 22:30:15.511550 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
753 22:30:15.540799 >> curl: (7) Failed to connect to conserv1.mayfield.sirena.org.uk port 16421 after 2 ms: Couldn't connect to server
754 22:30:15.542669 Returned 7 in 0 seconds
755 22:30:15.543006 Unable to run '['curl', 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01']'
757 22:30:15.543755 end: 4.1 power-off (duration 00:00:00) [common]
759 22:30:15.544717 Failed to run 'finalize': Unable to power-off: 'curl http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix\&port=solitude-01' failed
761 22:30:15.654502 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/847809
762 22:30:15.984012 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/847809
763 22:30:15.984679 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.