Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:47:37.281782 lava-dispatcher, installed at version: 2024.01
2 22:47:37.282596 start: 0 validate
3 22:47:37.283103 Start time: 2024-10-15 22:47:37.283071+00:00 (UTC)
4 22:47:37.283651 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:47:37.284232 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 22:47:37.327710 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:47:37.328307 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241015%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 22:47:37.361121 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:47:37.361767 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241015%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:47:38.418234 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:47:38.418747 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241015%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 22:47:38.468881 validate duration: 1.19
14 22:47:38.470804 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:47:38.471618 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:47:38.472416 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:47:38.473646 Not decompressing ramdisk as can be used compressed.
18 22:47:38.474605 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 22:47:38.475194 saving as /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/ramdisk/rootfs.cpio.gz
20 22:47:38.475824 total size: 8181887 (7 MB)
21 22:47:38.521650 progress 0 % (0 MB)
22 22:47:38.534022 progress 5 % (0 MB)
23 22:47:38.545739 progress 10 % (0 MB)
24 22:47:38.556948 progress 15 % (1 MB)
25 22:47:38.562550 progress 20 % (1 MB)
26 22:47:38.568405 progress 25 % (1 MB)
27 22:47:38.573794 progress 30 % (2 MB)
28 22:47:38.579676 progress 35 % (2 MB)
29 22:47:38.585052 progress 40 % (3 MB)
30 22:47:38.591057 progress 45 % (3 MB)
31 22:47:38.596731 progress 50 % (3 MB)
32 22:47:38.602856 progress 55 % (4 MB)
33 22:47:38.608534 progress 60 % (4 MB)
34 22:47:38.614453 progress 65 % (5 MB)
35 22:47:38.620079 progress 70 % (5 MB)
36 22:47:38.626112 progress 75 % (5 MB)
37 22:47:38.631668 progress 80 % (6 MB)
38 22:47:38.637687 progress 85 % (6 MB)
39 22:47:38.643263 progress 90 % (7 MB)
40 22:47:38.649209 progress 95 % (7 MB)
41 22:47:38.654586 progress 100 % (7 MB)
42 22:47:38.655330 7 MB downloaded in 0.18 s (43.47 MB/s)
43 22:47:38.655898 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:47:38.656830 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:47:38.657125 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:47:38.657397 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:47:38.657897 downloading http://storage.kernelci.org/next/master/next-20241015/arm64/defconfig+debug/gcc-12/kernel/Image
49 22:47:38.658148 saving as /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/kernel/Image
50 22:47:38.658359 total size: 170398208 (162 MB)
51 22:47:38.658572 No compression specified
52 22:47:38.697453 progress 0 % (0 MB)
53 22:47:38.802006 progress 5 % (8 MB)
54 22:47:38.904999 progress 10 % (16 MB)
55 22:47:39.012967 progress 15 % (24 MB)
56 22:47:39.117791 progress 20 % (32 MB)
57 22:47:39.222032 progress 25 % (40 MB)
58 22:47:39.326437 progress 30 % (48 MB)
59 22:47:39.431073 progress 35 % (56 MB)
60 22:47:39.534739 progress 40 % (65 MB)
61 22:47:39.649211 progress 45 % (73 MB)
62 22:47:39.753095 progress 50 % (81 MB)
63 22:47:39.857474 progress 55 % (89 MB)
64 22:47:39.960790 progress 60 % (97 MB)
65 22:47:40.064280 progress 65 % (105 MB)
66 22:47:40.167715 progress 70 % (113 MB)
67 22:47:40.270734 progress 75 % (121 MB)
68 22:47:40.373563 progress 80 % (130 MB)
69 22:47:40.476372 progress 85 % (138 MB)
70 22:47:40.579328 progress 90 % (146 MB)
71 22:47:40.695853 progress 95 % (154 MB)
72 22:47:40.799509 progress 100 % (162 MB)
73 22:47:40.800106 162 MB downloaded in 2.14 s (75.88 MB/s)
74 22:47:40.800590 end: 1.2.1 http-download (duration 00:00:02) [common]
76 22:47:40.801404 end: 1.2 download-retry (duration 00:00:02) [common]
77 22:47:40.801680 start: 1.3 download-retry (timeout 00:09:58) [common]
78 22:47:40.801944 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 22:47:40.802395 downloading http://storage.kernelci.org/next/master/next-20241015/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 22:47:40.802663 saving as /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/dtb/meson-g12b-a311d-libretech-cc.dtb
81 22:47:40.802872 total size: 54703 (0 MB)
82 22:47:40.803084 No compression specified
83 22:47:40.838893 progress 59 % (0 MB)
84 22:47:40.839732 progress 100 % (0 MB)
85 22:47:40.840314 0 MB downloaded in 0.04 s (1.39 MB/s)
86 22:47:40.840814 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:47:40.841629 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:47:40.841892 start: 1.4 download-retry (timeout 00:09:58) [common]
90 22:47:40.842158 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 22:47:40.842643 downloading http://storage.kernelci.org/next/master/next-20241015/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 22:47:40.842891 saving as /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/modules/modules.tar
93 22:47:40.843099 total size: 27688688 (26 MB)
94 22:47:40.843308 Using unxz to decompress xz
95 22:47:40.880458 progress 0 % (0 MB)
96 22:47:41.076780 progress 5 % (1 MB)
97 22:47:41.290470 progress 10 % (2 MB)
98 22:47:41.511890 progress 15 % (3 MB)
99 22:47:41.709431 progress 20 % (5 MB)
100 22:47:41.919116 progress 25 % (6 MB)
101 22:47:42.123540 progress 30 % (7 MB)
102 22:47:42.339825 progress 35 % (9 MB)
103 22:47:42.544948 progress 40 % (10 MB)
104 22:47:42.765164 progress 45 % (11 MB)
105 22:47:42.968126 progress 50 % (13 MB)
106 22:47:43.172821 progress 55 % (14 MB)
107 22:47:43.374799 progress 60 % (15 MB)
108 22:47:43.588902 progress 65 % (17 MB)
109 22:47:43.785371 progress 70 % (18 MB)
110 22:47:43.997778 progress 75 % (19 MB)
111 22:47:44.206596 progress 80 % (21 MB)
112 22:47:44.417070 progress 85 % (22 MB)
113 22:47:44.601588 progress 90 % (23 MB)
114 22:47:44.836776 progress 95 % (25 MB)
115 22:47:45.071256 progress 100 % (26 MB)
116 22:47:45.088886 26 MB downloaded in 4.25 s (6.22 MB/s)
117 22:47:45.089576 end: 1.4.1 http-download (duration 00:00:04) [common]
119 22:47:45.090432 end: 1.4 download-retry (duration 00:00:04) [common]
120 22:47:45.090710 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 22:47:45.090980 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 22:47:45.091233 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:47:45.091492 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 22:47:45.092360 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f
125 22:47:45.093352 makedir: /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin
126 22:47:45.094078 makedir: /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/tests
127 22:47:45.094766 makedir: /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/results
128 22:47:45.095450 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-add-keys
129 22:47:45.096569 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-add-sources
130 22:47:45.097641 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-background-process-start
131 22:47:45.098699 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-background-process-stop
132 22:47:45.099809 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-common-functions
133 22:47:45.100915 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-echo-ipv4
134 22:47:45.101932 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-install-packages
135 22:47:45.102940 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-installed-packages
136 22:47:45.103934 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-os-build
137 22:47:45.104984 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-probe-channel
138 22:47:45.105986 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-probe-ip
139 22:47:45.106975 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-target-ip
140 22:47:45.107943 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-target-mac
141 22:47:45.108973 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-target-storage
142 22:47:45.109964 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-test-case
143 22:47:45.110949 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-test-event
144 22:47:45.111915 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-test-feedback
145 22:47:45.112938 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-test-raise
146 22:47:45.113927 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-test-reference
147 22:47:45.114898 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-test-runner
148 22:47:45.115905 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-test-set
149 22:47:45.116930 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-test-shell
150 22:47:45.117912 Updating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-install-packages (oe)
151 22:47:45.118948 Updating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/bin/lava-installed-packages (oe)
152 22:47:45.119832 Creating /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/environment
153 22:47:45.120638 LAVA metadata
154 22:47:45.121166 - LAVA_JOB_ID=848140
155 22:47:45.121634 - LAVA_DISPATCHER_IP=192.168.6.2
156 22:47:45.122375 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 22:47:45.124460 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 22:47:45.125052 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 22:47:45.125467 skipped lava-vland-overlay
160 22:47:45.125957 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 22:47:45.126467 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 22:47:45.126890 skipped lava-multinode-overlay
163 22:47:45.127369 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 22:47:45.127865 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 22:47:45.128385 Loading test definitions
166 22:47:45.128930 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 22:47:45.129371 Using /lava-848140 at stage 0
168 22:47:45.131596 uuid=848140_1.5.2.4.1 testdef=None
169 22:47:45.132144 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 22:47:45.132424 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 22:47:45.134222 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 22:47:45.135020 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 22:47:45.137265 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 22:47:45.138104 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 22:47:45.140289 runner path: /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/0/tests/0_dmesg test_uuid 848140_1.5.2.4.1
178 22:47:45.140846 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 22:47:45.141614 Creating lava-test-runner.conf files
181 22:47:45.141818 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/848140/lava-overlay-e5wl617f/lava-848140/0 for stage 0
182 22:47:45.142148 - 0_dmesg
183 22:47:45.142492 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 22:47:45.142772 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 22:47:45.166497 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 22:47:45.166907 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 22:47:45.167174 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 22:47:45.167444 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 22:47:45.167708 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 22:47:46.103297 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 22:47:46.103756 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 22:47:46.104048 extracting modules file /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/848140/extract-overlay-ramdisk-0y_as84i/ramdisk
193 22:47:48.008739 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 22:47:48.009226 start: 1.5.5 apply-overlay-tftp (timeout 00:09:50) [common]
195 22:47:48.009501 [common] Applying overlay /var/lib/lava/dispatcher/tmp/848140/compress-overlay-saqk479j/overlay-1.5.2.5.tar.gz to ramdisk
196 22:47:48.009713 [common] Applying overlay /var/lib/lava/dispatcher/tmp/848140/compress-overlay-saqk479j/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/848140/extract-overlay-ramdisk-0y_as84i/ramdisk
197 22:47:48.039736 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 22:47:48.040184 start: 1.5.6 prepare-kernel (timeout 00:09:50) [common]
199 22:47:48.040459 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:50) [common]
200 22:47:48.040690 Converting downloaded kernel to a uImage
201 22:47:48.040991 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/kernel/Image /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/kernel/uImage
202 22:47:50.350155 output: Image Name:
203 22:47:50.350576 output: Created: Tue Oct 15 22:47:48 2024
204 22:47:50.350787 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 22:47:50.350991 output: Data Size: 170398208 Bytes = 166404.50 KiB = 162.50 MiB
206 22:47:50.351190 output: Load Address: 01080000
207 22:47:50.351387 output: Entry Point: 01080000
208 22:47:50.351582 output:
209 22:47:50.351916 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 22:47:50.352231 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 22:47:50.352504 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 22:47:50.352757 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 22:47:50.353013 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 22:47:50.353269 Building ramdisk /var/lib/lava/dispatcher/tmp/848140/extract-overlay-ramdisk-0y_as84i/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/848140/extract-overlay-ramdisk-0y_as84i/ramdisk
215 22:47:55.866918 >> 441959 blocks
216 22:48:14.534172 Adding RAMdisk u-boot header.
217 22:48:14.534848 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/848140/extract-overlay-ramdisk-0y_as84i/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/848140/extract-overlay-ramdisk-0y_as84i/ramdisk.cpio.gz.uboot
218 22:48:15.089396 output: Image Name:
219 22:48:15.089797 output: Created: Tue Oct 15 22:48:14 2024
220 22:48:15.090005 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 22:48:15.090210 output: Data Size: 53672514 Bytes = 52414.56 KiB = 51.19 MiB
222 22:48:15.090410 output: Load Address: 00000000
223 22:48:15.090608 output: Entry Point: 00000000
224 22:48:15.090805 output:
225 22:48:15.091457 rename /var/lib/lava/dispatcher/tmp/848140/extract-overlay-ramdisk-0y_as84i/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/ramdisk/ramdisk.cpio.gz.uboot
226 22:48:15.091876 end: 1.5.8 compress-ramdisk (duration 00:00:25) [common]
227 22:48:15.092457 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
228 22:48:15.093056 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:23) [common]
229 22:48:15.093558 No LXC device requested
230 22:48:15.094103 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 22:48:15.094659 start: 1.7 deploy-device-env (timeout 00:09:23) [common]
232 22:48:15.095195 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 22:48:15.095648 Checking files for TFTP limit of 4294967296 bytes.
234 22:48:15.098583 end: 1 tftp-deploy (duration 00:00:37) [common]
235 22:48:15.099204 start: 2 uboot-action (timeout 00:05:00) [common]
236 22:48:15.099775 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 22:48:15.100357 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 22:48:15.100911 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 22:48:15.101490 Using kernel file from prepare-kernel: 848140/tftp-deploy-6y3ttapl/kernel/uImage
240 22:48:15.102164 substitutions:
241 22:48:15.102615 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 22:48:15.103061 - {DTB_ADDR}: 0x01070000
243 22:48:15.103496 - {DTB}: 848140/tftp-deploy-6y3ttapl/dtb/meson-g12b-a311d-libretech-cc.dtb
244 22:48:15.103935 - {INITRD}: 848140/tftp-deploy-6y3ttapl/ramdisk/ramdisk.cpio.gz.uboot
245 22:48:15.104404 - {KERNEL_ADDR}: 0x01080000
246 22:48:15.104838 - {KERNEL}: 848140/tftp-deploy-6y3ttapl/kernel/uImage
247 22:48:15.105274 - {LAVA_MAC}: None
248 22:48:15.105746 - {PRESEED_CONFIG}: None
249 22:48:15.106179 - {PRESEED_LOCAL}: None
250 22:48:15.106608 - {RAMDISK_ADDR}: 0x08000000
251 22:48:15.107032 - {RAMDISK}: 848140/tftp-deploy-6y3ttapl/ramdisk/ramdisk.cpio.gz.uboot
252 22:48:15.107464 - {ROOT_PART}: None
253 22:48:15.107894 - {ROOT}: None
254 22:48:15.108355 - {SERVER_IP}: 192.168.6.2
255 22:48:15.108793 - {TEE_ADDR}: 0x83000000
256 22:48:15.109222 - {TEE}: None
257 22:48:15.109650 Parsed boot commands:
258 22:48:15.110065 - setenv autoload no
259 22:48:15.110492 - setenv initrd_high 0xffffffff
260 22:48:15.110918 - setenv fdt_high 0xffffffff
261 22:48:15.111344 - dhcp
262 22:48:15.111767 - setenv serverip 192.168.6.2
263 22:48:15.112226 - tftpboot 0x01080000 848140/tftp-deploy-6y3ttapl/kernel/uImage
264 22:48:15.112658 - tftpboot 0x08000000 848140/tftp-deploy-6y3ttapl/ramdisk/ramdisk.cpio.gz.uboot
265 22:48:15.113091 - tftpboot 0x01070000 848140/tftp-deploy-6y3ttapl/dtb/meson-g12b-a311d-libretech-cc.dtb
266 22:48:15.113520 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 22:48:15.113952 - bootm 0x01080000 0x08000000 0x01070000
268 22:48:15.114487 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 22:48:15.116132 start: 2.3 connect-device (timeout 00:05:00) [common]
271 22:48:15.116622 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 22:48:15.130961 Setting prompt string to ['lava-test: # ']
273 22:48:15.132577 end: 2.3 connect-device (duration 00:00:00) [common]
274 22:48:15.133232 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 22:48:15.133906 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 22:48:15.134557 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 22:48:15.135830 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 22:48:17.212346 >> OK - accepted request
279 22:48:17.214189 Returned 0 in 2 seconds
280 22:48:17.315402 end: 2.4.1.1 pdu-reboot (duration 00:00:02) [common]
282 22:48:17.317229 end: 2.4.1 reset-device (duration 00:00:02) [common]
283 22:48:17.317850 start: 2.4.2 bootloader-interrupt (timeout 00:04:58) [common]
284 22:48:17.318396 Setting prompt string to ['Hit any key to stop autoboot']
285 22:48:17.318893 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 22:48:17.320596 Trying 192.168.56.21...
287 22:48:17.321106 Connected to conserv1.
288 22:48:17.321548 Escape character is '^]'.
289 22:48:17.322009
290 22:48:17.322475 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 22:48:17.322935
292 22:48:28.833967 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 22:48:28.834647 bl2_stage_init 0x01
294 22:48:28.835151 bl2_stage_init 0x81
295 22:48:28.839196 hw id: 0x0000 - pwm id 0x01
296 22:48:28.839774 bl2_stage_init 0xc1
297 22:48:28.840288 bl2_stage_init 0x02
298 22:48:28.840745
299 22:48:28.845119 L0:00000000
300 22:48:28.845598 L1:20000703
301 22:48:28.846032 L2:00008067
302 22:48:28.846459 L3:14000000
303 22:48:28.850649 B2:00402000
304 22:48:28.851114 B1:e0f83180
305 22:48:28.851542
306 22:48:28.851973 TE: 58124
307 22:48:28.852440
308 22:48:28.855969 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 22:48:28.856464
310 22:48:28.856894 Board ID = 1
311 22:48:28.861666 Set A53 clk to 24M
312 22:48:28.862127 Set A73 clk to 24M
313 22:48:28.862553 Set clk81 to 24M
314 22:48:28.867170 A53 clk: 1200 MHz
315 22:48:28.867625 A73 clk: 1200 MHz
316 22:48:28.868085 CLK81: 166.6M
317 22:48:28.868514 smccc: 00012a92
318 22:48:28.872844 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 22:48:28.878463 board id: 1
320 22:48:28.884334 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 22:48:28.894970 fw parse done
322 22:48:28.901056 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 22:48:28.954501 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 22:48:28.955063 PIEI prepare done
325 22:48:28.955500 fastboot data load
326 22:48:28.955929 fastboot data verify
327 22:48:28.960108 verify result: 266
328 22:48:28.965573 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 22:48:28.966054 LPDDR4 probe
330 22:48:28.966481 ddr clk to 1584MHz
331 22:48:28.973660 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 22:48:29.010884
333 22:48:29.011368 dmc_version 0001
334 22:48:29.017578 Check phy result
335 22:48:29.023418 INFO : End of CA training
336 22:48:29.023907 INFO : End of initialization
337 22:48:29.029066 INFO : Training has run successfully!
338 22:48:29.029534 Check phy result
339 22:48:29.034577 INFO : End of initialization
340 22:48:29.035045 INFO : End of read enable training
341 22:48:29.040243 INFO : End of fine write leveling
342 22:48:29.045790 INFO : End of Write leveling coarse delay
343 22:48:29.046258 INFO : Training has run successfully!
344 22:48:29.046694 Check phy result
345 22:48:29.051389 INFO : End of initialization
346 22:48:29.051858 INFO : End of read dq deskew training
347 22:48:29.056974 INFO : End of MPR read delay center optimization
348 22:48:29.062575 INFO : End of write delay center optimization
349 22:48:29.068193 INFO : End of read delay center optimization
350 22:48:29.068662 INFO : End of max read latency training
351 22:48:29.073752 INFO : Training has run successfully!
352 22:48:29.074214 1D training succeed
353 22:48:29.083053 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 22:48:29.130639 Check phy result
355 22:48:29.131196 INFO : End of initialization
356 22:48:29.152269 INFO : End of 2D read delay Voltage center optimization
357 22:48:29.172488 INFO : End of 2D read delay Voltage center optimization
358 22:48:29.224585 INFO : End of 2D write delay Voltage center optimization
359 22:48:29.273907 INFO : End of 2D write delay Voltage center optimization
360 22:48:29.285239 INFO : Training has run successfully!
361 22:48:29.285773
362 22:48:29.286215 channel==0
363 22:48:29.286645 RxClkDly_Margin_A0==88 ps 9
364 22:48:29.287076 TxDqDly_Margin_A0==98 ps 10
365 22:48:29.290664 RxClkDly_Margin_A1==88 ps 9
366 22:48:29.291143 TxDqDly_Margin_A1==98 ps 10
367 22:48:29.291581 TrainedVREFDQ_A0==74
368 22:48:29.296277 TrainedVREFDQ_A1==74
369 22:48:29.296771 VrefDac_Margin_A0==25
370 22:48:29.297204 DeviceVref_Margin_A0==40
371 22:48:29.301892 VrefDac_Margin_A1==25
372 22:48:29.302364 DeviceVref_Margin_A1==40
373 22:48:29.302798
374 22:48:29.303230
375 22:48:29.307478 channel==1
376 22:48:29.307959 RxClkDly_Margin_A0==98 ps 10
377 22:48:29.308433 TxDqDly_Margin_A0==98 ps 10
378 22:48:29.313082 RxClkDly_Margin_A1==98 ps 10
379 22:48:29.313436 TxDqDly_Margin_A1==88 ps 9
380 22:48:29.318659 TrainedVREFDQ_A0==77
381 22:48:29.319140 TrainedVREFDQ_A1==77
382 22:48:29.319573 VrefDac_Margin_A0==22
383 22:48:29.324272 DeviceVref_Margin_A0==37
384 22:48:29.324739 VrefDac_Margin_A1==22
385 22:48:29.329874 DeviceVref_Margin_A1==37
386 22:48:29.330346
387 22:48:29.330785 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 22:48:29.335487
389 22:48:29.363447 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 22:48:29.364031 2D training succeed
391 22:48:29.369055 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 22:48:29.374666 auto size-- 65535DDR cs0 size: 2048MB
393 22:48:29.375130 DDR cs1 size: 2048MB
394 22:48:29.380246 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 22:48:29.380706 cs0 DataBus test pass
396 22:48:29.385934 cs1 DataBus test pass
397 22:48:29.386402 cs0 AddrBus test pass
398 22:48:29.386828 cs1 AddrBus test pass
399 22:48:29.387257
400 22:48:29.391473 100bdlr_step_size ps== 420
401 22:48:29.391951 result report
402 22:48:29.397063 boot times 0Enable ddr reg access
403 22:48:29.402510 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 22:48:29.416019 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 22:48:29.989799 0.0;M3 CHK:0;cm4_sp_mode 0
406 22:48:29.990211 MVN_1=0x00000000
407 22:48:29.995103 MVN_2=0x00000000
408 22:48:30.000883 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 22:48:30.001129 OPS=0x10
410 22:48:30.001345 ring efuse init
411 22:48:30.001550 chipver efuse init
412 22:48:30.012225 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 22:48:30.012465 [0.018961 Inits done]
414 22:48:30.012860 secure task start!
415 22:48:30.013261 high task start!
416 22:48:30.016676 low task start!
417 22:48:30.017101 run into bl31
418 22:48:30.023425 NOTICE: BL31: v1.3(release):4fc40b1
419 22:48:30.031166 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 22:48:30.031665 NOTICE: BL31: G12A normal boot!
421 22:48:30.056529 NOTICE: BL31: BL33 decompress pass
422 22:48:30.062264 ERROR: Error initializing runtime service opteed_fast
423 22:48:31.295141
424 22:48:31.295558
425 22:48:31.303445 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 22:48:31.303815
427 22:48:31.304176 Model: Libre Computer AML-A311D-CC Alta
428 22:48:31.511925 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 22:48:31.535262 DRAM: 2 GiB (effective 3.8 GiB)
430 22:48:31.678330 Core: 408 devices, 31 uclasses, devicetree: separate
431 22:48:31.684272 WDT: Not starting watchdog@f0d0
432 22:48:31.716447 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 22:48:31.728847 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 22:48:31.733834 ** Bad device specification mmc 0 **
435 22:48:31.744172 Card did not respond to voltage select! : -110
436 22:48:31.751782 ** Bad device specification mmc 0 **
437 22:48:31.752305 Couldn't find partition mmc 0
438 22:48:31.760186 Card did not respond to voltage select! : -110
439 22:48:31.765649 ** Bad device specification mmc 0 **
440 22:48:31.766133 Couldn't find partition mmc 0
441 22:48:31.770713 Error: could not access storage.
442 22:48:33.034229 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 22:48:33.034854 bl2_stage_init 0x01
444 22:48:33.035336 bl2_stage_init 0x81
445 22:48:33.251100 hw id: 0x0000 - pwm id 0x01
446 22:48:33.251763 bl2_stage_init 0xc1
447 22:48:33.252282 bl2_stage_init 0x02
448 22:48:33.252742
449 22:48:33.253195 L0:00000000
450 22:48:33.253640 L1:20000703
451 22:48:33.254078 L2:00008067
452 22:48:33.254515 L3:14000000
453 22:48:33.255396 B2:00402000
454 22:48:33.255869 B1:e0f83180
455 22:48:33.256348
456 22:48:33.256793 TE: 58167
457 22:48:33.257237
458 22:48:33.257672 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 22:48:33.258106
460 22:48:33.258538 Board ID = 1
461 22:48:33.258968 Set A53 clk to 24M
462 22:48:33.259398 Set A73 clk to 24M
463 22:48:33.259836 Set clk81 to 24M
464 22:48:33.260299 A53 clk: 1200 MHz
465 22:48:33.260736 A73 clk: 1200 MHz
466 22:48:33.261165 CLK81: 166.6M
467 22:48:33.261595 smccc: 00012abd
468 22:48:33.262025 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 22:48:33.262457 board id: 1
470 22:48:33.262881 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 22:48:33.263318 fw parse done
472 22:48:33.263749 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 22:48:33.264213 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 22:48:33.264651 PIEI prepare done
475 22:48:33.265078 fastboot data load
476 22:48:33.265509 fastboot data verify
477 22:48:33.265939 verify result: 266
478 22:48:33.266364 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 22:48:33.266787 LPDDR4 probe
480 22:48:33.267211 ddr clk to 1584MHz
481 22:48:33.267633 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 22:48:33.268082
483 22:48:33.268521 dmc_version 0001
484 22:48:33.268951 Check phy result
485 22:48:33.269377 INFO : End of CA training
486 22:48:33.269804 INFO : End of initialization
487 22:48:33.270227 INFO : Training has run successfully!
488 22:48:33.270651 Check phy result
489 22:48:33.271072 INFO : End of initialization
490 22:48:33.271493 INFO : End of read enable training
491 22:48:33.271919 INFO : End of fine write leveling
492 22:48:33.272379 INFO : End of Write leveling coarse delay
493 22:48:33.272810 INFO : Training has run successfully!
494 22:48:33.273236 Check phy result
495 22:48:33.273656 INFO : End of initialization
496 22:48:33.274077 INFO : End of read dq deskew training
497 22:48:33.274615 INFO : End of MPR read delay center optimization
498 22:48:33.275055 INFO : End of write delay center optimization
499 22:48:33.275491 INFO : End of read delay center optimization
500 22:48:33.275915 INFO : End of max read latency training
501 22:48:33.276371 INFO : Training has run successfully!
502 22:48:33.276798 1D training succeed
503 22:48:33.283575 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 22:48:33.331190 Check phy result
505 22:48:33.331712 INFO : End of initialization
506 22:48:33.353563 INFO : End of 2D read delay Voltage center optimization
507 22:48:33.373645 INFO : End of 2D read delay Voltage center optimization
508 22:48:33.425615 INFO : End of 2D write delay Voltage center optimization
509 22:48:33.474847 INFO : End of 2D write delay Voltage center optimization
510 22:48:33.480387 INFO : Training has run successfully!
511 22:48:33.480928
512 22:48:33.481355 channel==0
513 22:48:33.485907 RxClkDly_Margin_A0==88 ps 9
514 22:48:33.486357 TxDqDly_Margin_A0==98 ps 10
515 22:48:33.491574 RxClkDly_Margin_A1==88 ps 9
516 22:48:33.492044 TxDqDly_Margin_A1==98 ps 10
517 22:48:33.492471 TrainedVREFDQ_A0==74
518 22:48:33.497184 TrainedVREFDQ_A1==74
519 22:48:33.497648 VrefDac_Margin_A0==24
520 22:48:33.498069 DeviceVref_Margin_A0==40
521 22:48:33.502858 VrefDac_Margin_A1==24
522 22:48:33.503302 DeviceVref_Margin_A1==40
523 22:48:33.503712
524 22:48:33.504150
525 22:48:33.508385 channel==1
526 22:48:33.508830 RxClkDly_Margin_A0==98 ps 10
527 22:48:33.509243 TxDqDly_Margin_A0==98 ps 10
528 22:48:33.513966 RxClkDly_Margin_A1==88 ps 9
529 22:48:33.514406 TxDqDly_Margin_A1==88 ps 9
530 22:48:33.519571 TrainedVREFDQ_A0==77
531 22:48:33.520030 TrainedVREFDQ_A1==77
532 22:48:33.520450 VrefDac_Margin_A0==22
533 22:48:33.525167 DeviceVref_Margin_A0==37
534 22:48:33.525600 VrefDac_Margin_A1==24
535 22:48:33.530803 DeviceVref_Margin_A1==37
536 22:48:33.531236
537 22:48:33.531647 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 22:48:33.532087
539 22:48:33.564408 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 22:48:33.564903 2D training succeed
541 22:48:33.570029 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 22:48:33.575605 auto size-- 65535DDR cs0 size: 2048MB
543 22:48:33.576084 DDR cs1 size: 2048MB
544 22:48:33.581209 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 22:48:33.581663 cs0 DataBus test pass
546 22:48:33.586810 cs1 DataBus test pass
547 22:48:33.587268 cs0 AddrBus test pass
548 22:48:33.587681 cs1 AddrBus test pass
549 22:48:33.588114
550 22:48:33.592406 100bdlr_step_size ps== 420
551 22:48:33.592864 result report
552 22:48:33.597993 boot times 0Enable ddr reg access
553 22:48:33.603411 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 22:48:33.616811 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 22:48:34.189012 0.0;M3 CHK:0;cm4_sp_mode 0
556 22:48:34.189588 MVN_1=0x00000000
557 22:48:34.194483 MVN_2=0x00000000
558 22:48:34.200355 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 22:48:34.200836 OPS=0x10
560 22:48:34.201258 ring efuse init
561 22:48:34.201669 chipver efuse init
562 22:48:34.206014 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 22:48:34.216179 [0.018961 Inits done]
564 22:48:34.216602 secure task start!
565 22:48:34.216983 high task start!
566 22:48:34.217360 low task start!
567 22:48:34.217739 run into bl31
568 22:48:34.222639 NOTICE: BL31: v1.3(release):4fc40b1
569 22:48:34.230476 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 22:48:34.230917 NOTICE: BL31: G12A normal boot!
571 22:48:34.255823 NOTICE: BL31: BL33 decompress pass
572 22:48:34.261473 ERROR: Error initializing runtime service opteed_fast
573 22:48:35.494766
574 22:48:35.495360
575 22:48:35.711048 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 22:48:35.711608
577 22:48:35.712085 Model: Libre Computer AML-A311D-CC Alta
578 22:48:35.712841 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 22:48:35.734795 DRAM: 2 GiB (effective 3.8 GiB)
580 22:48:35.883699 Core: 408 devices, 31 uclasses, devicetree: separate
581 22:48:35.884240 WDT: Not starting watchdog@f0d0
582 22:48:35.915868 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 22:48:35.928553 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 22:48:35.933241 ** Bad device specification mmc 0 **
585 22:48:35.943570 Card did not respond to voltage select! : -110
586 22:48:35.951204 ** Bad device specification mmc 0 **
587 22:48:35.951637 Couldn't find partition mmc 0
588 22:48:35.959787 Card did not respond to voltage select! : -110
589 22:48:35.965298 ** Bad device specification mmc 0 **
590 22:48:35.965735 Couldn't find partition mmc 0
591 22:48:35.970261 Error: could not access storage.
592 22:48:36.313718 Net: eth0: ethernet@ff3f0000
593 22:48:36.314279 starting USB...
594 22:48:36.565533 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 22:48:36.566076 Starting the controller
596 22:48:36.572474 USB XHCI 1.10
597 22:48:38.285216 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 22:48:38.285833 bl2_stage_init 0x01
599 22:48:38.286277 bl2_stage_init 0x81
600 22:48:38.290831 hw id: 0x0000 - pwm id 0x01
601 22:48:38.291307 bl2_stage_init 0xc1
602 22:48:38.291741 bl2_stage_init 0x02
603 22:48:38.292225
604 22:48:38.296251 L0:00000000
605 22:48:38.296731 L1:20000703
606 22:48:38.297148 L2:00008067
607 22:48:38.297543 L3:14000000
608 22:48:38.299271 B2:00402000
609 22:48:38.299716 B1:e0f83180
610 22:48:38.300159
611 22:48:38.300582 TE: 58124
612 22:48:38.300990
613 22:48:38.310368 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 22:48:38.310939
615 22:48:38.311427 Board ID = 1
616 22:48:38.312078 Set A53 clk to 24M
617 22:48:38.312547 Set A73 clk to 24M
618 22:48:38.316101 Set clk81 to 24M
619 22:48:38.316632 A53 clk: 1200 MHz
620 22:48:38.317090 A73 clk: 1200 MHz
621 22:48:38.321637 CLK81: 166.6M
622 22:48:38.322169 smccc: 00012a92
623 22:48:38.327199 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 22:48:38.327727 board id: 1
625 22:48:38.335939 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 22:48:38.346470 fw parse done
627 22:48:38.352479 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 22:48:38.395012 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 22:48:38.405971 PIEI prepare done
630 22:48:38.406519 fastboot data load
631 22:48:38.407156 fastboot data verify
632 22:48:38.411597 verify result: 266
633 22:48:38.417209 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 22:48:38.417754 LPDDR4 probe
635 22:48:38.418211 ddr clk to 1584MHz
636 22:48:38.425070 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 22:48:38.462377
638 22:48:38.462967 dmc_version 0001
639 22:48:38.469134 Check phy result
640 22:48:38.474949 INFO : End of CA training
641 22:48:38.475507 INFO : End of initialization
642 22:48:38.480531 INFO : Training has run successfully!
643 22:48:38.481085 Check phy result
644 22:48:38.486112 INFO : End of initialization
645 22:48:38.486655 INFO : End of read enable training
646 22:48:38.489431 INFO : End of fine write leveling
647 22:48:38.494977 INFO : End of Write leveling coarse delay
648 22:48:38.500595 INFO : Training has run successfully!
649 22:48:38.501193 Check phy result
650 22:48:38.501851 INFO : End of initialization
651 22:48:38.506172 INFO : End of read dq deskew training
652 22:48:38.511801 INFO : End of MPR read delay center optimization
653 22:48:38.512391 INFO : End of write delay center optimization
654 22:48:38.517332 INFO : End of read delay center optimization
655 22:48:38.522932 INFO : End of max read latency training
656 22:48:38.523476 INFO : Training has run successfully!
657 22:48:38.528522 1D training succeed
658 22:48:38.534485 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 22:48:38.582032 Check phy result
660 22:48:38.582595 INFO : End of initialization
661 22:48:38.604512 INFO : End of 2D read delay Voltage center optimization
662 22:48:38.624628 INFO : End of 2D read delay Voltage center optimization
663 22:48:38.676610 INFO : End of 2D write delay Voltage center optimization
664 22:48:38.725848 INFO : End of 2D write delay Voltage center optimization
665 22:48:38.731454 INFO : Training has run successfully!
666 22:48:38.732042
667 22:48:38.732553 channel==0
668 22:48:38.737054 RxClkDly_Margin_A0==88 ps 9
669 22:48:38.737601 TxDqDly_Margin_A0==98 ps 10
670 22:48:38.740468 RxClkDly_Margin_A1==88 ps 9
671 22:48:38.741000 TxDqDly_Margin_A1==98 ps 10
672 22:48:38.746012 TrainedVREFDQ_A0==74
673 22:48:38.746555 TrainedVREFDQ_A1==75
674 22:48:38.747024 VrefDac_Margin_A0==24
675 22:48:38.751645 DeviceVref_Margin_A0==40
676 22:48:38.752214 VrefDac_Margin_A1==24
677 22:48:38.757225 DeviceVref_Margin_A1==39
678 22:48:38.757759
679 22:48:38.758219
680 22:48:38.758661 channel==1
681 22:48:38.759104 RxClkDly_Margin_A0==98 ps 10
682 22:48:38.760701 TxDqDly_Margin_A0==98 ps 10
683 22:48:38.766250 RxClkDly_Margin_A1==98 ps 10
684 22:48:38.766790 TxDqDly_Margin_A1==88 ps 9
685 22:48:38.767257 TrainedVREFDQ_A0==77
686 22:48:38.771893 TrainedVREFDQ_A1==77
687 22:48:38.772473 VrefDac_Margin_A0==22
688 22:48:38.777474 DeviceVref_Margin_A0==37
689 22:48:38.778012 VrefDac_Margin_A1==22
690 22:48:38.778465 DeviceVref_Margin_A1==37
691 22:48:38.778905
692 22:48:38.786262 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 22:48:38.786817
694 22:48:38.814221 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000016 00000018 00000015 00000017 00000018 00000017 00000018 00000018 0000001a 00000019 00000018 00000017 00000019 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
695 22:48:38.814840 2D training succeed
696 22:48:38.825392 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 22:48:38.825955 auto size-- 65535DDR cs0 size: 2048MB
698 22:48:38.826417 DDR cs1 size: 2048MB
699 22:48:38.831070 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 22:48:38.831608 cs0 DataBus test pass
701 22:48:38.836685 cs1 DataBus test pass
702 22:48:38.837250 cs0 AddrBus test pass
703 22:48:38.842257 cs1 AddrBus test pass
704 22:48:38.842801
705 22:48:38.843262 100bdlr_step_size ps== 420
706 22:48:38.843720 result report
707 22:48:38.847837 boot times 0Enable ddr reg access
708 22:48:38.854316 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 22:48:38.867812 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 22:48:39.439802 0.0;M3 CHK:0;cm4_sp_mode 0
711 22:48:39.440508 MVN_1=0x00000000
712 22:48:39.446278 MVN_2=0x00000000
713 22:48:39.451099 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 22:48:39.451730 OPS=0x10
715 22:48:39.452269 ring efuse init
716 22:48:39.452761 chipver efuse init
717 22:48:39.456643 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 22:48:39.462234 [0.018961 Inits done]
719 22:48:39.462794 secure task start!
720 22:48:39.463235 high task start!
721 22:48:39.473669 low task start!
722 22:48:39.474274 run into bl31
723 22:48:39.474786 NOTICE: BL31: v1.3(release):4fc40b1
724 22:48:39.481269 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 22:48:39.481846 NOTICE: BL31: G12A normal boot!
726 22:48:39.506680 NOTICE: BL31: BL33 decompress pass
727 22:48:39.512339 ERROR: Error initializing runtime service opteed_fast
728 22:48:40.745138
729 22:48:40.745808
730 22:48:40.753498 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 22:48:40.754006
732 22:48:40.754465 Model: Libre Computer AML-A311D-CC Alta
733 22:48:40.962007 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 22:48:40.985309 DRAM: 2 GiB (effective 3.8 GiB)
735 22:48:41.128314 Core: 408 devices, 31 uclasses, devicetree: separate
736 22:48:41.134126 WDT: Not starting watchdog@f0d0
737 22:48:41.166450 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 22:48:41.179032 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 22:48:41.183910 ** Bad device specification mmc 0 **
740 22:48:41.194244 Card did not respond to voltage select! : -110
741 22:48:41.201904 ** Bad device specification mmc 0 **
742 22:48:41.202423 Couldn't find partition mmc 0
743 22:48:41.210238 Card did not respond to voltage select! : -110
744 22:48:41.215759 ** Bad device specification mmc 0 **
745 22:48:41.216299 Couldn't find partition mmc 0
746 22:48:41.220810 Error: could not access storage.
747 22:48:41.563282 Net: eth0: ethernet@ff3f0000
748 22:48:41.563853 starting USB...
749 22:48:41.815134 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 22:48:41.815717 Starting the controller
751 22:48:41.822071 USB XHCI 1.10
752 22:48:43.984501 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 22:48:43.985136 bl2_stage_init 0x01
754 22:48:43.985602 bl2_stage_init 0x81
755 22:48:43.990080 hw id: 0x0000 - pwm id 0x01
756 22:48:43.990577 bl2_stage_init 0xc1
757 22:48:43.991028 bl2_stage_init 0x02
758 22:48:43.991471
759 22:48:43.995642 L0:00000000
760 22:48:43.996173 L1:20000703
761 22:48:43.996634 L2:00008067
762 22:48:43.997078 L3:14000000
763 22:48:43.998526 B2:00402000
764 22:48:43.999001 B1:e0f83180
765 22:48:43.999448
766 22:48:43.999890 TE: 58167
767 22:48:44.000377
768 22:48:44.009731 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 22:48:44.010227
770 22:48:44.010679 Board ID = 1
771 22:48:44.011116 Set A53 clk to 24M
772 22:48:44.011552 Set A73 clk to 24M
773 22:48:44.015320 Set clk81 to 24M
774 22:48:44.015803 A53 clk: 1200 MHz
775 22:48:44.016284 A73 clk: 1200 MHz
776 22:48:44.020918 CLK81: 166.6M
777 22:48:44.021399 smccc: 00012abe
778 22:48:44.026481 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 22:48:44.026964 board id: 1
780 22:48:44.045819 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 22:48:44.046325 fw parse done
782 22:48:44.051667 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 22:48:44.094313 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 22:48:44.105156 PIEI prepare done
785 22:48:44.105676 fastboot data load
786 22:48:44.106132 fastboot data verify
787 22:48:44.110849 verify result: 266
788 22:48:44.116455 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 22:48:44.116940 LPDDR4 probe
790 22:48:44.117387 ddr clk to 1584MHz
791 22:48:44.124429 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 22:48:44.161705
793 22:48:44.162201 dmc_version 0001
794 22:48:44.168390 Check phy result
795 22:48:44.174182 INFO : End of CA training
796 22:48:44.174667 INFO : End of initialization
797 22:48:44.179861 INFO : Training has run successfully!
798 22:48:44.180386 Check phy result
799 22:48:44.185454 INFO : End of initialization
800 22:48:44.185925 INFO : End of read enable training
801 22:48:44.188746 INFO : End of fine write leveling
802 22:48:44.194260 INFO : End of Write leveling coarse delay
803 22:48:44.199860 INFO : Training has run successfully!
804 22:48:44.200372 Check phy result
805 22:48:44.200823 INFO : End of initialization
806 22:48:44.205491 INFO : End of read dq deskew training
807 22:48:44.211078 INFO : End of MPR read delay center optimization
808 22:48:44.211561 INFO : End of write delay center optimization
809 22:48:44.216653 INFO : End of read delay center optimization
810 22:48:44.222348 INFO : End of max read latency training
811 22:48:44.222826 INFO : Training has run successfully!
812 22:48:44.227918 1D training succeed
813 22:48:44.233839 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 22:48:44.281468 Check phy result
815 22:48:44.281976 INFO : End of initialization
816 22:48:44.303186 INFO : End of 2D read delay Voltage center optimization
817 22:48:44.323459 INFO : End of 2D read delay Voltage center optimization
818 22:48:44.375547 INFO : End of 2D write delay Voltage center optimization
819 22:48:44.425017 INFO : End of 2D write delay Voltage center optimization
820 22:48:44.430572 INFO : Training has run successfully!
821 22:48:44.431072
822 22:48:44.431525 channel==0
823 22:48:44.436224 RxClkDly_Margin_A0==88 ps 9
824 22:48:44.436706 TxDqDly_Margin_A0==98 ps 10
825 22:48:44.439473 RxClkDly_Margin_A1==88 ps 9
826 22:48:44.439942 TxDqDly_Margin_A1==88 ps 9
827 22:48:44.445077 TrainedVREFDQ_A0==74
828 22:48:44.445571 TrainedVREFDQ_A1==74
829 22:48:44.446043 VrefDac_Margin_A0==25
830 22:48:44.450606 DeviceVref_Margin_A0==40
831 22:48:44.451133 VrefDac_Margin_A1==25
832 22:48:44.456281 DeviceVref_Margin_A1==40
833 22:48:44.456809
834 22:48:44.457239
835 22:48:44.457665 channel==1
836 22:48:44.458084 RxClkDly_Margin_A0==98 ps 10
837 22:48:44.459869 TxDqDly_Margin_A0==98 ps 10
838 22:48:44.465369 RxClkDly_Margin_A1==98 ps 10
839 22:48:44.465849 TxDqDly_Margin_A1==88 ps 9
840 22:48:44.466285 TrainedVREFDQ_A0==77
841 22:48:44.471101 TrainedVREFDQ_A1==77
842 22:48:44.471651 VrefDac_Margin_A0==22
843 22:48:44.476624 DeviceVref_Margin_A0==37
844 22:48:44.477125 VrefDac_Margin_A1==22
845 22:48:44.477553 DeviceVref_Margin_A1==37
846 22:48:44.477975
847 22:48:44.485600 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 22:48:44.486076
849 22:48:44.513600 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
850 22:48:44.514097 2D training succeed
851 22:48:44.519186 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 22:48:44.524749 auto size-- 65535DDR cs0 size: 2048MB
853 22:48:44.525230 DDR cs1 size: 2048MB
854 22:48:44.530389 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 22:48:44.530857 cs0 DataBus test pass
856 22:48:44.536004 cs1 DataBus test pass
857 22:48:44.536472 cs0 AddrBus test pass
858 22:48:44.536903 cs1 AddrBus test pass
859 22:48:44.541587
860 22:48:44.542048 100bdlr_step_size ps== 420
861 22:48:44.542484 result report
862 22:48:44.547202 boot times 0Enable ddr reg access
863 22:48:44.562539 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 22:48:44.566797 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 22:48:45.140509 0.0;M3 CHK:0;cm4_sp_mode 0
866 22:48:45.141148 MVN_1=0x00000000
867 22:48:45.145934 MVN_2=0x00000000
868 22:48:45.151676 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 22:48:45.152226 OPS=0x10
870 22:48:45.152692 ring efuse init
871 22:48:45.153142 chipver efuse init
872 22:48:45.157327 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 22:48:45.162893 [0.018960 Inits done]
874 22:48:45.163384 secure task start!
875 22:48:45.163833 high task start!
876 22:48:45.167536 low task start!
877 22:48:45.168063 run into bl31
878 22:48:45.174107 NOTICE: BL31: v1.3(release):4fc40b1
879 22:48:45.181838 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 22:48:45.182341 NOTICE: BL31: G12A normal boot!
881 22:48:45.207291 NOTICE: BL31: BL33 decompress pass
882 22:48:45.212957 ERROR: Error initializing runtime service opteed_fast
883 22:48:46.445861
884 22:48:46.446500
885 22:48:46.453345 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 22:48:46.453853
887 22:48:46.454315 Model: Libre Computer AML-A311D-CC Alta
888 22:48:46.662698 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 22:48:46.686157 DRAM: 2 GiB (effective 3.8 GiB)
890 22:48:46.829119 Core: 408 devices, 31 uclasses, devicetree: separate
891 22:48:46.834956 WDT: Not starting watchdog@f0d0
892 22:48:46.867217 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 22:48:46.879623 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 22:48:46.884578 ** Bad device specification mmc 0 **
895 22:48:46.894940 Card did not respond to voltage select! : -110
896 22:48:46.902605 ** Bad device specification mmc 0 **
897 22:48:46.903096 Couldn't find partition mmc 0
898 22:48:46.910920 Card did not respond to voltage select! : -110
899 22:48:46.916436 ** Bad device specification mmc 0 **
900 22:48:46.916916 Couldn't find partition mmc 0
901 22:48:46.921551 Error: could not access storage.
902 22:48:47.265012 Net: eth0: ethernet@ff3f0000
903 22:48:47.265605 starting USB...
904 22:48:47.516831 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 22:48:47.517497 Starting the controller
906 22:48:47.523855 USB XHCI 1.10
907 22:48:49.077888 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 22:48:49.086293 scanning usb for storage devices... 0 Storage Device(s) found
910 22:48:49.137986 Hit any key to stop autoboot: 1
911 22:48:49.138942 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 22:48:49.139609 start: 2.4.3 bootloader-commands (timeout 00:04:26) [common]
913 22:48:49.140215 Setting prompt string to ['=>']
914 22:48:49.140744 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:26)
915 22:48:49.153790 0
916 22:48:49.154775 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 22:48:49.155316 Sending with 10 millisecond of delay
919 22:48:50.290554 => setenv autoload no
920 22:48:50.301403 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
921 22:48:50.306931 setenv autoload no
922 22:48:50.307720 Sending with 10 millisecond of delay
924 22:48:52.105788 => setenv initrd_high 0xffffffff
925 22:48:52.116649 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
926 22:48:52.117659 setenv initrd_high 0xffffffff
927 22:48:52.118434 Sending with 10 millisecond of delay
929 22:48:53.734956 => setenv fdt_high 0xffffffff
930 22:48:53.745758 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
931 22:48:53.746566 setenv fdt_high 0xffffffff
932 22:48:53.747267 Sending with 10 millisecond of delay
934 22:48:54.039051 => dhcp
935 22:48:54.049791 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
936 22:48:54.195388 dhcp
937 22:48:54.195966 Speed: 1000, full duplex
938 22:48:54.196422 BOOTP broadcast 1
939 22:48:54.209293 DHCP client bound to address 192.168.6.10 (12 ms)
940 22:48:54.210001 Sending with 10 millisecond of delay
942 22:48:55.886521 => setenv serverip 192.168.6.2
943 22:48:55.897290 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
944 22:48:55.898127 setenv serverip 192.168.6.2
945 22:48:55.898814 Sending with 10 millisecond of delay
947 22:48:59.624541 => tftpboot 0x01080000 848140/tftp-deploy-6y3ttapl/kernel/uImage
948 22:48:59.635321 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
949 22:48:59.659594 tftpboot 0x01080000 848140/tftp-deploy-6y3ttapl/kernel/uImage
950 22:48:59.660140 Speed: 1000, full duplex
951 22:48:59.660581 Using ethernet@ff3f0000 device
952 22:48:59.664952 TFTP from server 192.168.6.2; our IP address is 192.168.6.10
953 22:48:59.670647 Filename '848140/tftp-deploy-6y3ttapl/kernel/uImage'.
954 22:48:59.673593 Load address: 0x1080000
955 22:49:34.469925 Loading: *T T T T T T UDP wrong checksum 000000ff 00000b11
956 22:49:34.508424 UDP wrong checksum 000000ff 00009503
957 22:49:37.938805 T UDP wrong checksum 000000ff 00009501
958 22:49:52.139302 T T T UDP wrong checksum 000000ff 000026f5
959 22:49:52.181758 UDP wrong checksum 000000ff 0000bbe7
960 22:49:54.926970
961 22:49:54.927400 Retry count exceeded; starting again
963 22:49:54.928296 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
966 22:49:54.929233 end: 2.4 uboot-commands (duration 00:01:40) [common]
968 22:49:54.929933 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
970 22:49:54.930481 end: 2 uboot-action (duration 00:01:40) [common]
972 22:49:54.931278 Cleaning after the job
973 22:49:54.931598 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/ramdisk
974 22:49:54.948670 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/kernel
975 22:49:54.996934 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/dtb
976 22:49:54.997817 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/848140/tftp-deploy-6y3ttapl/modules
977 22:49:55.054639 start: 4.1 power-off (timeout 00:00:30) [common]
978 22:49:55.055310 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
979 22:49:55.088689 >> OK - accepted request
980 22:49:55.090659 Returned 0 in 0 seconds
981 22:49:55.191433 end: 4.1 power-off (duration 00:00:00) [common]
983 22:49:55.192520 start: 4.2 read-feedback (timeout 00:10:00) [common]
984 22:49:55.193229 Listened to connection for namespace 'common' for up to 1s
985 22:49:56.194157 Finalising connection for namespace 'common'
986 22:49:56.194668 Disconnecting from shell: Finalise
987 22:49:56.194939 =>
988 22:49:56.295624 end: 4.2 read-feedback (duration 00:00:01) [common]
989 22:49:56.296186 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/848140
990 22:49:56.629659 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/848140
991 22:49:56.630442 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.