Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:34:49.625502 lava-dispatcher, installed at version: 2024.01
2 04:34:49.626276 start: 0 validate
3 04:34:49.626754 Start time: 2024-10-17 04:34:49.626725+00:00 (UTC)
4 04:34:49.627295 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:34:49.627835 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 04:34:49.666449 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:34:49.667045 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241016%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 04:34:49.703153 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:34:49.703763 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241016%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:34:50.760261 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:34:50.760789 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241016%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 04:34:50.812229 validate duration: 1.19
14 04:34:50.813701 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:34:50.814326 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:34:50.814900 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:34:50.815836 Not decompressing ramdisk as can be used compressed.
18 04:34:50.816623 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 04:34:50.817081 saving as /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/ramdisk/rootfs.cpio.gz
20 04:34:50.817564 total size: 8181887 (7 MB)
21 04:34:50.860526 progress 0 % (0 MB)
22 04:34:50.872832 progress 5 % (0 MB)
23 04:34:50.884779 progress 10 % (0 MB)
24 04:34:50.896791 progress 15 % (1 MB)
25 04:34:50.903855 progress 20 % (1 MB)
26 04:34:50.909838 progress 25 % (1 MB)
27 04:34:50.915434 progress 30 % (2 MB)
28 04:34:50.921414 progress 35 % (2 MB)
29 04:34:50.927271 progress 40 % (3 MB)
30 04:34:50.933288 progress 45 % (3 MB)
31 04:34:50.938876 progress 50 % (3 MB)
32 04:34:50.944891 progress 55 % (4 MB)
33 04:34:50.950474 progress 60 % (4 MB)
34 04:34:50.956506 progress 65 % (5 MB)
35 04:34:50.962063 progress 70 % (5 MB)
36 04:34:50.968050 progress 75 % (5 MB)
37 04:34:50.973585 progress 80 % (6 MB)
38 04:34:50.979486 progress 85 % (6 MB)
39 04:34:50.985050 progress 90 % (7 MB)
40 04:34:50.990992 progress 95 % (7 MB)
41 04:34:50.995905 progress 100 % (7 MB)
42 04:34:50.996585 7 MB downloaded in 0.18 s (43.59 MB/s)
43 04:34:50.997142 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:34:50.998045 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:34:50.998340 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:34:50.998612 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:34:50.999086 downloading http://storage.kernelci.org/next/master/next-20241016/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
49 04:34:50.999334 saving as /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/kernel/Image
50 04:34:50.999545 total size: 46066176 (43 MB)
51 04:34:50.999757 No compression specified
52 04:34:51.038145 progress 0 % (0 MB)
53 04:34:51.068146 progress 5 % (2 MB)
54 04:34:51.098934 progress 10 % (4 MB)
55 04:34:51.129456 progress 15 % (6 MB)
56 04:34:51.160267 progress 20 % (8 MB)
57 04:34:51.191025 progress 25 % (11 MB)
58 04:34:51.221339 progress 30 % (13 MB)
59 04:34:51.252062 progress 35 % (15 MB)
60 04:34:51.282443 progress 40 % (17 MB)
61 04:34:51.312764 progress 45 % (19 MB)
62 04:34:51.343253 progress 50 % (21 MB)
63 04:34:51.374190 progress 55 % (24 MB)
64 04:34:51.404669 progress 60 % (26 MB)
65 04:34:51.434968 progress 65 % (28 MB)
66 04:34:51.465546 progress 70 % (30 MB)
67 04:34:51.495721 progress 75 % (32 MB)
68 04:34:51.526301 progress 80 % (35 MB)
69 04:34:51.556536 progress 85 % (37 MB)
70 04:34:51.587255 progress 90 % (39 MB)
71 04:34:51.617551 progress 95 % (41 MB)
72 04:34:51.647326 progress 100 % (43 MB)
73 04:34:51.648095 43 MB downloaded in 0.65 s (67.74 MB/s)
74 04:34:51.648592 end: 1.2.1 http-download (duration 00:00:01) [common]
76 04:34:51.649411 end: 1.2 download-retry (duration 00:00:01) [common]
77 04:34:51.649689 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:34:51.649955 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:34:51.650419 downloading http://storage.kernelci.org/next/master/next-20241016/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 04:34:51.650692 saving as /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/dtb/meson-g12b-a311d-libretech-cc.dtb
81 04:34:51.650903 total size: 54703 (0 MB)
82 04:34:51.651115 No compression specified
83 04:34:51.687226 progress 59 % (0 MB)
84 04:34:51.688119 progress 100 % (0 MB)
85 04:34:51.688709 0 MB downloaded in 0.04 s (1.38 MB/s)
86 04:34:51.689184 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:34:51.690006 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:34:51.690271 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:34:51.690536 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:34:51.690990 downloading http://storage.kernelci.org/next/master/next-20241016/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
92 04:34:51.691233 saving as /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/modules/modules.tar
93 04:34:51.691439 total size: 11608308 (11 MB)
94 04:34:51.691649 Using unxz to decompress xz
95 04:34:51.734349 progress 0 % (0 MB)
96 04:34:51.800696 progress 5 % (0 MB)
97 04:34:51.874799 progress 10 % (1 MB)
98 04:34:51.954243 progress 15 % (1 MB)
99 04:34:52.030966 progress 20 % (2 MB)
100 04:34:52.106577 progress 25 % (2 MB)
101 04:34:52.184897 progress 30 % (3 MB)
102 04:34:52.257721 progress 35 % (3 MB)
103 04:34:52.336461 progress 40 % (4 MB)
104 04:34:52.421682 progress 45 % (5 MB)
105 04:34:52.501620 progress 50 % (5 MB)
106 04:34:52.579903 progress 55 % (6 MB)
107 04:34:52.661699 progress 60 % (6 MB)
108 04:34:52.745012 progress 65 % (7 MB)
109 04:34:52.820319 progress 70 % (7 MB)
110 04:34:52.900820 progress 75 % (8 MB)
111 04:34:52.982282 progress 80 % (8 MB)
112 04:34:53.061368 progress 85 % (9 MB)
113 04:34:53.129114 progress 90 % (9 MB)
114 04:34:53.226899 progress 95 % (10 MB)
115 04:34:53.323744 progress 100 % (11 MB)
116 04:34:53.335781 11 MB downloaded in 1.64 s (6.73 MB/s)
117 04:34:53.336683 end: 1.4.1 http-download (duration 00:00:02) [common]
119 04:34:53.338285 end: 1.4 download-retry (duration 00:00:02) [common]
120 04:34:53.338807 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 04:34:53.339330 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 04:34:53.339820 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:34:53.340363 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 04:34:53.341522 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr
125 04:34:53.342391 makedir: /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin
126 04:34:53.343032 makedir: /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/tests
127 04:34:53.343642 makedir: /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/results
128 04:34:53.344314 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-add-keys
129 04:34:53.345268 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-add-sources
130 04:34:53.346194 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-background-process-start
131 04:34:53.347133 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-background-process-stop
132 04:34:53.348141 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-common-functions
133 04:34:53.349079 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-echo-ipv4
134 04:34:53.349979 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-install-packages
135 04:34:53.350869 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-installed-packages
136 04:34:53.351746 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-os-build
137 04:34:53.352683 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-probe-channel
138 04:34:53.353581 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-probe-ip
139 04:34:53.354470 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-target-ip
140 04:34:53.355353 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-target-mac
141 04:34:53.356306 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-target-storage
142 04:34:53.357240 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-test-case
143 04:34:53.358140 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-test-event
144 04:34:53.359023 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-test-feedback
145 04:34:53.359926 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-test-raise
146 04:34:53.360870 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-test-reference
147 04:34:53.361765 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-test-runner
148 04:34:53.362659 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-test-set
149 04:34:53.363548 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-test-shell
150 04:34:53.364487 Updating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-install-packages (oe)
151 04:34:53.365458 Updating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/bin/lava-installed-packages (oe)
152 04:34:53.366292 Creating /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/environment
153 04:34:53.367011 LAVA metadata
154 04:34:53.367512 - LAVA_JOB_ID=851009
155 04:34:53.367943 - LAVA_DISPATCHER_IP=192.168.6.2
156 04:34:53.368640 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 04:34:53.370513 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 04:34:53.371144 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 04:34:53.371563 skipped lava-vland-overlay
160 04:34:53.372091 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 04:34:53.372615 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 04:34:53.373043 skipped lava-multinode-overlay
163 04:34:53.373533 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 04:34:53.374036 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 04:34:53.374519 Loading test definitions
166 04:34:53.375069 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 04:34:53.375517 Using /lava-851009 at stage 0
168 04:34:53.377705 uuid=851009_1.5.2.4.1 testdef=None
169 04:34:53.378302 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 04:34:53.378828 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 04:34:53.381235 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 04:34:53.382085 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 04:34:53.384408 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 04:34:53.385315 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 04:34:53.387544 runner path: /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/0/tests/0_dmesg test_uuid 851009_1.5.2.4.1
178 04:34:53.388170 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 04:34:53.388995 Creating lava-test-runner.conf files
181 04:34:53.389204 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/851009/lava-overlay-a7jbtmzr/lava-851009/0 for stage 0
182 04:34:53.389543 - 0_dmesg
183 04:34:53.389915 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 04:34:53.390214 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 04:34:53.413965 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 04:34:53.414391 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 04:34:53.414665 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 04:34:53.414939 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 04:34:53.415210 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 04:34:54.313004 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 04:34:54.313470 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 04:34:54.313728 extracting modules file /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/modules/modules.tar to /var/lib/lava/dispatcher/tmp/851009/extract-overlay-ramdisk-4livpqfx/ramdisk
193 04:34:55.613385 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 04:34:55.613873 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 04:34:55.614159 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851009/compress-overlay-9j5jeznn/overlay-1.5.2.5.tar.gz to ramdisk
196 04:34:55.614374 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851009/compress-overlay-9j5jeznn/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/851009/extract-overlay-ramdisk-4livpqfx/ramdisk
197 04:34:55.644230 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 04:34:55.644650 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 04:34:55.644920 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 04:34:55.645150 Converting downloaded kernel to a uImage
201 04:34:55.645460 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/kernel/Image /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/kernel/uImage
202 04:34:56.132372 output: Image Name:
203 04:34:56.132784 output: Created: Thu Oct 17 04:34:55 2024
204 04:34:56.132994 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 04:34:56.133203 output: Data Size: 46066176 Bytes = 44986.50 KiB = 43.93 MiB
206 04:34:56.133406 output: Load Address: 01080000
207 04:34:56.133609 output: Entry Point: 01080000
208 04:34:56.133808 output:
209 04:34:56.134139 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 04:34:56.134406 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 04:34:56.134672 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 04:34:56.134927 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 04:34:56.135184 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 04:34:56.135438 Building ramdisk /var/lib/lava/dispatcher/tmp/851009/extract-overlay-ramdisk-4livpqfx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/851009/extract-overlay-ramdisk-4livpqfx/ramdisk
215 04:34:58.536662 >> 181731 blocks
216 04:35:06.944036 Adding RAMdisk u-boot header.
217 04:35:06.944697 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/851009/extract-overlay-ramdisk-4livpqfx/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/851009/extract-overlay-ramdisk-4livpqfx/ramdisk.cpio.gz.uboot
218 04:35:07.226455 output: Image Name:
219 04:35:07.226876 output: Created: Thu Oct 17 04:35:06 2024
220 04:35:07.227088 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 04:35:07.227292 output: Data Size: 26066254 Bytes = 25455.33 KiB = 24.86 MiB
222 04:35:07.227493 output: Load Address: 00000000
223 04:35:07.227691 output: Entry Point: 00000000
224 04:35:07.227888 output:
225 04:35:07.228987 rename /var/lib/lava/dispatcher/tmp/851009/extract-overlay-ramdisk-4livpqfx/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/ramdisk/ramdisk.cpio.gz.uboot
226 04:35:07.229779 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 04:35:07.230369 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 04:35:07.230945 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 04:35:07.231441 No LXC device requested
230 04:35:07.232011 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 04:35:07.232580 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 04:35:07.233121 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 04:35:07.233572 Checking files for TFTP limit of 4294967296 bytes.
234 04:35:07.236502 end: 1 tftp-deploy (duration 00:00:16) [common]
235 04:35:07.237136 start: 2 uboot-action (timeout 00:05:00) [common]
236 04:35:07.237711 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 04:35:07.238259 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 04:35:07.238813 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 04:35:07.239393 Using kernel file from prepare-kernel: 851009/tftp-deploy-zzutosct/kernel/uImage
240 04:35:07.240102 substitutions:
241 04:35:07.240562 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 04:35:07.241006 - {DTB_ADDR}: 0x01070000
243 04:35:07.241447 - {DTB}: 851009/tftp-deploy-zzutosct/dtb/meson-g12b-a311d-libretech-cc.dtb
244 04:35:07.241888 - {INITRD}: 851009/tftp-deploy-zzutosct/ramdisk/ramdisk.cpio.gz.uboot
245 04:35:07.242327 - {KERNEL_ADDR}: 0x01080000
246 04:35:07.242761 - {KERNEL}: 851009/tftp-deploy-zzutosct/kernel/uImage
247 04:35:07.243194 - {LAVA_MAC}: None
248 04:35:07.243664 - {PRESEED_CONFIG}: None
249 04:35:07.244125 - {PRESEED_LOCAL}: None
250 04:35:07.244564 - {RAMDISK_ADDR}: 0x08000000
251 04:35:07.244995 - {RAMDISK}: 851009/tftp-deploy-zzutosct/ramdisk/ramdisk.cpio.gz.uboot
252 04:35:07.245431 - {ROOT_PART}: None
253 04:35:07.245864 - {ROOT}: None
254 04:35:07.246293 - {SERVER_IP}: 192.168.6.2
255 04:35:07.246728 - {TEE_ADDR}: 0x83000000
256 04:35:07.247160 - {TEE}: None
257 04:35:07.247592 Parsed boot commands:
258 04:35:07.248032 - setenv autoload no
259 04:35:07.248466 - setenv initrd_high 0xffffffff
260 04:35:07.248893 - setenv fdt_high 0xffffffff
261 04:35:07.249321 - dhcp
262 04:35:07.249753 - setenv serverip 192.168.6.2
263 04:35:07.250183 - tftpboot 0x01080000 851009/tftp-deploy-zzutosct/kernel/uImage
264 04:35:07.250616 - tftpboot 0x08000000 851009/tftp-deploy-zzutosct/ramdisk/ramdisk.cpio.gz.uboot
265 04:35:07.251045 - tftpboot 0x01070000 851009/tftp-deploy-zzutosct/dtb/meson-g12b-a311d-libretech-cc.dtb
266 04:35:07.251473 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 04:35:07.251910 - bootm 0x01080000 0x08000000 0x01070000
268 04:35:07.252543 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 04:35:07.254187 start: 2.3 connect-device (timeout 00:05:00) [common]
271 04:35:07.254676 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 04:35:07.270138 Setting prompt string to ['lava-test: # ']
273 04:35:07.271699 end: 2.3 connect-device (duration 00:00:00) [common]
274 04:35:07.272411 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 04:35:07.273012 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 04:35:07.273747 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 04:35:07.275002 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 04:35:07.312334 >> OK - accepted request
279 04:35:07.314522 Returned 0 in 0 seconds
280 04:35:07.415761 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 04:35:07.417651 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 04:35:07.418283 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 04:35:07.418838 Setting prompt string to ['Hit any key to stop autoboot']
285 04:35:07.419342 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 04:35:07.421141 Trying 192.168.56.21...
287 04:35:07.421681 Connected to conserv1.
288 04:35:07.422127 Escape character is '^]'.
289 04:35:07.422589
290 04:35:07.423054 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 04:35:07.423531
292 04:35:18.857231 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 04:35:18.857912 bl2_stage_init 0x81
294 04:35:18.862963 hw id: 0x0000 - pwm id 0x01
295 04:35:18.863463 bl2_stage_init 0xc1
296 04:35:18.863921 bl2_stage_init 0x02
297 04:35:18.864442
298 04:35:18.868346 L0:00000000
299 04:35:18.868835 L1:20000703
300 04:35:18.869282 L2:00008067
301 04:35:18.869715 L3:14000000
302 04:35:18.870137 B2:00402000
303 04:35:18.873841 B1:e0f83180
304 04:35:18.874299
305 04:35:18.874726 TE: 58141
306 04:35:18.875153
307 04:35:18.879565 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 04:35:18.880055
309 04:35:18.880490 Board ID = 1
310 04:35:18.885177 Set A53 clk to 24M
311 04:35:18.885636 Set A73 clk to 24M
312 04:35:18.886063 Set clk81 to 24M
313 04:35:18.890715 A53 clk: 1200 MHz
314 04:35:18.891165 A73 clk: 1200 MHz
315 04:35:18.891588 CLK81: 166.6M
316 04:35:18.892037 smccc: 00012aa3
317 04:35:18.896368 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 04:35:18.901860 board id: 1
319 04:35:18.918466 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 04:35:18.918974 fw parse done
321 04:35:18.923635 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 04:35:18.966366 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 04:35:18.977752 PIEI prepare done
324 04:35:18.978222 fastboot data load
325 04:35:18.978649 fastboot data verify
326 04:35:18.983525 verify result: 266
327 04:35:18.989046 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 04:35:18.989535 LPDDR4 probe
329 04:35:18.989962 ddr clk to 1584MHz
330 04:35:19.034365 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 04:35:19.034834
332 04:35:19.035269 dmc_version 0001
333 04:35:19.046952 Check phy result
334 04:35:19.047414 INFO : End of CA training
335 04:35:19.047839 INFO : End of initialization
336 04:35:19.052502 INFO : Training has run successfully!
337 04:35:19.052961 Check phy result
338 04:35:19.057965 INFO : End of initialization
339 04:35:19.058423 INFO : End of read enable training
340 04:35:19.067000 INFO : End of fine write leveling
341 04:35:19.067456 INFO : End of Write leveling coarse delay
342 04:35:19.072639 INFO : Training has run successfully!
343 04:35:19.073092 Check phy result
344 04:35:19.073519 INFO : End of initialization
345 04:35:19.078134 INFO : End of read dq deskew training
346 04:35:19.083784 INFO : End of MPR read delay center optimization
347 04:35:19.084274 INFO : End of write delay center optimization
348 04:35:19.089530 INFO : End of read delay center optimization
349 04:35:19.095090 INFO : End of max read latency training
350 04:35:19.095546 INFO : Training has run successfully!
351 04:35:19.100798 1D training succeed
352 04:35:19.106017 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 04:35:19.154245 Check phy result
354 04:35:19.154851 INFO : End of initialization
355 04:35:19.175303 INFO : End of 2D read delay Voltage center optimization
356 04:35:19.195226 INFO : End of 2D read delay Voltage center optimization
357 04:35:19.246232 INFO : End of 2D write delay Voltage center optimization
358 04:35:19.296565 INFO : End of 2D write delay Voltage center optimization
359 04:35:19.302143 INFO : Training has run successfully!
360 04:35:19.302630
361 04:35:19.303068 channel==0
362 04:35:19.307745 RxClkDly_Margin_A0==88 ps 9
363 04:35:19.308282 TxDqDly_Margin_A0==98 ps 10
364 04:35:19.313279 RxClkDly_Margin_A1==88 ps 9
365 04:35:19.313746 TxDqDly_Margin_A1==98 ps 10
366 04:35:19.314179 TrainedVREFDQ_A0==74
367 04:35:19.318853 TrainedVREFDQ_A1==74
368 04:35:19.319316 VrefDac_Margin_A0==25
369 04:35:19.319744 DeviceVref_Margin_A0==40
370 04:35:19.324408 VrefDac_Margin_A1==25
371 04:35:19.324866 DeviceVref_Margin_A1==40
372 04:35:19.325298
373 04:35:19.325731
374 04:35:19.330002 channel==1
375 04:35:19.330466 RxClkDly_Margin_A0==78 ps 8
376 04:35:19.330897 TxDqDly_Margin_A0==88 ps 9
377 04:35:19.335640 RxClkDly_Margin_A1==88 ps 9
378 04:35:19.336138 TxDqDly_Margin_A1==88 ps 9
379 04:35:19.341255 TrainedVREFDQ_A0==77
380 04:35:19.341715 TrainedVREFDQ_A1==77
381 04:35:19.342146 VrefDac_Margin_A0==23
382 04:35:19.346809 DeviceVref_Margin_A0==37
383 04:35:19.347260 VrefDac_Margin_A1==24
384 04:35:19.352385 DeviceVref_Margin_A1==37
385 04:35:19.352841
386 04:35:19.353269 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 04:35:19.353699
388 04:35:19.385992 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
389 04:35:19.386548 2D training succeed
390 04:35:19.391581 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 04:35:19.397213 auto size-- 65535DDR cs0 size: 2048MB
392 04:35:19.397675 DDR cs1 size: 2048MB
393 04:35:19.402817 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 04:35:19.403272 cs0 DataBus test pass
395 04:35:19.408385 cs1 DataBus test pass
396 04:35:19.408876 cs0 AddrBus test pass
397 04:35:19.409305 cs1 AddrBus test pass
398 04:35:19.409728
399 04:35:19.413998 100bdlr_step_size ps== 420
400 04:35:19.414471 result report
401 04:35:19.419664 boot times 0Enable ddr reg access
402 04:35:19.424361 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 04:35:19.437939 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 04:35:20.011952 0.0;M3 CHK:0;cm4_sp_mode 0
405 04:35:20.012515 MVN_1=0x00000000
406 04:35:20.017452 MVN_2=0x00000000
407 04:35:20.023198 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 04:35:20.023663 OPS=0x10
409 04:35:20.024131 ring efuse init
410 04:35:20.024561 chipver efuse init
411 04:35:20.028827 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 04:35:20.034442 [0.018961 Inits done]
413 04:35:20.034906 secure task start!
414 04:35:20.035334 high task start!
415 04:35:20.038073 low task start!
416 04:35:20.038535 run into bl31
417 04:35:20.045686 NOTICE: BL31: v1.3(release):4fc40b1
418 04:35:20.053068 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 04:35:20.053528 NOTICE: BL31: G12A normal boot!
420 04:35:20.078782 NOTICE: BL31: BL33 decompress pass
421 04:35:20.083693 ERROR: Error initializing runtime service opteed_fast
422 04:35:21.317398
423 04:35:21.318058
424 04:35:21.325705 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 04:35:21.326190
426 04:35:21.326643 Model: Libre Computer AML-A311D-CC Alta
427 04:35:21.535271 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 04:35:21.557586 DRAM: 2 GiB (effective 3.8 GiB)
429 04:35:21.700543 Core: 408 devices, 31 uclasses, devicetree: separate
430 04:35:21.738805 WDT: Not starting watchdog@f0d0
431 04:35:21.739317 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 04:35:21.751122 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 04:35:21.756105 ** Bad device specification mmc 0 **
434 04:35:21.766458 Card did not respond to voltage select! : -110
435 04:35:21.774082 ** Bad device specification mmc 0 **
436 04:35:21.774569 Couldn't find partition mmc 0
437 04:35:21.782429 Card did not respond to voltage select! : -110
438 04:35:21.787947 ** Bad device specification mmc 0 **
439 04:35:21.788466 Couldn't find partition mmc 0
440 04:35:21.792055 Error: could not access storage.
441 04:35:23.057166 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
442 04:35:23.057770 bl2_stage_init 0x01
443 04:35:23.058245 bl2_stage_init 0x81
444 04:35:23.062812 hw id: 0x0000 - pwm id 0x01
445 04:35:23.063281 bl2_stage_init 0xc1
446 04:35:23.063724 bl2_stage_init 0x02
447 04:35:23.064222
448 04:35:23.068342 L0:00000000
449 04:35:23.068812 L1:20000703
450 04:35:23.069253 L2:00008067
451 04:35:23.069686 L3:14000000
452 04:35:23.074036 B2:00402000
453 04:35:23.074498 B1:e0f83180
454 04:35:23.074938
455 04:35:23.075376 TE: 58124
456 04:35:23.075815
457 04:35:23.079549 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 04:35:23.080051
459 04:35:23.080500 Board ID = 1
460 04:35:23.085116 Set A53 clk to 24M
461 04:35:23.085579 Set A73 clk to 24M
462 04:35:23.086019 Set clk81 to 24M
463 04:35:23.090778 A53 clk: 1200 MHz
464 04:35:23.091241 A73 clk: 1200 MHz
465 04:35:23.091678 CLK81: 166.6M
466 04:35:23.092147 smccc: 00012a92
467 04:35:23.096304 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 04:35:23.102027 board id: 1
469 04:35:23.107839 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 04:35:23.118453 fw parse done
471 04:35:23.124431 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 04:35:23.167114 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 04:35:23.178060 PIEI prepare done
474 04:35:23.178533 fastboot data load
475 04:35:23.178980 fastboot data verify
476 04:35:23.183664 verify result: 266
477 04:35:23.189239 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 04:35:23.189716 LPDDR4 probe
479 04:35:23.190155 ddr clk to 1584MHz
480 04:35:23.197195 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 04:35:23.233575
482 04:35:23.234043 dmc_version 0001
483 04:35:23.241181 Check phy result
484 04:35:23.247114 INFO : End of CA training
485 04:35:23.247602 INFO : End of initialization
486 04:35:23.252592 INFO : Training has run successfully!
487 04:35:23.253081 Check phy result
488 04:35:23.258252 INFO : End of initialization
489 04:35:23.258732 INFO : End of read enable training
490 04:35:23.264022 INFO : End of fine write leveling
491 04:35:23.269430 INFO : End of Write leveling coarse delay
492 04:35:23.269911 INFO : Training has run successfully!
493 04:35:23.270352 Check phy result
494 04:35:23.275113 INFO : End of initialization
495 04:35:23.275584 INFO : End of read dq deskew training
496 04:35:23.280608 INFO : End of MPR read delay center optimization
497 04:35:23.286176 INFO : End of write delay center optimization
498 04:35:23.291860 INFO : End of read delay center optimization
499 04:35:23.292369 INFO : End of max read latency training
500 04:35:23.297355 INFO : Training has run successfully!
501 04:35:23.297826 1D training succeed
502 04:35:23.306551 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 04:35:23.353333 Check phy result
504 04:35:23.353915 INFO : End of initialization
505 04:35:23.375785 INFO : End of 2D read delay Voltage center optimization
506 04:35:23.395926 INFO : End of 2D read delay Voltage center optimization
507 04:35:23.497136 INFO : End of 2D write delay Voltage center optimization
508 04:35:23.497681 INFO : End of 2D write delay Voltage center optimization
509 04:35:23.502617 INFO : Training has run successfully!
510 04:35:23.503095
511 04:35:23.503548 channel==0
512 04:35:23.508237 RxClkDly_Margin_A0==88 ps 9
513 04:35:23.508713 TxDqDly_Margin_A0==98 ps 10
514 04:35:23.513802 RxClkDly_Margin_A1==88 ps 9
515 04:35:23.514265 TxDqDly_Margin_A1==98 ps 10
516 04:35:23.514712 TrainedVREFDQ_A0==74
517 04:35:23.519370 TrainedVREFDQ_A1==74
518 04:35:23.519836 VrefDac_Margin_A0==25
519 04:35:23.520314 DeviceVref_Margin_A0==40
520 04:35:23.524974 VrefDac_Margin_A1==25
521 04:35:23.525434 DeviceVref_Margin_A1==40
522 04:35:23.525873
523 04:35:23.526311
524 04:35:23.530571 channel==1
525 04:35:23.531032 RxClkDly_Margin_A0==88 ps 9
526 04:35:23.531469 TxDqDly_Margin_A0==98 ps 10
527 04:35:23.537009 RxClkDly_Margin_A1==88 ps 9
528 04:35:23.537471 TxDqDly_Margin_A1==88 ps 9
529 04:35:23.541807 TrainedVREFDQ_A0==77
530 04:35:23.542286 TrainedVREFDQ_A1==77
531 04:35:23.542729 VrefDac_Margin_A0==22
532 04:35:23.553096 DeviceVref_Margin_A0==37
533 04:35:23.553561 VrefDac_Margin_A1==24
534 04:35:23.553997 DeviceVref_Margin_A1==37
535 04:35:23.554430
536 04:35:23.554863 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 04:35:23.555293
538 04:35:23.586617 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000018 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
539 04:35:23.587132 2D training succeed
540 04:35:23.592210 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 04:35:23.597806 auto size-- 65535DDR cs0 size: 2048MB
542 04:35:23.598275 DDR cs1 size: 2048MB
543 04:35:23.603369 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 04:35:23.603840 cs0 DataBus test pass
545 04:35:23.608958 cs1 DataBus test pass
546 04:35:23.609427 cs0 AddrBus test pass
547 04:35:23.609869 cs1 AddrBus test pass
548 04:35:23.610304
549 04:35:23.614591 100bdlr_step_size ps== 420
550 04:35:23.615076 result report
551 04:35:23.620191 boot times 0Enable ddr reg access
552 04:35:23.625426 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 04:35:23.638877 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 04:35:24.211063 0.0;M3 CHK:0;cm4_sp_mode 0
555 04:35:24.211708 MVN_1=0x00000000
556 04:35:24.216505 MVN_2=0x00000000
557 04:35:24.222671 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 04:35:24.223116 OPS=0x10
559 04:35:24.223513 ring efuse init
560 04:35:24.223901 chipver efuse init
561 04:35:24.228226 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 04:35:24.233556 [0.018961 Inits done]
563 04:35:24.233989 secure task start!
564 04:35:24.234379 high task start!
565 04:35:24.238077 low task start!
566 04:35:24.238506 run into bl31
567 04:35:24.245184 NOTICE: BL31: v1.3(release):4fc40b1
568 04:35:24.278413 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 04:35:24.278929 NOTICE: BL31: G12A normal boot!
570 04:35:24.279341 NOTICE: BL31: BL33 decompress pass
571 04:35:24.283651 ERROR: Error initializing runtime service opteed_fast
572 04:35:25.516762
573 04:35:25.517189
574 04:35:25.524703 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 04:35:25.525135
576 04:35:25.525366 Model: Libre Computer AML-A311D-CC Alta
577 04:35:25.733472 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 04:35:25.756808 DRAM: 2 GiB (effective 3.8 GiB)
579 04:35:25.899783 Core: 408 devices, 31 uclasses, devicetree: separate
580 04:35:25.905751 WDT: Not starting watchdog@f0d0
581 04:35:25.937831 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 04:35:25.950205 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 04:35:25.955209 ** Bad device specification mmc 0 **
584 04:35:25.965570 Card did not respond to voltage select! : -110
585 04:35:25.973308 ** Bad device specification mmc 0 **
586 04:35:25.973727 Couldn't find partition mmc 0
587 04:35:25.981615 Card did not respond to voltage select! : -110
588 04:35:25.987047 ** Bad device specification mmc 0 **
589 04:35:25.987462 Couldn't find partition mmc 0
590 04:35:25.992153 Error: could not access storage.
591 04:35:26.335849 Net: eth0: ethernet@ff3f0000
592 04:35:26.336547 starting USB...
593 04:35:26.587528 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 04:35:26.588152 Starting the controller
595 04:35:26.594498 USB XHCI 1.10
596 04:35:28.309084 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
597 04:35:28.309755 bl2_stage_init 0x81
598 04:35:28.314784 hw id: 0x0000 - pwm id 0x01
599 04:35:28.315288 bl2_stage_init 0xc1
600 04:35:28.315746 bl2_stage_init 0x02
601 04:35:28.316253
602 04:35:28.320412 L0:00000000
603 04:35:28.320906 L1:20000703
604 04:35:28.321356 L2:00008067
605 04:35:28.321798 L3:14000000
606 04:35:28.322235 B2:00402000
607 04:35:28.325931 B1:e0f83180
608 04:35:28.326416
609 04:35:28.326868 TE: 58150
610 04:35:28.327310
611 04:35:28.331527 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
612 04:35:28.332057
613 04:35:28.332510 Board ID = 1
614 04:35:28.337128 Set A53 clk to 24M
615 04:35:28.337612 Set A73 clk to 24M
616 04:35:28.338063 Set clk81 to 24M
617 04:35:28.342661 A53 clk: 1200 MHz
618 04:35:28.343147 A73 clk: 1200 MHz
619 04:35:28.343594 CLK81: 166.6M
620 04:35:28.344071 smccc: 00012aac
621 04:35:28.348346 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
622 04:35:28.353909 board id: 1
623 04:35:28.359816 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
624 04:35:28.370367 fw parse done
625 04:35:28.375507 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
626 04:35:28.418849 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
627 04:35:28.429775 PIEI prepare done
628 04:35:28.430254 fastboot data load
629 04:35:28.430703 fastboot data verify
630 04:35:28.435386 verify result: 266
631 04:35:28.441040 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
632 04:35:28.441559 LPDDR4 probe
633 04:35:28.442013 ddr clk to 1584MHz
634 04:35:28.448924 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
635 04:35:28.486156
636 04:35:28.486668 dmc_version 0001
637 04:35:28.492651 Check phy result
638 04:35:28.498692 INFO : End of CA training
639 04:35:28.499171 INFO : End of initialization
640 04:35:28.504311 INFO : Training has run successfully!
641 04:35:28.504784 Check phy result
642 04:35:28.509949 INFO : End of initialization
643 04:35:28.510432 INFO : End of read enable training
644 04:35:28.515574 INFO : End of fine write leveling
645 04:35:28.521109 INFO : End of Write leveling coarse delay
646 04:35:28.521603 INFO : Training has run successfully!
647 04:35:28.522052 Check phy result
648 04:35:28.526711 INFO : End of initialization
649 04:35:28.527186 INFO : End of read dq deskew training
650 04:35:28.532311 INFO : End of MPR read delay center optimization
651 04:35:28.537912 INFO : End of write delay center optimization
652 04:35:28.543485 INFO : End of read delay center optimization
653 04:35:28.543959 INFO : End of max read latency training
654 04:35:28.549101 INFO : Training has run successfully!
655 04:35:28.549577 1D training succeed
656 04:35:28.557420 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
657 04:35:28.605944 Check phy result
658 04:35:28.606430 INFO : End of initialization
659 04:35:28.627603 INFO : End of 2D read delay Voltage center optimization
660 04:35:28.647068 INFO : End of 2D read delay Voltage center optimization
661 04:35:28.699054 INFO : End of 2D write delay Voltage center optimization
662 04:35:28.748381 INFO : End of 2D write delay Voltage center optimization
663 04:35:28.754028 INFO : Training has run successfully!
664 04:35:28.754514
665 04:35:28.754965 channel==0
666 04:35:28.759588 RxClkDly_Margin_A0==88 ps 9
667 04:35:28.760098 TxDqDly_Margin_A0==98 ps 10
668 04:35:28.765195 RxClkDly_Margin_A1==88 ps 9
669 04:35:28.765673 TxDqDly_Margin_A1==98 ps 10
670 04:35:28.766120 TrainedVREFDQ_A0==74
671 04:35:28.770864 TrainedVREFDQ_A1==74
672 04:35:28.771346 VrefDac_Margin_A0==25
673 04:35:28.771790 DeviceVref_Margin_A0==40
674 04:35:28.776405 VrefDac_Margin_A1==25
675 04:35:28.776878 DeviceVref_Margin_A1==40
676 04:35:28.777320
677 04:35:28.777759
678 04:35:28.782005 channel==1
679 04:35:28.782475 RxClkDly_Margin_A0==88 ps 9
680 04:35:28.782915 TxDqDly_Margin_A0==88 ps 9
681 04:35:28.787619 RxClkDly_Margin_A1==88 ps 9
682 04:35:28.788121 TxDqDly_Margin_A1==88 ps 9
683 04:35:28.793207 TrainedVREFDQ_A0==77
684 04:35:28.793678 TrainedVREFDQ_A1==77
685 04:35:28.794126 VrefDac_Margin_A0==23
686 04:35:28.798887 DeviceVref_Margin_A0==37
687 04:35:28.799361 VrefDac_Margin_A1==24
688 04:35:28.804379 DeviceVref_Margin_A1==37
689 04:35:28.804855
690 04:35:28.805299 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
691 04:35:28.805739
692 04:35:28.838055 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000019 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
693 04:35:28.838561 2D training succeed
694 04:35:28.843617 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
695 04:35:28.849192 auto size-- 65535DDR cs0 size: 2048MB
696 04:35:28.849666 DDR cs1 size: 2048MB
697 04:35:28.854871 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
698 04:35:28.855347 cs0 DataBus test pass
699 04:35:28.860390 cs1 DataBus test pass
700 04:35:28.860862 cs0 AddrBus test pass
701 04:35:28.861309 cs1 AddrBus test pass
702 04:35:28.861747
703 04:35:28.865989 100bdlr_step_size ps== 420
704 04:35:28.866474 result report
705 04:35:28.876913 boot times 0Enable ddr reg access
706 04:35:28.877398 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
707 04:35:28.890273 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
708 04:35:29.469699 0.0;M3 CHK:0;cm4_sp_mode 0
709 04:35:29.470276 MVN_1=0x00000000
710 04:35:29.470743 MVN_2=0x00000000
711 04:35:29.475247 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
712 04:35:29.475774 OPS=0x10
713 04:35:29.476329 ring efuse init
714 04:35:29.476772 chipver efuse init
715 04:35:29.483586 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
716 04:35:29.484182 [0.018961 Inits done]
717 04:35:29.484624 secure task start!
718 04:35:29.491069 high task start!
719 04:35:29.491537 low task start!
720 04:35:29.491960 run into bl31
721 04:35:29.497705 NOTICE: BL31: v1.3(release):4fc40b1
722 04:35:29.505488 NOTICE: BL31: Built : 15:58:17, May 22 2019
723 04:35:29.505967 NOTICE: BL31: G12A normal boot!
724 04:35:29.531007 NOTICE: BL31: BL33 decompress pass
725 04:35:29.536557 ERROR: Error initializing runtime service opteed_fast
726 04:35:30.769487
727 04:35:30.770113
728 04:35:30.777804 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
729 04:35:30.778294
730 04:35:30.778743 Model: Libre Computer AML-A311D-CC Alta
731 04:35:30.985928 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
732 04:35:31.008879 DRAM: 2 GiB (effective 3.8 GiB)
733 04:35:31.152692 Core: 408 devices, 31 uclasses, devicetree: separate
734 04:35:31.157787 WDT: Not starting watchdog@f0d0
735 04:35:31.190872 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
736 04:35:31.203305 Loading Environment from FAT... Card did not respond to voltage select! : -110
737 04:35:31.207370 ** Bad device specification mmc 0 **
738 04:35:31.218605 Card did not respond to voltage select! : -110
739 04:35:31.234742 ** Bad device specification mmc 0 **
740 04:35:31.235216 Couldn't find partition mmc 0
741 04:35:31.235662 Card did not respond to voltage select! : -110
742 04:35:31.240237 ** Bad device specification mmc 0 **
743 04:35:31.240718 Couldn't find partition mmc 0
744 04:35:31.244607 Error: could not access storage.
745 04:35:31.588742 Net: eth0: ethernet@ff3f0000
746 04:35:31.589283 starting USB...
747 04:35:31.840466 Bus usb@ff500000: Register 3000140 NbrPorts 3
748 04:35:31.840980 Starting the controller
749 04:35:31.847270 USB XHCI 1.10
750 04:35:34.007552 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
751 04:35:34.008227 bl2_stage_init 0x01
752 04:35:34.008695 bl2_stage_init 0x81
753 04:35:34.013122 hw id: 0x0000 - pwm id 0x01
754 04:35:34.013605 bl2_stage_init 0xc1
755 04:35:34.014050 bl2_stage_init 0x02
756 04:35:34.014497
757 04:35:34.018919 L0:00000000
758 04:35:34.019397 L1:20000703
759 04:35:34.019840 L2:00008067
760 04:35:34.020317 L3:14000000
761 04:35:34.021608 B2:00402000
762 04:35:34.022070 B1:e0f83180
763 04:35:34.022509
764 04:35:34.022947 TE: 58124
765 04:35:34.023388
766 04:35:34.032686 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 04:35:34.033182
768 04:35:34.033635 Board ID = 1
769 04:35:34.034073 Set A53 clk to 24M
770 04:35:34.034508 Set A73 clk to 24M
771 04:35:34.038253 Set clk81 to 24M
772 04:35:34.038728 A53 clk: 1200 MHz
773 04:35:34.039168 A73 clk: 1200 MHz
774 04:35:34.043963 CLK81: 166.6M
775 04:35:34.044461 smccc: 00012a91
776 04:35:34.055250 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 04:35:34.055726 board id: 1
778 04:35:34.056197 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 04:35:34.068883 fw parse done
780 04:35:34.074772 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 04:35:34.116576 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 04:35:34.128236 PIEI prepare done
783 04:35:34.128716 fastboot data load
784 04:35:34.129163 fastboot data verify
785 04:35:34.133811 verify result: 266
786 04:35:34.139405 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 04:35:34.139885 LPDDR4 probe
788 04:35:34.140381 ddr clk to 1584MHz
789 04:35:34.146567 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 04:35:34.184492
791 04:35:34.184988 dmc_version 0001
792 04:35:34.190595 Check phy result
793 04:35:34.197190 INFO : End of CA training
794 04:35:34.197657 INFO : End of initialization
795 04:35:34.202773 INFO : Training has run successfully!
796 04:35:34.203239 Check phy result
797 04:35:34.208397 INFO : End of initialization
798 04:35:34.208874 INFO : End of read enable training
799 04:35:34.213994 INFO : End of fine write leveling
800 04:35:34.219618 INFO : End of Write leveling coarse delay
801 04:35:34.220122 INFO : Training has run successfully!
802 04:35:34.220570 Check phy result
803 04:35:34.225181 INFO : End of initialization
804 04:35:34.225652 INFO : End of read dq deskew training
805 04:35:34.230783 INFO : End of MPR read delay center optimization
806 04:35:34.236408 INFO : End of write delay center optimization
807 04:35:34.241980 INFO : End of read delay center optimization
808 04:35:34.242454 INFO : End of max read latency training
809 04:35:34.247605 INFO : Training has run successfully!
810 04:35:34.248113 1D training succeed
811 04:35:34.255899 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 04:35:34.303847 Check phy result
813 04:35:34.304354 INFO : End of initialization
814 04:35:34.325726 INFO : End of 2D read delay Voltage center optimization
815 04:35:34.346193 INFO : End of 2D read delay Voltage center optimization
816 04:35:34.397857 INFO : End of 2D write delay Voltage center optimization
817 04:35:34.447706 INFO : End of 2D write delay Voltage center optimization
818 04:35:34.453328 INFO : Training has run successfully!
819 04:35:34.453817
820 04:35:34.454267 channel==0
821 04:35:34.464623 RxClkDly_Margin_A0==88 ps 9
822 04:35:34.465095 TxDqDly_Margin_A0==98 ps 10
823 04:35:34.465545 RxClkDly_Margin_A1==88 ps 9
824 04:35:34.465980 TxDqDly_Margin_A1==88 ps 9
825 04:35:34.466418 TrainedVREFDQ_A0==74
826 04:35:34.470084 TrainedVREFDQ_A1==74
827 04:35:34.470560 VrefDac_Margin_A0==25
828 04:35:34.471025 DeviceVref_Margin_A0==40
829 04:35:34.475706 VrefDac_Margin_A1==25
830 04:35:34.476252 DeviceVref_Margin_A1==40
831 04:35:34.476701
832 04:35:34.477143
833 04:35:34.477588 channel==1
834 04:35:34.487064 RxClkDly_Margin_A0==88 ps 9
835 04:35:34.487565 TxDqDly_Margin_A0==98 ps 10
836 04:35:34.488019 RxClkDly_Margin_A1==98 ps 10
837 04:35:34.488446 TxDqDly_Margin_A1==98 ps 10
838 04:35:34.492473 TrainedVREFDQ_A0==77
839 04:35:34.492933 TrainedVREFDQ_A1==77
840 04:35:34.493370 VrefDac_Margin_A0==22
841 04:35:34.498121 DeviceVref_Margin_A0==37
842 04:35:34.498584 VrefDac_Margin_A1==22
843 04:35:34.503699 DeviceVref_Margin_A1==37
844 04:35:34.504187
845 04:35:34.504614 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 04:35:34.505140
847 04:35:34.537287 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
848 04:35:34.537779 2D training succeed
849 04:35:34.542885 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 04:35:34.548490 auto size-- 65535DDR cs0 size: 2048MB
851 04:35:34.548944 DDR cs1 size: 2048MB
852 04:35:34.554058 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 04:35:34.554507 cs0 DataBus test pass
854 04:35:34.559720 cs1 DataBus test pass
855 04:35:34.560207 cs0 AddrBus test pass
856 04:35:34.560632 cs1 AddrBus test pass
857 04:35:34.561051
858 04:35:34.565283 100bdlr_step_size ps== 420
859 04:35:34.565749 result report
860 04:35:34.570900 boot times 0Enable ddr reg access
861 04:35:34.575388 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 04:35:34.588854 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 04:35:35.163438 0.0;M3 CHK:0;cm4_sp_mode 0
864 04:35:35.164061 MVN_1=0x00000000
865 04:35:35.168943 MVN_2=0x00000000
866 04:35:35.174766 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 04:35:35.175252 OPS=0x10
868 04:35:35.175698 ring efuse init
869 04:35:35.176170 chipver efuse init
870 04:35:35.182920 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 04:35:35.183423 [0.018961 Inits done]
872 04:35:35.190190 secure task start!
873 04:35:35.190659 high task start!
874 04:35:35.191097 low task start!
875 04:35:35.191529 run into bl31
876 04:35:35.197150 NOTICE: BL31: v1.3(release):4fc40b1
877 04:35:35.204839 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 04:35:35.205315 NOTICE: BL31: G12A normal boot!
879 04:35:35.230901 NOTICE: BL31: BL33 decompress pass
880 04:35:35.235776 ERROR: Error initializing runtime service opteed_fast
881 04:35:36.469520
882 04:35:36.470144
883 04:35:36.682606 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 04:35:36.683122
885 04:35:36.683544 Model: Libre Computer AML-A311D-CC Alta
886 04:35:36.686174 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 04:35:36.709652 DRAM: 2 GiB (effective 3.8 GiB)
888 04:35:36.852721 Core: 408 devices, 31 uclasses, devicetree: separate
889 04:35:36.857761 WDT: Not starting watchdog@f0d0
890 04:35:36.890886 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 04:35:36.903245 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 04:35:36.907692 ** Bad device specification mmc 0 **
893 04:35:36.918607 Card did not respond to voltage select! : -110
894 04:35:36.926229 ** Bad device specification mmc 0 **
895 04:35:36.926858 Couldn't find partition mmc 0
896 04:35:36.934632 Card did not respond to voltage select! : -110
897 04:35:36.940172 ** Bad device specification mmc 0 **
898 04:35:36.940647 Couldn't find partition mmc 0
899 04:35:36.944325 Error: could not access storage.
900 04:35:37.287751 Net: eth0: ethernet@ff3f0000
901 04:35:37.288308 starting USB...
902 04:35:37.540473 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 04:35:37.540978 Starting the controller
904 04:35:37.547503 USB XHCI 1.10
905 04:35:39.407306 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
906 04:35:39.407713 bl2_stage_init 0x01
907 04:35:39.407950 bl2_stage_init 0x81
908 04:35:39.412809 hw id: 0x0000 - pwm id 0x01
909 04:35:39.413129 bl2_stage_init 0xc1
910 04:35:39.413393 bl2_stage_init 0x02
911 04:35:39.413614
912 04:35:39.418367 L0:00000000
913 04:35:39.418805 L1:20000703
914 04:35:39.419148 L2:00008067
915 04:35:39.419472 L3:14000000
916 04:35:39.424049 B2:00402000
917 04:35:39.424473 B1:e0f83180
918 04:35:39.424814
919 04:35:39.425139 TE: 58124
920 04:35:39.425380
921 04:35:39.429530 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
922 04:35:39.429824
923 04:35:39.430036 Board ID = 1
924 04:35:39.435244 Set A53 clk to 24M
925 04:35:39.435636 Set A73 clk to 24M
926 04:35:39.435967 Set clk81 to 24M
927 04:35:39.440758 A53 clk: 1200 MHz
928 04:35:39.441168 A73 clk: 1200 MHz
929 04:35:39.441502 CLK81: 166.6M
930 04:35:39.441741 smccc: 00012a91
931 04:35:39.446340 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
932 04:35:39.452040 board id: 1
933 04:35:39.456897 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
934 04:35:39.468504 fw parse done
935 04:35:39.473629 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
936 04:35:39.516302 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
937 04:35:39.528614 PIEI prepare done
938 04:35:39.529293 fastboot data load
939 04:35:39.529830 fastboot data verify
940 04:35:39.533778 verify result: 266
941 04:35:39.539475 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
942 04:35:39.540173 LPDDR4 probe
943 04:35:39.540706 ddr clk to 1584MHz
944 04:35:39.546369 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
945 04:35:39.583669
946 04:35:39.584372 dmc_version 0001
947 04:35:39.590439 Check phy result
948 04:35:39.597181 INFO : End of CA training
949 04:35:39.597800 INFO : End of initialization
950 04:35:39.608562 INFO : Training has run successfully!
951 04:35:39.609213 Check phy result
952 04:35:39.609779 INFO : End of initialization
953 04:35:39.610305 INFO : End of read enable training
954 04:35:39.614016 INFO : End of fine write leveling
955 04:35:39.619594 INFO : End of Write leveling coarse delay
956 04:35:39.620281 INFO : Training has run successfully!
957 04:35:39.620846 Check phy result
958 04:35:39.625356 INFO : End of initialization
959 04:35:39.626029 INFO : End of read dq deskew training
960 04:35:39.630899 INFO : End of MPR read delay center optimization
961 04:35:39.636526 INFO : End of write delay center optimization
962 04:35:39.642011 INFO : End of read delay center optimization
963 04:35:39.642670 INFO : End of max read latency training
964 04:35:39.647679 INFO : Training has run successfully!
965 04:35:39.648388 1D training succeed
966 04:35:39.655836 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
967 04:35:39.703449 Check phy result
968 04:35:39.704157 INFO : End of initialization
969 04:35:39.745477 INFO : End of 2D read delay Voltage center optimization
970 04:35:39.746144 INFO : End of 2D read delay Voltage center optimization
971 04:35:39.797516 INFO : End of 2D write delay Voltage center optimization
972 04:35:39.847713 INFO : End of 2D write delay Voltage center optimization
973 04:35:39.853293 INFO : Training has run successfully!
974 04:35:39.853940
975 04:35:39.854496 channel==0
976 04:35:39.858884 RxClkDly_Margin_A0==88 ps 9
977 04:35:39.859528 TxDqDly_Margin_A0==98 ps 10
978 04:35:39.864572 RxClkDly_Margin_A1==88 ps 9
979 04:35:39.865214 TxDqDly_Margin_A1==98 ps 10
980 04:35:39.865765 TrainedVREFDQ_A0==74
981 04:35:39.870099 TrainedVREFDQ_A1==74
982 04:35:39.870754 VrefDac_Margin_A0==25
983 04:35:39.871306 DeviceVref_Margin_A0==40
984 04:35:39.875703 VrefDac_Margin_A1==25
985 04:35:39.876389 DeviceVref_Margin_A1==40
986 04:35:39.876925
987 04:35:39.877457
988 04:35:39.881308 channel==1
989 04:35:39.881949 RxClkDly_Margin_A0==88 ps 9
990 04:35:39.882500 TxDqDly_Margin_A0==98 ps 10
991 04:35:39.886889 RxClkDly_Margin_A1==88 ps 9
992 04:35:39.887543 TxDqDly_Margin_A1==88 ps 9
993 04:35:39.892574 TrainedVREFDQ_A0==77
994 04:35:39.893230 TrainedVREFDQ_A1==77
995 04:35:39.893793 VrefDac_Margin_A0==22
996 04:35:39.898085 DeviceVref_Margin_A0==37
997 04:35:39.898731 VrefDac_Margin_A1==24
998 04:35:39.903706 DeviceVref_Margin_A1==37
999 04:35:39.904391
1000 04:35:39.904955 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1001 04:35:39.905490
1002 04:35:39.937237 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1003 04:35:39.937934 2D training succeed
1004 04:35:39.942896 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1005 04:35:39.948560 auto size-- 65535DDR cs0 size: 2048MB
1006 04:35:39.949214 DDR cs1 size: 2048MB
1007 04:35:39.954108 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1008 04:35:39.954766 cs0 DataBus test pass
1009 04:35:39.959716 cs1 DataBus test pass
1010 04:35:39.960415 cs0 AddrBus test pass
1011 04:35:39.960964 cs1 AddrBus test pass
1012 04:35:39.961487
1013 04:35:39.965317 100bdlr_step_size ps== 420
1014 04:35:39.965981 result report
1015 04:35:39.970887 boot times 0Enable ddr reg access
1016 04:35:39.976140 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1017 04:35:39.989565 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1018 04:35:40.563241 0.0;M3 CHK:0;cm4_sp_mode 0
1019 04:35:40.563962 MVN_1=0x00000000
1020 04:35:40.569140 MVN_2=0x00000000
1021 04:35:40.574573 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1022 04:35:40.575229 OPS=0x10
1023 04:35:40.575790 ring efuse init
1024 04:35:40.576368 chipver efuse init
1025 04:35:40.582766 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1026 04:35:40.583426 [0.018961 Inits done]
1027 04:35:40.589496 secure task start!
1028 04:35:40.590136 high task start!
1029 04:35:40.590689 low task start!
1030 04:35:40.591224 run into bl31
1031 04:35:40.596983 NOTICE: BL31: v1.3(release):4fc40b1
1032 04:35:40.603858 NOTICE: BL31: Built : 15:58:17, May 22 2019
1033 04:35:40.604573 NOTICE: BL31: G12A normal boot!
1034 04:35:40.630084 NOTICE: BL31: BL33 decompress pass
1035 04:35:40.634778 ERROR: Error initializing runtime service opteed_fast
1036 04:35:41.868595
1037 04:35:41.869343
1038 04:35:41.877032 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1039 04:35:41.877707
1040 04:35:41.878269 Model: Libre Computer AML-A311D-CC Alta
1041 04:35:42.085402 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1042 04:35:42.108858 DRAM: 2 GiB (effective 3.8 GiB)
1043 04:35:42.251829 Core: 408 devices, 31 uclasses, devicetree: separate
1044 04:35:42.257665 WDT: Not starting watchdog@f0d0
1045 04:35:42.289911 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1046 04:35:42.302344 Loading Environment from FAT... Card did not respond to voltage select! : -110
1047 04:35:42.307366 ** Bad device specification mmc 0 **
1048 04:35:42.325539 Card did not respond to voltage select! : -110
1049 04:35:42.326213 ** Bad device specification mmc 0 **
1050 04:35:42.326786 Couldn't find partition mmc 0
1051 04:35:42.333812 Card did not respond to voltage select! : -110
1052 04:35:42.339212 ** Bad device specification mmc 0 **
1053 04:35:42.339863 Couldn't find partition mmc 0
1054 04:35:42.344250 Error: could not access storage.
1055 04:35:42.686791 Net: eth0: ethernet@ff3f0000
1056 04:35:42.687595 starting USB...
1057 04:35:42.938594 Bus usb@ff500000: Register 3000140 NbrPorts 3
1058 04:35:42.939390 Starting the controller
1059 04:35:42.945599 USB XHCI 1.10
1060 04:35:44.501772 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1061 04:35:44.510222 scanning usb for storage devices... 0 Storage Device(s) found
1063 04:35:44.562299 Hit any key to stop autoboot: 1
1064 04:35:44.563221 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1065 04:35:44.563972 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1066 04:35:44.564493 Setting prompt string to ['=>']
1067 04:35:44.564962 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1068 04:35:44.577551 0
1069 04:35:44.578661 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1070 04:35:44.579293 Sending with 10 millisecond of delay
1072 04:35:45.714602 => setenv autoload no
1073 04:35:45.725609 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1074 04:35:45.731860 setenv autoload no
1075 04:35:45.732829 Sending with 10 millisecond of delay
1077 04:35:47.530649 => setenv initrd_high 0xffffffff
1078 04:35:47.541440 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1079 04:35:47.542314 setenv initrd_high 0xffffffff
1080 04:35:47.543030 Sending with 10 millisecond of delay
1082 04:35:49.159032 => setenv fdt_high 0xffffffff
1083 04:35:49.169804 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1084 04:35:49.170654 setenv fdt_high 0xffffffff
1085 04:35:49.171374 Sending with 10 millisecond of delay
1087 04:35:49.463194 => dhcp
1088 04:35:49.473890 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1089 04:35:49.474703 dhcp
1090 04:35:49.475140 Speed: 1000, full duplex
1091 04:35:49.475552 BOOTP broadcast 1
1092 04:35:49.524538 DHCP client bound to address 192.168.6.244 (51 ms)
1093 04:35:49.525306 Sending with 10 millisecond of delay
1095 04:35:51.201876 => setenv serverip 192.168.6.2
1096 04:35:51.212660 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1097 04:35:51.213511 setenv serverip 192.168.6.2
1098 04:35:51.214222 Sending with 10 millisecond of delay
1100 04:35:54.938085 => tftpboot 0x01080000 851009/tftp-deploy-zzutosct/kernel/uImage
1101 04:35:54.948909 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1102 04:35:54.949762 tftpboot 0x01080000 851009/tftp-deploy-zzutosct/kernel/uImage
1103 04:35:54.950185 Speed: 1000, full duplex
1104 04:35:54.950580 Using ethernet@ff3f0000 device
1105 04:35:54.951509 TFTP from server 192.168.6.2; our IP address is 192.168.6.244
1106 04:35:54.956953 Filename '851009/tftp-deploy-zzutosct/kernel/uImage'.
1107 04:35:54.960131 Load address: 0x1080000
1108 04:36:50.027672 Loading: *T T T T T T T T T T
1109 04:36:50.028338 Retry count exceeded; starting again
1111 04:36:50.029743 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
1114 04:36:50.031574 end: 2.4 uboot-commands (duration 00:01:43) [common]
1116 04:36:50.032974 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1118 04:36:50.033975 end: 2 uboot-action (duration 00:01:43) [common]
1120 04:36:50.035432 Cleaning after the job
1121 04:36:50.035964 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/ramdisk
1122 04:36:50.051300 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/kernel
1123 04:36:50.076842 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/dtb
1124 04:36:50.078019 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851009/tftp-deploy-zzutosct/modules
1125 04:36:50.100305 start: 4.1 power-off (timeout 00:00:30) [common]
1126 04:36:50.100936 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1127 04:36:50.133990 >> OK - accepted request
1128 04:36:50.136058 Returned 0 in 0 seconds
1129 04:36:50.236750 end: 4.1 power-off (duration 00:00:00) [common]
1131 04:36:50.237594 start: 4.2 read-feedback (timeout 00:10:00) [common]
1132 04:36:50.238225 Listened to connection for namespace 'common' for up to 1s
1133 04:36:51.239137 Finalising connection for namespace 'common'
1134 04:36:51.239792 Disconnecting from shell: Finalise
1135 04:36:51.240380 =>
1136 04:36:51.341280 end: 4.2 read-feedback (duration 00:00:01) [common]
1137 04:36:51.341850 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/851009
1138 04:36:51.614996 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/851009
1139 04:36:51.615594 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.