Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:13:06.882514 lava-dispatcher, installed at version: 2024.01
2 08:13:06.883270 start: 0 validate
3 08:13:06.883738 Start time: 2024-10-16 08:13:06.883707+00:00 (UTC)
4 08:13:06.884311 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:13:06.884836 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 08:13:06.925539 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:13:06.926133 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241016%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 08:13:06.954749 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:13:06.955700 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241016%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 08:13:08.006006 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:13:08.006492 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241016%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 08:13:08.044219 validate duration: 1.16
14 08:13:08.045087 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:13:08.045427 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:13:08.045737 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:13:08.046341 Not decompressing ramdisk as can be used compressed.
18 08:13:08.046785 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 08:13:08.047069 saving as /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/ramdisk/rootfs.cpio.gz
20 08:13:08.047347 total size: 8181887 (7 MB)
21 08:13:08.087772 progress 0 % (0 MB)
22 08:13:08.097891 progress 5 % (0 MB)
23 08:13:08.108237 progress 10 % (0 MB)
24 08:13:08.119042 progress 15 % (1 MB)
25 08:13:08.124723 progress 20 % (1 MB)
26 08:13:08.130279 progress 25 % (1 MB)
27 08:13:08.135661 progress 30 % (2 MB)
28 08:13:08.141659 progress 35 % (2 MB)
29 08:13:08.147229 progress 40 % (3 MB)
30 08:13:08.152922 progress 45 % (3 MB)
31 08:13:08.158212 progress 50 % (3 MB)
32 08:13:08.163818 progress 55 % (4 MB)
33 08:13:08.169026 progress 60 % (4 MB)
34 08:13:08.174638 progress 65 % (5 MB)
35 08:13:08.194007 progress 70 % (5 MB)
36 08:13:08.199753 progress 75 % (5 MB)
37 08:13:08.205091 progress 80 % (6 MB)
38 08:13:08.210797 progress 85 % (6 MB)
39 08:13:08.216112 progress 90 % (7 MB)
40 08:13:08.221464 progress 95 % (7 MB)
41 08:13:08.226220 progress 100 % (7 MB)
42 08:13:08.226882 7 MB downloaded in 0.18 s (43.47 MB/s)
43 08:13:08.227467 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:13:08.228426 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:13:08.228752 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:13:08.229047 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:13:08.229546 downloading http://storage.kernelci.org/next/master/next-20241016/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/kernel/Image
49 08:13:08.229809 saving as /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/kernel/Image
50 08:13:08.230031 total size: 47393280 (45 MB)
51 08:13:08.230254 No compression specified
52 08:13:08.273010 progress 0 % (0 MB)
53 08:13:08.302374 progress 5 % (2 MB)
54 08:13:08.331507 progress 10 % (4 MB)
55 08:13:08.360851 progress 15 % (6 MB)
56 08:13:08.390971 progress 20 % (9 MB)
57 08:13:08.420303 progress 25 % (11 MB)
58 08:13:08.449438 progress 30 % (13 MB)
59 08:13:08.479308 progress 35 % (15 MB)
60 08:13:08.508846 progress 40 % (18 MB)
61 08:13:08.537955 progress 45 % (20 MB)
62 08:13:08.567432 progress 50 % (22 MB)
63 08:13:08.596896 progress 55 % (24 MB)
64 08:13:08.625921 progress 60 % (27 MB)
65 08:13:08.655482 progress 65 % (29 MB)
66 08:13:08.685320 progress 70 % (31 MB)
67 08:13:08.714608 progress 75 % (33 MB)
68 08:13:08.744342 progress 80 % (36 MB)
69 08:13:08.774291 progress 85 % (38 MB)
70 08:13:08.804498 progress 90 % (40 MB)
71 08:13:08.834516 progress 95 % (42 MB)
72 08:13:08.863099 progress 100 % (45 MB)
73 08:13:08.863719 45 MB downloaded in 0.63 s (71.33 MB/s)
74 08:13:08.864259 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:13:08.865130 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:13:08.865435 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:13:08.865726 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:13:08.866196 downloading http://storage.kernelci.org/next/master/next-20241016/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 08:13:08.866487 saving as /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 08:13:08.866711 total size: 53209 (0 MB)
82 08:13:08.866933 No compression specified
83 08:13:08.912486 progress 61 % (0 MB)
84 08:13:08.913351 progress 100 % (0 MB)
85 08:13:08.913910 0 MB downloaded in 0.05 s (1.08 MB/s)
86 08:13:08.914401 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:13:08.915266 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:13:08.915550 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:13:08.915833 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:13:08.916349 downloading http://storage.kernelci.org/next/master/next-20241016/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/modules.tar.xz
92 08:13:08.916620 saving as /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/modules/modules.tar
93 08:13:08.916842 total size: 11602724 (11 MB)
94 08:13:08.917069 Using unxz to decompress xz
95 08:13:08.954313 progress 0 % (0 MB)
96 08:13:09.031124 progress 5 % (0 MB)
97 08:13:09.108648 progress 10 % (1 MB)
98 08:13:09.191474 progress 15 % (1 MB)
99 08:13:09.268173 progress 20 % (2 MB)
100 08:13:09.343955 progress 25 % (2 MB)
101 08:13:09.422693 progress 30 % (3 MB)
102 08:13:09.494784 progress 35 % (3 MB)
103 08:13:09.575028 progress 40 % (4 MB)
104 08:13:09.660744 progress 45 % (5 MB)
105 08:13:09.743000 progress 50 % (5 MB)
106 08:13:09.821466 progress 55 % (6 MB)
107 08:13:09.902146 progress 60 % (6 MB)
108 08:13:09.986392 progress 65 % (7 MB)
109 08:13:10.062792 progress 70 % (7 MB)
110 08:13:10.144017 progress 75 % (8 MB)
111 08:13:10.232293 progress 80 % (8 MB)
112 08:13:10.309227 progress 85 % (9 MB)
113 08:13:10.381776 progress 90 % (9 MB)
114 08:13:10.482156 progress 95 % (10 MB)
115 08:13:10.595464 progress 100 % (11 MB)
116 08:13:10.607745 11 MB downloaded in 1.69 s (6.54 MB/s)
117 08:13:10.608669 end: 1.4.1 http-download (duration 00:00:02) [common]
119 08:13:10.610463 end: 1.4 download-retry (duration 00:00:02) [common]
120 08:13:10.611042 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 08:13:10.611614 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 08:13:10.612195 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:13:10.612755 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 08:13:10.613843 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g
125 08:13:10.614798 makedir: /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin
126 08:13:10.615511 makedir: /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/tests
127 08:13:10.616231 makedir: /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/results
128 08:13:10.616926 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-add-keys
129 08:13:10.617974 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-add-sources
130 08:13:10.619000 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-background-process-start
131 08:13:10.620067 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-background-process-stop
132 08:13:10.621184 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-common-functions
133 08:13:10.622230 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-echo-ipv4
134 08:13:10.623273 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-install-packages
135 08:13:10.624347 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-installed-packages
136 08:13:10.625356 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-os-build
137 08:13:10.626341 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-probe-channel
138 08:13:10.627329 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-probe-ip
139 08:13:10.628478 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-target-ip
140 08:13:10.629537 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-target-mac
141 08:13:10.630595 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-target-storage
142 08:13:10.631606 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-test-case
143 08:13:10.632660 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-test-event
144 08:13:10.633639 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-test-feedback
145 08:13:10.634613 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-test-raise
146 08:13:10.635591 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-test-reference
147 08:13:10.636609 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-test-runner
148 08:13:10.637593 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-test-set
149 08:13:10.638618 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-test-shell
150 08:13:10.639633 Updating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-install-packages (oe)
151 08:13:10.640789 Updating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/bin/lava-installed-packages (oe)
152 08:13:10.641714 Creating /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/environment
153 08:13:10.642505 LAVA metadata
154 08:13:10.643044 - LAVA_JOB_ID=851060
155 08:13:10.643514 - LAVA_DISPATCHER_IP=192.168.6.2
156 08:13:10.644280 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 08:13:10.646254 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 08:13:10.646919 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 08:13:10.647377 skipped lava-vland-overlay
160 08:13:10.647916 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 08:13:10.648550 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 08:13:10.648983 skipped lava-multinode-overlay
163 08:13:10.649490 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 08:13:10.649990 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 08:13:10.650472 Loading test definitions
166 08:13:10.651018 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 08:13:10.651457 Using /lava-851060 at stage 0
168 08:13:10.653696 uuid=851060_1.5.2.4.1 testdef=None
169 08:13:10.654295 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 08:13:10.654819 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 08:13:10.657291 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 08:13:10.658132 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 08:13:10.660545 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 08:13:10.661447 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 08:13:10.663680 runner path: /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/0/tests/0_dmesg test_uuid 851060_1.5.2.4.1
178 08:13:10.664308 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 08:13:10.665113 Creating lava-test-runner.conf files
181 08:13:10.665321 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/851060/lava-overlay-f0uf517g/lava-851060/0 for stage 0
182 08:13:10.665660 - 0_dmesg
183 08:13:10.666020 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 08:13:10.666311 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 08:13:10.690314 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 08:13:10.690752 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 08:13:10.691022 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 08:13:10.691294 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 08:13:10.691560 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 08:13:11.615298 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 08:13:11.615766 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 08:13:11.616099 extracting modules file /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/851060/extract-overlay-ramdisk-vt9v0zek/ramdisk
193 08:13:12.995561 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 08:13:12.996075 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 08:13:12.996362 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851060/compress-overlay-dlexy537/overlay-1.5.2.5.tar.gz to ramdisk
196 08:13:12.996578 [common] Applying overlay /var/lib/lava/dispatcher/tmp/851060/compress-overlay-dlexy537/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/851060/extract-overlay-ramdisk-vt9v0zek/ramdisk
197 08:13:13.026899 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 08:13:13.027309 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 08:13:13.027581 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 08:13:13.027809 Converting downloaded kernel to a uImage
201 08:13:13.028141 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/kernel/Image /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/kernel/uImage
202 08:13:13.528231 output: Image Name:
203 08:13:13.528653 output: Created: Wed Oct 16 08:13:13 2024
204 08:13:13.528865 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 08:13:13.529073 output: Data Size: 47393280 Bytes = 46282.50 KiB = 45.20 MiB
206 08:13:13.529276 output: Load Address: 01080000
207 08:13:13.529475 output: Entry Point: 01080000
208 08:13:13.529672 output:
209 08:13:13.530008 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 08:13:13.530278 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 08:13:13.530547 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 08:13:13.530798 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 08:13:13.531054 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 08:13:13.531307 Building ramdisk /var/lib/lava/dispatcher/tmp/851060/extract-overlay-ramdisk-vt9v0zek/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/851060/extract-overlay-ramdisk-vt9v0zek/ramdisk
215 08:13:15.965707 >> 181815 blocks
216 08:13:24.404081 Adding RAMdisk u-boot header.
217 08:13:24.404536 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/851060/extract-overlay-ramdisk-vt9v0zek/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/851060/extract-overlay-ramdisk-vt9v0zek/ramdisk.cpio.gz.uboot
218 08:13:24.691869 output: Image Name:
219 08:13:24.692487 output: Created: Wed Oct 16 08:13:24 2024
220 08:13:24.692901 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 08:13:24.693302 output: Data Size: 26062119 Bytes = 25451.29 KiB = 24.85 MiB
222 08:13:24.693699 output: Load Address: 00000000
223 08:13:24.694090 output: Entry Point: 00000000
224 08:13:24.694474 output:
225 08:13:24.695543 rename /var/lib/lava/dispatcher/tmp/851060/extract-overlay-ramdisk-vt9v0zek/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/ramdisk/ramdisk.cpio.gz.uboot
226 08:13:24.696279 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 08:13:24.696819 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 08:13:24.697337 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 08:13:24.697786 No LXC device requested
230 08:13:24.698277 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 08:13:24.698777 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 08:13:24.699259 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 08:13:24.699667 Checking files for TFTP limit of 4294967296 bytes.
234 08:13:24.702314 end: 1 tftp-deploy (duration 00:00:17) [common]
235 08:13:24.702882 start: 2 uboot-action (timeout 00:05:00) [common]
236 08:13:24.703392 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 08:13:24.703881 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 08:13:24.704418 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 08:13:24.704943 Using kernel file from prepare-kernel: 851060/tftp-deploy-9n87iejz/kernel/uImage
240 08:13:24.705558 substitutions:
241 08:13:24.705963 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 08:13:24.706362 - {DTB_ADDR}: 0x01070000
243 08:13:24.706758 - {DTB}: 851060/tftp-deploy-9n87iejz/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 08:13:24.707154 - {INITRD}: 851060/tftp-deploy-9n87iejz/ramdisk/ramdisk.cpio.gz.uboot
245 08:13:24.707548 - {KERNEL_ADDR}: 0x01080000
246 08:13:24.707935 - {KERNEL}: 851060/tftp-deploy-9n87iejz/kernel/uImage
247 08:13:24.708355 - {LAVA_MAC}: None
248 08:13:24.708785 - {PRESEED_CONFIG}: None
249 08:13:24.709177 - {PRESEED_LOCAL}: None
250 08:13:24.709563 - {RAMDISK_ADDR}: 0x08000000
251 08:13:24.709949 - {RAMDISK}: 851060/tftp-deploy-9n87iejz/ramdisk/ramdisk.cpio.gz.uboot
252 08:13:24.710342 - {ROOT_PART}: None
253 08:13:24.710729 - {ROOT}: None
254 08:13:24.711115 - {SERVER_IP}: 192.168.6.2
255 08:13:24.711504 - {TEE_ADDR}: 0x83000000
256 08:13:24.711888 - {TEE}: None
257 08:13:24.712300 Parsed boot commands:
258 08:13:24.712677 - setenv autoload no
259 08:13:24.713062 - setenv initrd_high 0xffffffff
260 08:13:24.713446 - setenv fdt_high 0xffffffff
261 08:13:24.713830 - dhcp
262 08:13:24.714214 - setenv serverip 192.168.6.2
263 08:13:24.714598 - tftpboot 0x01080000 851060/tftp-deploy-9n87iejz/kernel/uImage
264 08:13:24.714983 - tftpboot 0x08000000 851060/tftp-deploy-9n87iejz/ramdisk/ramdisk.cpio.gz.uboot
265 08:13:24.715369 - tftpboot 0x01070000 851060/tftp-deploy-9n87iejz/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 08:13:24.715751 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 08:13:24.716200 - bootm 0x01080000 0x08000000 0x01070000
268 08:13:24.716691 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 08:13:24.718164 start: 2.3 connect-device (timeout 00:05:00) [common]
271 08:13:24.718602 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 08:13:24.732639 Setting prompt string to ['lava-test: # ']
273 08:13:24.734086 end: 2.3 connect-device (duration 00:00:00) [common]
274 08:13:24.734674 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 08:13:24.735214 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 08:13:24.735724 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 08:13:24.736912 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 08:13:24.775654 >> OK - accepted request
279 08:13:24.778058 Returned 0 in 0 seconds
280 08:13:24.879147 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 08:13:24.880789 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 08:13:24.881349 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 08:13:24.881848 Setting prompt string to ['Hit any key to stop autoboot']
285 08:13:24.882294 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 08:13:24.883880 Trying 192.168.56.21...
287 08:13:24.884390 Connected to conserv1.
288 08:13:24.884813 Escape character is '^]'.
289 08:13:24.885233
290 08:13:24.885657 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 08:13:24.886079
292 08:13:32.198393 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 08:13:32.199196 bl2_stage_init 0x01
294 08:13:32.199762 bl2_stage_init 0x81
295 08:13:32.204042 hw id: 0x0000 - pwm id 0x01
296 08:13:32.204689 bl2_stage_init 0xc1
297 08:13:32.205197 bl2_stage_init 0x02
298 08:13:32.205732
299 08:13:32.209522 L0:00000000
300 08:13:32.210106 L1:00000703
301 08:13:32.210640 L2:00008067
302 08:13:32.211163 L3:15000000
303 08:13:32.211645 S1:00000000
304 08:13:32.215195 B2:20282000
305 08:13:32.215748 B1:a0f83180
306 08:13:32.216316
307 08:13:32.216851 TE: 71721
308 08:13:32.217372
309 08:13:32.220669 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 08:13:32.221257
311 08:13:32.226361 Board ID = 1
312 08:13:32.226942 Set cpu clk to 24M
313 08:13:32.227476 Set clk81 to 24M
314 08:13:32.231924 Use GP1_pll as DSU clk.
315 08:13:32.232517 DSU clk: 1200 Mhz
316 08:13:32.233049 CPU clk: 1200 MHz
317 08:13:32.233574 Set clk81 to 166.6M
318 08:13:32.243262 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 08:13:32.243832 board id: 1
320 08:13:32.249444 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 08:13:32.260103 fw parse done
322 08:13:32.266119 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 08:13:32.308722 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 08:13:32.319647 PIEI prepare done
325 08:13:32.320246 fastboot data load
326 08:13:32.320782 fastboot data verify
327 08:13:32.325204 verify result: 266
328 08:13:32.330823 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 08:13:32.331397 LPDDR4 probe
330 08:13:32.331933 ddr clk to 1584MHz
331 08:13:32.338826 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 08:13:32.376148
333 08:13:32.376761 dmc_version 0001
334 08:13:32.382802 Check phy result
335 08:13:32.388730 INFO : End of CA training
336 08:13:32.389304 INFO : End of initialization
337 08:13:32.394261 INFO : Training has run successfully!
338 08:13:32.394824 Check phy result
339 08:13:32.399911 INFO : End of initialization
340 08:13:32.400533 INFO : End of read enable training
341 08:13:32.405470 INFO : End of fine write leveling
342 08:13:32.411192 INFO : End of Write leveling coarse delay
343 08:13:32.411756 INFO : Training has run successfully!
344 08:13:32.412345 Check phy result
345 08:13:32.416695 INFO : End of initialization
346 08:13:32.417252 INFO : End of read dq deskew training
347 08:13:32.422307 INFO : End of MPR read delay center optimization
348 08:13:32.427908 INFO : End of write delay center optimization
349 08:13:32.433459 INFO : End of read delay center optimization
350 08:13:32.434035 INFO : End of max read latency training
351 08:13:32.439185 INFO : Training has run successfully!
352 08:13:32.439753 1D training succeed
353 08:13:32.448320 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 08:13:32.495804 Check phy result
355 08:13:32.496437 INFO : End of initialization
356 08:13:32.518244 INFO : End of 2D read delay Voltage center optimization
357 08:13:32.537399 INFO : End of 2D read delay Voltage center optimization
358 08:13:32.589330 INFO : End of 2D write delay Voltage center optimization
359 08:13:32.638532 INFO : End of 2D write delay Voltage center optimization
360 08:13:32.644114 INFO : Training has run successfully!
361 08:13:32.644694
362 08:13:32.645183 channel==0
363 08:13:32.649643 RxClkDly_Margin_A0==78 ps 8
364 08:13:32.650212 TxDqDly_Margin_A0==98 ps 10
365 08:13:32.652981 RxClkDly_Margin_A1==78 ps 8
366 08:13:32.653541 TxDqDly_Margin_A1==88 ps 9
367 08:13:32.658536 TrainedVREFDQ_A0==74
368 08:13:32.659125 TrainedVREFDQ_A1==74
369 08:13:32.659659 VrefDac_Margin_A0==22
370 08:13:32.664096 DeviceVref_Margin_A0==40
371 08:13:32.664655 VrefDac_Margin_A1==22
372 08:13:32.669711 DeviceVref_Margin_A1==40
373 08:13:32.670281
374 08:13:32.670817
375 08:13:32.671337 channel==1
376 08:13:32.671812 RxClkDly_Margin_A0==78 ps 8
377 08:13:32.675242 TxDqDly_Margin_A0==98 ps 10
378 08:13:32.675810 RxClkDly_Margin_A1==88 ps 9
379 08:13:32.680845 TxDqDly_Margin_A1==78 ps 8
380 08:13:32.681404 TrainedVREFDQ_A0==78
381 08:13:32.681941 TrainedVREFDQ_A1==75
382 08:13:32.686450 VrefDac_Margin_A0==22
383 08:13:32.687023 DeviceVref_Margin_A0==36
384 08:13:32.692103 VrefDac_Margin_A1==22
385 08:13:32.692659 DeviceVref_Margin_A1==39
386 08:13:32.693190
387 08:13:32.697622 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 08:13:32.698181
389 08:13:32.731425 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 08:13:32.732082 2D training succeed
391 08:13:32.736796 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 08:13:32.737356 auto size-- 65535DDR cs0 size: 2048MB
393 08:13:32.742425 DDR cs1 size: 2048MB
394 08:13:32.742992 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 08:13:32.748068 cs0 DataBus test pass
396 08:13:32.748643 cs1 DataBus test pass
397 08:13:32.749166 cs0 AddrBus test pass
398 08:13:32.753594 cs1 AddrBus test pass
399 08:13:32.754157
400 08:13:32.754689 100bdlr_step_size ps== 478
401 08:13:32.755226 result report
402 08:13:32.759234 boot times 0Enable ddr reg access
403 08:13:32.766831 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 08:13:32.780676 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 08:13:33.436254 bl2z: ptr: 05129330, size: 00001e40
406 08:13:33.443850 0.0;M3 CHK:0;cm4_sp_mode 0
407 08:13:33.444758 MVN_1=0x00000000
408 08:13:33.445222 MVN_2=0x00000000
409 08:13:33.455416 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 08:13:33.455962 OPS=0x04
411 08:13:33.456445 ring efuse init
412 08:13:33.458409 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 08:13:33.464210 [0.017319 Inits done]
414 08:13:33.464737 secure task start!
415 08:13:33.465185 high task start!
416 08:13:33.465619 low task start!
417 08:13:33.468515 run into bl31
418 08:13:33.477128 NOTICE: BL31: v1.3(release):4fc40b1
419 08:13:33.484915 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 08:13:33.485444 NOTICE: BL31: G12A normal boot!
421 08:13:33.500498 NOTICE: BL31: BL33 decompress pass
422 08:13:33.506130 ERROR: Error initializing runtime service opteed_fast
423 08:13:36.247006 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 08:13:36.247658 bl2_stage_init 0x01
425 08:13:36.248159 bl2_stage_init 0x81
426 08:13:36.252592 hw id: 0x0000 - pwm id 0x01
427 08:13:36.253120 bl2_stage_init 0xc1
428 08:13:36.257890 bl2_stage_init 0x02
429 08:13:36.258453
430 08:13:36.258902 L0:00000000
431 08:13:36.259331 L1:00000703
432 08:13:36.259760 L2:00008067
433 08:13:36.260233 L3:15000000
434 08:13:36.263408 S1:00000000
435 08:13:36.263923 B2:20282000
436 08:13:36.264400 B1:a0f83180
437 08:13:36.264829
438 08:13:36.265255 TE: 69979
439 08:13:36.265679
440 08:13:36.268985 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 08:13:36.274557
442 08:13:36.275066 Board ID = 1
443 08:13:36.275500 Set cpu clk to 24M
444 08:13:36.275927 Set clk81 to 24M
445 08:13:36.278123 Use GP1_pll as DSU clk.
446 08:13:36.278634 DSU clk: 1200 Mhz
447 08:13:36.283751 CPU clk: 1200 MHz
448 08:13:36.284286 Set clk81 to 166.6M
449 08:13:36.289345 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 08:13:36.289931 board id: 1
451 08:13:36.299118 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 08:13:36.309625 fw parse done
453 08:13:36.315698 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 08:13:36.358183 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 08:13:36.369086 PIEI prepare done
456 08:13:36.369630 fastboot data load
457 08:13:36.370077 fastboot data verify
458 08:13:36.374776 verify result: 266
459 08:13:36.380310 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 08:13:36.380855 LPDDR4 probe
461 08:13:36.381296 ddr clk to 1584MHz
462 08:13:36.388295 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 08:13:36.425488
464 08:13:36.426020 dmc_version 0001
465 08:13:36.432235 Check phy result
466 08:13:36.438147 INFO : End of CA training
467 08:13:36.438711 INFO : End of initialization
468 08:13:36.443803 INFO : Training has run successfully!
469 08:13:36.444400 Check phy result
470 08:13:36.449305 INFO : End of initialization
471 08:13:36.449855 INFO : End of read enable training
472 08:13:36.452645 INFO : End of fine write leveling
473 08:13:36.458221 INFO : End of Write leveling coarse delay
474 08:13:36.463838 INFO : Training has run successfully!
475 08:13:36.464413 Check phy result
476 08:13:36.464883 INFO : End of initialization
477 08:13:36.469427 INFO : End of read dq deskew training
478 08:13:36.472855 INFO : End of MPR read delay center optimization
479 08:13:36.478440 INFO : End of write delay center optimization
480 08:13:36.484034 INFO : End of read delay center optimization
481 08:13:36.484567 INFO : End of max read latency training
482 08:13:36.489589 INFO : Training has run successfully!
483 08:13:36.490126 1D training succeed
484 08:13:36.497776 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 08:13:36.545334 Check phy result
486 08:13:36.545870 INFO : End of initialization
487 08:13:36.567719 INFO : End of 2D read delay Voltage center optimization
488 08:13:36.586921 INFO : End of 2D read delay Voltage center optimization
489 08:13:36.688213 INFO : End of 2D write delay Voltage center optimization
490 08:13:36.688771 INFO : End of 2D write delay Voltage center optimization
491 08:13:36.693574 INFO : Training has run successfully!
492 08:13:36.694108
493 08:13:36.694572 channel==0
494 08:13:36.699133 RxClkDly_Margin_A0==78 ps 8
495 08:13:36.699660 TxDqDly_Margin_A0==98 ps 10
496 08:13:36.702617 RxClkDly_Margin_A1==78 ps 8
497 08:13:36.703147 TxDqDly_Margin_A1==88 ps 9
498 08:13:36.708202 TrainedVREFDQ_A0==74
499 08:13:36.708743 TrainedVREFDQ_A1==74
500 08:13:36.709208 VrefDac_Margin_A0==24
501 08:13:36.713988 DeviceVref_Margin_A0==40
502 08:13:36.714523 VrefDac_Margin_A1==23
503 08:13:36.719414 DeviceVref_Margin_A1==40
504 08:13:36.719941
505 08:13:36.720444
506 08:13:36.720892 channel==1
507 08:13:36.721330 RxClkDly_Margin_A0==78 ps 8
508 08:13:36.725007 TxDqDly_Margin_A0==98 ps 10
509 08:13:36.725546 RxClkDly_Margin_A1==88 ps 9
510 08:13:36.730518 TxDqDly_Margin_A1==88 ps 9
511 08:13:36.731058 TrainedVREFDQ_A0==78
512 08:13:36.731520 TrainedVREFDQ_A1==75
513 08:13:36.736251 VrefDac_Margin_A0==22
514 08:13:36.736793 DeviceVref_Margin_A0==36
515 08:13:36.737252 VrefDac_Margin_A1==22
516 08:13:36.741820 DeviceVref_Margin_A1==39
517 08:13:36.742348
518 08:13:36.747302 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 08:13:36.747836
520 08:13:36.775317 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000062
521 08:13:36.780912 2D training succeed
522 08:13:36.792243 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 08:13:36.792800 auto size-- 65535DDR cs0 size: 2048MB
524 08:13:36.793261 DDR cs1 size: 2048MB
525 08:13:36.793705 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 08:13:36.797676 cs0 DataBus test pass
527 08:13:36.798215 cs1 DataBus test pass
528 08:13:36.798675 cs0 AddrBus test pass
529 08:13:36.803272 cs1 AddrBus test pass
530 08:13:36.803831
531 08:13:36.804353 100bdlr_step_size ps== 478
532 08:13:36.804817 result report
533 08:13:36.808854 boot times 0Enable ddr reg access
534 08:13:36.816236 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 08:13:36.830003 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 08:13:37.485992 bl2z: ptr: 05129330, size: 00001e40
537 08:13:37.493018 0.0;M3 CHK:0;cm4_sp_mode 0
538 08:13:37.493570 MVN_1=0x00000000
539 08:13:37.494036 MVN_2=0x00000000
540 08:13:37.504452 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 08:13:37.505000 OPS=0x04
542 08:13:37.505467 ring efuse init
543 08:13:37.507519 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 08:13:37.514009 [0.017319 Inits done]
545 08:13:37.514543 secure task start!
546 08:13:37.515002 high task start!
547 08:13:37.515447 low task start!
548 08:13:37.518255 run into bl31
549 08:13:37.526881 NOTICE: BL31: v1.3(release):4fc40b1
550 08:13:37.550282 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 08:13:37.550822 NOTICE: BL31: G12A normal boot!
552 08:13:37.551295 NOTICE: BL31: BL33 decompress pass
553 08:13:37.555974 ERROR: Error initializing runtime service opteed_fast
554 08:13:38.816719 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 08:13:38.817384 bl2_stage_init 0x01
556 08:13:38.817853 bl2_stage_init 0x81
557 08:13:38.822999 hw id: 0x0000 - pwm id 0x01
558 08:13:38.823647 bl2_stage_init 0xc1
559 08:13:38.827045 bl2_stage_init 0x02
560 08:13:38.827626
561 08:13:38.828109 L0:00000000
562 08:13:38.828556 L1:00000703
563 08:13:38.828992 L2:00008067
564 08:13:38.832679 L3:15000000
565 08:13:38.833300 S1:00000000
566 08:13:38.833787 B2:20282000
567 08:13:38.834269 B1:a0f83180
568 08:13:38.834730
569 08:13:38.835178 TE: 70885
570 08:13:38.835620
571 08:13:38.843659 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 08:13:38.844233
573 08:13:38.844694 Board ID = 1
574 08:13:38.845137 Set cpu clk to 24M
575 08:13:38.845575 Set clk81 to 24M
576 08:13:38.849286 Use GP1_pll as DSU clk.
577 08:13:38.849808 DSU clk: 1200 Mhz
578 08:13:38.850260 CPU clk: 1200 MHz
579 08:13:38.854951 Set clk81 to 166.6M
580 08:13:38.860476 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 08:13:38.860995 board id: 1
582 08:13:38.868588 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 08:13:38.879476 fw parse done
584 08:13:38.885459 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 08:13:38.939860 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 08:13:38.940453 PIEI prepare done
587 08:13:38.940918 fastboot data load
588 08:13:38.941377 fastboot data verify
589 08:13:38.945397 verify result: 266
590 08:13:38.951139 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 08:13:38.951663 LPDDR4 probe
592 08:13:38.952163 ddr clk to 1584MHz
593 08:13:38.958974 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 08:13:38.996696
595 08:13:38.997217 dmc_version 0001
596 08:13:39.003702 Check phy result
597 08:13:39.009744 INFO : End of CA training
598 08:13:39.010266 INFO : End of initialization
599 08:13:39.015281 INFO : Training has run successfully!
600 08:13:39.015800 Check phy result
601 08:13:39.020873 INFO : End of initialization
602 08:13:39.021392 INFO : End of read enable training
603 08:13:39.026506 INFO : End of fine write leveling
604 08:13:39.032095 INFO : End of Write leveling coarse delay
605 08:13:39.032617 INFO : Training has run successfully!
606 08:13:39.033073 Check phy result
607 08:13:39.037706 INFO : End of initialization
608 08:13:39.038216 INFO : End of read dq deskew training
609 08:13:39.043339 INFO : End of MPR read delay center optimization
610 08:13:39.048926 INFO : End of write delay center optimization
611 08:13:39.054500 INFO : End of read delay center optimization
612 08:13:39.055021 INFO : End of max read latency training
613 08:13:39.060099 INFO : Training has run successfully!
614 08:13:39.060616 1D training succeed
615 08:13:39.069264 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 08:13:39.117574 Check phy result
617 08:13:39.118095 INFO : End of initialization
618 08:13:39.144933 INFO : End of 2D read delay Voltage center optimization
619 08:13:39.169200 INFO : End of 2D read delay Voltage center optimization
620 08:13:39.225842 INFO : End of 2D write delay Voltage center optimization
621 08:13:39.279847 INFO : End of 2D write delay Voltage center optimization
622 08:13:39.285464 INFO : Training has run successfully!
623 08:13:39.285995
624 08:13:39.286463 channel==0
625 08:13:39.291144 RxClkDly_Margin_A0==78 ps 8
626 08:13:39.291661 TxDqDly_Margin_A0==98 ps 10
627 08:13:39.296655 RxClkDly_Margin_A1==88 ps 9
628 08:13:39.297175 TxDqDly_Margin_A1==88 ps 9
629 08:13:39.297633 TrainedVREFDQ_A0==74
630 08:13:39.302240 TrainedVREFDQ_A1==74
631 08:13:39.302760 VrefDac_Margin_A0==24
632 08:13:39.303213 DeviceVref_Margin_A0==40
633 08:13:39.313503 VrefDac_Margin_A1==22
634 08:13:39.314030 DeviceVref_Margin_A1==40
635 08:13:39.314480
636 08:13:39.314925
637 08:13:39.315370 channel==1
638 08:13:39.315803 RxClkDly_Margin_A0==78 ps 8
639 08:13:39.316293 TxDqDly_Margin_A0==98 ps 10
640 08:13:39.319143 RxClkDly_Margin_A1==78 ps 8
641 08:13:39.319664 TxDqDly_Margin_A1==78 ps 8
642 08:13:39.324681 TrainedVREFDQ_A0==75
643 08:13:39.325205 TrainedVREFDQ_A1==75
644 08:13:39.325660 VrefDac_Margin_A0==22
645 08:13:39.330228 DeviceVref_Margin_A0==39
646 08:13:39.330748 VrefDac_Margin_A1==22
647 08:13:39.335833 DeviceVref_Margin_A1==39
648 08:13:39.336379
649 08:13:39.336836 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 08:13:39.337281
651 08:13:39.369388 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000062
652 08:13:39.369942 2D training succeed
653 08:13:39.375135 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 08:13:39.380640 auto size-- 65535DDR cs0 size: 2048MB
655 08:13:39.381163 DDR cs1 size: 2048MB
656 08:13:39.386214 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 08:13:39.386734 cs0 DataBus test pass
658 08:13:39.391833 cs1 DataBus test pass
659 08:13:39.392393 cs0 AddrBus test pass
660 08:13:39.392853 cs1 AddrBus test pass
661 08:13:39.393295
662 08:13:39.403231 100bdlr_step_size ps== 478
663 08:13:39.403760 result report
664 08:13:39.404262 boot times 0Enable ddr reg access
665 08:13:39.408272 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 08:13:39.422167 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 08:13:40.081346 bl2z: ptr: 05129330, size: 00001e40
668 08:13:40.090169 0.0;M3 CHK:0;cm4_sp_mode 0
669 08:13:40.090726 MVN_1=0x00000000
670 08:13:40.091191 MVN_2=0x00000000
671 08:13:40.101558 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 08:13:40.102097 OPS=0x04
673 08:13:40.102558 ring efuse init
674 08:13:40.107224 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 08:13:40.107755 [0.017354 Inits done]
676 08:13:40.108261 secure task start!
677 08:13:40.114626 high task start!
678 08:13:40.115142 low task start!
679 08:13:40.115598 run into bl31
680 08:13:40.123219 NOTICE: BL31: v1.3(release):4fc40b1
681 08:13:40.131034 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 08:13:40.131565 NOTICE: BL31: G12A normal boot!
683 08:13:40.146630 NOTICE: BL31: BL33 decompress pass
684 08:13:40.152383 ERROR: Error initializing runtime service opteed_fast
685 08:13:40.947714
686 08:13:40.948387
687 08:13:40.953131 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 08:13:40.953666
689 08:13:40.956617 Model: Libre Computer AML-S905D3-CC Solitude
690 08:13:41.103596 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 08:13:41.119063 DRAM: 2 GiB (effective 3.8 GiB)
692 08:13:41.220052 Core: 406 devices, 33 uclasses, devicetree: separate
693 08:13:41.225904 WDT: Not starting watchdog@f0d0
694 08:13:41.254339 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 08:13:41.263350 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 08:13:41.268234 ** Bad device specification mmc 0 **
697 08:13:41.278310 Card did not respond to voltage select! : -110
698 08:13:41.285864 ** Bad device specification mmc 0 **
699 08:13:41.286364 Couldn't find partition mmc 0
700 08:13:41.294297 Card did not respond to voltage select! : -110
701 08:13:41.299713 ** Bad device specification mmc 0 **
702 08:13:41.300251 Couldn't find partition mmc 0
703 08:13:41.304776 Error: could not access storage.
704 08:13:41.602171 Net: eth0: ethernet@ff3f0000
705 08:13:41.602730 starting USB...
706 08:13:41.847550 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 08:13:41.848144 Starting the controller
708 08:13:41.853195 USB XHCI 1.10
709 08:13:43.410156 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 08:13:43.418548 scanning usb for storage devices... 0 Storage Device(s) found
712 08:13:43.470212 Hit any key to stop autoboot: 1
713 08:13:43.471303 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 08:13:43.472076 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 08:13:43.472661 Setting prompt string to ['=>']
716 08:13:43.473226 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 08:13:43.484621 0
718 08:13:43.485652 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 08:13:43.586967 => setenv autoload no
721 08:13:43.587899 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 08:13:43.593234 setenv autoload no
724 08:13:43.694826 => setenv initrd_high 0xffffffff
725 08:13:43.695718 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 08:13:43.700253 setenv initrd_high 0xffffffff
728 08:13:43.801807 => setenv fdt_high 0xffffffff
729 08:13:43.802700 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 08:13:43.807159 setenv fdt_high 0xffffffff
732 08:13:43.908786 => dhcp
733 08:13:43.909671 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 08:13:43.913074 dhcp
735 08:13:44.519286 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 08:13:44.519959 Speed: 1000, full duplex
737 08:13:44.520498 BOOTP broadcast 1
738 08:13:44.558417 DHCP client bound to address 192.168.6.19 (38 ms)
740 08:13:44.660049 => setenv serverip 192.168.6.2
741 08:13:44.660970 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 08:13:44.665367 setenv serverip 192.168.6.2
744 08:13:44.766924 => tftpboot 0x01080000 851060/tftp-deploy-9n87iejz/kernel/uImage
745 08:13:44.767811 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 08:13:44.774407 tftpboot 0x01080000 851060/tftp-deploy-9n87iejz/kernel/uImage
747 08:13:44.774929 Speed: 1000, full duplex
748 08:13:44.775387 Using ethernet@ff3f0000 device
749 08:13:44.780007 TFTP from server 192.168.6.2; our IP address is 192.168.6.19
750 08:13:44.785536 Filename '851060/tftp-deploy-9n87iejz/kernel/uImage'.
751 08:13:44.789402 Load address: 0x1080000
752 08:14:22.716105 Loading: *T T T T T T T UDP wrong checksum 000000ff 000074fd
753 08:14:22.752496 UDP wrong checksum 000000ff 0000feef
754 08:14:27.623068 T UDP wrong checksum 000000ff 0000550e
755 08:14:27.652659 UDP wrong checksum 000000ff 0000b000
756 08:14:39.884132 T T
757 08:14:39.884815 Retry count exceeded; starting again
759 08:14:39.886536 end: 2.4.3 bootloader-commands (duration 00:00:56) [common]
762 08:14:39.887535 end: 2.4 uboot-commands (duration 00:01:15) [common]
764 08:14:39.888323 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
766 08:14:39.888917 end: 2 uboot-action (duration 00:01:15) [common]
768 08:14:39.889780 Cleaning after the job
769 08:14:39.890128 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/ramdisk
770 08:14:39.897843 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/kernel
771 08:14:39.913338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/dtb
772 08:14:39.914210 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/851060/tftp-deploy-9n87iejz/modules
773 08:14:39.935926 start: 4.1 power-off (timeout 00:00:30) [common]
774 08:14:39.936648 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
775 08:14:39.970455 >> OK - accepted request
776 08:14:39.972527 Returned 0 in 0 seconds
777 08:14:40.074220 end: 4.1 power-off (duration 00:00:00) [common]
779 08:14:40.075305 start: 4.2 read-feedback (timeout 00:10:00) [common]
780 08:14:40.076041 Listened to connection for namespace 'common' for up to 1s
781 08:14:41.076231 Finalising connection for namespace 'common'
782 08:14:41.076744 Disconnecting from shell: Finalise
783 08:14:41.077020 =>
784 08:14:41.177714 end: 4.2 read-feedback (duration 00:00:01) [common]
785 08:14:41.178230 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/851060
786 08:14:41.459943 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/851060
787 08:14:41.460556 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.