Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:25:01.293439 lava-dispatcher, installed at version: 2024.01
2 08:25:01.294224 start: 0 validate
3 08:25:01.294698 Start time: 2024-10-21 08:25:01.294668+00:00 (UTC)
4 08:25:01.295245 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:25:01.295776 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 08:25:01.336180 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:25:01.336779 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241021%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 08:25:01.367346 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:25:01.368270 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241021%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 08:25:02.418641 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:25:02.419142 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241021%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 08:25:02.460137 validate duration: 1.17
14 08:25:02.461014 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:25:02.461349 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:25:02.461663 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:25:02.462319 Not decompressing ramdisk as can be used compressed.
18 08:25:02.462772 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 08:25:02.463051 saving as /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/ramdisk/rootfs.cpio.gz
20 08:25:02.463335 total size: 8181887 (7 MB)
21 08:25:02.500237 progress 0 % (0 MB)
22 08:25:02.511685 progress 5 % (0 MB)
23 08:25:02.522918 progress 10 % (0 MB)
24 08:25:02.533124 progress 15 % (1 MB)
25 08:25:02.538335 progress 20 % (1 MB)
26 08:25:02.543928 progress 25 % (1 MB)
27 08:25:02.549156 progress 30 % (2 MB)
28 08:25:02.554719 progress 35 % (2 MB)
29 08:25:02.559906 progress 40 % (3 MB)
30 08:25:02.565470 progress 45 % (3 MB)
31 08:25:02.570570 progress 50 % (3 MB)
32 08:25:02.576128 progress 55 % (4 MB)
33 08:25:02.581257 progress 60 % (4 MB)
34 08:25:02.586928 progress 65 % (5 MB)
35 08:25:02.592102 progress 70 % (5 MB)
36 08:25:02.597589 progress 75 % (5 MB)
37 08:25:02.602730 progress 80 % (6 MB)
38 08:25:02.608213 progress 85 % (6 MB)
39 08:25:02.613287 progress 90 % (7 MB)
40 08:25:02.618737 progress 95 % (7 MB)
41 08:25:02.623476 progress 100 % (7 MB)
42 08:25:02.624140 7 MB downloaded in 0.16 s (48.53 MB/s)
43 08:25:02.624721 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:25:02.625672 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:25:02.625992 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:25:02.626282 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:25:02.626766 downloading http://storage.kernelci.org/next/master/next-20241021/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
49 08:25:02.627022 saving as /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/kernel/Image
50 08:25:02.627244 total size: 46064128 (43 MB)
51 08:25:02.627463 No compression specified
52 08:25:02.662214 progress 0 % (0 MB)
53 08:25:02.690551 progress 5 % (2 MB)
54 08:25:02.717992 progress 10 % (4 MB)
55 08:25:02.745619 progress 15 % (6 MB)
56 08:25:02.773545 progress 20 % (8 MB)
57 08:25:02.801534 progress 25 % (11 MB)
58 08:25:02.829111 progress 30 % (13 MB)
59 08:25:02.857110 progress 35 % (15 MB)
60 08:25:02.884982 progress 40 % (17 MB)
61 08:25:02.912692 progress 45 % (19 MB)
62 08:25:02.940137 progress 50 % (21 MB)
63 08:25:02.968105 progress 55 % (24 MB)
64 08:25:02.996211 progress 60 % (26 MB)
65 08:25:03.024021 progress 65 % (28 MB)
66 08:25:03.051914 progress 70 % (30 MB)
67 08:25:03.080074 progress 75 % (32 MB)
68 08:25:03.107714 progress 80 % (35 MB)
69 08:25:03.135444 progress 85 % (37 MB)
70 08:25:03.163410 progress 90 % (39 MB)
71 08:25:03.191196 progress 95 % (41 MB)
72 08:25:03.218419 progress 100 % (43 MB)
73 08:25:03.219127 43 MB downloaded in 0.59 s (74.22 MB/s)
74 08:25:03.219636 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:25:03.220540 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:25:03.220841 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:25:03.221128 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:25:03.221607 downloading http://storage.kernelci.org/next/master/next-20241021/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 08:25:03.221891 saving as /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 08:25:03.222109 total size: 53209 (0 MB)
82 08:25:03.222329 No compression specified
83 08:25:03.256944 progress 61 % (0 MB)
84 08:25:03.257789 progress 100 % (0 MB)
85 08:25:03.258336 0 MB downloaded in 0.04 s (1.40 MB/s)
86 08:25:03.258817 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:25:03.259675 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:25:03.259950 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:25:03.260265 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:25:03.260728 downloading http://storage.kernelci.org/next/master/next-20241021/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
92 08:25:03.260983 saving as /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/modules/modules.tar
93 08:25:03.261203 total size: 11616808 (11 MB)
94 08:25:03.261424 Using unxz to decompress xz
95 08:25:03.298049 progress 0 % (0 MB)
96 08:25:03.364370 progress 5 % (0 MB)
97 08:25:03.438393 progress 10 % (1 MB)
98 08:25:03.516955 progress 15 % (1 MB)
99 08:25:03.591518 progress 20 % (2 MB)
100 08:25:03.666107 progress 25 % (2 MB)
101 08:25:03.744058 progress 30 % (3 MB)
102 08:25:03.818704 progress 35 % (3 MB)
103 08:25:03.895654 progress 40 % (4 MB)
104 08:25:03.980530 progress 45 % (5 MB)
105 08:25:04.059972 progress 50 % (5 MB)
106 08:25:04.137275 progress 55 % (6 MB)
107 08:25:04.216724 progress 60 % (6 MB)
108 08:25:04.300318 progress 65 % (7 MB)
109 08:25:04.382917 progress 70 % (7 MB)
110 08:25:04.457547 progress 75 % (8 MB)
111 08:25:04.539123 progress 80 % (8 MB)
112 08:25:04.617750 progress 85 % (9 MB)
113 08:25:04.689094 progress 90 % (10 MB)
114 08:25:04.782068 progress 95 % (10 MB)
115 08:25:04.881106 progress 100 % (11 MB)
116 08:25:04.893443 11 MB downloaded in 1.63 s (6.79 MB/s)
117 08:25:04.894026 end: 1.4.1 http-download (duration 00:00:02) [common]
119 08:25:04.894866 end: 1.4 download-retry (duration 00:00:02) [common]
120 08:25:04.895142 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 08:25:04.895413 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 08:25:04.895664 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:25:04.895924 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 08:25:04.896947 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m
125 08:25:04.897831 makedir: /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin
126 08:25:04.898525 makedir: /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/tests
127 08:25:04.899192 makedir: /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/results
128 08:25:04.899865 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-add-keys
129 08:25:04.900952 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-add-sources
130 08:25:04.901962 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-background-process-start
131 08:25:04.902983 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-background-process-stop
132 08:25:04.904082 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-common-functions
133 08:25:04.905099 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-echo-ipv4
134 08:25:04.906081 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-install-packages
135 08:25:04.907044 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-installed-packages
136 08:25:04.908030 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-os-build
137 08:25:04.909009 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-probe-channel
138 08:25:04.909977 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-probe-ip
139 08:25:04.910951 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-target-ip
140 08:25:04.911909 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-target-mac
141 08:25:04.912915 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-target-storage
142 08:25:04.913903 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-test-case
143 08:25:04.914877 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-test-event
144 08:25:04.915831 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-test-feedback
145 08:25:04.916884 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-test-raise
146 08:25:04.917841 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-test-reference
147 08:25:04.918809 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-test-runner
148 08:25:04.919777 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-test-set
149 08:25:04.920811 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-test-shell
150 08:25:04.921800 Updating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-install-packages (oe)
151 08:25:04.922863 Updating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/bin/lava-installed-packages (oe)
152 08:25:04.923762 Creating /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/environment
153 08:25:04.924579 LAVA metadata
154 08:25:04.925119 - LAVA_JOB_ID=872368
155 08:25:04.925594 - LAVA_DISPATCHER_IP=192.168.6.2
156 08:25:04.926299 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 08:25:04.928260 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 08:25:04.928925 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 08:25:04.929387 skipped lava-vland-overlay
160 08:25:04.929929 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 08:25:04.930495 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 08:25:04.930968 skipped lava-multinode-overlay
163 08:25:04.931505 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 08:25:04.932099 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 08:25:04.932596 Loading test definitions
166 08:25:04.933146 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 08:25:04.933590 Using /lava-872368 at stage 0
168 08:25:04.935761 uuid=872368_1.5.2.4.1 testdef=None
169 08:25:04.936252 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 08:25:04.936531 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 08:25:04.938343 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 08:25:04.939173 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 08:25:04.941452 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 08:25:04.942341 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 08:25:04.944611 runner path: /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/0/tests/0_dmesg test_uuid 872368_1.5.2.4.1
178 08:25:04.945187 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 08:25:04.945983 Creating lava-test-runner.conf files
181 08:25:04.946191 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/872368/lava-overlay-zrkwho3m/lava-872368/0 for stage 0
182 08:25:04.946524 - 0_dmesg
183 08:25:04.946880 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 08:25:04.947171 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 08:25:04.970692 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 08:25:04.971087 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 08:25:04.971362 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 08:25:04.971635 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 08:25:04.971904 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 08:25:05.882529 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 08:25:05.883060 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 08:25:05.883568 extracting modules file /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/872368/extract-overlay-ramdisk-ddgm38sp/ramdisk
193 08:25:07.238784 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 08:25:07.239268 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 08:25:07.239545 [common] Applying overlay /var/lib/lava/dispatcher/tmp/872368/compress-overlay-nbr4ot22/overlay-1.5.2.5.tar.gz to ramdisk
196 08:25:07.239759 [common] Applying overlay /var/lib/lava/dispatcher/tmp/872368/compress-overlay-nbr4ot22/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/872368/extract-overlay-ramdisk-ddgm38sp/ramdisk
197 08:25:07.270064 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 08:25:07.270463 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 08:25:07.270749 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 08:25:07.270982 Converting downloaded kernel to a uImage
201 08:25:07.271290 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/kernel/Image /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/kernel/uImage
202 08:25:07.788672 output: Image Name:
203 08:25:07.789103 output: Created: Mon Oct 21 08:25:07 2024
204 08:25:07.789320 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 08:25:07.789530 output: Data Size: 46064128 Bytes = 44984.50 KiB = 43.93 MiB
206 08:25:07.789734 output: Load Address: 01080000
207 08:25:07.789936 output: Entry Point: 01080000
208 08:25:07.790136 output:
209 08:25:07.790474 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 08:25:07.790743 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 08:25:07.791014 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 08:25:07.791272 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 08:25:07.791532 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 08:25:07.791790 Building ramdisk /var/lib/lava/dispatcher/tmp/872368/extract-overlay-ramdisk-ddgm38sp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/872368/extract-overlay-ramdisk-ddgm38sp/ramdisk
215 08:25:10.119879 >> 182286 blocks
216 08:25:18.545687 Adding RAMdisk u-boot header.
217 08:25:18.546356 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/872368/extract-overlay-ramdisk-ddgm38sp/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/872368/extract-overlay-ramdisk-ddgm38sp/ramdisk.cpio.gz.uboot
218 08:25:18.837762 output: Image Name:
219 08:25:18.838178 output: Created: Mon Oct 21 08:25:18 2024
220 08:25:18.838389 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 08:25:18.838596 output: Data Size: 26101957 Bytes = 25490.19 KiB = 24.89 MiB
222 08:25:18.838802 output: Load Address: 00000000
223 08:25:18.839001 output: Entry Point: 00000000
224 08:25:18.839199 output:
225 08:25:18.839827 rename /var/lib/lava/dispatcher/tmp/872368/extract-overlay-ramdisk-ddgm38sp/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/ramdisk/ramdisk.cpio.gz.uboot
226 08:25:18.840549 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 08:25:18.841174 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 08:25:18.841754 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 08:25:18.842253 No LXC device requested
230 08:25:18.842799 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 08:25:18.843354 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 08:25:18.843896 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 08:25:18.844387 Checking files for TFTP limit of 4294967296 bytes.
234 08:25:18.847289 end: 1 tftp-deploy (duration 00:00:16) [common]
235 08:25:18.847917 start: 2 uboot-action (timeout 00:05:00) [common]
236 08:25:18.848531 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 08:25:18.849086 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 08:25:18.849639 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 08:25:18.850222 Using kernel file from prepare-kernel: 872368/tftp-deploy-7rlkq2rc/kernel/uImage
240 08:25:18.850909 substitutions:
241 08:25:18.851364 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 08:25:18.851812 - {DTB_ADDR}: 0x01070000
243 08:25:18.852284 - {DTB}: 872368/tftp-deploy-7rlkq2rc/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 08:25:18.852729 - {INITRD}: 872368/tftp-deploy-7rlkq2rc/ramdisk/ramdisk.cpio.gz.uboot
245 08:25:18.853168 - {KERNEL_ADDR}: 0x01080000
246 08:25:18.853608 - {KERNEL}: 872368/tftp-deploy-7rlkq2rc/kernel/uImage
247 08:25:18.854048 - {LAVA_MAC}: None
248 08:25:18.854524 - {PRESEED_CONFIG}: None
249 08:25:18.854965 - {PRESEED_LOCAL}: None
250 08:25:18.855396 - {RAMDISK_ADDR}: 0x08000000
251 08:25:18.855824 - {RAMDISK}: 872368/tftp-deploy-7rlkq2rc/ramdisk/ramdisk.cpio.gz.uboot
252 08:25:18.856294 - {ROOT_PART}: None
253 08:25:18.856733 - {ROOT}: None
254 08:25:18.857170 - {SERVER_IP}: 192.168.6.2
255 08:25:18.857607 - {TEE_ADDR}: 0x83000000
256 08:25:18.858041 - {TEE}: None
257 08:25:18.858474 Parsed boot commands:
258 08:25:18.858897 - setenv autoload no
259 08:25:18.859328 - setenv initrd_high 0xffffffff
260 08:25:18.859760 - setenv fdt_high 0xffffffff
261 08:25:18.860222 - dhcp
262 08:25:18.860656 - setenv serverip 192.168.6.2
263 08:25:18.861090 - tftpboot 0x01080000 872368/tftp-deploy-7rlkq2rc/kernel/uImage
264 08:25:18.861525 - tftpboot 0x08000000 872368/tftp-deploy-7rlkq2rc/ramdisk/ramdisk.cpio.gz.uboot
265 08:25:18.861957 - tftpboot 0x01070000 872368/tftp-deploy-7rlkq2rc/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 08:25:18.862391 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 08:25:18.862831 - bootm 0x01080000 0x08000000 0x01070000
268 08:25:18.863371 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 08:25:18.865040 start: 2.3 connect-device (timeout 00:05:00) [common]
271 08:25:18.865526 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 08:25:18.880904 Setting prompt string to ['lava-test: # ']
273 08:25:18.882485 end: 2.3 connect-device (duration 00:00:00) [common]
274 08:25:18.883132 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 08:25:18.883732 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 08:25:18.884351 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 08:25:18.885596 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 08:25:18.928216 >> OK - accepted request
279 08:25:18.930345 Returned 0 in 0 seconds
280 08:25:19.031474 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 08:25:19.033183 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 08:25:19.033793 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 08:25:19.034341 Setting prompt string to ['Hit any key to stop autoboot']
285 08:25:19.034821 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 08:25:19.036550 Trying 192.168.56.21...
287 08:25:19.037074 Connected to conserv1.
288 08:25:19.037527 Escape character is '^]'.
289 08:25:19.037990
290 08:25:19.038453 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 08:25:19.038922
292 08:25:26.399669 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 08:25:26.400345 bl2_stage_init 0x01
294 08:25:26.400811 bl2_stage_init 0x81
295 08:25:26.405217 hw id: 0x0000 - pwm id 0x01
296 08:25:26.405719 bl2_stage_init 0xc1
297 08:25:26.410923 bl2_stage_init 0x02
298 08:25:26.411412
299 08:25:26.411852 L0:00000000
300 08:25:26.412321 L1:00000703
301 08:25:26.412761 L2:00008067
302 08:25:26.413186 L3:15000000
303 08:25:26.416315 S1:00000000
304 08:25:26.416786 B2:20282000
305 08:25:26.417218 B1:a0f83180
306 08:25:26.417644
307 08:25:26.418072 TE: 72318
308 08:25:26.418499
309 08:25:26.421997 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 08:25:26.422462
311 08:25:26.427613 Board ID = 1
312 08:25:26.428105 Set cpu clk to 24M
313 08:25:26.428539 Set clk81 to 24M
314 08:25:26.433161 Use GP1_pll as DSU clk.
315 08:25:26.433619 DSU clk: 1200 Mhz
316 08:25:26.434051 CPU clk: 1200 MHz
317 08:25:26.438910 Set clk81 to 166.6M
318 08:25:26.444493 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 08:25:26.444960 board id: 1
320 08:25:26.451442 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 08:25:26.462380 fw parse done
322 08:25:26.468319 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 08:25:26.510700 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 08:25:26.522587 PIEI prepare done
325 08:25:26.523049 fastboot data load
326 08:25:26.523483 fastboot data verify
327 08:25:26.528187 verify result: 266
328 08:25:26.533751 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 08:25:26.534205 LPDDR4 probe
330 08:25:26.534633 ddr clk to 1584MHz
331 08:25:26.541732 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 08:25:26.579534
333 08:25:26.580029 dmc_version 0001
334 08:25:26.586527 Check phy result
335 08:25:26.592491 INFO : End of CA training
336 08:25:26.592951 INFO : End of initialization
337 08:25:26.598074 INFO : Training has run successfully!
338 08:25:26.598524 Check phy result
339 08:25:26.603664 INFO : End of initialization
340 08:25:26.604149 INFO : End of read enable training
341 08:25:26.609333 INFO : End of fine write leveling
342 08:25:26.614873 INFO : End of Write leveling coarse delay
343 08:25:26.615331 INFO : Training has run successfully!
344 08:25:26.615759 Check phy result
345 08:25:26.620499 INFO : End of initialization
346 08:25:26.620974 INFO : End of read dq deskew training
347 08:25:26.626079 INFO : End of MPR read delay center optimization
348 08:25:26.631671 INFO : End of write delay center optimization
349 08:25:26.637327 INFO : End of read delay center optimization
350 08:25:26.637793 INFO : End of max read latency training
351 08:25:26.642870 INFO : Training has run successfully!
352 08:25:26.643328 1D training succeed
353 08:25:26.652081 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 08:25:26.700335 Check phy result
355 08:25:26.700790 INFO : End of initialization
356 08:25:26.727716 INFO : End of 2D read delay Voltage center optimization
357 08:25:26.752210 INFO : End of 2D read delay Voltage center optimization
358 08:25:26.808577 INFO : End of 2D write delay Voltage center optimization
359 08:25:26.862628 INFO : End of 2D write delay Voltage center optimization
360 08:25:26.868222 INFO : Training has run successfully!
361 08:25:26.868678
362 08:25:26.869112 channel==0
363 08:25:26.873797 RxClkDly_Margin_A0==78 ps 8
364 08:25:26.874250 TxDqDly_Margin_A0==98 ps 10
365 08:25:26.879494 RxClkDly_Margin_A1==88 ps 9
366 08:25:26.879954 TxDqDly_Margin_A1==88 ps 9
367 08:25:26.880434 TrainedVREFDQ_A0==74
368 08:25:26.885022 TrainedVREFDQ_A1==74
369 08:25:26.885479 VrefDac_Margin_A0==24
370 08:25:26.885908 DeviceVref_Margin_A0==40
371 08:25:26.890621 VrefDac_Margin_A1==23
372 08:25:26.891075 DeviceVref_Margin_A1==40
373 08:25:26.891504
374 08:25:26.891934
375 08:25:26.892401 channel==1
376 08:25:26.896217 RxClkDly_Margin_A0==78 ps 8
377 08:25:26.896671 TxDqDly_Margin_A0==98 ps 10
378 08:25:26.901775 RxClkDly_Margin_A1==88 ps 9
379 08:25:26.902243 TxDqDly_Margin_A1==78 ps 8
380 08:25:26.907490 TrainedVREFDQ_A0==75
381 08:25:26.907946 TrainedVREFDQ_A1==75
382 08:25:26.908413 VrefDac_Margin_A0==22
383 08:25:26.913011 DeviceVref_Margin_A0==39
384 08:25:26.913464 VrefDac_Margin_A1==22
385 08:25:26.918618 DeviceVref_Margin_A1==38
386 08:25:26.919070
387 08:25:26.919506 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 08:25:26.919935
389 08:25:26.952221 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000016 00000018 00000018 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 08:25:26.952747 2D training succeed
391 08:25:26.957800 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 08:25:26.963516 auto size-- 65535DDR cs0 size: 2048MB
393 08:25:26.963973 DDR cs1 size: 2048MB
394 08:25:26.969003 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 08:25:26.969456 cs0 DataBus test pass
396 08:25:26.974616 cs1 DataBus test pass
397 08:25:26.975067 cs0 AddrBus test pass
398 08:25:26.975494 cs1 AddrBus test pass
399 08:25:26.975916
400 08:25:26.980223 100bdlr_step_size ps== 471
401 08:25:26.980690 result report
402 08:25:26.985789 boot times 0Enable ddr reg access
403 08:25:26.990979 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 08:25:27.004921 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 08:25:27.664482 bl2z: ptr: 05129330, size: 00001e40
406 08:25:27.672770 0.0;M3 CHK:0;cm4_sp_mode 0
407 08:25:27.673256 MVN_1=0x00000000
408 08:25:27.673703 MVN_2=0x00000000
409 08:25:27.684283 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 08:25:27.684774 OPS=0x04
411 08:25:27.685225 ring efuse init
412 08:25:27.687193 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 08:25:27.693120 [0.017354 Inits done]
414 08:25:27.693584 secure task start!
415 08:25:27.694027 high task start!
416 08:25:27.694462 low task start!
417 08:25:27.697488 run into bl31
418 08:25:27.706039 NOTICE: BL31: v1.3(release):4fc40b1
419 08:25:27.713861 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 08:25:27.714342 NOTICE: BL31: G12A normal boot!
421 08:25:27.729421 NOTICE: BL31: BL33 decompress pass
422 08:25:27.735048 ERROR: Error initializing runtime service opteed_fast
423 08:25:30.446940 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 08:25:30.447508 bl2_stage_init 0x01
425 08:25:30.447975 bl2_stage_init 0x81
426 08:25:30.452540 hw id: 0x0000 - pwm id 0x01
427 08:25:30.453047 bl2_stage_init 0xc1
428 08:25:30.458134 bl2_stage_init 0x02
429 08:25:30.458658
430 08:25:30.459093 L0:00000000
431 08:25:30.459514 L1:00000703
432 08:25:30.459935 L2:00008067
433 08:25:30.460399 L3:15000000
434 08:25:30.464388 S1:00000000
435 08:25:30.464847 B2:20282000
436 08:25:30.465271 B1:a0f83180
437 08:25:30.465693
438 08:25:30.466115 TE: 70018
439 08:25:30.466537
440 08:25:30.469990 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 08:25:30.470450
442 08:25:30.475590 Board ID = 1
443 08:25:30.476079 Set cpu clk to 24M
444 08:25:30.476507 Set clk81 to 24M
445 08:25:30.478984 Use GP1_pll as DSU clk.
446 08:25:30.479429 DSU clk: 1200 Mhz
447 08:25:30.484579 CPU clk: 1200 MHz
448 08:25:30.485025 Set clk81 to 166.6M
449 08:25:30.490173 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 08:25:30.490627 board id: 1
451 08:25:30.495772 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 08:25:30.509561 fw parse done
453 08:25:30.515498 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 08:25:30.557783 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 08:25:30.569120 PIEI prepare done
456 08:25:30.569569 fastboot data load
457 08:25:30.570000 fastboot data verify
458 08:25:30.574716 verify result: 266
459 08:25:30.580306 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 08:25:30.580758 LPDDR4 probe
461 08:25:30.581180 ddr clk to 1584MHz
462 08:25:30.588283 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 08:25:30.625519
464 08:25:30.625985 dmc_version 0001
465 08:25:30.632216 Check phy result
466 08:25:30.638147 INFO : End of CA training
467 08:25:30.638592 INFO : End of initialization
468 08:25:30.643780 INFO : Training has run successfully!
469 08:25:30.644294 Check phy result
470 08:25:30.649327 INFO : End of initialization
471 08:25:30.649800 INFO : End of read enable training
472 08:25:30.655010 INFO : End of fine write leveling
473 08:25:30.660534 INFO : End of Write leveling coarse delay
474 08:25:30.660995 INFO : Training has run successfully!
475 08:25:30.661437 Check phy result
476 08:25:30.666152 INFO : End of initialization
477 08:25:30.666612 INFO : End of read dq deskew training
478 08:25:30.671709 INFO : End of MPR read delay center optimization
479 08:25:30.677344 INFO : End of write delay center optimization
480 08:25:30.683003 INFO : End of read delay center optimization
481 08:25:30.683465 INFO : End of max read latency training
482 08:25:30.688533 INFO : Training has run successfully!
483 08:25:30.689014 1D training succeed
484 08:25:30.697747 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 08:25:30.745274 Check phy result
486 08:25:30.745737 INFO : End of initialization
487 08:25:30.767650 INFO : End of 2D read delay Voltage center optimization
488 08:25:30.786828 INFO : End of 2D read delay Voltage center optimization
489 08:25:30.838677 INFO : End of 2D write delay Voltage center optimization
490 08:25:30.887939 INFO : End of 2D write delay Voltage center optimization
491 08:25:30.893485 INFO : Training has run successfully!
492 08:25:30.893951
493 08:25:30.894392 channel==0
494 08:25:30.899056 RxClkDly_Margin_A0==78 ps 8
495 08:25:30.899518 TxDqDly_Margin_A0==88 ps 9
496 08:25:30.904666 RxClkDly_Margin_A1==88 ps 9
497 08:25:30.905126 TxDqDly_Margin_A1==98 ps 10
498 08:25:30.905569 TrainedVREFDQ_A0==74
499 08:25:30.910245 TrainedVREFDQ_A1==75
500 08:25:30.910711 VrefDac_Margin_A0==22
501 08:25:30.911154 DeviceVref_Margin_A0==40
502 08:25:30.915854 VrefDac_Margin_A1==23
503 08:25:30.916349 DeviceVref_Margin_A1==39
504 08:25:30.916796
505 08:25:30.917233
506 08:25:30.917670 channel==1
507 08:25:30.921439 RxClkDly_Margin_A0==78 ps 8
508 08:25:30.921907 TxDqDly_Margin_A0==98 ps 10
509 08:25:30.927036 RxClkDly_Margin_A1==78 ps 8
510 08:25:30.927506 TxDqDly_Margin_A1==98 ps 10
511 08:25:30.932665 TrainedVREFDQ_A0==75
512 08:25:30.933131 TrainedVREFDQ_A1==78
513 08:25:30.933581 VrefDac_Margin_A0==22
514 08:25:30.938264 DeviceVref_Margin_A0==39
515 08:25:30.938727 VrefDac_Margin_A1==22
516 08:25:30.943857 DeviceVref_Margin_A1==36
517 08:25:30.944349
518 08:25:30.944796 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 08:25:30.945235
520 08:25:30.977468 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000014 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000014 00000016 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
521 08:25:30.977969 2D training succeed
522 08:25:30.983045 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 08:25:30.988661 auto size-- 65535DDR cs0 size: 2048MB
524 08:25:30.989124 DDR cs1 size: 2048MB
525 08:25:30.994256 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 08:25:30.994727 cs0 DataBus test pass
527 08:25:30.999871 cs1 DataBus test pass
528 08:25:31.000377 cs0 AddrBus test pass
529 08:25:31.000819 cs1 AddrBus test pass
530 08:25:31.001255
531 08:25:31.005465 100bdlr_step_size ps== 478
532 08:25:31.005941 result report
533 08:25:31.011067 boot times 0Enable ddr reg access
534 08:25:31.016322 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 08:25:31.030200 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 08:25:31.686131 bl2z: ptr: 05129330, size: 00001e40
537 08:25:31.693746 0.0;M3 CHK:0;cm4_sp_mode 0
538 08:25:31.694233 MVN_1=0x00000000
539 08:25:31.694678 MVN_2=0x00000000
540 08:25:31.705376 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 08:25:31.705856 OPS=0x04
542 08:25:31.706300 ring efuse init
543 08:25:31.710851 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 08:25:31.711335 [0.017319 Inits done]
545 08:25:31.711779 secure task start!
546 08:25:31.718467 high task start!
547 08:25:31.718939 low task start!
548 08:25:31.719377 run into bl31
549 08:25:31.727032 NOTICE: BL31: v1.3(release):4fc40b1
550 08:25:31.734864 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 08:25:31.735336 NOTICE: BL31: G12A normal boot!
552 08:25:31.750288 NOTICE: BL31: BL33 decompress pass
553 08:25:31.756032 ERROR: Error initializing runtime service opteed_fast
554 08:25:33.149024 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 08:25:33.149592 bl2_stage_init 0x01
556 08:25:33.150055 bl2_stage_init 0x81
557 08:25:33.155613 hw id: 0x0000 - pwm id 0x01
558 08:25:33.156191 bl2_stage_init 0xc1
559 08:25:33.159237 bl2_stage_init 0x02
560 08:25:33.159745
561 08:25:33.160234 L0:00000000
562 08:25:33.160681 L1:00000703
563 08:25:33.161117 L2:00008067
564 08:25:33.165490 L3:15000000
565 08:25:33.166111 S1:00000000
566 08:25:33.166586 B2:20282000
567 08:25:33.167040 B1:a0f83180
568 08:25:33.167487
569 08:25:33.167940 TE: 71323
570 08:25:33.168442
571 08:25:33.175915 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 08:25:33.176498
573 08:25:33.176969 Board ID = 1
574 08:25:33.177422 Set cpu clk to 24M
575 08:25:33.177867 Set clk81 to 24M
576 08:25:33.181587 Use GP1_pll as DSU clk.
577 08:25:33.182114 DSU clk: 1200 Mhz
578 08:25:33.182573 CPU clk: 1200 MHz
579 08:25:33.187114 Set clk81 to 166.6M
580 08:25:33.192675 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 08:25:33.193172 board id: 1
582 08:25:33.200731 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 08:25:33.211597 fw parse done
584 08:25:33.217577 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 08:25:33.259742 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 08:25:33.271875 PIEI prepare done
587 08:25:33.272395 fastboot data load
588 08:25:33.272856 fastboot data verify
589 08:25:33.277437 verify result: 266
590 08:25:33.283054 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 08:25:33.283544 LPDDR4 probe
592 08:25:33.284117 ddr clk to 1584MHz
593 08:25:33.291040 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 08:25:33.328800
595 08:25:33.329312 dmc_version 0001
596 08:25:33.335769 Check phy result
597 08:25:33.341782 INFO : End of CA training
598 08:25:33.342306 INFO : End of initialization
599 08:25:33.347467 INFO : Training has run successfully!
600 08:25:33.347932 Check phy result
601 08:25:33.352962 INFO : End of initialization
602 08:25:33.353417 INFO : End of read enable training
603 08:25:33.356323 INFO : End of fine write leveling
604 08:25:33.361952 INFO : End of Write leveling coarse delay
605 08:25:33.367570 INFO : Training has run successfully!
606 08:25:33.368101 Check phy result
607 08:25:33.368528 INFO : End of initialization
608 08:25:33.373107 INFO : End of read dq deskew training
609 08:25:33.378688 INFO : End of MPR read delay center optimization
610 08:25:33.379148 INFO : End of write delay center optimization
611 08:25:33.384283 INFO : End of read delay center optimization
612 08:25:33.389931 INFO : End of max read latency training
613 08:25:33.390373 INFO : Training has run successfully!
614 08:25:33.395521 1D training succeed
615 08:25:33.401406 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 08:25:33.449638 Check phy result
617 08:25:33.450082 INFO : End of initialization
618 08:25:33.477030 INFO : End of 2D read delay Voltage center optimization
619 08:25:33.501349 INFO : End of 2D read delay Voltage center optimization
620 08:25:33.558001 INFO : End of 2D write delay Voltage center optimization
621 08:25:33.612261 INFO : End of 2D write delay Voltage center optimization
622 08:25:33.617894 INFO : Training has run successfully!
623 08:25:33.618338
624 08:25:33.618750 channel==0
625 08:25:33.623314 RxClkDly_Margin_A0==88 ps 9
626 08:25:33.623759 TxDqDly_Margin_A0==98 ps 10
627 08:25:33.628915 RxClkDly_Margin_A1==88 ps 9
628 08:25:33.629359 TxDqDly_Margin_A1==98 ps 10
629 08:25:33.629772 TrainedVREFDQ_A0==74
630 08:25:33.634436 TrainedVREFDQ_A1==75
631 08:25:33.634879 VrefDac_Margin_A0==24
632 08:25:33.635281 DeviceVref_Margin_A0==40
633 08:25:33.640141 VrefDac_Margin_A1==23
634 08:25:33.640582 DeviceVref_Margin_A1==39
635 08:25:33.640986
636 08:25:33.641386
637 08:25:33.645815 channel==1
638 08:25:33.646252 RxClkDly_Margin_A0==88 ps 9
639 08:25:33.646662 TxDqDly_Margin_A0==98 ps 10
640 08:25:33.651266 RxClkDly_Margin_A1==88 ps 9
641 08:25:33.651704 TxDqDly_Margin_A1==78 ps 8
642 08:25:33.656863 TrainedVREFDQ_A0==78
643 08:25:33.657309 TrainedVREFDQ_A1==75
644 08:25:33.657715 VrefDac_Margin_A0==23
645 08:25:33.662696 DeviceVref_Margin_A0==36
646 08:25:33.663132 VrefDac_Margin_A1==22
647 08:25:33.668149 DeviceVref_Margin_A1==39
648 08:25:33.668593
649 08:25:33.669000 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 08:25:33.669400
651 08:25:33.701476 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
652 08:25:33.701946 2D training succeed
653 08:25:33.707051 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 08:25:33.712636 auto size-- 65535DDR cs0 size: 2048MB
655 08:25:33.713078 DDR cs1 size: 2048MB
656 08:25:33.718296 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 08:25:33.718735 cs0 DataBus test pass
658 08:25:33.723855 cs1 DataBus test pass
659 08:25:33.724338 cs0 AddrBus test pass
660 08:25:33.724744 cs1 AddrBus test pass
661 08:25:33.725137
662 08:25:33.729468 100bdlr_step_size ps== 471
663 08:25:33.729925 result report
664 08:25:33.735039 boot times 0Enable ddr reg access
665 08:25:33.740359 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 08:25:33.754162 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 08:25:34.413567 bl2z: ptr: 05129330, size: 00001e40
668 08:25:34.421538 0.0;M3 CHK:0;cm4_sp_mode 0
669 08:25:34.422012 MVN_1=0x00000000
670 08:25:34.422426 MVN_2=0x00000000
671 08:25:34.433047 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 08:25:34.433505 OPS=0x04
673 08:25:34.433915 ring efuse init
674 08:25:34.438664 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 08:25:34.439126 [0.017354 Inits done]
676 08:25:34.439535 secure task start!
677 08:25:34.446414 high task start!
678 08:25:34.446919 low task start!
679 08:25:34.447338 run into bl31
680 08:25:34.455479 NOTICE: BL31: v1.3(release):4fc40b1
681 08:25:34.463179 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 08:25:34.463640 NOTICE: BL31: G12A normal boot!
683 08:25:34.478733 NOTICE: BL31: BL33 decompress pass
684 08:25:34.484413 ERROR: Error initializing runtime service opteed_fast
685 08:25:35.279887
686 08:25:35.280471
687 08:25:35.285256 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 08:25:35.285731
689 08:25:35.288776 Model: Libre Computer AML-S905D3-CC Solitude
690 08:25:35.435785 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 08:25:35.451131 DRAM: 2 GiB (effective 3.8 GiB)
692 08:25:35.552120 Core: 406 devices, 33 uclasses, devicetree: separate
693 08:25:35.558001 WDT: Not starting watchdog@f0d0
694 08:25:35.583041 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 08:25:35.595353 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 08:25:35.600310 ** Bad device specification mmc 0 **
697 08:25:35.610328 Card did not respond to voltage select! : -110
698 08:25:35.617966 ** Bad device specification mmc 0 **
699 08:25:35.618423 Couldn't find partition mmc 0
700 08:25:35.626309 Card did not respond to voltage select! : -110
701 08:25:35.631830 ** Bad device specification mmc 0 **
702 08:25:35.632323 Couldn't find partition mmc 0
703 08:25:35.636868 Error: could not access storage.
704 08:25:35.933388 Net: eth0: ethernet@ff3f0000
705 08:25:35.933914 starting USB...
706 08:25:36.177992 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 08:25:36.178517 Starting the controller
708 08:25:36.184013 USB XHCI 1.10
709 08:25:37.739093 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 08:25:37.747273 scanning usb for storage devices... 0 Storage Device(s) found
712 08:25:37.798815 Hit any key to stop autoboot: 1
713 08:25:37.799668 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 08:25:37.800321 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 08:25:37.800824 Setting prompt string to ['=>']
716 08:25:37.801307 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 08:25:37.813347 0
718 08:25:37.814229 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 08:25:37.915436 => setenv autoload no
721 08:25:37.916132 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 08:25:37.920908 setenv autoload no
724 08:25:38.022385 => setenv initrd_high 0xffffffff
725 08:25:38.023057 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 08:25:38.027322 setenv initrd_high 0xffffffff
728 08:25:38.128785 => setenv fdt_high 0xffffffff
729 08:25:38.129452 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 08:25:38.133794 setenv fdt_high 0xffffffff
732 08:25:38.235244 => dhcp
733 08:25:38.235958 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 08:25:38.240730 dhcp
735 08:25:38.795715 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 08:25:38.796398 Speed: 1000, full duplex
737 08:25:38.796860 BOOTP broadcast 1
738 08:25:38.884304 DHCP client bound to address 192.168.9.7 (88 ms)
740 08:25:38.985902 => setenv serverip 192.168.6.2
741 08:25:38.986642 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 08:25:38.991268 setenv serverip 192.168.6.2
744 08:25:39.092854 => tftpboot 0x01080000 872368/tftp-deploy-7rlkq2rc/kernel/uImage
745 08:25:39.093579 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 08:25:39.100370 tftpboot 0x01080000 872368/tftp-deploy-7rlkq2rc/kernel/uImage
747 08:25:39.100908 Speed: 1000, full duplex
748 08:25:39.101352 Using ethernet@ff3f0000 device
749 08:25:39.111317 TFTP from server 192.168.6.2; our IP address is 192.168.9.7; sending through gateway 192.168.8.1
750 08:25:39.119418 Filename '872368/tftp-deploy-7rlkq2rc/kernel/uImage'.
751 08:25:39.119955 Load address: 0x1080000
752 08:26:34.129442 Loading: *T T T T T T T T T T
753 08:26:34.130095 Retry count exceeded; starting again
755 08:26:34.131522 end: 2.4.3 bootloader-commands (duration 00:00:56) [common]
758 08:26:34.133504 end: 2.4 uboot-commands (duration 00:01:15) [common]
760 08:26:34.134928 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
762 08:26:34.136030 end: 2 uboot-action (duration 00:01:15) [common]
764 08:26:34.137671 Cleaning after the job
765 08:26:34.138253 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/ramdisk
766 08:26:34.154838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/kernel
767 08:26:34.182600 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/dtb
768 08:26:34.183912 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872368/tftp-deploy-7rlkq2rc/modules
769 08:26:34.206591 start: 4.1 power-off (timeout 00:00:30) [common]
770 08:26:34.207221 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
771 08:26:34.244296 >> OK - accepted request
772 08:26:34.246342 Returned 0 in 0 seconds
773 08:26:34.347173 end: 4.1 power-off (duration 00:00:00) [common]
775 08:26:34.348934 start: 4.2 read-feedback (timeout 00:10:00) [common]
776 08:26:34.350116 Listened to connection for namespace 'common' for up to 1s
777 08:26:35.350853 Finalising connection for namespace 'common'
778 08:26:35.351542 Disconnecting from shell: Finalise
779 08:26:35.352112 =>
780 08:26:35.453076 end: 4.2 read-feedback (duration 00:00:01) [common]
781 08:26:35.453702 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/872368
782 08:26:35.741892 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/872368
783 08:26:35.742454 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.