Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:27:01.375755 lava-dispatcher, installed at version: 2024.01
2 08:27:01.376547 start: 0 validate
3 08:27:01.377029 Start time: 2024-10-21 08:27:01.377000+00:00 (UTC)
4 08:27:01.377571 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:27:01.378104 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 08:27:01.418260 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:27:01.418835 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241021%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 08:27:01.453416 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:27:01.454447 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241021%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 08:27:02.500891 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:27:02.501376 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241021%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 08:27:02.540559 validate duration: 1.16
14 08:27:02.541407 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:27:02.541745 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:27:02.542062 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:27:02.542730 Not decompressing ramdisk as can be used compressed.
18 08:27:02.543188 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 08:27:02.543466 saving as /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/ramdisk/rootfs.cpio.gz
20 08:27:02.543740 total size: 8181887 (7 MB)
21 08:27:02.580428 progress 0 % (0 MB)
22 08:27:02.590914 progress 5 % (0 MB)
23 08:27:02.601350 progress 10 % (0 MB)
24 08:27:02.610358 progress 15 % (1 MB)
25 08:27:02.615771 progress 20 % (1 MB)
26 08:27:02.621556 progress 25 % (1 MB)
27 08:27:02.626898 progress 30 % (2 MB)
28 08:27:02.632735 progress 35 % (2 MB)
29 08:27:02.638106 progress 40 % (3 MB)
30 08:27:02.643970 progress 45 % (3 MB)
31 08:27:02.649399 progress 50 % (3 MB)
32 08:27:02.655173 progress 55 % (4 MB)
33 08:27:02.660551 progress 60 % (4 MB)
34 08:27:02.666302 progress 65 % (5 MB)
35 08:27:02.671799 progress 70 % (5 MB)
36 08:27:02.677566 progress 75 % (5 MB)
37 08:27:02.682926 progress 80 % (6 MB)
38 08:27:02.688665 progress 85 % (6 MB)
39 08:27:02.694053 progress 90 % (7 MB)
40 08:27:02.699839 progress 95 % (7 MB)
41 08:27:02.704798 progress 100 % (7 MB)
42 08:27:02.705455 7 MB downloaded in 0.16 s (48.26 MB/s)
43 08:27:02.706033 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:27:02.706954 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:27:02.707269 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:27:02.707555 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:27:02.708165 downloading http://storage.kernelci.org/next/master/next-20241021/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/kernel/Image
49 08:27:02.708454 saving as /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/kernel/Image
50 08:27:02.708678 total size: 47389184 (45 MB)
51 08:27:02.708901 No compression specified
52 08:27:02.748131 progress 0 % (0 MB)
53 08:27:02.777743 progress 5 % (2 MB)
54 08:27:02.806732 progress 10 % (4 MB)
55 08:27:02.835849 progress 15 % (6 MB)
56 08:27:02.865239 progress 20 % (9 MB)
57 08:27:02.894597 progress 25 % (11 MB)
58 08:27:02.923489 progress 30 % (13 MB)
59 08:27:02.952952 progress 35 % (15 MB)
60 08:27:02.982451 progress 40 % (18 MB)
61 08:27:03.011592 progress 45 % (20 MB)
62 08:27:03.041144 progress 50 % (22 MB)
63 08:27:03.072681 progress 55 % (24 MB)
64 08:27:03.101963 progress 60 % (27 MB)
65 08:27:03.131351 progress 65 % (29 MB)
66 08:27:03.160709 progress 70 % (31 MB)
67 08:27:03.189773 progress 75 % (33 MB)
68 08:27:03.218789 progress 80 % (36 MB)
69 08:27:03.248593 progress 85 % (38 MB)
70 08:27:03.277485 progress 90 % (40 MB)
71 08:27:03.306431 progress 95 % (42 MB)
72 08:27:03.335317 progress 100 % (45 MB)
73 08:27:03.335883 45 MB downloaded in 0.63 s (72.06 MB/s)
74 08:27:03.336412 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:27:03.337220 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:27:03.337494 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:27:03.337760 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:27:03.338225 downloading http://storage.kernelci.org/next/master/next-20241021/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 08:27:03.338504 saving as /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 08:27:03.338713 total size: 53209 (0 MB)
82 08:27:03.338922 No compression specified
83 08:27:03.384649 progress 61 % (0 MB)
84 08:27:03.385495 progress 100 % (0 MB)
85 08:27:03.386026 0 MB downloaded in 0.05 s (1.07 MB/s)
86 08:27:03.386483 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:27:03.387290 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:27:03.387551 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:27:03.387814 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:27:03.388291 downloading http://storage.kernelci.org/next/master/next-20241021/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/modules.tar.xz
92 08:27:03.388539 saving as /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/modules/modules.tar
93 08:27:03.388742 total size: 11621680 (11 MB)
94 08:27:03.388952 Using unxz to decompress xz
95 08:27:03.427055 progress 0 % (0 MB)
96 08:27:03.493755 progress 5 % (0 MB)
97 08:27:03.567140 progress 10 % (1 MB)
98 08:27:03.646006 progress 15 % (1 MB)
99 08:27:03.721000 progress 20 % (2 MB)
100 08:27:03.797073 progress 25 % (2 MB)
101 08:27:03.875332 progress 30 % (3 MB)
102 08:27:03.950737 progress 35 % (3 MB)
103 08:27:04.025065 progress 40 % (4 MB)
104 08:27:04.109487 progress 45 % (5 MB)
105 08:27:04.189118 progress 50 % (5 MB)
106 08:27:04.271164 progress 55 % (6 MB)
107 08:27:04.346508 progress 60 % (6 MB)
108 08:27:04.429518 progress 65 % (7 MB)
109 08:27:04.510511 progress 70 % (7 MB)
110 08:27:04.585576 progress 75 % (8 MB)
111 08:27:04.666857 progress 80 % (8 MB)
112 08:27:04.746890 progress 85 % (9 MB)
113 08:27:04.818561 progress 90 % (10 MB)
114 08:27:04.911018 progress 95 % (10 MB)
115 08:27:05.007950 progress 100 % (11 MB)
116 08:27:05.021195 11 MB downloaded in 1.63 s (6.79 MB/s)
117 08:27:05.021921 end: 1.4.1 http-download (duration 00:00:02) [common]
119 08:27:05.023616 end: 1.4 download-retry (duration 00:00:02) [common]
120 08:27:05.024214 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 08:27:05.024761 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 08:27:05.025273 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:27:05.025791 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 08:27:05.027027 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd
125 08:27:05.027925 makedir: /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin
126 08:27:05.028655 makedir: /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/tests
127 08:27:05.029304 makedir: /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/results
128 08:27:05.029950 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-add-keys
129 08:27:05.030911 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-add-sources
130 08:27:05.031864 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-background-process-start
131 08:27:05.032891 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-background-process-stop
132 08:27:05.033905 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-common-functions
133 08:27:05.034880 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-echo-ipv4
134 08:27:05.035843 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-install-packages
135 08:27:05.036823 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-installed-packages
136 08:27:05.037752 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-os-build
137 08:27:05.038672 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-probe-channel
138 08:27:05.039591 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-probe-ip
139 08:27:05.040558 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-target-ip
140 08:27:05.041483 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-target-mac
141 08:27:05.042417 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-target-storage
142 08:27:05.043367 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-test-case
143 08:27:05.044342 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-test-event
144 08:27:05.045278 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-test-feedback
145 08:27:05.046203 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-test-raise
146 08:27:05.047122 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-test-reference
147 08:27:05.048082 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-test-runner
148 08:27:05.049025 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-test-set
149 08:27:05.049964 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-test-shell
150 08:27:05.050908 Updating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-install-packages (oe)
151 08:27:05.051910 Updating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/bin/lava-installed-packages (oe)
152 08:27:05.052820 Creating /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/environment
153 08:27:05.053560 LAVA metadata
154 08:27:05.054074 - LAVA_JOB_ID=872488
155 08:27:05.054518 - LAVA_DISPATCHER_IP=192.168.6.2
156 08:27:05.055184 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 08:27:05.057021 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 08:27:05.057643 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 08:27:05.058076 skipped lava-vland-overlay
160 08:27:05.058572 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 08:27:05.059088 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 08:27:05.059523 skipped lava-multinode-overlay
163 08:27:05.060055 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 08:27:05.060590 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 08:27:05.061079 Loading test definitions
166 08:27:05.061641 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 08:27:05.062093 Using /lava-872488 at stage 0
168 08:27:05.064273 uuid=872488_1.5.2.4.1 testdef=None
169 08:27:05.064617 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 08:27:05.064911 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 08:27:05.066778 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 08:27:05.067625 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 08:27:05.069937 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 08:27:05.070813 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 08:27:05.073077 runner path: /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/0/tests/0_dmesg test_uuid 872488_1.5.2.4.1
178 08:27:05.073663 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 08:27:05.074473 Creating lava-test-runner.conf files
181 08:27:05.074688 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/872488/lava-overlay-hqayjfwd/lava-872488/0 for stage 0
182 08:27:05.075036 - 0_dmesg
183 08:27:05.075416 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 08:27:05.075725 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 08:27:05.099428 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 08:27:05.099821 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 08:27:05.100144 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 08:27:05.100434 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 08:27:05.100716 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 08:27:06.003111 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 08:27:06.003585 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 08:27:06.003864 extracting modules file /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/872488/extract-overlay-ramdisk-x1xyg1bo/ramdisk
193 08:27:07.329748 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 08:27:07.330230 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 08:27:07.330534 [common] Applying overlay /var/lib/lava/dispatcher/tmp/872488/compress-overlay-o9rm9mda/overlay-1.5.2.5.tar.gz to ramdisk
196 08:27:07.330775 [common] Applying overlay /var/lib/lava/dispatcher/tmp/872488/compress-overlay-o9rm9mda/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/872488/extract-overlay-ramdisk-x1xyg1bo/ramdisk
197 08:27:07.362753 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 08:27:07.363170 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 08:27:07.363441 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 08:27:07.363669 Converting downloaded kernel to a uImage
201 08:27:07.364001 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/kernel/Image /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/kernel/uImage
202 08:27:07.888836 output: Image Name:
203 08:27:07.889255 output: Created: Mon Oct 21 08:27:07 2024
204 08:27:07.889467 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 08:27:07.889672 output: Data Size: 47389184 Bytes = 46278.50 KiB = 45.19 MiB
206 08:27:07.889872 output: Load Address: 01080000
207 08:27:07.890069 output: Entry Point: 01080000
208 08:27:07.890267 output:
209 08:27:07.890602 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 08:27:07.890873 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 08:27:07.891144 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 08:27:07.891400 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 08:27:07.891656 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 08:27:07.891913 Building ramdisk /var/lib/lava/dispatcher/tmp/872488/extract-overlay-ramdisk-x1xyg1bo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/872488/extract-overlay-ramdisk-x1xyg1bo/ramdisk
215 08:27:10.238453 >> 182371 blocks
216 08:27:18.733657 Adding RAMdisk u-boot header.
217 08:27:18.734314 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/872488/extract-overlay-ramdisk-x1xyg1bo/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/872488/extract-overlay-ramdisk-x1xyg1bo/ramdisk.cpio.gz.uboot
218 08:27:19.038363 output: Image Name:
219 08:27:19.038780 output: Created: Mon Oct 21 08:27:18 2024
220 08:27:19.039206 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 08:27:19.039623 output: Data Size: 26100394 Bytes = 25488.67 KiB = 24.89 MiB
222 08:27:19.040075 output: Load Address: 00000000
223 08:27:19.040485 output: Entry Point: 00000000
224 08:27:19.040882 output:
225 08:27:19.041918 rename /var/lib/lava/dispatcher/tmp/872488/extract-overlay-ramdisk-x1xyg1bo/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/ramdisk/ramdisk.cpio.gz.uboot
226 08:27:19.042642 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 08:27:19.043201 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 08:27:19.043736 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 08:27:19.044240 No LXC device requested
230 08:27:19.044760 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 08:27:19.045281 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 08:27:19.045779 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 08:27:19.046194 Checking files for TFTP limit of 4294967296 bytes.
234 08:27:19.048907 end: 1 tftp-deploy (duration 00:00:17) [common]
235 08:27:19.049491 start: 2 uboot-action (timeout 00:05:00) [common]
236 08:27:19.050023 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 08:27:19.050525 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 08:27:19.051047 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 08:27:19.051584 Using kernel file from prepare-kernel: 872488/tftp-deploy-78i9ha6x/kernel/uImage
240 08:27:19.052214 substitutions:
241 08:27:19.052631 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 08:27:19.053034 - {DTB_ADDR}: 0x01070000
243 08:27:19.053428 - {DTB}: 872488/tftp-deploy-78i9ha6x/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 08:27:19.053822 - {INITRD}: 872488/tftp-deploy-78i9ha6x/ramdisk/ramdisk.cpio.gz.uboot
245 08:27:19.054216 - {KERNEL_ADDR}: 0x01080000
246 08:27:19.054605 - {KERNEL}: 872488/tftp-deploy-78i9ha6x/kernel/uImage
247 08:27:19.055000 - {LAVA_MAC}: None
248 08:27:19.055434 - {PRESEED_CONFIG}: None
249 08:27:19.055832 - {PRESEED_LOCAL}: None
250 08:27:19.056253 - {RAMDISK_ADDR}: 0x08000000
251 08:27:19.056645 - {RAMDISK}: 872488/tftp-deploy-78i9ha6x/ramdisk/ramdisk.cpio.gz.uboot
252 08:27:19.057037 - {ROOT_PART}: None
253 08:27:19.057427 - {ROOT}: None
254 08:27:19.057814 - {SERVER_IP}: 192.168.6.2
255 08:27:19.058204 - {TEE_ADDR}: 0x83000000
256 08:27:19.058588 - {TEE}: None
257 08:27:19.058977 Parsed boot commands:
258 08:27:19.059350 - setenv autoload no
259 08:27:19.059736 - setenv initrd_high 0xffffffff
260 08:27:19.060152 - setenv fdt_high 0xffffffff
261 08:27:19.060543 - dhcp
262 08:27:19.060930 - setenv serverip 192.168.6.2
263 08:27:19.061314 - tftpboot 0x01080000 872488/tftp-deploy-78i9ha6x/kernel/uImage
264 08:27:19.061699 - tftpboot 0x08000000 872488/tftp-deploy-78i9ha6x/ramdisk/ramdisk.cpio.gz.uboot
265 08:27:19.062085 - tftpboot 0x01070000 872488/tftp-deploy-78i9ha6x/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 08:27:19.062470 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 08:27:19.062859 - bootm 0x01080000 0x08000000 0x01070000
268 08:27:19.063353 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 08:27:19.064867 start: 2.3 connect-device (timeout 00:05:00) [common]
271 08:27:19.065320 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 08:27:19.080169 Setting prompt string to ['lava-test: # ']
273 08:27:19.081616 end: 2.3 connect-device (duration 00:00:00) [common]
274 08:27:19.082240 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 08:27:19.082803 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 08:27:19.083334 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 08:27:19.084682 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 08:27:19.121570 >> OK - accepted request
279 08:27:19.123720 Returned 0 in 0 seconds
280 08:27:19.224897 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 08:27:19.226496 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 08:27:19.227069 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 08:27:19.227588 Setting prompt string to ['Hit any key to stop autoboot']
285 08:27:19.228081 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 08:27:19.229646 Trying 192.168.56.21...
287 08:27:19.230130 Connected to conserv1.
288 08:27:19.230561 Escape character is '^]'.
289 08:27:19.230988
290 08:27:19.231415 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 08:27:19.231845
292 08:27:27.007539 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 08:27:27.008172 bl2_stage_init 0x01
294 08:27:27.008602 bl2_stage_init 0x81
295 08:27:27.012985 hw id: 0x0000 - pwm id 0x01
296 08:27:27.013444 bl2_stage_init 0xc1
297 08:27:27.018466 bl2_stage_init 0x02
298 08:27:27.018912
299 08:27:27.019318 L0:00000000
300 08:27:27.019706 L1:00000703
301 08:27:27.020118 L2:00008067
302 08:27:27.020513 L3:15000000
303 08:27:27.024020 S1:00000000
304 08:27:27.024445 B2:20282000
305 08:27:27.024831 B1:a0f83180
306 08:27:27.025212
307 08:27:27.025595 TE: 69802
308 08:27:27.025981
309 08:27:27.029630 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 08:27:27.030051
311 08:27:27.035220 Board ID = 1
312 08:27:27.035638 Set cpu clk to 24M
313 08:27:27.036050 Set clk81 to 24M
314 08:27:27.038737 Use GP1_pll as DSU clk.
315 08:27:27.039150 DSU clk: 1200 Mhz
316 08:27:27.044288 CPU clk: 1200 MHz
317 08:27:27.044705 Set clk81 to 166.6M
318 08:27:27.049937 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 08:27:27.050354 board id: 1
320 08:27:27.059385 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 08:27:27.070034 fw parse done
322 08:27:27.076064 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 08:27:27.118690 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 08:27:27.129512 PIEI prepare done
325 08:27:27.129926 fastboot data load
326 08:27:27.130318 fastboot data verify
327 08:27:27.135242 verify result: 266
328 08:27:27.140703 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 08:27:27.141118 LPDDR4 probe
330 08:27:27.141501 ddr clk to 1584MHz
331 08:27:27.148689 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 08:27:27.185927
333 08:27:27.186352 dmc_version 0001
334 08:27:27.192603 Check phy result
335 08:27:27.198515 INFO : End of CA training
336 08:27:27.198932 INFO : End of initialization
337 08:27:27.204267 INFO : Training has run successfully!
338 08:27:27.204683 Check phy result
339 08:27:27.209735 INFO : End of initialization
340 08:27:27.210148 INFO : End of read enable training
341 08:27:27.213072 INFO : End of fine write leveling
342 08:27:27.218589 INFO : End of Write leveling coarse delay
343 08:27:27.224266 INFO : Training has run successfully!
344 08:27:27.224675 Check phy result
345 08:27:27.225064 INFO : End of initialization
346 08:27:27.229816 INFO : End of read dq deskew training
347 08:27:27.235391 INFO : End of MPR read delay center optimization
348 08:27:27.235803 INFO : End of write delay center optimization
349 08:27:27.241057 INFO : End of read delay center optimization
350 08:27:27.246650 INFO : End of max read latency training
351 08:27:27.247062 INFO : Training has run successfully!
352 08:27:27.252281 1D training succeed
353 08:27:27.258164 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 08:27:27.305719 Check phy result
355 08:27:27.306127 INFO : End of initialization
356 08:27:27.328199 INFO : End of 2D read delay Voltage center optimization
357 08:27:27.347224 INFO : End of 2D read delay Voltage center optimization
358 08:27:27.399080 INFO : End of 2D write delay Voltage center optimization
359 08:27:27.448418 INFO : End of 2D write delay Voltage center optimization
360 08:27:27.453913 INFO : Training has run successfully!
361 08:27:27.454325
362 08:27:27.454718 channel==0
363 08:27:27.459478 RxClkDly_Margin_A0==88 ps 9
364 08:27:27.459887 TxDqDly_Margin_A0==88 ps 9
365 08:27:27.462857 RxClkDly_Margin_A1==88 ps 9
366 08:27:27.463290 TxDqDly_Margin_A1==98 ps 10
367 08:27:27.468441 TrainedVREFDQ_A0==74
368 08:27:27.468855 TrainedVREFDQ_A1==75
369 08:27:27.469244 VrefDac_Margin_A0==23
370 08:27:27.473934 DeviceVref_Margin_A0==40
371 08:27:27.474341 VrefDac_Margin_A1==23
372 08:27:27.479654 DeviceVref_Margin_A1==39
373 08:27:27.480099
374 08:27:27.480492
375 08:27:27.480877 channel==1
376 08:27:27.481260 RxClkDly_Margin_A0==88 ps 9
377 08:27:27.483062 TxDqDly_Margin_A0==98 ps 10
378 08:27:27.488583 RxClkDly_Margin_A1==78 ps 8
379 08:27:27.488999 TxDqDly_Margin_A1==88 ps 9
380 08:27:27.489390 TrainedVREFDQ_A0==78
381 08:27:27.494244 TrainedVREFDQ_A1==76
382 08:27:27.494656 VrefDac_Margin_A0==23
383 08:27:27.499767 DeviceVref_Margin_A0==36
384 08:27:27.500202 VrefDac_Margin_A1==22
385 08:27:27.500589 DeviceVref_Margin_A1==38
386 08:27:27.500968
387 08:27:27.508855 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 08:27:27.509275
389 08:27:27.534755 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
390 08:27:27.540362 2D training succeed
391 08:27:27.545934 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 08:27:27.546348 auto size-- 65535DDR cs0 size: 2048MB
393 08:27:27.551417 DDR cs1 size: 2048MB
394 08:27:27.551826 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 08:27:27.557005 cs0 DataBus test pass
396 08:27:27.557417 cs1 DataBus test pass
397 08:27:27.562604 cs0 AddrBus test pass
398 08:27:27.563016 cs1 AddrBus test pass
399 08:27:27.563400
400 08:27:27.563781 100bdlr_step_size ps== 478
401 08:27:27.568265 result report
402 08:27:27.568677 boot times 0Enable ddr reg access
403 08:27:27.576549 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 08:27:27.590384 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 08:27:28.244266 bl2z: ptr: 05129330, size: 00001e40
406 08:27:28.250822 0.0;M3 CHK:0;cm4_sp_mode 0
407 08:27:28.251268 MVN_1=0x00000000
408 08:27:28.251676 MVN_2=0x00000000
409 08:27:28.262322 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 08:27:28.262759 OPS=0x04
411 08:27:28.263165 ring efuse init
412 08:27:28.265300 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 08:27:28.271313 [0.017319 Inits done]
414 08:27:28.271740 secure task start!
415 08:27:28.272182 high task start!
416 08:27:28.272582 low task start!
417 08:27:28.275512 run into bl31
418 08:27:28.284146 NOTICE: BL31: v1.3(release):4fc40b1
419 08:27:28.291919 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 08:27:28.292399 NOTICE: BL31: G12A normal boot!
421 08:27:28.307439 NOTICE: BL31: BL33 decompress pass
422 08:27:28.313155 ERROR: Error initializing runtime service opteed_fast
423 08:27:31.058156 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 08:27:31.058775 bl2_stage_init 0x01
425 08:27:31.059211 bl2_stage_init 0x81
426 08:27:31.063743 hw id: 0x0000 - pwm id 0x01
427 08:27:31.064285 bl2_stage_init 0xc1
428 08:27:31.069387 bl2_stage_init 0x02
429 08:27:31.069888
430 08:27:31.070281 L0:00000000
431 08:27:31.070665 L1:00000703
432 08:27:31.071042 L2:00008067
433 08:27:31.071422 L3:15000000
434 08:27:31.074998 S1:00000000
435 08:27:31.075418 B2:20282000
436 08:27:31.075804 B1:a0f83180
437 08:27:31.076219
438 08:27:31.076603 TE: 69431
439 08:27:31.076985
440 08:27:31.080595 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 08:27:31.081011
442 08:27:31.086198 Board ID = 1
443 08:27:31.086624 Set cpu clk to 24M
444 08:27:31.087009 Set clk81 to 24M
445 08:27:31.091803 Use GP1_pll as DSU clk.
446 08:27:31.092252 DSU clk: 1200 Mhz
447 08:27:31.092639 CPU clk: 1200 MHz
448 08:27:31.097411 Set clk81 to 166.6M
449 08:27:31.102992 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 08:27:31.103407 board id: 1
451 08:27:31.110133 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 08:27:31.120775 fw parse done
453 08:27:31.126746 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 08:27:31.169480 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 08:27:31.180332 PIEI prepare done
456 08:27:31.180762 fastboot data load
457 08:27:31.181156 fastboot data verify
458 08:27:31.185923 verify result: 266
459 08:27:31.191629 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 08:27:31.192083 LPDDR4 probe
461 08:27:31.192471 ddr clk to 1584MHz
462 08:27:31.199581 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 08:27:31.236795
464 08:27:31.237208 dmc_version 0001
465 08:27:31.243463 Check phy result
466 08:27:31.249405 INFO : End of CA training
467 08:27:31.249886 INFO : End of initialization
468 08:27:31.254966 INFO : Training has run successfully!
469 08:27:31.255393 Check phy result
470 08:27:31.260660 INFO : End of initialization
471 08:27:31.261095 INFO : End of read enable training
472 08:27:31.266152 INFO : End of fine write leveling
473 08:27:31.271739 INFO : End of Write leveling coarse delay
474 08:27:31.272195 INFO : Training has run successfully!
475 08:27:31.272601 Check phy result
476 08:27:31.277389 INFO : End of initialization
477 08:27:31.277808 INFO : End of read dq deskew training
478 08:27:31.282964 INFO : End of MPR read delay center optimization
479 08:27:31.288640 INFO : End of write delay center optimization
480 08:27:31.294159 INFO : End of read delay center optimization
481 08:27:31.294575 INFO : End of max read latency training
482 08:27:31.299775 INFO : Training has run successfully!
483 08:27:31.300233 1D training succeed
484 08:27:31.308971 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 08:27:31.356494 Check phy result
486 08:27:31.356913 INFO : End of initialization
487 08:27:31.378900 INFO : End of 2D read delay Voltage center optimization
488 08:27:31.398036 INFO : End of 2D read delay Voltage center optimization
489 08:27:31.449932 INFO : End of 2D write delay Voltage center optimization
490 08:27:31.499096 INFO : End of 2D write delay Voltage center optimization
491 08:27:31.504762 INFO : Training has run successfully!
492 08:27:31.505185
493 08:27:31.505589 channel==0
494 08:27:31.510284 RxClkDly_Margin_A0==78 ps 8
495 08:27:31.510704 TxDqDly_Margin_A0==98 ps 10
496 08:27:31.513695 RxClkDly_Margin_A1==88 ps 9
497 08:27:31.514111 TxDqDly_Margin_A1==88 ps 9
498 08:27:31.519205 TrainedVREFDQ_A0==74
499 08:27:31.519629 TrainedVREFDQ_A1==74
500 08:27:31.520072 VrefDac_Margin_A0==24
501 08:27:31.524815 DeviceVref_Margin_A0==40
502 08:27:31.525237 VrefDac_Margin_A1==23
503 08:27:31.530430 DeviceVref_Margin_A1==40
504 08:27:31.530853
505 08:27:31.531257
506 08:27:31.531655 channel==1
507 08:27:31.532073 RxClkDly_Margin_A0==88 ps 9
508 08:27:31.536011 TxDqDly_Margin_A0==98 ps 10
509 08:27:31.536441 RxClkDly_Margin_A1==88 ps 9
510 08:27:31.541671 TxDqDly_Margin_A1==88 ps 9
511 08:27:31.542103 TrainedVREFDQ_A0==78
512 08:27:31.542503 TrainedVREFDQ_A1==75
513 08:27:31.547218 VrefDac_Margin_A0==22
514 08:27:31.547644 DeviceVref_Margin_A0==36
515 08:27:31.552806 VrefDac_Margin_A1==22
516 08:27:31.553226 DeviceVref_Margin_A1==39
517 08:27:31.553624
518 08:27:31.558424 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 08:27:31.558865
520 08:27:31.586423 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000014 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
521 08:27:31.592020 2D training succeed
522 08:27:31.597675 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 08:27:31.598115 auto size-- 65535DDR cs0 size: 2048MB
524 08:27:31.603206 DDR cs1 size: 2048MB
525 08:27:31.603633 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 08:27:31.608807 cs0 DataBus test pass
527 08:27:31.609228 cs1 DataBus test pass
528 08:27:31.609626 cs0 AddrBus test pass
529 08:27:31.614446 cs1 AddrBus test pass
530 08:27:31.614883
531 08:27:31.615283 100bdlr_step_size ps== 478
532 08:27:31.615686 result report
533 08:27:31.620007 boot times 0Enable ddr reg access
534 08:27:31.627465 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 08:27:31.641307 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 08:27:32.296176 bl2z: ptr: 05129330, size: 00001e40
537 08:27:32.302264 0.0;M3 CHK:0;cm4_sp_mode 0
538 08:27:32.302713 MVN_1=0x00000000
539 08:27:32.303113 MVN_2=0x00000000
540 08:27:32.313771 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 08:27:32.314211 OPS=0x04
542 08:27:32.314618 ring efuse init
543 08:27:32.319383 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 08:27:32.319824 [0.017319 Inits done]
545 08:27:32.320282 secure task start!
546 08:27:32.327431 high task start!
547 08:27:32.327872 low task start!
548 08:27:32.328312 run into bl31
549 08:27:32.336054 NOTICE: BL31: v1.3(release):4fc40b1
550 08:27:32.343852 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 08:27:32.344315 NOTICE: BL31: G12A normal boot!
552 08:27:32.359339 NOTICE: BL31: BL33 decompress pass
553 08:27:32.365034 ERROR: Error initializing runtime service opteed_fast
554 08:27:33.757323 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 08:27:33.757921 bl2_stage_init 0x01
556 08:27:33.758338 bl2_stage_init 0x81
557 08:27:33.762784 hw id: 0x0000 - pwm id 0x01
558 08:27:33.763219 bl2_stage_init 0xc1
559 08:27:33.767848 bl2_stage_init 0x02
560 08:27:33.768332
561 08:27:33.768739 L0:00000000
562 08:27:33.769134 L1:00000703
563 08:27:33.769526 L2:00008067
564 08:27:33.773293 L3:15000000
565 08:27:33.773716 S1:00000000
566 08:27:33.774115 B2:20282000
567 08:27:33.774508 B1:a0f83180
568 08:27:33.774899
569 08:27:33.775293 TE: 69339
570 08:27:33.775689
571 08:27:33.784510 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 08:27:33.784941
573 08:27:33.785339 Board ID = 1
574 08:27:33.785732 Set cpu clk to 24M
575 08:27:33.786121 Set clk81 to 24M
576 08:27:33.788106 Use GP1_pll as DSU clk.
577 08:27:33.788552 DSU clk: 1200 Mhz
578 08:27:33.793623 CPU clk: 1200 MHz
579 08:27:33.794049 Set clk81 to 166.6M
580 08:27:33.799284 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 08:27:33.799714 board id: 1
582 08:27:33.809083 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 08:27:33.819716 fw parse done
584 08:27:33.825705 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 08:27:33.868488 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 08:27:33.879283 PIEI prepare done
587 08:27:33.879705 fastboot data load
588 08:27:33.880151 fastboot data verify
589 08:27:33.884894 verify result: 266
590 08:27:33.890474 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 08:27:33.890897 LPDDR4 probe
592 08:27:33.891294 ddr clk to 1584MHz
593 08:27:33.898467 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 08:27:33.935774
595 08:27:33.936236 dmc_version 0001
596 08:27:33.942469 Check phy result
597 08:27:33.948371 INFO : End of CA training
598 08:27:33.948792 INFO : End of initialization
599 08:27:33.953956 INFO : Training has run successfully!
600 08:27:33.954384 Check phy result
601 08:27:33.959595 INFO : End of initialization
602 08:27:33.960046 INFO : End of read enable training
603 08:27:33.965150 INFO : End of fine write leveling
604 08:27:33.970804 INFO : End of Write leveling coarse delay
605 08:27:33.971225 INFO : Training has run successfully!
606 08:27:33.971620 Check phy result
607 08:27:33.976343 INFO : End of initialization
608 08:27:33.976766 INFO : End of read dq deskew training
609 08:27:33.981943 INFO : End of MPR read delay center optimization
610 08:27:33.987553 INFO : End of write delay center optimization
611 08:27:33.993141 INFO : End of read delay center optimization
612 08:27:33.993571 INFO : End of max read latency training
613 08:27:33.998788 INFO : Training has run successfully!
614 08:27:33.999210 1D training succeed
615 08:27:34.007974 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 08:27:34.055498 Check phy result
617 08:27:34.055921 INFO : End of initialization
618 08:27:34.077867 INFO : End of 2D read delay Voltage center optimization
619 08:27:34.097045 INFO : End of 2D read delay Voltage center optimization
620 08:27:34.148930 INFO : End of 2D write delay Voltage center optimization
621 08:27:34.198169 INFO : End of 2D write delay Voltage center optimization
622 08:27:34.203692 INFO : Training has run successfully!
623 08:27:34.204153
624 08:27:34.204562 channel==0
625 08:27:34.209236 RxClkDly_Margin_A0==78 ps 8
626 08:27:34.209661 TxDqDly_Margin_A0==98 ps 10
627 08:27:34.214910 RxClkDly_Margin_A1==88 ps 9
628 08:27:34.215331 TxDqDly_Margin_A1==98 ps 10
629 08:27:34.215733 TrainedVREFDQ_A0==74
630 08:27:34.220504 TrainedVREFDQ_A1==75
631 08:27:34.220935 VrefDac_Margin_A0==23
632 08:27:34.221334 DeviceVref_Margin_A0==40
633 08:27:34.226166 VrefDac_Margin_A1==23
634 08:27:34.226585 DeviceVref_Margin_A1==39
635 08:27:34.226980
636 08:27:34.227373
637 08:27:34.231717 channel==1
638 08:27:34.232174 RxClkDly_Margin_A0==88 ps 9
639 08:27:34.232580 TxDqDly_Margin_A0==98 ps 10
640 08:27:34.237277 RxClkDly_Margin_A1==78 ps 8
641 08:27:34.237704 TxDqDly_Margin_A1==88 ps 9
642 08:27:34.242972 TrainedVREFDQ_A0==78
643 08:27:34.243400 TrainedVREFDQ_A1==75
644 08:27:34.243802 VrefDac_Margin_A0==22
645 08:27:34.248498 DeviceVref_Margin_A0==36
646 08:27:34.248919 VrefDac_Margin_A1==22
647 08:27:34.254076 DeviceVref_Margin_A1==39
648 08:27:34.254502
649 08:27:34.254898 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 08:27:34.255291
651 08:27:34.287613 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
652 08:27:34.288087 2D training succeed
653 08:27:34.293214 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 08:27:34.298830 auto size-- 65535DDR cs0 size: 2048MB
655 08:27:34.299254 DDR cs1 size: 2048MB
656 08:27:34.304410 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 08:27:34.304834 cs0 DataBus test pass
658 08:27:34.310094 cs1 DataBus test pass
659 08:27:34.310519 cs0 AddrBus test pass
660 08:27:34.310918 cs1 AddrBus test pass
661 08:27:34.311308
662 08:27:34.315589 100bdlr_step_size ps== 478
663 08:27:34.316051 result report
664 08:27:34.321228 boot times 0Enable ddr reg access
665 08:27:34.326492 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 08:27:34.340327 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 08:27:34.995501 bl2z: ptr: 05129330, size: 00001e40
668 08:27:35.001360 0.0;M3 CHK:0;cm4_sp_mode 0
669 08:27:35.001807 MVN_1=0x00000000
670 08:27:35.002207 MVN_2=0x00000000
671 08:27:35.012870 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 08:27:35.013306 OPS=0x04
673 08:27:35.013709 ring efuse init
674 08:27:35.018441 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 08:27:35.018878 [0.017319 Inits done]
676 08:27:35.019279 secure task start!
677 08:27:35.026535 high task start!
678 08:27:35.026963 low task start!
679 08:27:35.027361 run into bl31
680 08:27:35.035265 NOTICE: BL31: v1.3(release):4fc40b1
681 08:27:35.042918 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 08:27:35.043352 NOTICE: BL31: G12A normal boot!
683 08:27:35.058518 NOTICE: BL31: BL33 decompress pass
684 08:27:35.064253 ERROR: Error initializing runtime service opteed_fast
685 08:27:35.859740
686 08:27:35.860275
687 08:27:35.865148 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 08:27:35.865582
689 08:27:35.868788 Model: Libre Computer AML-S905D3-CC Solitude
690 08:27:36.015690 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 08:27:36.031122 DRAM: 2 GiB (effective 3.8 GiB)
692 08:27:36.131879 Core: 406 devices, 33 uclasses, devicetree: separate
693 08:27:36.137934 WDT: Not starting watchdog@f0d0
694 08:27:36.162965 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 08:27:36.175274 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 08:27:36.180163 ** Bad device specification mmc 0 **
697 08:27:36.190217 Card did not respond to voltage select! : -110
698 08:27:36.197883 ** Bad device specification mmc 0 **
699 08:27:36.198297 Couldn't find partition mmc 0
700 08:27:36.206217 Card did not respond to voltage select! : -110
701 08:27:36.211644 ** Bad device specification mmc 0 **
702 08:27:36.212084 Couldn't find partition mmc 0
703 08:27:36.216734 Error: could not access storage.
704 08:27:36.513095 Net: eth0: ethernet@ff3f0000
705 08:27:36.513572 starting USB...
706 08:27:36.757793 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 08:27:36.758226 Starting the controller
708 08:27:36.764911 USB XHCI 1.10
709 08:27:38.321220 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 08:27:38.329565 scanning usb for storage devices... 0 Storage Device(s) found
712 08:27:38.380955 Hit any key to stop autoboot: 1
713 08:27:38.381696 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 08:27:38.382260 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 08:27:38.382730 Setting prompt string to ['=>']
716 08:27:38.383207 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 08:27:38.395564 0
718 08:27:38.396448 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 08:27:38.497592 => setenv autoload no
721 08:27:38.498191 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 08:27:38.502865 setenv autoload no
724 08:27:38.604293 => setenv initrd_high 0xffffffff
725 08:27:38.605015 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 08:27:38.609974 setenv initrd_high 0xffffffff
728 08:27:38.711499 => setenv fdt_high 0xffffffff
729 08:27:38.712196 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 08:27:38.716963 setenv fdt_high 0xffffffff
732 08:27:38.818372 => dhcp
733 08:27:38.818950 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 08:27:38.822366 dhcp
735 08:27:39.679171 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 08:27:39.679645 Speed: 1000, full duplex
737 08:27:39.680112 BOOTP broadcast 1
738 08:27:39.927602 BOOTP broadcast 2
739 08:27:40.004012 DHCP client bound to address 192.168.9.7 (324 ms)
741 08:27:40.105378 => setenv serverip 192.168.6.2
742 08:27:40.105933 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
743 08:27:40.110519 setenv serverip 192.168.6.2
745 08:27:40.211864 => tftpboot 0x01080000 872488/tftp-deploy-78i9ha6x/kernel/uImage
746 08:27:40.212483 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
747 08:27:40.219195 tftpboot 0x01080000 872488/tftp-deploy-78i9ha6x/kernel/uImage
748 08:27:40.219643 Speed: 1000, full duplex
749 08:27:40.220078 Using ethernet@ff3f0000 device
750 08:27:40.230299 TFTP from server 192.168.6.2; our IP address is 192.168.9.7; sending through gateway 192.168.8.1
751 08:27:40.238253 Filename '872488/tftp-deploy-78i9ha6x/kernel/uImage'.
752 08:27:40.238715 Load address: 0x1080000
753 08:28:35.247157 Loading: *T T T T T T T T T T
754 08:28:35.247758 Retry count exceeded; starting again
756 08:28:35.249145 end: 2.4.3 bootloader-commands (duration 00:00:57) [common]
759 08:28:35.250853 end: 2.4 uboot-commands (duration 00:01:16) [common]
761 08:28:35.252189 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
763 08:28:35.253312 end: 2 uboot-action (duration 00:01:16) [common]
765 08:28:35.254810 Cleaning after the job
766 08:28:35.255342 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/ramdisk
767 08:28:35.270511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/kernel
768 08:28:35.296705 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/dtb
769 08:28:35.297890 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872488/tftp-deploy-78i9ha6x/modules
770 08:28:35.320558 start: 4.1 power-off (timeout 00:00:30) [common]
771 08:28:35.321212 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
772 08:28:35.353878 >> OK - accepted request
773 08:28:35.355896 Returned 0 in 0 seconds
774 08:28:35.456597 end: 4.1 power-off (duration 00:00:00) [common]
776 08:28:35.457422 start: 4.2 read-feedback (timeout 00:10:00) [common]
777 08:28:35.458052 Listened to connection for namespace 'common' for up to 1s
778 08:28:36.458920 Finalising connection for namespace 'common'
779 08:28:36.459516 Disconnecting from shell: Finalise
780 08:28:36.460046 =>
781 08:28:36.560910 end: 4.2 read-feedback (duration 00:00:01) [common]
782 08:28:36.561455 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/872488
783 08:28:36.833239 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/872488
784 08:28:36.833831 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.