Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:41:01.949573 lava-dispatcher, installed at version: 2024.01
2 08:41:01.950334 start: 0 validate
3 08:41:01.950819 Start time: 2024-10-21 08:41:01.950789+00:00 (UTC)
4 08:41:01.951341 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:41:01.951876 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 08:41:01.994647 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:41:01.995207 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241021%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 08:41:02.026690 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:41:02.027285 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241021%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:41:02.059719 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:41:02.060221 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:41:02.091444 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:41:02.091905 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241021%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
14 08:41:02.129442 validate duration: 0.18
16 08:41:02.130287 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:41:02.130614 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:41:02.130934 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:41:02.131522 Not decompressing ramdisk as can be used compressed.
20 08:41:02.131963 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 08:41:02.132279 saving as /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/ramdisk/initrd.cpio.gz
22 08:41:02.132554 total size: 5628182 (5 MB)
23 08:41:02.170326 progress 0 % (0 MB)
24 08:41:02.177324 progress 5 % (0 MB)
25 08:41:02.185399 progress 10 % (0 MB)
26 08:41:02.192498 progress 15 % (0 MB)
27 08:41:02.198290 progress 20 % (1 MB)
28 08:41:02.202035 progress 25 % (1 MB)
29 08:41:02.206068 progress 30 % (1 MB)
30 08:41:02.210033 progress 35 % (1 MB)
31 08:41:02.213706 progress 40 % (2 MB)
32 08:41:02.217675 progress 45 % (2 MB)
33 08:41:02.221306 progress 50 % (2 MB)
34 08:41:02.225299 progress 55 % (2 MB)
35 08:41:02.229259 progress 60 % (3 MB)
36 08:41:02.232927 progress 65 % (3 MB)
37 08:41:02.236909 progress 70 % (3 MB)
38 08:41:02.240466 progress 75 % (4 MB)
39 08:41:02.244425 progress 80 % (4 MB)
40 08:41:02.247951 progress 85 % (4 MB)
41 08:41:02.251915 progress 90 % (4 MB)
42 08:41:02.255843 progress 95 % (5 MB)
43 08:41:02.259081 progress 100 % (5 MB)
44 08:41:02.259710 5 MB downloaded in 0.13 s (42.22 MB/s)
45 08:41:02.260276 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:41:02.261161 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:41:02.261452 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:41:02.261721 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:41:02.262184 downloading http://storage.kernelci.org/next/master/next-20241021/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/kernel/Image
51 08:41:02.262421 saving as /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/kernel/Image
52 08:41:02.262628 total size: 47389184 (45 MB)
53 08:41:02.262835 No compression specified
54 08:41:02.301232 progress 0 % (0 MB)
55 08:41:02.330479 progress 5 % (2 MB)
56 08:41:02.359250 progress 10 % (4 MB)
57 08:41:02.387790 progress 15 % (6 MB)
58 08:41:02.416870 progress 20 % (9 MB)
59 08:41:02.445510 progress 25 % (11 MB)
60 08:41:02.474037 progress 30 % (13 MB)
61 08:41:02.503111 progress 35 % (15 MB)
62 08:41:02.531875 progress 40 % (18 MB)
63 08:41:02.560470 progress 45 % (20 MB)
64 08:41:02.589508 progress 50 % (22 MB)
65 08:41:02.618339 progress 55 % (24 MB)
66 08:41:02.647355 progress 60 % (27 MB)
67 08:41:02.676366 progress 65 % (29 MB)
68 08:41:02.705140 progress 70 % (31 MB)
69 08:41:02.733911 progress 75 % (33 MB)
70 08:41:02.762512 progress 80 % (36 MB)
71 08:41:02.791538 progress 85 % (38 MB)
72 08:41:02.820163 progress 90 % (40 MB)
73 08:41:02.848885 progress 95 % (42 MB)
74 08:41:02.877122 progress 100 % (45 MB)
75 08:41:02.877652 45 MB downloaded in 0.62 s (73.48 MB/s)
76 08:41:02.878122 end: 1.2.1 http-download (duration 00:00:01) [common]
78 08:41:02.878933 end: 1.2 download-retry (duration 00:00:01) [common]
79 08:41:02.879206 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:41:02.879471 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:41:02.879928 downloading http://storage.kernelci.org/next/master/next-20241021/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 08:41:02.880217 saving as /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/dtb/meson-g12b-a311d-libretech-cc.dtb
83 08:41:02.880428 total size: 54703 (0 MB)
84 08:41:02.880635 No compression specified
85 08:41:02.922308 progress 59 % (0 MB)
86 08:41:02.923147 progress 100 % (0 MB)
87 08:41:02.923695 0 MB downloaded in 0.04 s (1.21 MB/s)
88 08:41:02.924184 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:41:02.925003 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:41:02.925263 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:41:02.925524 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:41:02.925965 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 08:41:02.926199 saving as /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/nfsrootfs/full.rootfs.tar
95 08:41:02.926399 total size: 107552908 (102 MB)
96 08:41:02.926604 Using unxz to decompress xz
97 08:41:02.959358 progress 0 % (0 MB)
98 08:41:03.711063 progress 5 % (5 MB)
99 08:41:04.430525 progress 10 % (10 MB)
100 08:41:05.146532 progress 15 % (15 MB)
101 08:41:05.890292 progress 20 % (20 MB)
102 08:41:06.454503 progress 25 % (25 MB)
103 08:41:07.069501 progress 30 % (30 MB)
104 08:41:07.799079 progress 35 % (35 MB)
105 08:41:08.160131 progress 40 % (41 MB)
106 08:41:08.588555 progress 45 % (46 MB)
107 08:41:09.271913 progress 50 % (51 MB)
108 08:41:09.941234 progress 55 % (56 MB)
109 08:41:10.686510 progress 60 % (61 MB)
110 08:41:11.429932 progress 65 % (66 MB)
111 08:41:12.158030 progress 70 % (71 MB)
112 08:41:12.922439 progress 75 % (76 MB)
113 08:41:13.602849 progress 80 % (82 MB)
114 08:41:14.301850 progress 85 % (87 MB)
115 08:41:15.069547 progress 90 % (92 MB)
116 08:41:15.820038 progress 95 % (97 MB)
117 08:41:16.578597 progress 100 % (102 MB)
118 08:41:16.590264 102 MB downloaded in 13.66 s (7.51 MB/s)
119 08:41:16.590816 end: 1.4.1 http-download (duration 00:00:14) [common]
121 08:41:16.591644 end: 1.4 download-retry (duration 00:00:14) [common]
122 08:41:16.591907 start: 1.5 download-retry (timeout 00:09:46) [common]
123 08:41:16.592601 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 08:41:16.593719 downloading http://storage.kernelci.org/next/master/next-20241021/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/modules.tar.xz
125 08:41:16.594218 saving as /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/modules/modules.tar
126 08:41:16.594637 total size: 11621680 (11 MB)
127 08:41:16.595070 Using unxz to decompress xz
128 08:41:16.643097 progress 0 % (0 MB)
129 08:41:16.709640 progress 5 % (0 MB)
130 08:41:16.782734 progress 10 % (1 MB)
131 08:41:16.861301 progress 15 % (1 MB)
132 08:41:16.935908 progress 20 % (2 MB)
133 08:41:17.010462 progress 25 % (2 MB)
134 08:41:17.089551 progress 30 % (3 MB)
135 08:41:17.164309 progress 35 % (3 MB)
136 08:41:17.238405 progress 40 % (4 MB)
137 08:41:17.322388 progress 45 % (5 MB)
138 08:41:17.404198 progress 50 % (5 MB)
139 08:41:17.485893 progress 55 % (6 MB)
140 08:41:17.562373 progress 60 % (6 MB)
141 08:41:17.644823 progress 65 % (7 MB)
142 08:41:17.725538 progress 70 % (7 MB)
143 08:41:17.802699 progress 75 % (8 MB)
144 08:41:17.883249 progress 80 % (8 MB)
145 08:41:17.961836 progress 85 % (9 MB)
146 08:41:18.032913 progress 90 % (10 MB)
147 08:41:18.124574 progress 95 % (10 MB)
148 08:41:18.222623 progress 100 % (11 MB)
149 08:41:18.235553 11 MB downloaded in 1.64 s (6.75 MB/s)
150 08:41:18.236400 end: 1.5.1 http-download (duration 00:00:02) [common]
152 08:41:18.238151 end: 1.5 download-retry (duration 00:00:02) [common]
153 08:41:18.238676 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 08:41:18.239193 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 08:41:27.785731 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/872500/extract-nfsrootfs-29ov8p7q
156 08:41:27.786341 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 08:41:27.786637 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 08:41:27.787258 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6
159 08:41:27.787701 makedir: /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin
160 08:41:27.788092 makedir: /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/tests
161 08:41:27.788427 makedir: /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/results
162 08:41:27.788769 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-add-keys
163 08:41:27.789336 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-add-sources
164 08:41:27.789864 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-background-process-start
165 08:41:27.790377 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-background-process-stop
166 08:41:27.790911 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-common-functions
167 08:41:27.791418 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-echo-ipv4
168 08:41:27.791933 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-install-packages
169 08:41:27.792507 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-installed-packages
170 08:41:27.793004 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-os-build
171 08:41:27.793499 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-probe-channel
172 08:41:27.793985 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-probe-ip
173 08:41:27.794473 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-target-ip
174 08:41:27.794956 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-target-mac
175 08:41:27.795444 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-target-storage
176 08:41:27.795954 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-test-case
177 08:41:27.796505 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-test-event
178 08:41:27.797009 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-test-feedback
179 08:41:27.797501 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-test-raise
180 08:41:27.797985 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-test-reference
181 08:41:27.798473 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-test-runner
182 08:41:27.798965 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-test-set
183 08:41:27.799455 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-test-shell
184 08:41:27.799976 Updating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-install-packages (oe)
185 08:41:27.800636 Updating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/bin/lava-installed-packages (oe)
186 08:41:27.801124 Creating /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/environment
187 08:41:27.801510 LAVA metadata
188 08:41:27.801776 - LAVA_JOB_ID=872500
189 08:41:27.801996 - LAVA_DISPATCHER_IP=192.168.6.2
190 08:41:27.802353 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 08:41:27.803315 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 08:41:27.803642 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 08:41:27.803858 skipped lava-vland-overlay
194 08:41:27.804132 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 08:41:27.804397 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 08:41:27.804622 skipped lava-multinode-overlay
197 08:41:27.804870 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 08:41:27.805127 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 08:41:27.805381 Loading test definitions
200 08:41:27.805668 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 08:41:27.805895 Using /lava-872500 at stage 0
202 08:41:27.807058 uuid=872500_1.6.2.4.1 testdef=None
203 08:41:27.807372 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 08:41:27.807641 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 08:41:27.809546 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 08:41:27.810358 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 08:41:27.812638 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 08:41:27.813484 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 08:41:27.815645 runner path: /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/0/tests/0_dmesg test_uuid 872500_1.6.2.4.1
212 08:41:27.816219 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 08:41:27.816995 Creating lava-test-runner.conf files
215 08:41:27.817199 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/872500/lava-overlay-7ac4e1l6/lava-872500/0 for stage 0
216 08:41:27.817536 - 0_dmesg
217 08:41:27.817883 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 08:41:27.818165 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 08:41:27.839815 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 08:41:27.840196 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 08:41:27.840466 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 08:41:27.840734 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 08:41:27.840997 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 08:41:28.447591 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 08:41:28.448127 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
226 08:41:28.448393 extracting modules file /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/872500/extract-nfsrootfs-29ov8p7q
227 08:41:29.796547 extracting modules file /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/872500/extract-overlay-ramdisk-qjhhg595/ramdisk
228 08:41:31.187324 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 08:41:31.187782 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
230 08:41:31.188096 [common] Applying overlay to NFS
231 08:41:31.188315 [common] Applying overlay /var/lib/lava/dispatcher/tmp/872500/compress-overlay-9gndbzpz/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/872500/extract-nfsrootfs-29ov8p7q
232 08:41:31.217558 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 08:41:31.217927 start: 1.6.6 prepare-kernel (timeout 00:09:31) [common]
234 08:41:31.218201 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:31) [common]
235 08:41:31.218431 Converting downloaded kernel to a uImage
236 08:41:31.218733 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/kernel/Image /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/kernel/uImage
237 08:41:31.726118 output: Image Name:
238 08:41:31.726520 output: Created: Mon Oct 21 08:41:31 2024
239 08:41:31.726743 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 08:41:31.726956 output: Data Size: 47389184 Bytes = 46278.50 KiB = 45.19 MiB
241 08:41:31.727162 output: Load Address: 01080000
242 08:41:31.727364 output: Entry Point: 01080000
243 08:41:31.727565 output:
244 08:41:31.727905 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 08:41:31.728612 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 08:41:31.729240 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 08:41:31.729803 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 08:41:31.730367 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 08:41:31.730920 Building ramdisk /var/lib/lava/dispatcher/tmp/872500/extract-overlay-ramdisk-qjhhg595/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/872500/extract-overlay-ramdisk-qjhhg595/ramdisk
250 08:41:33.846463 >> 167588 blocks
251 08:41:41.554186 Adding RAMdisk u-boot header.
252 08:41:41.554836 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/872500/extract-overlay-ramdisk-qjhhg595/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/872500/extract-overlay-ramdisk-qjhhg595/ramdisk.cpio.gz.uboot
253 08:41:41.822760 output: Image Name:
254 08:41:41.823178 output: Created: Mon Oct 21 08:41:41 2024
255 08:41:41.823392 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 08:41:41.823596 output: Data Size: 23473321 Bytes = 22923.17 KiB = 22.39 MiB
257 08:41:41.823799 output: Load Address: 00000000
258 08:41:41.824092 output: Entry Point: 00000000
259 08:41:41.824499 output:
260 08:41:41.825606 rename /var/lib/lava/dispatcher/tmp/872500/extract-overlay-ramdisk-qjhhg595/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/ramdisk/ramdisk.cpio.gz.uboot
261 08:41:41.826341 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 08:41:41.826884 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 08:41:41.827407 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 08:41:41.827864 No LXC device requested
265 08:41:41.828413 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 08:41:41.828930 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 08:41:41.829424 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 08:41:41.829836 Checking files for TFTP limit of 4294967296 bytes.
269 08:41:41.832515 end: 1 tftp-deploy (duration 00:00:40) [common]
270 08:41:41.833106 start: 2 uboot-action (timeout 00:05:00) [common]
271 08:41:41.833630 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 08:41:41.834122 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 08:41:41.834619 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 08:41:41.835147 Using kernel file from prepare-kernel: 872500/tftp-deploy-f7v6n9i7/kernel/uImage
275 08:41:41.835769 substitutions:
276 08:41:41.836207 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 08:41:41.836610 - {DTB_ADDR}: 0x01070000
278 08:41:41.837005 - {DTB}: 872500/tftp-deploy-f7v6n9i7/dtb/meson-g12b-a311d-libretech-cc.dtb
279 08:41:41.837399 - {INITRD}: 872500/tftp-deploy-f7v6n9i7/ramdisk/ramdisk.cpio.gz.uboot
280 08:41:41.837794 - {KERNEL_ADDR}: 0x01080000
281 08:41:41.838182 - {KERNEL}: 872500/tftp-deploy-f7v6n9i7/kernel/uImage
282 08:41:41.838569 - {LAVA_MAC}: None
283 08:41:41.838994 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/872500/extract-nfsrootfs-29ov8p7q
284 08:41:41.839389 - {NFS_SERVER_IP}: 192.168.6.2
285 08:41:41.839774 - {PRESEED_CONFIG}: None
286 08:41:41.840192 - {PRESEED_LOCAL}: None
287 08:41:41.840582 - {RAMDISK_ADDR}: 0x08000000
288 08:41:41.840961 - {RAMDISK}: 872500/tftp-deploy-f7v6n9i7/ramdisk/ramdisk.cpio.gz.uboot
289 08:41:41.841347 - {ROOT_PART}: None
290 08:41:41.841730 - {ROOT}: None
291 08:41:41.842114 - {SERVER_IP}: 192.168.6.2
292 08:41:41.842497 - {TEE_ADDR}: 0x83000000
293 08:41:41.842879 - {TEE}: None
294 08:41:41.843262 Parsed boot commands:
295 08:41:41.843636 - setenv autoload no
296 08:41:41.844058 - setenv initrd_high 0xffffffff
297 08:41:41.844448 - setenv fdt_high 0xffffffff
298 08:41:41.844834 - dhcp
299 08:41:41.845214 - setenv serverip 192.168.6.2
300 08:41:41.845595 - tftpboot 0x01080000 872500/tftp-deploy-f7v6n9i7/kernel/uImage
301 08:41:41.845977 - tftpboot 0x08000000 872500/tftp-deploy-f7v6n9i7/ramdisk/ramdisk.cpio.gz.uboot
302 08:41:41.846356 - tftpboot 0x01070000 872500/tftp-deploy-f7v6n9i7/dtb/meson-g12b-a311d-libretech-cc.dtb
303 08:41:41.846738 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/872500/extract-nfsrootfs-29ov8p7q,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 08:41:41.847131 - bootm 0x01080000 0x08000000 0x01070000
305 08:41:41.847625 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 08:41:41.849202 start: 2.3 connect-device (timeout 00:05:00) [common]
308 08:41:41.849631 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 08:41:41.863257 Setting prompt string to ['lava-test: # ']
310 08:41:41.864752 end: 2.3 connect-device (duration 00:00:00) [common]
311 08:41:41.865342 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 08:41:41.865886 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 08:41:41.866395 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 08:41:41.867702 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 08:41:41.905130 >> OK - accepted request
316 08:41:41.907166 Returned 0 in 0 seconds
317 08:41:42.008235 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 08:41:42.009777 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 08:41:42.010335 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 08:41:42.010832 Setting prompt string to ['Hit any key to stop autoboot']
322 08:41:42.011282 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 08:41:42.012808 Trying 192.168.56.21...
324 08:41:42.013299 Connected to conserv1.
325 08:41:42.013724 Escape character is '^]'.
326 08:41:42.014141
327 08:41:42.014563 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 08:41:42.014994
329 08:41:53.403388 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 08:41:53.404053 bl2_stage_init 0x81
331 08:41:53.408980 hw id: 0x0000 - pwm id 0x01
332 08:41:53.409429 bl2_stage_init 0xc1
333 08:41:53.409823 bl2_stage_init 0x02
334 08:41:53.410221
335 08:41:53.414423 L0:00000000
336 08:41:53.414849 L1:20000703
337 08:41:53.415239 L2:00008067
338 08:41:53.415624 L3:14000000
339 08:41:53.416052 B2:00402000
340 08:41:53.417327 B1:e0f83180
341 08:41:53.417756
342 08:41:53.418148 TE: 58150
343 08:41:53.418537
344 08:41:53.428500 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 08:41:53.428922
346 08:41:53.429315 Board ID = 1
347 08:41:53.429703 Set A53 clk to 24M
348 08:41:53.430089 Set A73 clk to 24M
349 08:41:53.434106 Set clk81 to 24M
350 08:41:53.434519 A53 clk: 1200 MHz
351 08:41:53.434907 A73 clk: 1200 MHz
352 08:41:53.439786 CLK81: 166.6M
353 08:41:53.440232 smccc: 00012aac
354 08:41:53.445279 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 08:41:53.445702 board id: 1
356 08:41:53.453872 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 08:41:53.464415 fw parse done
358 08:41:53.470388 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 08:41:53.512998 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 08:41:53.523875 PIEI prepare done
361 08:41:53.524343 fastboot data load
362 08:41:53.524732 fastboot data verify
363 08:41:53.529588 verify result: 266
364 08:41:53.535161 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 08:41:53.535571 LPDDR4 probe
366 08:41:53.535954 ddr clk to 1584MHz
367 08:41:53.543167 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 08:41:53.580387
369 08:41:53.580801 dmc_version 0001
370 08:41:53.587095 Check phy result
371 08:41:53.592950 INFO : End of CA training
372 08:41:53.593363 INFO : End of initialization
373 08:41:53.598526 INFO : Training has run successfully!
374 08:41:53.598937 Check phy result
375 08:41:53.604155 INFO : End of initialization
376 08:41:53.604565 INFO : End of read enable training
377 08:41:53.609810 INFO : End of fine write leveling
378 08:41:53.615315 INFO : End of Write leveling coarse delay
379 08:41:53.615730 INFO : Training has run successfully!
380 08:41:53.616147 Check phy result
381 08:41:53.620966 INFO : End of initialization
382 08:41:53.621386 INFO : End of read dq deskew training
383 08:41:53.626571 INFO : End of MPR read delay center optimization
384 08:41:53.632225 INFO : End of write delay center optimization
385 08:41:53.637822 INFO : End of read delay center optimization
386 08:41:53.638232 INFO : End of max read latency training
387 08:41:53.643339 INFO : Training has run successfully!
388 08:41:53.643752 1D training succeed
389 08:41:53.652587 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 08:41:53.700154 Check phy result
391 08:41:53.700563 INFO : End of initialization
392 08:41:53.721945 INFO : End of 2D read delay Voltage center optimization
393 08:41:53.741235 INFO : End of 2D read delay Voltage center optimization
394 08:41:53.793236 INFO : End of 2D write delay Voltage center optimization
395 08:41:53.842653 INFO : End of 2D write delay Voltage center optimization
396 08:41:53.848349 INFO : Training has run successfully!
397 08:41:53.848756
398 08:41:53.849148 channel==0
399 08:41:53.853963 RxClkDly_Margin_A0==88 ps 9
400 08:41:53.854376 TxDqDly_Margin_A0==98 ps 10
401 08:41:53.857310 RxClkDly_Margin_A1==88 ps 9
402 08:41:53.857719 TxDqDly_Margin_A1==98 ps 10
403 08:41:53.862920 TrainedVREFDQ_A0==74
404 08:41:53.863332 TrainedVREFDQ_A1==74
405 08:41:53.863725 VrefDac_Margin_A0==25
406 08:41:53.868440 DeviceVref_Margin_A0==40
407 08:41:53.868865 VrefDac_Margin_A1==25
408 08:41:53.874063 DeviceVref_Margin_A1==40
409 08:41:53.874471
410 08:41:53.874862
411 08:41:53.875251 channel==1
412 08:41:53.875634 RxClkDly_Margin_A0==98 ps 10
413 08:41:53.877503 TxDqDly_Margin_A0==98 ps 10
414 08:41:53.883071 RxClkDly_Margin_A1==88 ps 9
415 08:41:53.883481 TxDqDly_Margin_A1==88 ps 9
416 08:41:53.883874 TrainedVREFDQ_A0==77
417 08:41:53.888674 TrainedVREFDQ_A1==77
418 08:41:53.889089 VrefDac_Margin_A0==23
419 08:41:53.894181 DeviceVref_Margin_A0==37
420 08:41:53.894593 VrefDac_Margin_A1==24
421 08:41:53.894980 DeviceVref_Margin_A1==37
422 08:41:53.895365
423 08:41:53.903363 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 08:41:53.903786
425 08:41:53.931249 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
426 08:41:53.931733 2D training succeed
427 08:41:53.936828 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 08:41:53.942405 auto size-- 65535DDR cs0 size: 2048MB
429 08:41:53.942819 DDR cs1 size: 2048MB
430 08:41:53.948045 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 08:41:53.948459 cs0 DataBus test pass
432 08:41:53.953605 cs1 DataBus test pass
433 08:41:53.954014 cs0 AddrBus test pass
434 08:41:53.959220 cs1 AddrBus test pass
435 08:41:53.959631
436 08:41:53.960048 100bdlr_step_size ps== 420
437 08:41:53.960446 result report
438 08:41:53.964829 boot times 0Enable ddr reg access
439 08:41:53.971122 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 08:41:53.984605 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 08:41:54.557533 0.0;M3 CHK:0;cm4_sp_mode 0
442 08:41:54.557976 MVN_1=0x00000000
443 08:41:54.563095 MVN_2=0x00000000
444 08:41:54.568831 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 08:41:54.569247 OPS=0x10
446 08:41:54.569638 ring efuse init
447 08:41:54.570022 chipver efuse init
448 08:41:54.574457 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 08:41:54.580089 [0.018961 Inits done]
450 08:41:54.580497 secure task start!
451 08:41:54.580882 high task start!
452 08:41:54.584640 low task start!
453 08:41:54.585048 run into bl31
454 08:41:54.591259 NOTICE: BL31: v1.3(release):4fc40b1
455 08:41:54.599073 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 08:41:54.599504 NOTICE: BL31: G12A normal boot!
457 08:41:54.624481 NOTICE: BL31: BL33 decompress pass
458 08:41:54.630174 ERROR: Error initializing runtime service opteed_fast
459 08:41:55.862922
460 08:41:55.863440
461 08:41:55.871395 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 08:41:55.871830
463 08:41:55.872281 Model: Libre Computer AML-A311D-CC Alta
464 08:41:56.079726 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 08:41:56.103202 DRAM: 2 GiB (effective 3.8 GiB)
466 08:41:56.246112 Core: 408 devices, 31 uclasses, devicetree: separate
467 08:41:56.252163 WDT: Not starting watchdog@f0d0
468 08:41:56.284269 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
469 08:41:56.296807 Loading Environment from FAT... Card did not respond to voltage select! : -110
470 08:41:56.301756 ** Bad device specification mmc 0 **
471 08:41:56.312062 Card did not respond to voltage select! : -110
472 08:41:56.319769 ** Bad device specification mmc 0 **
473 08:41:56.320255 Couldn't find partition mmc 0
474 08:41:56.328069 Card did not respond to voltage select! : -110
475 08:41:56.333569 ** Bad device specification mmc 0 **
476 08:41:56.333996 Couldn't find partition mmc 0
477 08:41:56.338658 Error: could not access storage.
478 08:41:57.603364 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
479 08:41:57.603794 bl2_stage_init 0x01
480 08:41:57.604073 bl2_stage_init 0x81
481 08:41:57.608919 hw id: 0x0000 - pwm id 0x01
482 08:41:57.609297 bl2_stage_init 0xc1
483 08:41:57.609552 bl2_stage_init 0x02
484 08:41:57.609791
485 08:41:57.614492 L0:00000000
486 08:41:57.615084 L1:20000703
487 08:41:57.615499 L2:00008067
488 08:41:57.615768 L3:14000000
489 08:41:57.617270 B2:00402000
490 08:41:57.617577 B1:e0f83180
491 08:41:57.617812
492 08:41:57.618034 TE: 58124
493 08:41:57.618250
494 08:41:57.628460 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 08:41:57.628843
496 08:41:57.629080 Board ID = 1
497 08:41:57.629358 Set A53 clk to 24M
498 08:41:57.629853 Set A73 clk to 24M
499 08:41:57.634002 Set clk81 to 24M
500 08:41:57.634342 A53 clk: 1200 MHz
501 08:41:57.634575 A73 clk: 1200 MHz
502 08:41:57.639518 CLK81: 166.6M
503 08:41:57.639803 smccc: 00012a92
504 08:41:57.645168 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 08:41:57.645442 board id: 1
506 08:41:57.650742 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 08:41:57.664620 fw parse done
508 08:41:57.670588 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 08:41:57.713232 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 08:41:57.724151 PIEI prepare done
511 08:41:57.725392 fastboot data load
512 08:41:57.725752 fastboot data verify
513 08:41:57.730121 verify result: 266
514 08:41:57.735491 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 08:41:57.736023 LPDDR4 probe
516 08:41:57.736294 ddr clk to 1584MHz
517 08:41:57.743516 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 08:41:57.780939
519 08:41:57.781460 dmc_version 0001
520 08:41:57.787314 Check phy result
521 08:41:57.796007 INFO : End of CA training
522 08:41:57.796587 INFO : End of initialization
523 08:41:57.798723 INFO : Training has run successfully!
524 08:41:57.799220 Check phy result
525 08:41:57.804687 INFO : End of initialization
526 08:41:57.805254 INFO : End of read enable training
527 08:41:57.809992 INFO : End of fine write leveling
528 08:41:57.815581 INFO : End of Write leveling coarse delay
529 08:41:57.816143 INFO : Training has run successfully!
530 08:41:57.816615 Check phy result
531 08:41:57.821101 INFO : End of initialization
532 08:41:57.821634 INFO : End of read dq deskew training
533 08:41:57.826699 INFO : End of MPR read delay center optimization
534 08:41:57.832406 INFO : End of write delay center optimization
535 08:41:57.844548 INFO : End of read delay center optimization
536 08:41:57.845105 INFO : End of max read latency training
537 08:41:57.845601 INFO : Training has run successfully!
538 08:41:57.846073 1D training succeed
539 08:41:57.855330 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 08:41:57.900364 Check phy result
541 08:41:57.900932 INFO : End of initialization
542 08:41:57.923667 INFO : End of 2D read delay Voltage center optimization
543 08:41:57.944493 INFO : End of 2D read delay Voltage center optimization
544 08:41:58.011007 INFO : End of 2D write delay Voltage center optimization
545 08:41:58.061008 INFO : End of 2D write delay Voltage center optimization
546 08:41:58.061549 INFO : Training has run successfully!
547 08:41:58.062012
548 08:41:58.062466 channel==0
549 08:41:58.062913 RxClkDly_Margin_A0==88 ps 9
550 08:41:58.063356 TxDqDly_Margin_A0==98 ps 10
551 08:41:58.063807 RxClkDly_Margin_A1==88 ps 9
552 08:41:58.064310 TxDqDly_Margin_A1==98 ps 10
553 08:41:58.064769 TrainedVREFDQ_A0==74
554 08:41:58.065549 TrainedVREFDQ_A1==74
555 08:41:58.066047 VrefDac_Margin_A0==25
556 08:41:58.066501 DeviceVref_Margin_A0==40
557 08:41:58.070732 VrefDac_Margin_A1==25
558 08:41:58.071228 DeviceVref_Margin_A1==40
559 08:41:58.071677
560 08:41:58.072161
561 08:41:58.076375 channel==1
562 08:41:58.076859 RxClkDly_Margin_A0==98 ps 10
563 08:41:58.077306 TxDqDly_Margin_A0==88 ps 9
564 08:41:58.081917 RxClkDly_Margin_A1==98 ps 10
565 08:41:58.082397 TxDqDly_Margin_A1==88 ps 9
566 08:41:58.087532 TrainedVREFDQ_A0==77
567 08:41:58.088056 TrainedVREFDQ_A1==77
568 08:41:58.088515 VrefDac_Margin_A0==23
569 08:41:58.093102 DeviceVref_Margin_A0==37
570 08:41:58.093580 VrefDac_Margin_A1==23
571 08:41:58.098744 DeviceVref_Margin_A1==37
572 08:41:58.099221
573 08:41:58.099669 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 08:41:58.100152
575 08:41:58.132407 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
576 08:41:58.132939 2D training succeed
577 08:41:58.137877 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 08:41:58.143530 auto size-- 65535DDR cs0 size: 2048MB
579 08:41:58.144073 DDR cs1 size: 2048MB
580 08:41:58.149100 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 08:41:58.149604 cs0 DataBus test pass
582 08:41:58.154697 cs1 DataBus test pass
583 08:41:58.155187 cs0 AddrBus test pass
584 08:41:58.155636 cs1 AddrBus test pass
585 08:41:58.156110
586 08:41:58.160389 100bdlr_step_size ps== 420
587 08:41:58.160908 result report
588 08:41:58.165899 boot times 0Enable ddr reg access
589 08:41:58.171245 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 08:41:58.184760 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 08:41:58.758460 0.0;M3 CHK:0;cm4_sp_mode 0
592 08:41:58.758994 MVN_1=0x00000000
593 08:41:58.763956 MVN_2=0x00000000
594 08:41:58.769694 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 08:41:58.770207 OPS=0x10
596 08:41:58.770658 ring efuse init
597 08:41:58.771093 chipver efuse init
598 08:41:58.775349 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 08:41:58.780912 [0.018961 Inits done]
600 08:41:58.781399 secure task start!
601 08:41:58.781837 high task start!
602 08:41:58.785484 low task start!
603 08:41:58.785954 run into bl31
604 08:41:58.792082 NOTICE: BL31: v1.3(release):4fc40b1
605 08:41:58.799904 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 08:41:58.800414 NOTICE: BL31: G12A normal boot!
607 08:41:58.825243 NOTICE: BL31: BL33 decompress pass
608 08:41:58.830889 ERROR: Error initializing runtime service opteed_fast
609 08:42:00.063861
610 08:42:00.064484
611 08:42:00.072416 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 08:42:00.072920
613 08:42:00.073381 Model: Libre Computer AML-A311D-CC Alta
614 08:42:00.280782 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 08:42:00.304153 DRAM: 2 GiB (effective 3.8 GiB)
616 08:42:00.447128 Core: 408 devices, 31 uclasses, devicetree: separate
617 08:42:00.453012 WDT: Not starting watchdog@f0d0
618 08:42:00.485180 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 08:42:00.497748 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 08:42:00.502682 ** Bad device specification mmc 0 **
621 08:42:00.512900 Card did not respond to voltage select! : -110
622 08:42:00.520648 ** Bad device specification mmc 0 **
623 08:42:00.521164 Couldn't find partition mmc 0
624 08:42:00.529005 Card did not respond to voltage select! : -110
625 08:42:00.534434 ** Bad device specification mmc 0 **
626 08:42:00.534925 Couldn't find partition mmc 0
627 08:42:00.539552 Error: could not access storage.
628 08:42:00.882230 Net: eth0: ethernet@ff3f0000
629 08:42:00.882807 starting USB...
630 08:42:01.134010 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 08:42:01.134647 Starting the controller
632 08:42:01.140826 USB XHCI 1.10
633 08:42:02.853737 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 08:42:02.854396 bl2_stage_init 0x01
635 08:42:02.854879 bl2_stage_init 0x81
636 08:42:02.859283 hw id: 0x0000 - pwm id 0x01
637 08:42:02.859786 bl2_stage_init 0xc1
638 08:42:02.860311 bl2_stage_init 0x02
639 08:42:02.860774
640 08:42:02.865024 L0:00000000
641 08:42:02.865517 L1:20000703
642 08:42:02.865975 L2:00008067
643 08:42:02.866423 L3:14000000
644 08:42:02.867805 B2:00402000
645 08:42:02.868326 B1:e0f83180
646 08:42:02.868779
647 08:42:02.869226 TE: 58167
648 08:42:02.869671
649 08:42:02.879174 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 08:42:02.879680
651 08:42:02.880173 Board ID = 1
652 08:42:02.880627 Set A53 clk to 24M
653 08:42:02.881070 Set A73 clk to 24M
654 08:42:02.884623 Set clk81 to 24M
655 08:42:02.885115 A53 clk: 1200 MHz
656 08:42:02.885573 A73 clk: 1200 MHz
657 08:42:02.890122 CLK81: 166.6M
658 08:42:02.890609 smccc: 00012abd
659 08:42:02.895810 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 08:42:02.896335 board id: 1
661 08:42:02.904640 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 08:42:02.915018 fw parse done
663 08:42:02.920914 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 08:42:02.963615 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 08:42:02.974423 PIEI prepare done
666 08:42:02.974919 fastboot data load
667 08:42:02.975374 fastboot data verify
668 08:42:02.980111 verify result: 266
669 08:42:02.985670 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 08:42:02.986160 LPDDR4 probe
671 08:42:02.986614 ddr clk to 1584MHz
672 08:42:02.993658 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 08:42:03.030960
674 08:42:03.031525 dmc_version 0001
675 08:42:03.037720 Check phy result
676 08:42:03.043485 INFO : End of CA training
677 08:42:03.043975 INFO : End of initialization
678 08:42:03.049126 INFO : Training has run successfully!
679 08:42:03.049616 Check phy result
680 08:42:03.054746 INFO : End of initialization
681 08:42:03.055241 INFO : End of read enable training
682 08:42:03.058169 INFO : End of fine write leveling
683 08:42:03.063975 INFO : End of Write leveling coarse delay
684 08:42:03.069508 INFO : Training has run successfully!
685 08:42:03.070110 Check phy result
686 08:42:03.070519 INFO : End of initialization
687 08:42:03.075450 INFO : End of read dq deskew training
688 08:42:03.080672 INFO : End of MPR read delay center optimization
689 08:42:03.081266 INFO : End of write delay center optimization
690 08:42:03.086339 INFO : End of read delay center optimization
691 08:42:03.091877 INFO : End of max read latency training
692 08:42:03.092467 INFO : Training has run successfully!
693 08:42:03.097589 1D training succeed
694 08:42:03.103424 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 08:42:03.150827 Check phy result
696 08:42:03.151521 INFO : End of initialization
697 08:42:03.172572 INFO : End of 2D read delay Voltage center optimization
698 08:42:03.192787 INFO : End of 2D read delay Voltage center optimization
699 08:42:03.244894 INFO : End of 2D write delay Voltage center optimization
700 08:42:03.294157 INFO : End of 2D write delay Voltage center optimization
701 08:42:03.299849 INFO : Training has run successfully!
702 08:42:03.300418
703 08:42:03.300853 channel==0
704 08:42:03.305347 RxClkDly_Margin_A0==88 ps 9
705 08:42:03.305859 TxDqDly_Margin_A0==98 ps 10
706 08:42:03.308666 RxClkDly_Margin_A1==88 ps 9
707 08:42:03.309171 TxDqDly_Margin_A1==98 ps 10
708 08:42:03.314173 TrainedVREFDQ_A0==74
709 08:42:03.314677 TrainedVREFDQ_A1==74
710 08:42:03.319847 VrefDac_Margin_A0==25
711 08:42:03.320375 DeviceVref_Margin_A0==40
712 08:42:03.320797 VrefDac_Margin_A1==25
713 08:42:03.325414 DeviceVref_Margin_A1==40
714 08:42:03.325906
715 08:42:03.326332
716 08:42:03.326745 channel==1
717 08:42:03.327147 RxClkDly_Margin_A0==98 ps 10
718 08:42:03.328887 TxDqDly_Margin_A0==98 ps 10
719 08:42:03.334426 RxClkDly_Margin_A1==98 ps 10
720 08:42:03.334916 TxDqDly_Margin_A1==88 ps 9
721 08:42:03.335338 TrainedVREFDQ_A0==77
722 08:42:03.340082 TrainedVREFDQ_A1==77
723 08:42:03.340594 VrefDac_Margin_A0==22
724 08:42:03.345702 DeviceVref_Margin_A0==37
725 08:42:03.346196 VrefDac_Margin_A1==22
726 08:42:03.346611 DeviceVref_Margin_A1==37
727 08:42:03.347011
728 08:42:03.351258 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 08:42:03.351748
730 08:42:03.384754 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
731 08:42:03.385307 2D training succeed
732 08:42:03.390451 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 08:42:03.396043 auto size-- 65535DDR cs0 size: 2048MB
734 08:42:03.396532 DDR cs1 size: 2048MB
735 08:42:03.401661 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 08:42:03.402160 cs0 DataBus test pass
737 08:42:03.402574 cs1 DataBus test pass
738 08:42:03.407250 cs0 AddrBus test pass
739 08:42:03.407734 cs1 AddrBus test pass
740 08:42:03.408202
741 08:42:03.412795 100bdlr_step_size ps== 420
742 08:42:03.413292 result report
743 08:42:03.413704 boot times 0Enable ddr reg access
744 08:42:03.422689 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 08:42:03.436261 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 08:42:04.009916 0.0;M3 CHK:0;cm4_sp_mode 0
747 08:42:04.010523 MVN_1=0x00000000
748 08:42:04.015588 MVN_2=0x00000000
749 08:42:04.021302 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 08:42:04.021819 OPS=0x10
751 08:42:04.022216 ring efuse init
752 08:42:04.022601 chipver efuse init
753 08:42:04.029373 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 08:42:04.029855 [0.018960 Inits done]
755 08:42:04.036999 secure task start!
756 08:42:04.037466 high task start!
757 08:42:04.037856 low task start!
758 08:42:04.038237 run into bl31
759 08:42:04.043585 NOTICE: BL31: v1.3(release):4fc40b1
760 08:42:04.051379 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 08:42:04.051847 NOTICE: BL31: G12A normal boot!
762 08:42:04.076701 NOTICE: BL31: BL33 decompress pass
763 08:42:04.082385 ERROR: Error initializing runtime service opteed_fast
764 08:42:05.315210
765 08:42:05.315803
766 08:42:05.323772 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 08:42:05.324289
768 08:42:05.324718 Model: Libre Computer AML-A311D-CC Alta
769 08:42:05.532565 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 08:42:05.555549 DRAM: 2 GiB (effective 3.8 GiB)
771 08:42:05.698434 Core: 408 devices, 31 uclasses, devicetree: separate
772 08:42:05.704383 WDT: Not starting watchdog@f0d0
773 08:42:05.736635 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 08:42:05.749068 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 08:42:05.754060 ** Bad device specification mmc 0 **
776 08:42:05.764313 Card did not respond to voltage select! : -110
777 08:42:05.772114 ** Bad device specification mmc 0 **
778 08:42:05.772591 Couldn't find partition mmc 0
779 08:42:05.780344 Card did not respond to voltage select! : -110
780 08:42:05.785878 ** Bad device specification mmc 0 **
781 08:42:05.786341 Couldn't find partition mmc 0
782 08:42:05.791022 Error: could not access storage.
783 08:42:06.133400 Net: eth0: ethernet@ff3f0000
784 08:42:06.133891 starting USB...
785 08:42:06.385249 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 08:42:06.385792 Starting the controller
787 08:42:06.392297 USB XHCI 1.10
788 08:42:08.553953 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
789 08:42:08.554598 bl2_stage_init 0x81
790 08:42:08.559733 hw id: 0x0000 - pwm id 0x01
791 08:42:08.560247 bl2_stage_init 0xc1
792 08:42:08.560666 bl2_stage_init 0x02
793 08:42:08.561076
794 08:42:08.565126 L0:00000000
795 08:42:08.565595 L1:20000703
796 08:42:08.566007 L2:00008067
797 08:42:08.566411 L3:14000000
798 08:42:08.566809 B2:00402000
799 08:42:08.568086 B1:e0f83180
800 08:42:08.568552
801 08:42:08.568967 TE: 58150
802 08:42:08.569372
803 08:42:08.579181 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
804 08:42:08.579653
805 08:42:08.580104 Board ID = 1
806 08:42:08.580514 Set A53 clk to 24M
807 08:42:08.580914 Set A73 clk to 24M
808 08:42:08.584747 Set clk81 to 24M
809 08:42:08.585213 A53 clk: 1200 MHz
810 08:42:08.585627 A73 clk: 1200 MHz
811 08:42:08.590419 CLK81: 166.6M
812 08:42:08.590899 smccc: 00012aac
813 08:42:08.595967 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
814 08:42:08.596463 board id: 1
815 08:42:08.604698 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
816 08:42:08.615297 fw parse done
817 08:42:08.621274 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
818 08:42:08.663717 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
819 08:42:08.674616 PIEI prepare done
820 08:42:08.675080 fastboot data load
821 08:42:08.675493 fastboot data verify
822 08:42:08.680347 verify result: 266
823 08:42:08.685948 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
824 08:42:08.686416 LPDDR4 probe
825 08:42:08.686826 ddr clk to 1584MHz
826 08:42:08.693921 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
827 08:42:08.731135
828 08:42:08.731603 dmc_version 0001
829 08:42:08.737844 Check phy result
830 08:42:08.743728 INFO : End of CA training
831 08:42:08.744222 INFO : End of initialization
832 08:42:08.749314 INFO : Training has run successfully!
833 08:42:08.749778 Check phy result
834 08:42:08.754966 INFO : End of initialization
835 08:42:08.755430 INFO : End of read enable training
836 08:42:08.758224 INFO : End of fine write leveling
837 08:42:08.763743 INFO : End of Write leveling coarse delay
838 08:42:08.769359 INFO : Training has run successfully!
839 08:42:08.769824 Check phy result
840 08:42:08.770242 INFO : End of initialization
841 08:42:08.775035 INFO : End of read dq deskew training
842 08:42:08.778371 INFO : End of MPR read delay center optimization
843 08:42:08.784046 INFO : End of write delay center optimization
844 08:42:08.789493 INFO : End of read delay center optimization
845 08:42:08.789958 INFO : End of max read latency training
846 08:42:08.795093 INFO : Training has run successfully!
847 08:42:08.795557 1D training succeed
848 08:42:08.803296 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 08:42:08.850904 Check phy result
850 08:42:08.851366 INFO : End of initialization
851 08:42:08.872610 INFO : End of 2D read delay Voltage center optimization
852 08:42:08.892157 INFO : End of 2D read delay Voltage center optimization
853 08:42:08.944171 INFO : End of 2D write delay Voltage center optimization
854 08:42:08.993354 INFO : End of 2D write delay Voltage center optimization
855 08:42:08.999093 INFO : Training has run successfully!
856 08:42:08.999555
857 08:42:08.999969 channel==0
858 08:42:09.004595 RxClkDly_Margin_A0==88 ps 9
859 08:42:09.005059 TxDqDly_Margin_A0==98 ps 10
860 08:42:09.007905 RxClkDly_Margin_A1==88 ps 9
861 08:42:09.008405 TxDqDly_Margin_A1==98 ps 10
862 08:42:09.013529 TrainedVREFDQ_A0==74
863 08:42:09.013998 TrainedVREFDQ_A1==74
864 08:42:09.019148 VrefDac_Margin_A0==25
865 08:42:09.019632 DeviceVref_Margin_A0==40
866 08:42:09.020082 VrefDac_Margin_A1==25
867 08:42:09.024655 DeviceVref_Margin_A1==40
868 08:42:09.025124
869 08:42:09.025512
870 08:42:09.025897 channel==1
871 08:42:09.026274 RxClkDly_Margin_A0==88 ps 9
872 08:42:09.030205 TxDqDly_Margin_A0==98 ps 10
873 08:42:09.030666 RxClkDly_Margin_A1==88 ps 9
874 08:42:09.035843 TxDqDly_Margin_A1==88 ps 9
875 08:42:09.036326 TrainedVREFDQ_A0==77
876 08:42:09.036718 TrainedVREFDQ_A1==77
877 08:42:09.041504 VrefDac_Margin_A0==23
878 08:42:09.041956 DeviceVref_Margin_A0==37
879 08:42:09.047090 VrefDac_Margin_A1==24
880 08:42:09.047537 DeviceVref_Margin_A1==37
881 08:42:09.047921
882 08:42:09.052588 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
883 08:42:09.053039
884 08:42:09.080631 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
885 08:42:09.086214 2D training succeed
886 08:42:09.091753 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
887 08:42:09.092241 auto size-- 65535DDR cs0 size: 2048MB
888 08:42:09.097329 DDR cs1 size: 2048MB
889 08:42:09.097782 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
890 08:42:09.103003 cs0 DataBus test pass
891 08:42:09.103456 cs1 DataBus test pass
892 08:42:09.103844 cs0 AddrBus test pass
893 08:42:09.108526 cs1 AddrBus test pass
894 08:42:09.108977
895 08:42:09.109366 100bdlr_step_size ps== 420
896 08:42:09.109760 result report
897 08:42:09.114127 boot times 0Enable ddr reg access
898 08:42:09.121745 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
899 08:42:09.135205 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
900 08:42:09.708900 0.0;M3 CHK:0;cm4_sp_mode 0
901 08:42:09.709422 MVN_1=0x00000000
902 08:42:09.714394 MVN_2=0x00000000
903 08:42:09.720208 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
904 08:42:09.720700 OPS=0x10
905 08:42:09.721125 ring efuse init
906 08:42:09.721530 chipver efuse init
907 08:42:09.725763 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
908 08:42:09.731362 [0.018961 Inits done]
909 08:42:09.731820 secure task start!
910 08:42:09.732273 high task start!
911 08:42:09.736089 low task start!
912 08:42:09.736554 run into bl31
913 08:42:09.742619 NOTICE: BL31: v1.3(release):4fc40b1
914 08:42:09.750430 NOTICE: BL31: Built : 15:58:17, May 22 2019
915 08:42:09.750903 NOTICE: BL31: G12A normal boot!
916 08:42:09.775754 NOTICE: BL31: BL33 decompress pass
917 08:42:09.781561 ERROR: Error initializing runtime service opteed_fast
918 08:42:11.014325
919 08:42:11.014832
920 08:42:11.022818 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
921 08:42:11.023299
922 08:42:11.023712 Model: Libre Computer AML-A311D-CC Alta
923 08:42:11.231152 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
924 08:42:11.254600 DRAM: 2 GiB (effective 3.8 GiB)
925 08:42:11.397562 Core: 408 devices, 31 uclasses, devicetree: separate
926 08:42:11.403447 WDT: Not starting watchdog@f0d0
927 08:42:11.435728 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
928 08:42:11.448196 Loading Environment from FAT... Card did not respond to voltage select! : -110
929 08:42:11.453293 ** Bad device specification mmc 0 **
930 08:42:11.463478 Card did not respond to voltage select! : -110
931 08:42:11.471129 ** Bad device specification mmc 0 **
932 08:42:11.471600 Couldn't find partition mmc 0
933 08:42:11.479499 Card did not respond to voltage select! : -110
934 08:42:11.484980 ** Bad device specification mmc 0 **
935 08:42:11.485448 Couldn't find partition mmc 0
936 08:42:11.490073 Error: could not access storage.
937 08:42:11.833522 Net: eth0: ethernet@ff3f0000
938 08:42:11.834004 starting USB...
939 08:42:12.085380 Bus usb@ff500000: Register 3000140 NbrPorts 3
940 08:42:12.085844 Starting the controller
941 08:42:12.092398 USB XHCI 1.10
942 08:42:13.646391 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
943 08:42:13.654753 scanning usb for storage devices... 0 Storage Device(s) found
945 08:42:13.706352 Hit any key to stop autoboot: 1
946 08:42:13.707168 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
947 08:42:13.707923 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
948 08:42:13.708461 Setting prompt string to ['=>']
949 08:42:13.708955 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
950 08:42:13.722189 0
951 08:42:13.723085 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
952 08:42:13.723589 Sending with 10 millisecond of delay
954 08:42:14.858087 => setenv autoload no
955 08:42:14.868870 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
956 08:42:14.873739 setenv autoload no
957 08:42:14.874460 Sending with 10 millisecond of delay
959 08:42:16.670948 => setenv initrd_high 0xffffffff
960 08:42:16.681716 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
961 08:42:16.682569 setenv initrd_high 0xffffffff
962 08:42:16.683280 Sending with 10 millisecond of delay
964 08:42:18.299110 => setenv fdt_high 0xffffffff
965 08:42:18.309789 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
966 08:42:18.310582 setenv fdt_high 0xffffffff
967 08:42:18.311283 Sending with 10 millisecond of delay
969 08:42:18.603054 => dhcp
970 08:42:18.613694 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
971 08:42:18.614474 dhcp
972 08:42:18.614908 Speed: 1000, full duplex
973 08:42:18.615320 BOOTP broadcast 1
974 08:42:18.848827 DHCP client bound to address 192.168.10.240 (235 ms)
975 08:42:18.849552 Sending with 10 millisecond of delay
977 08:42:20.525536 => setenv serverip 192.168.6.2
978 08:42:20.536245 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
979 08:42:20.537087 setenv serverip 192.168.6.2
980 08:42:20.537769 Sending with 10 millisecond of delay
982 08:42:24.260106 => tftpboot 0x01080000 872500/tftp-deploy-f7v6n9i7/kernel/uImage
983 08:42:24.270872 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
984 08:42:24.271692 tftpboot 0x01080000 872500/tftp-deploy-f7v6n9i7/kernel/uImage
985 08:42:24.272197 Speed: 1000, full duplex
986 08:42:24.272617 Using ethernet@ff3f0000 device
987 08:42:24.279737 TFTP from server 192.168.6.2; our IP address is 192.168.10.240; sending through gateway 192.168.8.1
988 08:42:24.287483 Filename '872500/tftp-deploy-f7v6n9i7/kernel/uImage'.
989 08:42:24.287962 Load address: 0x1080000
990 08:43:19.297353 Loading: *T T T T T T T T T T
991 08:43:19.297988 Retry count exceeded; starting again
993 08:43:19.299388 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
996 08:43:19.301330 end: 2.4 uboot-commands (duration 00:01:37) [common]
998 08:43:19.302722 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1000 08:43:19.303727 end: 2 uboot-action (duration 00:01:37) [common]
1002 08:43:19.305244 Cleaning after the job
1003 08:43:19.305773 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/ramdisk
1004 08:43:19.318269 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/kernel
1005 08:43:19.342534 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/dtb
1006 08:43:19.343652 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/nfsrootfs
1007 08:43:19.484128 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/872500/tftp-deploy-f7v6n9i7/modules
1008 08:43:19.502965 start: 4.1 power-off (timeout 00:00:30) [common]
1009 08:43:19.503581 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1010 08:43:19.536559 >> OK - accepted request
1011 08:43:19.538226 Returned 0 in 0 seconds
1012 08:43:19.638910 end: 4.1 power-off (duration 00:00:00) [common]
1014 08:43:19.639802 start: 4.2 read-feedback (timeout 00:10:00) [common]
1015 08:43:19.640484 Listened to connection for namespace 'common' for up to 1s
1016 08:43:20.640446 Finalising connection for namespace 'common'
1017 08:43:20.641083 Disconnecting from shell: Finalise
1018 08:43:20.641591 =>
1019 08:43:20.742501 end: 4.2 read-feedback (duration 00:00:01) [common]
1020 08:43:20.743108 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/872500
1021 08:43:22.423254 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/872500
1022 08:43:22.423860 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.