Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 10:30:19.868346 lava-dispatcher, installed at version: 2024.01
2 10:30:19.869171 start: 0 validate
3 10:30:19.869681 Start time: 2024-10-22 10:30:19.869648+00:00 (UTC)
4 10:30:19.870280 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:30:19.870875 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 10:30:19.913969 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:30:19.914526 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm%2Fmulti_v7_defconfig%2Fclang-17%2Fkernel%2FzImage exists
8 10:30:19.948379 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:30:19.949103 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm%2Fmulti_v7_defconfig%2Fclang-17%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 10:30:19.984466 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:30:19.984980 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 10:30:20.019607 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 10:30:20.020118 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm%2Fmulti_v7_defconfig%2Fclang-17%2Fmodules.tar.xz exists
14 10:30:20.061729 validate duration: 0.19
16 10:30:20.063263 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:30:20.063862 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:30:20.064480 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:30:20.065707 Not decompressing ramdisk as can be used compressed.
20 10:30:20.066587 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 10:30:20.067136 saving as /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/ramdisk/initrd.cpio.gz
22 10:30:20.067694 total size: 4775763 (4 MB)
23 10:30:20.103464 progress 0 % (0 MB)
24 10:30:20.107274 progress 5 % (0 MB)
25 10:30:20.110617 progress 10 % (0 MB)
26 10:30:20.113893 progress 15 % (0 MB)
27 10:30:20.117477 progress 20 % (0 MB)
28 10:30:20.120664 progress 25 % (1 MB)
29 10:30:20.123885 progress 30 % (1 MB)
30 10:30:20.127504 progress 35 % (1 MB)
31 10:30:20.130731 progress 40 % (1 MB)
32 10:30:20.133945 progress 45 % (2 MB)
33 10:30:20.137167 progress 50 % (2 MB)
34 10:30:20.140765 progress 55 % (2 MB)
35 10:30:20.143900 progress 60 % (2 MB)
36 10:30:20.147068 progress 65 % (2 MB)
37 10:30:20.150615 progress 70 % (3 MB)
38 10:30:20.153743 progress 75 % (3 MB)
39 10:30:20.157068 progress 80 % (3 MB)
40 10:30:20.160231 progress 85 % (3 MB)
41 10:30:20.163525 progress 90 % (4 MB)
42 10:30:20.166406 progress 95 % (4 MB)
43 10:30:20.169283 progress 100 % (4 MB)
44 10:30:20.169930 4 MB downloaded in 0.10 s (44.55 MB/s)
45 10:30:20.170469 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:30:20.171368 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:30:20.171673 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:30:20.171955 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:30:20.172463 downloading http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/clang-17/kernel/zImage
51 10:30:20.172718 saving as /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/kernel/zImage
52 10:30:20.172938 total size: 12100096 (11 MB)
53 10:30:20.173157 No compression specified
54 10:30:20.215795 progress 0 % (0 MB)
55 10:30:20.223719 progress 5 % (0 MB)
56 10:30:20.231387 progress 10 % (1 MB)
57 10:30:20.240074 progress 15 % (1 MB)
58 10:30:20.247806 progress 20 % (2 MB)
59 10:30:20.255904 progress 25 % (2 MB)
60 10:30:20.263602 progress 30 % (3 MB)
61 10:30:20.271622 progress 35 % (4 MB)
62 10:30:20.279254 progress 40 % (4 MB)
63 10:30:20.287287 progress 45 % (5 MB)
64 10:30:20.295005 progress 50 % (5 MB)
65 10:30:20.303415 progress 55 % (6 MB)
66 10:30:20.311184 progress 60 % (6 MB)
67 10:30:20.319309 progress 65 % (7 MB)
68 10:30:20.326981 progress 70 % (8 MB)
69 10:30:20.334597 progress 75 % (8 MB)
70 10:30:20.342574 progress 80 % (9 MB)
71 10:30:20.350282 progress 85 % (9 MB)
72 10:30:20.358368 progress 90 % (10 MB)
73 10:30:20.366018 progress 95 % (10 MB)
74 10:30:20.373367 progress 100 % (11 MB)
75 10:30:20.373911 11 MB downloaded in 0.20 s (57.42 MB/s)
76 10:30:20.374393 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:30:20.375236 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:30:20.375529 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:30:20.375807 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:30:20.376296 downloading http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/clang-17/dtbs/ti/omap/am335x-boneblack.dtb
82 10:30:20.376565 saving as /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/dtb/am335x-boneblack.dtb
83 10:30:20.376786 total size: 70544 (0 MB)
84 10:30:20.377008 No compression specified
85 10:30:20.421376 progress 46 % (0 MB)
86 10:30:20.422219 progress 92 % (0 MB)
87 10:30:20.422923 progress 100 % (0 MB)
88 10:30:20.423524 0 MB downloaded in 0.05 s (1.44 MB/s)
89 10:30:20.424460 end: 1.3.1 http-download (duration 00:00:00) [common]
91 10:30:20.425385 end: 1.3 download-retry (duration 00:00:00) [common]
92 10:30:20.425692 start: 1.4 download-retry (timeout 00:10:00) [common]
93 10:30:20.425990 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 10:30:20.426501 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 10:30:20.426772 saving as /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/nfsrootfs/full.rootfs.tar
96 10:30:20.427000 total size: 117747780 (112 MB)
97 10:30:20.427245 Using unxz to decompress xz
98 10:30:20.468930 progress 0 % (0 MB)
99 10:30:21.310818 progress 5 % (5 MB)
100 10:30:22.095091 progress 10 % (11 MB)
101 10:30:22.857525 progress 15 % (16 MB)
102 10:30:23.567185 progress 20 % (22 MB)
103 10:30:24.141663 progress 25 % (28 MB)
104 10:30:24.937360 progress 30 % (33 MB)
105 10:30:25.740454 progress 35 % (39 MB)
106 10:30:26.071670 progress 40 % (44 MB)
107 10:30:26.421111 progress 45 % (50 MB)
108 10:30:27.100914 progress 50 % (56 MB)
109 10:30:27.917005 progress 55 % (61 MB)
110 10:30:28.656988 progress 60 % (67 MB)
111 10:30:29.370231 progress 65 % (73 MB)
112 10:30:30.137389 progress 70 % (78 MB)
113 10:30:30.898124 progress 75 % (84 MB)
114 10:30:31.695551 progress 80 % (89 MB)
115 10:30:32.422114 progress 85 % (95 MB)
116 10:30:33.241316 progress 90 % (101 MB)
117 10:30:34.026461 progress 95 % (106 MB)
118 10:30:34.856020 progress 100 % (112 MB)
119 10:30:34.868375 112 MB downloaded in 14.44 s (7.78 MB/s)
120 10:30:34.869521 end: 1.4.1 http-download (duration 00:00:14) [common]
122 10:30:34.871633 end: 1.4 download-retry (duration 00:00:14) [common]
123 10:30:34.872361 start: 1.5 download-retry (timeout 00:09:45) [common]
124 10:30:34.873040 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 10:30:34.874118 downloading http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/clang-17/modules.tar.xz
126 10:30:34.874726 saving as /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/modules/modules.tar
127 10:30:34.875266 total size: 6920612 (6 MB)
128 10:30:34.875811 Using unxz to decompress xz
129 10:30:34.922020 progress 0 % (0 MB)
130 10:30:34.961659 progress 5 % (0 MB)
131 10:30:35.009794 progress 10 % (0 MB)
132 10:30:35.056774 progress 15 % (1 MB)
133 10:30:35.108360 progress 20 % (1 MB)
134 10:30:35.153853 progress 25 % (1 MB)
135 10:30:35.203959 progress 30 % (2 MB)
136 10:30:35.248281 progress 35 % (2 MB)
137 10:30:35.297253 progress 40 % (2 MB)
138 10:30:35.347035 progress 45 % (3 MB)
139 10:30:35.391814 progress 50 % (3 MB)
140 10:30:35.439893 progress 55 % (3 MB)
141 10:30:35.484291 progress 60 % (3 MB)
142 10:30:35.532431 progress 65 % (4 MB)
143 10:30:35.574131 progress 70 % (4 MB)
144 10:30:35.625008 progress 75 % (4 MB)
145 10:30:35.671381 progress 80 % (5 MB)
146 10:30:35.720228 progress 85 % (5 MB)
147 10:30:35.768691 progress 90 % (5 MB)
148 10:30:35.816336 progress 95 % (6 MB)
149 10:30:35.864058 progress 100 % (6 MB)
150 10:30:35.876312 6 MB downloaded in 1.00 s (6.59 MB/s)
151 10:30:35.876942 end: 1.5.1 http-download (duration 00:00:01) [common]
153 10:30:35.877779 end: 1.5 download-retry (duration 00:00:01) [common]
154 10:30:35.878049 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 10:30:35.878314 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 10:30:54.233424 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/880499/extract-nfsrootfs-p7fkpgfb
157 10:30:54.234042 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
158 10:30:54.234336 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
159 10:30:54.234987 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea
160 10:30:54.235573 makedir: /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin
161 10:30:54.235967 makedir: /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/tests
162 10:30:54.236334 makedir: /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/results
163 10:30:54.236709 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-add-keys
164 10:30:54.237682 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-add-sources
165 10:30:54.238389 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-background-process-start
166 10:30:54.239953 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-background-process-stop
167 10:30:54.240945 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-common-functions
168 10:30:54.241661 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-echo-ipv4
169 10:30:54.242225 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-install-packages
170 10:30:54.242779 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-installed-packages
171 10:30:54.243383 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-os-build
172 10:30:54.244001 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-probe-channel
173 10:30:54.244672 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-probe-ip
174 10:30:54.245443 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-target-ip
175 10:30:54.246007 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-target-mac
176 10:30:54.246573 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-target-storage
177 10:30:54.247447 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-test-case
178 10:30:54.248045 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-test-event
179 10:30:54.248592 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-test-feedback
180 10:30:54.249122 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-test-raise
181 10:30:54.249685 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-test-reference
182 10:30:54.250208 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-test-runner
183 10:30:54.250783 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-test-set
184 10:30:54.251359 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-test-shell
185 10:30:54.251929 Updating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-add-keys (debian)
186 10:30:54.252631 Updating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-add-sources (debian)
187 10:30:54.253200 Updating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-install-packages (debian)
188 10:30:54.253718 Updating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-installed-packages (debian)
189 10:30:54.254222 Updating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/bin/lava-os-build (debian)
190 10:30:54.254665 Creating /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/environment
191 10:30:54.255052 LAVA metadata
192 10:30:54.255336 - LAVA_JOB_ID=880499
193 10:30:54.255560 - LAVA_DISPATCHER_IP=192.168.6.2
194 10:30:54.256008 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
195 10:30:54.257127 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 10:30:54.257506 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
197 10:30:54.257722 skipped lava-vland-overlay
198 10:30:54.257968 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 10:30:54.258232 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
200 10:30:54.258459 skipped lava-multinode-overlay
201 10:30:54.258707 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 10:30:54.258968 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
203 10:30:54.259228 Loading test definitions
204 10:30:54.259518 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
205 10:30:54.259741 Using /lava-880499 at stage 0
206 10:30:54.260992 uuid=880499_1.6.2.4.1 testdef=None
207 10:30:54.261361 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 10:30:54.261640 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
209 10:30:54.264271 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 10:30:54.265307 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
212 10:30:54.268550 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 10:30:54.269870 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
215 10:30:54.272550 runner path: /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/0/tests/0_timesync-off test_uuid 880499_1.6.2.4.1
216 10:30:54.273350 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 10:30:54.274417 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
219 10:30:54.274704 Using /lava-880499 at stage 0
220 10:30:54.275153 Fetching tests from https://github.com/kernelci/test-definitions.git
221 10:30:54.275517 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/0/tests/1_kselftest-dt'
222 10:30:57.807842 Running '/usr/bin/git checkout kernelci.org
223 10:30:58.258712 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 10:30:58.260281 uuid=880499_1.6.2.4.5 testdef=None
225 10:30:58.260670 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 10:30:58.261450 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
228 10:30:58.264431 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 10:30:58.265288 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
231 10:30:58.269173 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 10:30:58.270199 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
234 10:30:58.273973 runner path: /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/0/tests/1_kselftest-dt test_uuid 880499_1.6.2.4.5
235 10:30:58.274281 BOARD='beaglebone-black'
236 10:30:58.274487 BRANCH='next'
237 10:30:58.274685 SKIPFILE='/dev/null'
238 10:30:58.274882 SKIP_INSTALL='True'
239 10:30:58.275077 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz'
240 10:30:58.275275 TST_CASENAME=''
241 10:30:58.275469 TST_CMDFILES='dt'
242 10:30:58.276058 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 10:30:58.276863 Creating lava-test-runner.conf files
245 10:30:58.277070 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/880499/lava-overlay-y93zemea/lava-880499/0 for stage 0
246 10:30:58.277432 - 0_timesync-off
247 10:30:58.277677 - 1_kselftest-dt
248 10:30:58.278013 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 10:30:58.278295 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
250 10:31:21.788211 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 10:31:21.788665 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
252 10:31:21.788962 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 10:31:21.789274 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 10:31:21.789571 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
255 10:31:22.170447 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 10:31:22.170930 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
257 10:31:22.171200 extracting modules file /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/modules/modules.tar to /var/lib/lava/dispatcher/tmp/880499/extract-nfsrootfs-p7fkpgfb
258 10:31:23.086591 extracting modules file /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/modules/modules.tar to /var/lib/lava/dispatcher/tmp/880499/extract-overlay-ramdisk-2enesqel/ramdisk
259 10:31:24.055113 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 10:31:24.055606 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
261 10:31:24.055896 [common] Applying overlay to NFS
262 10:31:24.056149 [common] Applying overlay /var/lib/lava/dispatcher/tmp/880499/compress-overlay-ov5ejy7k/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/880499/extract-nfsrootfs-p7fkpgfb
263 10:31:26.804092 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 10:31:26.804558 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
265 10:31:26.804833 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
266 10:31:26.805105 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 10:31:26.805355 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 10:31:26.805607 start: 1.6.7 configure-preseed-file (timeout 00:08:53) [common]
269 10:31:26.805854 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 10:31:26.806108 start: 1.6.8 compress-ramdisk (timeout 00:08:53) [common]
271 10:31:26.806353 Building ramdisk /var/lib/lava/dispatcher/tmp/880499/extract-overlay-ramdisk-2enesqel/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/880499/extract-overlay-ramdisk-2enesqel/ramdisk
272 10:31:27.933127 >> 79249 blocks
273 10:31:32.948783 Adding RAMdisk u-boot header.
274 10:31:32.949254 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/880499/extract-overlay-ramdisk-2enesqel/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/880499/extract-overlay-ramdisk-2enesqel/ramdisk.cpio.gz.uboot
275 10:31:33.113691 output: Image Name:
276 10:31:33.114118 output: Created: Tue Oct 22 10:31:32 2024
277 10:31:33.114329 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 10:31:33.114535 output: Data Size: 15370148 Bytes = 15009.91 KiB = 14.66 MiB
279 10:31:33.114738 output: Load Address: 00000000
280 10:31:33.114937 output: Entry Point: 00000000
281 10:31:33.115135 output:
282 10:31:33.115730 rename /var/lib/lava/dispatcher/tmp/880499/extract-overlay-ramdisk-2enesqel/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/ramdisk/ramdisk.cpio.gz.uboot
283 10:31:33.116328 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 10:31:33.116939 end: 1.6 prepare-tftp-overlay (duration 00:00:57) [common]
285 10:31:33.117538 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:47) [common]
286 10:31:33.118052 No LXC device requested
287 10:31:33.118599 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 10:31:33.119152 start: 1.8 deploy-device-env (timeout 00:08:47) [common]
289 10:31:33.119690 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 10:31:33.120171 Checking files for TFTP limit of 4294967296 bytes.
291 10:31:33.123158 end: 1 tftp-deploy (duration 00:01:13) [common]
292 10:31:33.123786 start: 2 uboot-action (timeout 00:05:00) [common]
293 10:31:33.124401 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 10:31:33.124947 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 10:31:33.125497 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 10:31:33.126311 substitutions:
297 10:31:33.126764 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 10:31:33.127203 - {DTB_ADDR}: 0x88000000
299 10:31:33.127641 - {DTB}: 880499/tftp-deploy-v4sag_ox/dtb/am335x-boneblack.dtb
300 10:31:33.128106 - {INITRD}: 880499/tftp-deploy-v4sag_ox/ramdisk/ramdisk.cpio.gz.uboot
301 10:31:33.128544 - {KERNEL_ADDR}: 0x82000000
302 10:31:33.128971 - {KERNEL}: 880499/tftp-deploy-v4sag_ox/kernel/zImage
303 10:31:33.129402 - {LAVA_MAC}: None
304 10:31:33.129872 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/880499/extract-nfsrootfs-p7fkpgfb
305 10:31:33.130310 - {NFS_SERVER_IP}: 192.168.6.2
306 10:31:33.130740 - {PRESEED_CONFIG}: None
307 10:31:33.131169 - {PRESEED_LOCAL}: None
308 10:31:33.131597 - {RAMDISK_ADDR}: 0x83000000
309 10:31:33.132051 - {RAMDISK}: 880499/tftp-deploy-v4sag_ox/ramdisk/ramdisk.cpio.gz.uboot
310 10:31:33.132489 - {ROOT_PART}: None
311 10:31:33.132914 - {ROOT}: None
312 10:31:33.133338 - {SERVER_IP}: 192.168.6.2
313 10:31:33.133759 - {TEE_ADDR}: 0x83000000
314 10:31:33.134179 - {TEE}: None
315 10:31:33.134601 Parsed boot commands:
316 10:31:33.135009 - setenv autoload no
317 10:31:33.135429 - setenv initrd_high 0xffffffff
318 10:31:33.135851 - setenv fdt_high 0xffffffff
319 10:31:33.136303 - dhcp
320 10:31:33.136723 - setenv serverip 192.168.6.2
321 10:31:33.137143 - tftp 0x82000000 880499/tftp-deploy-v4sag_ox/kernel/zImage
322 10:31:33.137565 - tftp 0x83000000 880499/tftp-deploy-v4sag_ox/ramdisk/ramdisk.cpio.gz.uboot
323 10:31:33.137986 - setenv initrd_size ${filesize}
324 10:31:33.138405 - tftp 0x88000000 880499/tftp-deploy-v4sag_ox/dtb/am335x-boneblack.dtb
325 10:31:33.138826 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/880499/extract-nfsrootfs-p7fkpgfb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 10:31:33.139259 - bootz 0x82000000 0x83000000 0x88000000
327 10:31:33.139791 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 10:31:33.141437 start: 2.3 connect-device (timeout 00:05:00) [common]
330 10:31:33.141892 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 10:31:33.158397 Setting prompt string to ['lava-test: # ']
332 10:31:33.160121 end: 2.3 connect-device (duration 00:00:00) [common]
333 10:31:33.160809 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 10:31:33.161414 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 10:31:33.162007 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 10:31:33.163328 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 10:31:33.197799 >> OK - accepted request
338 10:31:33.199718 Returned 0 in 0 seconds
339 10:31:33.301050 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 10:31:33.302969 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 10:31:33.303588 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 10:31:33.304216 Setting prompt string to ['Hit any key to stop autoboot']
344 10:31:33.304724 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 10:31:33.306538 Trying 192.168.56.21...
346 10:31:33.307074 Connected to conserv1.
347 10:31:33.307521 Escape character is '^]'.
348 10:31:33.307967
349 10:31:33.308486 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 10:31:33.308966
351 10:31:41.230673
352 10:31:41.231365 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 10:31:41.235649 Trying to boot from MMC1
354 10:31:41.808460
355 10:31:41.809103
356 10:31:41.809530 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 10:31:41.809943
358 10:31:41.813659 CPU : AM335X-GP rev 2.1
359 10:31:41.814158 Model: TI AM335x BeagleBone Black
360 10:31:41.817873 DRAM: 512 MiB
361 10:31:41.900669 Core: 160 devices, 18 uclasses, devicetree: separate
362 10:31:41.910177 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 10:31:45.286705 7[r[999;999H[6n8NAND:
364 10:31:45.287364 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 10:31:45.291841 Trying to boot from MMC1
366 10:31:45.864926
367 10:31:45.865538
368 10:31:45.865970 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 10:31:45.866393
370 10:31:45.870253 CPU : AM335X-GP rev 2.1
371 10:31:45.870748 Model: TI AM335x BeagleBone Black
372 10:31:45.874345 DRAM: 512 MiB
373 10:31:45.957224 Core: 160 devices, 18 uclasses, devicetree: separate
374 10:31:45.966857 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 10:31:47.987616 7[r[999;999H[6n8NAND:
376 10:31:47.988093 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 10:31:47.992855 Trying to boot from MMC1
378 10:31:48.564953
379 10:31:48.565421
380 10:31:48.565719 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 10:31:48.565995
382 10:31:48.570630 CPU : AM335X-GP rev 2.1
383 10:31:48.571058 Model: TI AM335x BeagleBone Black
384 10:31:48.574751 DRAM: 512 MiB
385 10:31:48.660260 Core: 160 devices, 18 uclasses, devicetree: separate
386 10:31:48.667322 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 10:31:49.172237 7[r[999;999H[6n8NAND: 0 MiB
388 10:31:49.182551 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 10:31:49.255313 Loading Environment from FAT... Unable to use mmc 0:1...
390 10:31:49.276526 <ethaddr> not set. Validating first E-fuse MAC
391 10:31:49.306940 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 10:31:49.365590 Hit any key to stop autoboot: 2
394 10:31:49.366535 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 10:31:49.367128 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 10:31:49.367604 Setting prompt string to ['=>']
397 10:31:49.368132 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 10:31:49.375569 0
399 10:31:49.376471 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 10:31:49.376959 Sending with 10 millisecond of delay
402 10:31:50.513338 => setenv autoload no
403 10:31:50.524160 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 10:31:50.529058 setenv autoload no
405 10:31:50.529781 Sending with 10 millisecond of delay
407 10:31:52.326815 => setenv initrd_high 0xffffffff
408 10:31:52.337597 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 10:31:52.338439 setenv initrd_high 0xffffffff
410 10:31:52.339145 Sending with 10 millisecond of delay
412 10:31:53.955832 => setenv fdt_high 0xffffffff
413 10:31:53.966674 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 10:31:53.967481 setenv fdt_high 0xffffffff
415 10:31:53.968188 Sending with 10 millisecond of delay
417 10:31:54.260047 => dhcp
418 10:31:54.270820 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 10:31:54.271621 dhcp
420 10:31:54.273486 link up on port 0, speed 100, full duplex
421 10:31:54.273928 BOOTP broadcast 1
422 10:31:54.297321 DHCP client bound to address 192.168.6.12 (20 ms)
423 10:31:54.298076 Sending with 10 millisecond of delay
425 10:31:55.974880 => setenv serverip 192.168.6.2
426 10:31:55.985450 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 10:31:55.986055 setenv serverip 192.168.6.2
428 10:31:55.986506 Sending with 10 millisecond of delay
430 10:31:59.469295 => tftp 0x82000000 880499/tftp-deploy-v4sag_ox/kernel/zImage
431 10:31:59.480073 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 10:31:59.480676 tftp 0x82000000 880499/tftp-deploy-v4sag_ox/kernel/zImage
433 10:31:59.480965 link up on port 0, speed 100, full duplex
434 10:31:59.484708 Using ethernet@4a100000 device
435 10:31:59.490081 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 10:31:59.497454 Filename '880499/tftp-deploy-v4sag_ox/kernel/zImage'.
437 10:31:59.497787 Load address: 0x82000000
438 10:32:02.070805 Loading: *################################################## 11.5 MiB
439 10:32:02.071247 4.5 MiB/s
440 10:32:02.071471 done
441 10:32:02.074827 Bytes transferred = 12100096 (b8a200 hex)
442 10:32:02.075414 Sending with 10 millisecond of delay
444 10:32:06.520849 => tftp 0x83000000 880499/tftp-deploy-v4sag_ox/ramdisk/ramdisk.cpio.gz.uboot
445 10:32:06.531885 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 10:32:06.533028 tftp 0x83000000 880499/tftp-deploy-v4sag_ox/ramdisk/ramdisk.cpio.gz.uboot
447 10:32:06.533631 link up on port 0, speed 100, full duplex
448 10:32:06.536622 Using ethernet@4a100000 device
449 10:32:06.542210 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 10:32:06.550235 Filename '880499/tftp-deploy-v4sag_ox/ramdisk/ramdisk.cpio.gz.uboot'.
451 10:32:06.550872 Load address: 0x83000000
452 10:32:09.380048 Loading: *################################################## 14.7 MiB
453 10:32:09.380478 5.2 MiB/s
454 10:32:09.380718 done
455 10:32:09.384136 Bytes transferred = 15370212 (ea87e4 hex)
456 10:32:09.384694 Sending with 10 millisecond of delay
458 10:32:11.241923 => setenv initrd_size ${filesize}
459 10:32:11.252476 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 10:32:11.253003 setenv initrd_size ${filesize}
461 10:32:11.253482 Sending with 10 millisecond of delay
463 10:32:15.398921 => tftp 0x88000000 880499/tftp-deploy-v4sag_ox/dtb/am335x-boneblack.dtb
464 10:32:15.409918 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 10:32:15.411044 tftp 0x88000000 880499/tftp-deploy-v4sag_ox/dtb/am335x-boneblack.dtb
466 10:32:15.411598 link up on port 0, speed 100, full duplex
467 10:32:15.415028 Using ethernet@4a100000 device
468 10:32:15.420443 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 10:32:15.428474 Filename '880499/tftp-deploy-v4sag_ox/dtb/am335x-boneblack.dtb'.
470 10:32:15.429052 Load address: 0x88000000
471 10:32:15.461687 Loading: *################################################## 68.9 KiB
472 10:32:15.462367 2 MiB/s
473 10:32:15.469408 done
474 10:32:15.469967 Bytes transferred = 70544 (11390 hex)
475 10:32:15.470783 Sending with 10 millisecond of delay
477 10:32:28.655902 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/880499/extract-nfsrootfs-p7fkpgfb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 10:32:28.666792 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
479 10:32:28.667743 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/880499/extract-nfsrootfs-p7fkpgfb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 10:32:28.668656 Sending with 10 millisecond of delay
482 10:32:31.008385 => bootz 0x82000000 0x83000000 0x88000000
483 10:32:31.018958 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 10:32:31.019519 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 10:32:31.020292 bootz 0x82000000 0x83000000 0x88000000
486 10:32:31.020559 Kernel image @ 0x82000000 [ 0x000000 - 0xb8a200 ]
487 10:32:31.021105 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 10:32:31.026684 Image Name:
489 10:32:31.027187 Created: 2024-10-22 10:31:32 UTC
490 10:32:31.030057 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 10:32:31.052288 Data Size: 15370148 Bytes = 14.7 MiB
492 10:32:31.052803 Load Address: 00000000
493 10:32:31.053223 Entry Point: 00000000
494 10:32:31.218896 Verifying Checksum ... OK
495 10:32:31.219665 ## Flattened Device Tree blob at 88000000
496 10:32:31.225388 Booting using the fdt blob at 0x88000000
497 10:32:31.230254 Using Device Tree in place at 88000000, end 8801438f
498 10:32:31.243859
499 10:32:31.244674 Starting kernel ...
500 10:32:31.245254
501 10:32:31.246477 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 10:32:31.247299 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 10:32:31.247929 Setting prompt string to ['Linux version [0-9]']
504 10:32:31.248583 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 10:32:31.249211 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 10:32:32.161517 [ 0.000000] Booting Linux on physical CPU 0x0
507 10:32:32.167415 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 10:32:32.168263 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 10:32:32.168894 Setting prompt string to []
510 10:32:32.169543 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 10:32:32.170435 Using line separator: #'\n'#
512 10:32:32.171043 No login prompt set.
513 10:32:32.171630 Parsing kernel messages
514 10:32:32.172195 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 10:32:32.173256 [login-action] Waiting for messages, (timeout 00:04:01)
516 10:32:32.174107 Waiting using forced prompt support (timeout 00:02:00)
517 10:32:32.187163 [ 0.000000] Linux version 6.12.0-rc4-next-20241022 (KernelCI@build-j351007-arm-clang-17-multi-v7-defconfig-rvc6v) (Debian clang version 17.0.6 (++20231208085813+6009708b4367-1~exp1~20231208085906.81), Debian LLD 17.0.6) #1 SMP Tue Oct 22 09:31:45 UTC 2024
518 10:32:32.192969 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 10:32:32.198593 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 10:32:32.204421 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 10:32:32.215868 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 10:32:32.216496 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 10:32:32.221530 [ 0.000000] Memory policy: Data cache writeback
524 10:32:32.228528 [ 0.000000] efi: UEFI not found.
525 10:32:32.237120 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 10:32:32.237830 [ 0.000000] Zone ranges:
527 10:32:32.242728 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 10:32:32.248623 [ 0.000000] Normal empty
529 10:32:32.249341 [ 0.000000] HighMem empty
530 10:32:32.254559 [ 0.000000] Movable zone start for each node
531 10:32:32.260012 [ 0.000000] Early memory node ranges
532 10:32:32.265747 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 10:32:32.272977 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 10:32:32.285834 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
535 10:32:32.299451 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 10:32:32.304912 [ 0.000000] AM335X ES2.1 (sgx neon)
537 10:32:32.316790 [ 0.000000] percpu: Embedded 17 pages/cpu s40396 r8192 d21044 u69632
538 10:32:32.337149 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/880499/extract-nfsrootfs-p7fkpgfb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 10:32:32.343152 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
540 10:32:32.351389 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
541 10:32:32.362727 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
542 10:32:32.368475 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
543 10:32:32.375219 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
544 10:32:32.404536 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
545 10:32:32.410533 <6>[ 0.000000] trace event string verifier disabled
546 10:32:32.411065 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
547 10:32:32.416355 <6>[ 0.000000] rcu: RCU event tracing is enabled.
548 10:32:32.427669 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
549 10:32:32.428305 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
550 10:32:32.439143 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
551 10:32:32.444987 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
552 10:32:32.455863 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
553 10:32:32.470943 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
554 10:32:32.489362 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
555 10:32:32.496082 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
556 10:32:32.599932 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
557 10:32:32.608395 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
558 10:32:32.621455 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
559 10:32:32.629296 <6>[ 0.019245] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
560 10:32:32.639054 <6>[ 0.034519] Console: colour dummy device 80x30
561 10:32:32.645134 Matched prompt #6: WARNING:
562 10:32:32.645618 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
563 10:32:32.650520 <3>[ 0.039418] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
564 10:32:32.656295 <3>[ 0.046493] This ensures that you still see kernel messages. Please
565 10:32:32.659562 <3>[ 0.053221] update your kernel commandline.
566 10:32:32.699671 <6>[ 0.057828] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
567 10:32:32.705463 <6>[ 0.096252] CPU: Testing write buffer coherency: ok
568 10:32:32.711400 <6>[ 0.101614] CPU0: Spectre v2: using BPIALL workaround
569 10:32:32.711947 <6>[ 0.107083] pid_max: default: 32768 minimum: 301
570 10:32:32.722793 <6>[ 0.112281] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
571 10:32:32.729740 <6>[ 0.120111] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
572 10:32:32.736823 <6>[ 0.129481] CPU0: thread -1, cpu 0, socket -1, mpidr 0
573 10:32:32.745481 <6>[ 0.136570] Setting up static identity map for 0x80300000 - 0x803000ac
574 10:32:32.751401 <6>[ 0.146393] rcu: Hierarchical SRCU implementation.
575 10:32:32.758886 <6>[ 0.151675] rcu: Max phase no-delay instances is 1000.
576 10:32:32.767717 <6>[ 0.163196] EFI services will not be available.
577 10:32:32.773545 <6>[ 0.168475] smp: Bringing up secondary CPUs ...
578 10:32:32.779234 <6>[ 0.173530] smp: Brought up 1 node, 1 CPU
579 10:32:32.787538 <6>[ 0.177930] SMP: Total of 1 processors activated (996.14 BogoMIPS).
580 10:32:32.794741 <6>[ 0.184702] CPU: All CPU(s) started in SVC mode.
581 10:32:32.805703 <6>[ 0.189900] Memory: 404416K/522240K available (17408K kernel code, 2535K rwdata, 6716K rodata, 2048K init, 428K bss, 50628K reserved, 65536K cma-reserved, 0K highmem)
582 10:32:32.811475 <6>[ 0.206192] devtmpfs: initialized
583 10:32:32.834440 <6>[ 0.223990] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
584 10:32:32.845912 <6>[ 0.232580] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
585 10:32:32.851844 <6>[ 0.243026] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
586 10:32:32.862616 <6>[ 0.255384] pinctrl core: initialized pinctrl subsystem
587 10:32:32.872396 <6>[ 0.266387] DMI not present or invalid.
588 10:32:32.880695 <6>[ 0.272276] NET: Registered PF_NETLINK/PF_ROUTE protocol family
589 10:32:32.890190 <6>[ 0.281256] DMA: preallocated 256 KiB pool for atomic coherent allocations
590 10:32:32.905494 <6>[ 0.292934] thermal_sys: Registered thermal governor 'step_wise'
591 10:32:32.906037 <6>[ 0.293118] cpuidle: using governor menu
592 10:32:32.928072 <6>[ 0.323703] No ATAGs?
593 10:32:32.934317 <6>[ 0.326346] hw-breakpoint: debug architecture 0x4 unsupported.
594 10:32:32.944707 <6>[ 0.338555] Serial: AMBA PL011 UART driver
595 10:32:32.980285 <6>[ 0.375731] iommu: Default domain type: Translated
596 10:32:32.989468 <6>[ 0.381081] iommu: DMA domain TLB invalidation policy: strict mode
597 10:32:33.016871 <5>[ 0.410989] SCSI subsystem initialized
598 10:32:33.030205 <6>[ 0.420123] usbcore: registered new interface driver usbfs
599 10:32:33.037309 <6>[ 0.426082] usbcore: registered new interface driver hub
600 10:32:33.037949 <6>[ 0.431910] usbcore: registered new device driver usb
601 10:32:33.042971 <6>[ 0.438465] pps_core: LinuxPPS API ver. 1 registered
602 10:32:33.054465 <6>[ 0.443901] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
603 10:32:33.063266 <6>[ 0.453625] PTP clock support registered
604 10:32:33.063828 <6>[ 0.458078] EDAC MC: Ver: 3.0.0
605 10:32:33.108839 <6>[ 0.501881] scmi_core: SCMI protocol bus registered
606 10:32:33.123110 <6>[ 0.518408] vgaarb: loaded
607 10:32:33.134865 <6>[ 0.530560] clocksource: Switched to clocksource dmtimer
608 10:32:33.176141 <6>[ 0.571392] NET: Registered PF_INET protocol family
609 10:32:33.188821 <6>[ 0.577000] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
610 10:32:33.194636 <6>[ 0.586052] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
611 10:32:33.206148 <6>[ 0.594995] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
612 10:32:33.211861 <6>[ 0.603258] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
613 10:32:33.223533 <6>[ 0.611550] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
614 10:32:33.229495 <6>[ 0.619251] TCP: Hash tables configured (established 4096 bind 4096)
615 10:32:33.235036 <6>[ 0.626178] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
616 10:32:33.240948 <6>[ 0.633212] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
617 10:32:33.248546 <6>[ 0.640820] NET: Registered PF_UNIX/PF_LOCAL protocol family
618 10:32:33.329493 <6>[ 0.719400] RPC: Registered named UNIX socket transport module.
619 10:32:33.330154 <6>[ 0.725850] RPC: Registered udp transport module.
620 10:32:33.335217 <6>[ 0.730977] RPC: Registered tcp transport module.
621 10:32:33.340912 <6>[ 0.736080] RPC: Registered tcp-with-tls transport module.
622 10:32:33.354198 <6>[ 0.742004] RPC: Registered tcp NFSv4.1 backchannel transport module.
623 10:32:33.354627 <6>[ 0.748912] PCI: CLS 0 bytes, default 64
624 10:32:33.361749 <5>[ 0.754771] Initialise system trusted keyrings
625 10:32:33.379609 <6>[ 0.772145] Trying to unpack rootfs image as initramfs...
626 10:32:33.451669 <6>[ 0.840990] workingset: timestamp_bits=30 max_order=17 bucket_order=0
627 10:32:33.456540 <6>[ 0.848511] squashfs: version 4.0 (2009/01/31) Phillip Lougher
628 10:32:33.502334 <5>[ 0.897790] NFS: Registering the id_resolver key type
629 10:32:33.508115 <5>[ 0.903471] Key type id_resolver registered
630 10:32:33.513878 <5>[ 0.908054] Key type id_legacy registered
631 10:32:33.519559 <6>[ 0.912522] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
632 10:32:33.529095 <6>[ 0.919687] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
633 10:32:33.595369 <5>[ 0.990972] Key type asymmetric registered
634 10:32:33.601164 <5>[ 0.995497] Asymmetric key parser 'x509' registered
635 10:32:33.609620 <6>[ 1.000974] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
636 10:32:33.615531 <6>[ 1.008862] io scheduler mq-deadline registered
637 10:32:33.624253 <6>[ 1.013823] io scheduler kyber registered
638 10:32:33.624897 <6>[ 1.018274] io scheduler bfq registered
639 10:32:33.729238 <6>[ 1.121045] ledtrig-cpu: registered to indicate activity on CPUs
640 10:32:34.089377 <6>[ 1.481047] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
641 10:32:34.120135 <6>[ 1.515553] msm_serial: driver initialized
642 10:32:34.126261 <6>[ 1.520347] SuperH (H)SCI(F) driver initialized
643 10:32:34.132211 <6>[ 1.525691] STMicroelectronics ASC driver initialized
644 10:32:34.137411 <6>[ 1.531365] STM32 USART driver initialized
645 10:32:34.267809 <6>[ 1.662812] brd: module loaded
646 10:32:34.307837 <6>[ 1.702819] loop: module loaded
647 10:32:34.354208 <6>[ 1.748908] CAN device driver interface
648 10:32:34.360966 <6>[ 1.754270] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
649 10:32:34.366785 <6>[ 1.761396] e1000e: Intel(R) PRO/1000 Network Driver
650 10:32:34.372511 <6>[ 1.766784] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
651 10:32:34.378499 <6>[ 1.773271] igb: Intel(R) Gigabit Ethernet Network Driver
652 10:32:34.386999 <6>[ 1.779094] igb: Copyright (c) 2007-2014 Intel Corporation.
653 10:32:34.398572 <6>[ 1.788626] pegasus: Pegasus/Pegasus II USB Ethernet driver
654 10:32:34.404710 <6>[ 1.794793] usbcore: registered new interface driver pegasus
655 10:32:34.410332 <6>[ 1.800965] usbcore: registered new interface driver asix
656 10:32:34.416203 <6>[ 1.806816] usbcore: registered new interface driver ax88179_178a
657 10:32:34.421803 <6>[ 1.813410] usbcore: registered new interface driver cdc_ether
658 10:32:34.427761 <6>[ 1.819712] usbcore: registered new interface driver smsc75xx
659 10:32:34.433356 <6>[ 1.825951] usbcore: registered new interface driver smsc95xx
660 10:32:34.439238 <6>[ 1.832183] usbcore: registered new interface driver net1080
661 10:32:34.444937 <6>[ 1.838303] usbcore: registered new interface driver cdc_subset
662 10:32:34.450706 <6>[ 1.844711] usbcore: registered new interface driver zaurus
663 10:32:34.458376 <6>[ 1.850777] usbcore: registered new interface driver cdc_ncm
664 10:32:34.468641 <6>[ 1.860627] usbcore: registered new interface driver usb-storage
665 10:32:34.759009 <6>[ 2.152810] i2c_dev: i2c /dev entries driver
666 10:32:34.815662 <5>[ 2.203250] cpuidle: enable-method property 'ti,am3352' found operations
667 10:32:34.821347 <6>[ 2.212896] sdhci: Secure Digital Host Controller Interface driver
668 10:32:34.829030 <6>[ 2.219554] sdhci: Copyright(c) Pierre Ossman
669 10:32:34.836645 <6>[ 2.226200] Synopsys Designware Multimedia Card Interface Driver
670 10:32:34.841891 <6>[ 2.234314] sdhci-pltfm: SDHCI platform and OF driver helper
671 10:32:34.964393 <6>[ 2.352592] usbcore: registered new interface driver usbhid
672 10:32:34.964834 <6>[ 2.358633] usbhid: USB HID core driver
673 10:32:35.014565 <6>[ 2.407603] NET: Registered PF_INET6 protocol family
674 10:32:35.055818 <6>[ 2.451615] Segment Routing with IPv6
675 10:32:35.061728 <6>[ 2.455763] In-situ OAM (IOAM) with IPv6
676 10:32:35.068575 <6>[ 2.460163] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
677 10:32:35.075933 <6>[ 2.467626] NET: Registered PF_PACKET protocol family
678 10:32:35.081835 <6>[ 2.473197] can: controller area network core
679 10:32:35.082342 <6>[ 2.478027] NET: Registered PF_CAN protocol family
680 10:32:35.087567 <6>[ 2.483254] can: raw protocol
681 10:32:35.093324 <6>[ 2.486584] can: broadcast manager protocol
682 10:32:35.100340 <6>[ 2.491182] can: netlink gateway - max_hops=1
683 10:32:35.100829 <5>[ 2.496716] Key type dns_resolver registered
684 10:32:35.105989 <6>[ 2.501782] ThumbEE CPU extension supported.
685 10:32:35.112440 <5>[ 2.506469] Registering SWP/SWPB emulation handler
686 10:32:35.120653 <3>[ 2.512169] omap_voltage_late_init: Voltage driver support not added
687 10:32:35.318088 <5>[ 2.711231] Loading compiled-in X.509 certificates
688 10:32:35.440669 <6>[ 2.823311] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
689 10:32:35.447944 <6>[ 2.840024] pinctrl-single 44e10800.pinmux: 142 pins, size 568
690 10:32:35.474747 <3>[ 2.864353] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
691 10:32:35.663573 <3>[ 3.053162] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
692 10:32:35.797371 <6>[ 3.191387] OMAP GPIO hardware version 0.1
693 10:32:35.818376 <6>[ 3.210446] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
694 10:32:35.880664 <4>[ 3.272296] at24 2-0054: supply vcc not found, using dummy regulator
695 10:32:35.914246 <4>[ 3.305947] at24 2-0055: supply vcc not found, using dummy regulator
696 10:32:35.952758 <4>[ 3.344454] at24 2-0056: supply vcc not found, using dummy regulator
697 10:32:35.994875 <4>[ 3.386489] at24 2-0057: supply vcc not found, using dummy regulator
698 10:32:36.030997 <6>[ 3.423537] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
699 10:32:36.089002 <3>[ 3.477471] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
700 10:32:36.113989 <6>[ 3.498633] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
701 10:32:36.136256 <4>[ 3.525088] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
702 10:32:36.144087 <4>[ 3.534383] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
703 10:32:36.250603 <6>[ 3.645852] Freeing initrd memory: 15012K
704 10:32:36.258950 <6>[ 3.650664] omap_rng 48310000.rng: Random Number Generator ver. 20
705 10:32:36.282657 <5>[ 3.677281] random: crng init done
706 10:32:36.330154 <6>[ 3.720580] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
707 10:32:36.377941 <6>[ 3.767317] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
708 10:32:36.383739 <6>[ 3.777682] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
709 10:32:36.395492 <6>[ 3.785049] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
710 10:32:36.401333 <6>[ 3.792578] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
711 10:32:36.412917 <6>[ 3.800715] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
712 10:32:36.420420 <6>[ 3.812353] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
713 10:32:36.433504 <5>[ 3.821526] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
714 10:32:36.461926 <3>[ 3.851991] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
715 10:32:36.467717 <6>[ 3.860460] edma 49000000.dma: TI EDMA DMA engine driver
716 10:32:36.540788 <3>[ 3.930079] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
717 10:32:36.556048 <6>[ 3.944904] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
718 10:32:36.569090 <3>[ 3.962069] l3-aon-clkctrl:0000:0: failed to disable
719 10:32:36.618693 <6>[ 4.008561] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
720 10:32:36.624396 <6>[ 4.018067] printk: legacy console [ttyS0] enabled
721 10:32:36.630013 <6>[ 4.018067] printk: legacy console [ttyS0] enabled
722 10:32:36.635723 <6>[ 4.028410] printk: legacy bootconsole [omap8250] disabled
723 10:32:36.641582 <6>[ 4.028410] printk: legacy bootconsole [omap8250] disabled
724 10:32:36.682363 <4>[ 4.071304] tps65217-pmic: Failed to locate of_node [id: -1]
725 10:32:36.686087 <4>[ 4.078715] tps65217-bl: Failed to locate of_node [id: -1]
726 10:32:36.702816 <6>[ 4.098783] tps65217 0-0024: TPS65217 ID 0xe version 1.2
727 10:32:36.721265 <6>[ 4.105745] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
728 10:32:36.733002 <6>[ 4.119524] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
729 10:32:36.738730 <6>[ 4.131422] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
730 10:32:36.761271 <6>[ 4.151621] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
731 10:32:36.767153 <6>[ 4.160762] sdhci-omap 48060000.mmc: Got CD GPIO
732 10:32:36.775180 <4>[ 4.165882] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
733 10:32:36.789703 <4>[ 4.179402] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
734 10:32:36.796313 <4>[ 4.188059] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
735 10:32:36.806091 <4>[ 4.196808] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
736 10:32:36.930854 <6>[ 4.322241] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
737 10:32:36.977519 <6>[ 4.365028] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
738 10:32:36.983536 <6>[ 4.375980] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
739 10:32:36.993066 <6>[ 4.384902] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
740 10:32:37.044107 <6>[ 4.430648] mmc0: new high speed SDHC card at address 1234
741 10:32:37.044684 <6>[ 4.438014] mmcblk0: mmc0:1234 SA32G 29.1 GiB
742 10:32:37.051120 <6>[ 4.446821] mmcblk0: p1
743 10:32:37.074062 <6>[ 4.461758] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
744 10:32:37.093056 <6>[ 4.479232] mmc1: new high speed MMC card at address 0001
745 10:32:37.093600 <6>[ 4.486828] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
746 10:32:37.101590 <6>[ 4.495020] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
747 10:32:37.109526 <6>[ 4.502737] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
748 10:32:37.115079 <6>[ 4.510256] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
749 10:32:39.201521 <6>[ 6.591618] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
750 10:32:39.274804 <5>[ 6.630666] Sending DHCP requests ., OK
751 10:32:39.286243 <6>[ 6.675083] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
752 10:32:39.286783 <6>[ 6.683211] IP-Config: Complete:
753 10:32:39.300168 <6>[ 6.686749] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
754 10:32:39.305938 <6>[ 6.697293] host=192.168.6.12, domain=, nis-domain=(none)
755 10:32:39.311704 <6>[ 6.703508] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
756 10:32:39.318299 <6>[ 6.703545] nameserver0=10.255.253.1
757 10:32:39.327492 <6>[ 6.716114] clk: Disabling unused clocks
758 10:32:39.328052 <6>[ 6.720918] PM: genpd: Disabling unused power domains
759 10:32:39.345325 <6>[ 6.737890] Freeing unused kernel image (initmem) memory: 2048K
760 10:32:39.352919 <6>[ 6.747770] Run /init as init process
761 10:32:39.376202 Loading, please wait...
762 10:32:39.453665 Starting systemd-udevd version 252.22-1~deb12u1
763 10:32:42.547669 <4>[ 9.936552] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
764 10:32:42.688518 <4>[ 10.077349] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
765 10:32:42.883473 <6>[ 10.279753] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
766 10:32:42.894272 <6>[ 10.285574] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
767 10:32:43.098863 <6>[ 10.493653] hub 1-0:1.0: USB hub found
768 10:32:43.116094 <6>[ 10.510820] hub 1-0:1.0: 1 port detected
769 10:32:43.229494 <6>[ 10.624033] tda998x 0-0070: found TDA19988
770 10:32:46.144377 Begin: Loading essential drivers ... done.
771 10:32:46.149856 Begin: Running /scripts/init-premount ... done.
772 10:32:46.155349 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
773 10:32:46.168592 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
774 10:32:46.169103 Device /sys/class/net/eth0 found
775 10:32:46.169549 done.
776 10:32:46.245929 Begin: Waiting up to 180 secs for any network device to become available ... done.
777 10:32:46.336540 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
778 10:32:46.357795 IP-Config: eth0 guessed broadcast address 192.168.6.255
779 10:32:46.363339 IP-Config: eth0 complete (dhcp from 192.168.6.1):
780 10:32:46.369060 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
781 10:32:46.380169 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
782 10:32:46.380686 rootserver: 192.168.6.1 rootpath:
783 10:32:46.382575 filename :
784 10:32:46.503416 done.
785 10:32:46.512255 Begin: Running /scripts/nfs-bottom ... done.
786 10:32:46.581135 Begin: Running /scripts/init-bottom ... done.
787 10:32:48.145499 <30>[ 15.537754] systemd[1]: System time before build time, advancing clock.
788 10:32:48.361299 <30>[ 15.727359] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
789 10:32:48.370088 <30>[ 15.764069] systemd[1]: Detected architecture arm.
790 10:32:48.382687
791 10:32:48.383196 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
792 10:32:48.383657
793 10:32:48.408479 <30>[ 15.801329] systemd[1]: Hostname set to <debian-bookworm-armhf>.
794 10:32:50.630317 <30>[ 18.022115] systemd[1]: Queued start job for default target graphical.target.
795 10:32:50.647416 <30>[ 18.037036] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
796 10:32:50.654933 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
797 10:32:50.684485 <30>[ 18.076509] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
798 10:32:50.694940 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
799 10:32:50.722557 <30>[ 18.113323] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
800 10:32:50.733051 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
801 10:32:50.765416 <30>[ 18.154419] systemd[1]: Created slice user.slice - User and Session Slice.
802 10:32:50.771173 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
803 10:32:50.797324 <30>[ 18.181823] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
804 10:32:50.802587 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
805 10:32:50.821465 <30>[ 18.211672] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
806 10:32:50.831577 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
807 10:32:50.862492 <30>[ 18.241717] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
808 10:32:50.868986 <30>[ 18.262199] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
809 10:32:50.877473 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
810 10:32:50.900640 <30>[ 18.291073] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
811 10:32:50.908937 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
812 10:32:50.931282 <30>[ 18.321408] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
813 10:32:50.939836 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
814 10:32:50.961277 <30>[ 18.351627] systemd[1]: Reached target paths.target - Path Units.
815 10:32:50.966416 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
816 10:32:50.990847 <30>[ 18.381214] systemd[1]: Reached target remote-fs.target - Remote File Systems.
817 10:32:50.998273 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
818 10:32:51.020871 <30>[ 18.411106] systemd[1]: Reached target slices.target - Slice Units.
819 10:32:51.026230 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
820 10:32:51.052840 <30>[ 18.442591] systemd[1]: Reached target swap.target - Swaps.
821 10:32:51.056907 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
822 10:32:51.081111 <30>[ 18.471262] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
823 10:32:51.089992 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
824 10:32:51.112366 <30>[ 18.502225] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
825 10:32:51.120411 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
826 10:32:51.210215 <30>[ 18.596174] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
827 10:32:51.223719 <30>[ 18.613909] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
828 10:32:51.232195 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
829 10:32:51.254407 <30>[ 18.643466] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
830 10:32:51.261935 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
831 10:32:51.283620 <30>[ 18.673739] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
832 10:32:51.291903 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
833 10:32:51.315349 <30>[ 18.705361] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
834 10:32:51.320904 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
835 10:32:51.353558 <30>[ 18.742321] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
836 10:32:51.361033 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
837 10:32:51.388232 <30>[ 18.772388] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
838 10:32:51.406944 <30>[ 18.790997] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
839 10:32:51.451341 <30>[ 18.842387] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
840 10:32:51.470735 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
841 10:32:51.533068 <30>[ 18.923866] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
842 10:32:51.552056 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
843 10:32:51.613231 <30>[ 19.004156] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
844 10:32:51.651433 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
845 10:32:51.702711 <30>[ 19.093277] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
846 10:32:51.734982 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
847 10:32:51.794130 <30>[ 19.185112] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
848 10:32:51.819244 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
849 10:32:51.871908 <30>[ 19.263374] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
850 10:32:51.897455 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
851 10:32:51.952328 <30>[ 19.342534] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
852 10:32:51.971885 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
853 10:32:52.285769 <30>[ 19.422028] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
854 10:32:52.287104 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
855 10:32:52.287637 <30>[ 19.466921] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
856 10:32:52.288188 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
857 10:32:52.288665 <28>[ 19.522876] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
858 10:32:52.289130 <28>[ 19.537481] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
859 10:32:52.289588 <30>[ 19.581903] systemd[1]: Starting systemd-journald.service - Journal Service...
860 10:32:52.290041 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
861 10:32:52.290504 <30>[ 19.651942] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
862 10:32:52.291058 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
863 10:32:52.342222 <30>[ 19.733423] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
864 10:32:52.403911 Starting [0;1;39msystemd-network-g… units from Kernel command line...
865 10:32:52.462783 <30>[ 19.852594] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
866 10:32:52.502225 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
867 10:32:52.585162 <30>[ 19.975777] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
868 10:32:52.628408 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
869 10:32:52.694419 <30>[ 20.085935] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
870 10:32:52.731752 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
871 10:32:52.771355 <30>[ 20.162798] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
872 10:32:52.808772 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
873 10:32:52.846196 <30>[ 20.236512] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
874 10:32:52.871299 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
875 10:32:53.031286 <30>[ 20.423369] systemd[1]: modprobe@configfs.service: Deactivated successfully.
876 10:32:53.061618 <30>[ 20.452593] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
877 10:32:53.090425 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
878 10:32:53.111222 <30>[ 20.503441] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
879 10:32:53.143071 <30>[ 20.534285] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
880 10:32:53.170484 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
881 10:32:53.191898 <30>[ 20.582425] systemd[1]: Started systemd-journald.service - Journal Service.
882 10:32:53.198748 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
883 10:32:53.232446 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
884 10:32:53.261026 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
885 10:32:53.286195 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
886 10:32:53.325117 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
887 10:32:53.360752 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
888 10:32:53.383090 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
889 10:32:53.413131 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
890 10:32:53.435760 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
891 10:32:53.500917 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
892 10:32:53.543578 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
893 10:32:53.612825 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
894 10:32:53.696108 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
895 10:32:53.779861 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
896 10:32:53.915037 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
897 10:32:54.002026 <46>[ 21.393356] systemd-journald[164]: Received client request to flush runtime journal.
898 10:32:54.081218 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
899 10:32:54.178545 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
900 10:32:54.971591 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
901 10:32:55.047840 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
902 10:32:55.760586 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
903 10:32:55.913020 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
904 10:32:55.932381 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
905 10:32:55.951346 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
906 10:32:56.024456 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
907 10:32:56.088642 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
908 10:32:57.042718 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
909 10:32:57.110223 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
910 10:32:57.263034 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
911 10:32:57.340534 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
912 10:32:57.394217 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
913 10:32:59.328575 [[0m[0;31m* [0m] (1 of 5) Job systemd-timesyncd.service/start running (8s / 1min 36s)
914 10:32:59.455104 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
915 10:33:00.032508 [K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
916 10:33:00.141519 <5>[ 27.534242] cfg80211: Loading compiled-in X.509 certificates for regulatory database
917 10:33:01.046748 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
918 10:33:01.533980 <5>[ 28.929011] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
919 10:33:01.617354 <5>[ 29.007170] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
920 10:33:01.623182 <4>[ 29.016683] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
921 10:33:01.630738 <6>[ 29.025876] cfg80211: failed to load regulatory.db
922 10:33:02.049874 <46>[ 29.432770] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
923 10:33:02.093032 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
924 10:33:02.237431 <46>[ 29.623406] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
925 10:33:02.738187 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
926 10:33:11.279712 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
927 10:33:11.300371 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
928 10:33:11.324929 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
929 10:33:11.357877 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
930 10:33:11.411407 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
931 10:33:11.460846 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
932 10:33:11.522471 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
933 10:33:11.563897 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
934 10:33:11.620955 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
935 10:33:11.645888 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
936 10:33:11.674840 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
937 10:33:11.716802 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
938 10:33:11.743737 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
939 10:33:11.791008 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
940 10:33:11.814601 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
941 10:33:11.847793 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
942 10:33:11.881757 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
943 10:33:11.917554 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
944 10:33:11.941470 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
945 10:33:11.960419 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
946 10:33:11.988244 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
947 10:33:12.010784 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
948 10:33:12.032802 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
949 10:33:12.110118 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
950 10:33:12.154547 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
951 10:33:12.247050 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
952 10:33:12.333443 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
953 10:33:12.430899 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
954 10:33:12.471431 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
955 10:33:12.508685 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
956 10:33:12.722154 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
957 10:33:12.787797 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
958 10:33:12.851367 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
959 10:33:12.870711 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
960 10:33:12.904200 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
961 10:33:13.075038 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
962 10:33:13.490529 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
963 10:33:13.532220 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
964 10:33:13.565745 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
965 10:33:13.650755 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
966 10:33:13.825998 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
967 10:33:13.972263
968 10:33:13.976497 Debian GNU/Linux 12 debian-bookworm-armhfworm-armhf login: root (automatic login)
969 10:33:13.976992
970 10:33:14.350753 Linux debian-bookworm-armhf 6.12.0-rc4-next-20241022 #1 SMP Tue Oct 22 09:31:45 UTC 2024 armv7l
971 10:33:14.351329
972 10:33:14.356393 The programs included with the Debian GNU/Linux system are free software;
973 10:33:14.362113 the exact distribution terms for each program are described in the
974 10:33:14.367520 individual files in /usr/share/doc/*/copyright.
975 10:33:14.368292
976 10:33:14.373189 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
977 10:33:14.376987 permitted by applicable law.
978 10:33:19.086846 Unable to match end of the kernel message
980 10:33:19.088653 Setting prompt string to ['/ #']
981 10:33:19.089295 end: 2.4.4.1 login-action (duration 00:00:47) [common]
983 10:33:19.090856 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
984 10:33:19.091484 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
985 10:33:19.092063 Setting prompt string to ['/ #']
986 10:33:19.092578 Forcing a shell prompt, looking for ['/ #']
988 10:33:19.143647 / #
989 10:33:19.144494 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
990 10:33:19.145055 Waiting using forced prompt support (timeout 00:02:30)
991 10:33:19.149541
992 10:33:19.155932 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
993 10:33:19.156617 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
994 10:33:19.157123 Sending with 10 millisecond of delay
996 10:33:24.147618 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/880499/extract-nfsrootfs-p7fkpgfb'
997 10:33:24.158795 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/880499/extract-nfsrootfs-p7fkpgfb'
998 10:33:24.170965 Sending with 10 millisecond of delay
1000 10:33:26.270199 / # export NFS_SERVER_IP='192.168.6.2'
1001 10:33:26.281198 export NFS_SERVER_IP='192.168.6.2'
1002 10:33:26.282756 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1003 10:33:26.283409 end: 2.4 uboot-commands (duration 00:01:53) [common]
1004 10:33:26.284086 end: 2 uboot-action (duration 00:01:53) [common]
1005 10:33:26.284718 start: 3 lava-test-retry (timeout 00:06:54) [common]
1006 10:33:26.285360 start: 3.1 lava-test-shell (timeout 00:06:54) [common]
1007 10:33:26.286061 Using namespace: common
1009 10:33:26.387386 / # #
1010 10:33:26.388230 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1011 10:33:26.392887 #
1012 10:33:26.398794 Using /lava-880499
1014 10:33:26.499968 / # export SHELL=/bin/bash
1015 10:33:26.505595 export SHELL=/bin/bash
1017 10:33:26.613126 / # . /lava-880499/environment
1018 10:33:26.618832 . /lava-880499/environment
1020 10:33:26.731828 / # /lava-880499/bin/lava-test-runner /lava-880499/0
1021 10:33:26.732595 Test shell timeout: 10s (minimum of the action and connection timeout)
1022 10:33:26.737304 /lava-880499/bin/lava-test-runner /lava-880499/0
1023 10:33:27.136179 + export TESTRUN_ID=0_timesync-off
1024 10:33:27.144009 + TESTRUN_ID=0_timesync-off
1025 10:33:27.144480 + cd /lava-880499/0/tests/0_timesync-off
1026 10:33:27.144905 ++ cat uuid
1027 10:33:27.160508 + UUID=880499_1.6.2.4.1
1028 10:33:27.161032 + set +x
1029 10:33:27.169211 <LAVA_SIGNAL_STARTRUN 0_timesync-off 880499_1.6.2.4.1>
1030 10:33:27.169717 + systemctl stop systemd-timesyncd
1031 10:33:27.170475 Received signal: <STARTRUN> 0_timesync-off 880499_1.6.2.4.1
1032 10:33:27.170970 Starting test lava.0_timesync-off (880499_1.6.2.4.1)
1033 10:33:27.171557 Skipping test definition patterns.
1034 10:33:27.460585 + set +x
1035 10:33:27.461218 <LAVA_SIGNAL_ENDRUN 0_timesync-off 880499_1.6.2.4.1>
1036 10:33:27.461913 Received signal: <ENDRUN> 0_timesync-off 880499_1.6.2.4.1
1037 10:33:27.462407 Ending use of test pattern.
1038 10:33:27.462819 Ending test lava.0_timesync-off (880499_1.6.2.4.1), duration 0.29
1040 10:33:27.673479 + export TESTRUN_ID=1_kselftest-dt
1041 10:33:27.681391 + TESTRUN_ID=1_kselftest-dt
1042 10:33:27.681924 + cd /lava-880499/0/tests/1_kselftest-dt
1043 10:33:27.682392 ++ cat uuid
1044 10:33:27.697866 + UUID=880499_1.6.2.4.5
1045 10:33:27.698410 + set +x
1046 10:33:27.703491 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 880499_1.6.2.4.5>
1047 10:33:27.703805 + cd ./automated/linux/kselftest/
1048 10:33:27.704310 Received signal: <STARTRUN> 1_kselftest-dt 880499_1.6.2.4.5
1049 10:33:27.704555 Starting test lava.1_kselftest-dt (880499_1.6.2.4.5)
1050 10:33:27.704852 Skipping test definition patterns.
1051 10:33:27.729806 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1052 10:33:27.846186 INFO: install_deps skipped
1053 10:33:28.473686 --2024-10-22 10:33:28-- http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/clang-17/kselftest.tar.xz
1054 10:33:28.494354 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1055 10:33:28.639187 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1056 10:33:28.783367 HTTP request sent, awaiting response... 200 OK
1057 10:33:28.783917 Length: 2765512 (2.6M) [application/octet-stream]
1058 10:33:28.788954 Saving to: 'kselftest_armhf.tar.gz'
1059 10:33:28.789451
1060 10:33:30.263150
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 177KB/s
kselftest_armhf.tar 8%[> ] 216.29K 381KB/s
kselftest_armhf.tar 32%[=====> ] 888.48K 1.02MB/s
kselftest_armhf.tar 41%[=======> ] 1.11M 1.02MB/s
kselftest_armhf.tar 59%[==========> ] 1.56M 1.22MB/s
kselftest_armhf.tar 100%[===================>] 2.64M 1.79MB/s in 1.5s
1061 10:33:30.263790
1062 10:33:30.703368 2024-10-22 10:33:30 (1.79 MB/s) - 'kselftest_armhf.tar.gz' saved [2765512/2765512]
1063 10:33:30.704048
1064 10:33:41.935866 skiplist:
1065 10:33:41.936310 ========================================
1066 10:33:41.941590 ========================================
1067 10:33:42.041180 dt:test_unprobed_devices.sh
1068 10:33:42.072666 ============== Tests to run ===============
1069 10:33:42.080399 dt:test_unprobed_devices.sh
1070 10:33:42.084501 ===========End Tests to run ===============
1071 10:33:42.095920 shardfile-dt pass
1072 10:33:42.320936 <12>[ 69.718241] kselftest: Running tests in dt
1073 10:33:42.349717 TAP version 13
1074 10:33:42.373591 1..1
1075 10:33:42.428291 # timeout set to 45
1076 10:33:42.428804 # selftests: dt: test_unprobed_devices.sh
1077 10:33:43.293922 # TAP version 13
1078 10:34:08.670412 # 1..257
1079 10:34:08.858968 # ok 1 / # SKIP
1080 10:34:08.879132 # ok 2 /clk_mcasp0
1081 10:34:08.957926 # ok 3 /clk_mcasp0_fixed # SKIP
1082 10:34:09.025206 # ok 4 /cpus/cpu@0 # SKIP
1083 10:34:09.101072 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1084 10:34:09.119718 # ok 6 /fixedregulator0
1085 10:34:09.140937 # ok 7 /leds
1086 10:34:09.166703 # ok 8 /ocp
1087 10:34:09.186031 # ok 9 /ocp/interconnect@44c00000
1088 10:34:09.217818 # ok 10 /ocp/interconnect@44c00000/segment@0
1089 10:34:09.234019 # ok 11 /ocp/interconnect@44c00000/segment@100000
1090 10:34:09.263396 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1091 10:34:09.334608 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1092 10:34:09.355580 # ok 14 /ocp/interconnect@44c00000/segment@200000
1093 10:34:09.383233 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1094 10:34:09.489258 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1095 10:34:09.563954 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1096 10:34:09.638261 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1097 10:34:09.715157 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1098 10:34:09.788622 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1099 10:34:09.862053 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1100 10:34:09.938803 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1101 10:34:10.009661 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1102 10:34:10.083601 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1103 10:34:10.157019 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1104 10:34:10.230558 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1105 10:34:10.304546 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1106 10:34:10.378529 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1107 10:34:10.451976 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1108 10:34:10.524717 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1109 10:34:10.603488 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1110 10:34:10.674983 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1111 10:34:10.751921 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1112 10:34:10.819733 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1113 10:34:10.893719 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1114 10:34:10.966386 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1115 10:34:11.041177 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1116 10:34:11.115217 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1117 10:34:11.189981 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1118 10:34:11.263355 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1119 10:34:11.337584 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1120 10:34:11.412401 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1121 10:34:11.486560 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1122 10:34:11.565060 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1123 10:34:11.636871 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1124 10:34:11.713379 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1125 10:34:11.786941 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1126 10:34:11.862991 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1127 10:34:11.933239 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1128 10:34:12.009811 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1129 10:34:12.081406 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1130 10:34:12.155561 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1131 10:34:12.229537 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1132 10:34:12.304024 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1133 10:34:12.381268 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1134 10:34:12.452597 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1135 10:34:12.526369 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1136 10:34:12.600259 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1137 10:34:12.674048 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1138 10:34:12.748783 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1139 10:34:12.822525 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1140 10:34:12.902899 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1141 10:34:12.976288 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1142 10:34:13.054165 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1143 10:34:13.125624 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1144 10:34:13.203173 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1145 10:34:13.272271 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1146 10:34:13.345181 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1147 10:34:13.419507 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1148 10:34:13.492703 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1149 10:34:13.572178 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1150 10:34:13.641452 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1151 10:34:13.714923 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1152 10:34:13.789693 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1153 10:34:13.863778 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1154 10:34:13.937901 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1155 10:34:14.011833 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1156 10:34:14.085207 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1157 10:34:14.159201 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1158 10:34:14.232845 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1159 10:34:14.306043 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1160 10:34:14.384235 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1161 10:34:14.454937 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1162 10:34:14.532579 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1163 10:34:14.605199 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1164 10:34:14.675629 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1165 10:34:14.751657 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1166 10:34:14.826370 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1167 10:34:14.901060 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1168 10:34:14.976046 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1169 10:34:15.052010 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1170 10:34:15.127216 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1171 10:34:15.198531 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1172 10:34:15.271121 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1173 10:34:15.293048 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1174 10:34:15.317846 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1175 10:34:15.342333 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1176 10:34:15.367081 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1177 10:34:15.391356 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1178 10:34:15.419773 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1179 10:34:15.444194 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1180 10:34:15.468481 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1181 10:34:15.572467 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1182 10:34:15.598222 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1183 10:34:15.622860 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1184 10:34:15.647250 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1185 10:34:15.754585 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1186 10:34:15.831513 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1187 10:34:15.904997 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1188 10:34:15.980884 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1189 10:34:16.054301 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1190 10:34:16.129755 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1191 10:34:16.202593 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1192 10:34:16.277228 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1193 10:34:16.356854 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1194 10:34:16.427583 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1195 10:34:16.502749 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1196 10:34:16.576429 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1197 10:34:16.648595 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1198 10:34:16.725978 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1199 10:34:16.805523 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1200 10:34:16.875909 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1201 10:34:16.898203 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1202 10:34:16.970723 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1203 10:34:17.041592 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1204 10:34:17.116853 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1205 10:34:17.139034 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1206 10:34:17.212186 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1207 10:34:17.235499 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1208 10:34:17.307722 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1209 10:34:17.330905 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1210 10:34:17.355894 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1211 10:34:17.379052 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1212 10:34:17.404480 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1213 10:34:17.431170 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1214 10:34:17.453619 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1215 10:34:17.478510 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
1216 10:34:17.553340 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
1217 10:34:17.577316 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1218 10:34:17.601091 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1219 10:34:17.675895 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1220 10:34:17.747227 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1221 10:34:17.769528 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1222 10:34:17.872798 # not ok 144 /ocp/interconnect@47c00000
1223 10:34:17.945599 # not ok 145 /ocp/interconnect@47c00000/segment@0
1224 10:34:17.967079 # ok 146 /ocp/interconnect@48000000
1225 10:34:17.995777 # ok 147 /ocp/interconnect@48000000/segment@0
1226 10:34:18.021398 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1227 10:34:18.042843 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1228 10:34:18.068983 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1229 10:34:18.091818 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1230 10:34:18.112586 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1231 10:34:18.137460 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1232 10:34:18.162876 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1233 10:34:18.238643 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1234 10:34:18.319354 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1235 10:34:18.336518 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1236 10:34:18.361921 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1237 10:34:18.385369 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1238 10:34:18.409642 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1239 10:34:18.437502 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1240 10:34:18.457553 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1241 10:34:18.480997 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1242 10:34:18.505919 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1243 10:34:18.528453 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1244 10:34:18.554546 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1245 10:34:18.580264 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1246 10:34:18.603219 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1247 10:34:18.624741 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1248 10:34:18.649048 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1249 10:34:18.677015 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1250 10:34:18.698287 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1251 10:34:18.720991 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1252 10:34:18.746604 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1253 10:34:18.767274 # ok 175 /ocp/interconnect@48000000/segment@100000
1254 10:34:18.797304 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1255 10:34:18.817859 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1256 10:34:18.892196 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
1257 10:34:18.968564 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
1258 10:34:19.039273 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
1259 10:34:19.114965 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
1260 10:34:19.185972 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
1261 10:34:19.262000 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
1262 10:34:19.333297 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
1263 10:34:19.408946 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
1264 10:34:19.429456 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1265 10:34:19.453864 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1266 10:34:19.477633 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1267 10:34:19.502876 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1268 10:34:19.525870 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1269 10:34:19.550403 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1270 10:34:19.573696 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1271 10:34:19.598820 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1272 10:34:19.623100 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1273 10:34:19.646182 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1274 10:34:19.669752 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1275 10:34:19.695219 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1276 10:34:19.716215 # ok 198 /ocp/interconnect@48000000/segment@200000
1277 10:34:19.742690 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1278 10:34:19.815961 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1279 10:34:19.836303 # ok 201 /ocp/interconnect@48000000/segment@300000
1280 10:34:19.861367 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1281 10:34:19.886090 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1282 10:34:19.913540 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1283 10:34:19.933768 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1284 10:34:19.962736 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1285 10:34:19.987738 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1286 10:34:20.061238 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1287 10:34:20.078921 # ok 209 /ocp/interconnect@4a000000
1288 10:34:20.101471 # ok 210 /ocp/interconnect@4a000000/segment@0
1289 10:34:20.127540 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1290 10:34:20.153491 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1291 10:34:20.178190 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1292 10:34:20.200258 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1293 10:34:20.274842 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1294 10:34:20.381173 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1295 10:34:20.457374 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1296 10:34:20.563897 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1297 10:34:20.637360 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1298 10:34:20.710448 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1299 10:34:20.812092 # not ok 221 /ocp/interconnect@4b140000
1300 10:34:20.885653 # not ok 222 /ocp/interconnect@4b140000/segment@0
1301 10:34:20.961341 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1302 10:34:20.984451 # ok 224 /ocp/target-module@40300000
1303 10:34:21.005858 # ok 225 /ocp/target-module@40300000/sram@0
1304 10:34:21.082753 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1305 10:34:21.154832 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1306 10:34:21.174668 # ok 228 /ocp/target-module@47400000
1307 10:34:21.201809 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1308 10:34:21.226231 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1309 10:34:21.250209 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1310 10:34:21.268518 # ok 232 /ocp/target-module@47400000/usb@1400
1311 10:34:21.292431 # ok 233 /ocp/target-module@47400000/usb@1800
1312 10:34:21.318414 # ok 234 /ocp/target-module@47810000
1313 10:34:21.340068 # ok 235 /ocp/target-module@49000000
1314 10:34:21.365259 # ok 236 /ocp/target-module@49000000/dma@0
1315 10:34:21.387913 # ok 237 /ocp/target-module@49800000
1316 10:34:21.409651 # ok 238 /ocp/target-module@49800000/dma@0
1317 10:34:21.437859 # ok 239 /ocp/target-module@49900000
1318 10:34:21.453773 # ok 240 /ocp/target-module@49900000/dma@0
1319 10:34:21.479878 # ok 241 /ocp/target-module@49a00000
1320 10:34:21.505167 # ok 242 /ocp/target-module@49a00000/dma@0
1321 10:34:21.527396 # ok 243 /ocp/target-module@4c000000
1322 10:34:21.601020 # not ok 244 /ocp/target-module@4c000000/emif@0
1323 10:34:21.618834 # ok 245 /ocp/target-module@50000000
1324 10:34:21.641998 # ok 246 /ocp/target-module@53100000
1325 10:34:21.715542 # not ok 247 /ocp/target-module@53100000/sham@0
1326 10:34:21.737249 # ok 248 /ocp/target-module@53500000
1327 10:34:21.811440 # not ok 249 /ocp/target-module@53500000/aes@0
1328 10:34:21.837542 # ok 250 /ocp/target-module@56000000
1329 10:34:21.942111 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1330 10:34:22.016836 # ok 252 /opp-table # SKIP
1331 10:34:22.087853 # ok 253 /soc # SKIP
1332 10:34:22.107859 # ok 254 /sound
1333 10:34:22.135706 # ok 255 /target-module@4b000000
1334 10:34:22.156034 # ok 256 /target-module@4b000000/target-module@140000
1335 10:34:22.178226 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1336 10:34:22.186609 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1337 10:34:22.194924 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1338 10:34:24.354612 dt_test_unprobed_devices_sh_ skip
1339 10:34:24.360030 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1340 10:34:24.365712 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1341 10:34:24.365979 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1342 10:34:24.371242 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1343 10:34:24.376755 dt_test_unprobed_devices_sh_fixedregulator0 pass
1344 10:34:24.382535 dt_test_unprobed_devices_sh_leds pass
1345 10:34:24.382803 dt_test_unprobed_devices_sh_ocp pass
1346 10:34:24.388037 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1347 10:34:24.393666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1348 10:34:24.399295 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1349 10:34:24.410591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1350 10:34:24.416018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1351 10:34:24.421680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1352 10:34:24.432911 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1353 10:34:24.438623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1354 10:34:24.449661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1355 10:34:24.460971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1356 10:34:24.472073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1357 10:34:24.477675 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1358 10:34:24.488876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1359 10:34:24.500136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1360 10:34:24.511329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1361 10:34:24.522561 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1362 10:34:24.528153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1363 10:34:24.539332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1364 10:34:24.550486 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1365 10:34:24.561704 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1366 10:34:24.572846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1367 10:34:24.578444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1368 10:34:24.589644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1369 10:34:24.600862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1370 10:34:24.612050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1371 10:34:24.617630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1372 10:34:24.628806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1373 10:34:24.640022 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1374 10:34:24.651221 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1375 10:34:24.662366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1376 10:34:24.667946 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1377 10:34:24.679173 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1378 10:34:24.690329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1379 10:34:24.701567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1380 10:34:24.712776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1381 10:34:24.723960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1382 10:34:24.735144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1383 10:34:24.746346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1384 10:34:24.757528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1385 10:34:24.768736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1386 10:34:24.779886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1387 10:34:24.791102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1388 10:34:24.802271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1389 10:34:24.813450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1390 10:34:24.824686 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1391 10:34:24.835870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1392 10:34:24.847074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1393 10:34:24.858251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1394 10:34:24.869471 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1395 10:34:24.880560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1396 10:34:24.891812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1397 10:34:24.903117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1398 10:34:24.914313 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1399 10:34:24.925532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1400 10:34:24.936778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1401 10:34:24.948006 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1402 10:34:24.953601 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1403 10:34:24.964848 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1404 10:34:24.976070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1405 10:34:24.987256 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1406 10:34:24.998533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1407 10:34:25.009818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1408 10:34:25.021026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1409 10:34:25.032253 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1410 10:34:25.043405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1411 10:34:25.054575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1412 10:34:25.065768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1413 10:34:25.077015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1414 10:34:25.088186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1415 10:34:25.099394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1416 10:34:25.110564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1417 10:34:25.121767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1418 10:34:25.132956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1419 10:34:25.144159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1420 10:34:25.149755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1421 10:34:25.160944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1422 10:34:25.172141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1423 10:34:25.183280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1424 10:34:25.194587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1425 10:34:25.200129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1426 10:34:25.216868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1427 10:34:25.228054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1428 10:34:25.233667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1429 10:34:25.250545 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1430 10:34:25.261657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1431 10:34:25.272834 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1432 10:34:25.278451 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1433 10:34:25.289571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1434 10:34:25.300817 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1435 10:34:25.306432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1436 10:34:25.317625 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1437 10:34:25.328888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1438 10:34:25.334466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1439 10:34:25.345613 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1440 10:34:25.351208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1441 10:34:25.362438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1442 10:34:25.373638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1443 10:34:25.384770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1444 10:34:25.396144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1445 10:34:25.407171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1446 10:34:25.418387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1447 10:34:25.429590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1448 10:34:25.440764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1449 10:34:25.452012 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1450 10:34:25.463138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1451 10:34:25.474350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1452 10:34:25.485588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1453 10:34:25.502321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1454 10:34:25.513522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1455 10:34:25.524688 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1456 10:34:25.535860 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1457 10:34:25.547098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1458 10:34:25.563871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1459 10:34:25.575053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1460 10:34:25.586222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1461 10:34:25.597507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1462 10:34:25.603016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1463 10:34:25.614274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1464 10:34:25.625427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1465 10:34:25.631028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1466 10:34:25.642176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1467 10:34:25.647774 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1468 10:34:25.658996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1469 10:34:25.664625 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1470 10:34:25.675779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1471 10:34:25.681403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1472 10:34:25.692633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1473 10:34:25.698241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1474 10:34:25.709376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
1475 10:34:25.720657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
1476 10:34:25.731782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1477 10:34:25.737385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1478 10:34:25.748546 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1479 10:34:25.759769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1480 10:34:25.765341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1481 10:34:25.770917 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1482 10:34:25.782103 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1483 10:34:25.782567 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1484 10:34:25.793314 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1485 10:34:25.798978 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1486 10:34:25.804526 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1487 10:34:25.815694 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1488 10:34:25.821295 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1489 10:34:25.832453 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1490 10:34:25.838081 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1491 10:34:25.849256 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1492 10:34:25.854912 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1493 10:34:25.860473 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1494 10:34:25.871681 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1495 10:34:25.877261 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1496 10:34:25.888452 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1497 10:34:25.894011 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1498 10:34:25.905232 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1499 10:34:25.910844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1500 10:34:25.922052 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1501 10:34:25.927667 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1502 10:34:25.938828 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1503 10:34:25.944447 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1504 10:34:25.955672 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1505 10:34:25.961206 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1506 10:34:25.966779 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1507 10:34:25.977962 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1508 10:34:25.983570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1509 10:34:25.994791 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1510 10:34:26.000469 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1511 10:34:26.011649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1512 10:34:26.017191 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1513 10:34:26.028438 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1514 10:34:26.034036 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1515 10:34:26.045294 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
1516 10:34:26.056506 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
1517 10:34:26.067714 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
1518 10:34:26.078924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
1519 10:34:26.084482 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
1520 10:34:26.095685 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
1521 10:34:26.106900 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
1522 10:34:26.118080 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
1523 10:34:26.123683 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1524 10:34:26.134847 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1525 10:34:26.140455 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1526 10:34:26.151677 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1527 10:34:26.157272 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1528 10:34:26.168474 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1529 10:34:26.174088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1530 10:34:26.185233 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1531 10:34:26.190798 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1532 10:34:26.202074 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1533 10:34:26.207678 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1534 10:34:26.218892 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1535 10:34:26.224468 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1536 10:34:26.235644 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1537 10:34:26.241280 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1538 10:34:26.246908 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1539 10:34:26.258110 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1540 10:34:26.263726 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1541 10:34:26.274964 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1542 10:34:26.280602 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1543 10:34:26.291829 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1544 10:34:26.297436 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1545 10:34:26.308590 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1546 10:34:26.314183 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1547 10:34:26.319819 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1548 10:34:26.325426 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1549 10:34:26.336706 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1550 10:34:26.342198 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1551 10:34:26.353408 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1552 10:34:26.359281 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1553 10:34:26.370177 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1554 10:34:26.381375 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1555 10:34:26.392568 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1556 10:34:26.403876 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1557 10:34:26.409386 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1558 10:34:26.415004 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1559 10:34:26.420598 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1560 10:34:26.426217 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1561 10:34:26.431781 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1562 10:34:26.437398 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1563 10:34:26.448619 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1564 10:34:26.454246 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1565 10:34:26.459874 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1566 10:34:26.465464 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1567 10:34:26.471008 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1568 10:34:26.482250 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1569 10:34:26.487821 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1570 10:34:26.493450 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1571 10:34:26.499043 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1572 10:34:26.504764 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1573 10:34:26.510291 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1574 10:34:26.515896 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1575 10:34:26.521502 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1576 10:34:26.527100 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1577 10:34:26.532740 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1578 10:34:26.538250 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1579 10:34:26.543847 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1580 10:34:26.549463 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1581 10:34:26.555088 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1582 10:34:26.560728 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1583 10:34:26.566290 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1584 10:34:26.571884 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1585 10:34:26.577513 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1586 10:34:26.583103 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1587 10:34:26.588739 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1588 10:34:26.594268 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1589 10:34:26.594737 dt_test_unprobed_devices_sh_opp-table skip
1590 10:34:26.599895 dt_test_unprobed_devices_sh_soc skip
1591 10:34:26.605544 dt_test_unprobed_devices_sh_sound pass
1592 10:34:26.606011 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1593 10:34:26.616744 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1594 10:34:26.622321 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1595 10:34:26.627908 dt_test_unprobed_devices_sh fail
1596 10:34:26.628402 + ../../utils/send-to-lava.sh ./output/result.txt
1597 10:34:26.633612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1598 10:34:26.634561 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1600 10:34:26.639364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1602 10:34:26.642315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1603 10:34:26.737587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1604 10:34:26.738345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1606 10:34:26.830810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1607 10:34:26.831590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1609 10:34:26.918250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1610 10:34:26.919011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1612 10:34:27.006757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1613 10:34:27.007518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1615 10:34:27.098642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1616 10:34:27.099415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1618 10:34:27.190401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1619 10:34:27.191153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1621 10:34:27.278070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1622 10:34:27.278849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1624 10:34:27.367918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1625 10:34:27.368740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1627 10:34:27.461694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1628 10:34:27.462456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1630 10:34:27.549234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1631 10:34:27.549992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1633 10:34:27.637424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1634 10:34:27.638209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1636 10:34:27.734317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1637 10:34:27.735221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1639 10:34:27.821251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1640 10:34:27.822110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1642 10:34:27.914957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1643 10:34:27.915821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1645 10:34:28.009772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1646 10:34:28.010622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1648 10:34:28.103740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1649 10:34:28.104614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1651 10:34:28.192248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1652 10:34:28.193071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1654 10:34:28.285457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1655 10:34:28.286329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1657 10:34:28.376855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1658 10:34:28.377817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1660 10:34:28.464416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1661 10:34:28.465305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1663 10:34:28.549378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1664 10:34:28.550187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1666 10:34:28.635281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1667 10:34:28.636100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1669 10:34:28.721734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1670 10:34:28.722540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1672 10:34:28.806466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1673 10:34:28.807254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1675 10:34:28.892426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1676 10:34:28.893221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1678 10:34:28.979041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1679 10:34:28.979824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1681 10:34:29.066225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1682 10:34:29.067018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1684 10:34:29.152373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1685 10:34:29.153185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1687 10:34:29.237720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1688 10:34:29.238524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1690 10:34:29.325413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1691 10:34:29.326207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1693 10:34:29.416481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1694 10:34:29.417263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1696 10:34:29.504238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1697 10:34:29.505107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1699 10:34:29.590053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1700 10:34:29.590876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1702 10:34:29.682584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1703 10:34:29.683349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1705 10:34:29.768079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1706 10:34:29.768697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1708 10:34:29.860898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1709 10:34:29.861503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1711 10:34:29.948067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1712 10:34:29.948686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1714 10:34:30.032415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1715 10:34:30.033011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1717 10:34:30.116198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1718 10:34:30.116998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1720 10:34:30.200231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1721 10:34:30.201006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1723 10:34:30.287450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1724 10:34:30.288210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1726 10:34:30.374158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1727 10:34:30.374911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1729 10:34:30.460223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1730 10:34:30.460965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1732 10:34:30.552631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1733 10:34:30.553369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1735 10:34:30.638941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1736 10:34:30.639674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1738 10:34:30.730656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1739 10:34:30.731424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1741 10:34:30.822652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1742 10:34:30.823448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1744 10:34:30.909645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1745 10:34:30.910415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1747 10:34:31.001650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1748 10:34:31.002430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1750 10:34:31.094891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1751 10:34:31.095673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1753 10:34:31.180751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1754 10:34:31.181585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1756 10:34:31.267894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1757 10:34:31.268764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1759 10:34:31.355250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1760 10:34:31.356075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1762 10:34:31.441266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1763 10:34:31.442076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1765 10:34:31.528496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1766 10:34:31.529256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1768 10:34:31.619903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1769 10:34:31.620711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1771 10:34:31.711673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1772 10:34:31.712482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1774 10:34:31.798694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1775 10:34:31.799468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1777 10:34:31.894130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1778 10:34:31.894913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1780 10:34:31.979794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1781 10:34:31.980601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1783 10:34:32.072848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1784 10:34:32.073604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1786 10:34:32.159394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1787 10:34:32.160158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1789 10:34:32.245779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1790 10:34:32.246549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1792 10:34:32.337411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1793 10:34:32.338186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1795 10:34:32.425074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1796 10:34:32.425831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1798 10:34:32.516514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1799 10:34:32.517266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1801 10:34:32.602547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1802 10:34:32.603316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1804 10:34:32.688033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1805 10:34:32.688789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1807 10:34:32.776214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1808 10:34:32.776974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1810 10:34:32.869388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1811 10:34:32.870148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1813 10:34:32.961086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1814 10:34:32.961847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1816 10:34:33.047014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1817 10:34:33.047766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1819 10:34:33.139389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1820 10:34:33.140170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1822 10:34:33.233528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1823 10:34:33.234289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1825 10:34:33.319449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1826 10:34:33.320304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1828 10:34:33.410620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1829 10:34:33.411404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1831 10:34:33.495772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1832 10:34:33.496575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1834 10:34:33.582627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1835 10:34:33.583451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1837 10:34:33.714830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1838 10:34:33.715635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1840 10:34:33.811137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1841 10:34:33.811923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1843 10:34:33.896652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1844 10:34:33.897440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1846 10:34:33.981077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1847 10:34:33.981848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1849 10:34:34.066128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1850 10:34:34.066892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1852 10:34:34.150652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1853 10:34:34.151431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1855 10:34:34.234860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1856 10:34:34.235624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1858 10:34:34.320499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1859 10:34:34.321330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1861 10:34:34.425082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1862 10:34:34.425886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1864 10:34:34.519293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1865 10:34:34.520176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1867 10:34:34.605930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1868 10:34:34.606752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1870 10:34:34.692094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1871 10:34:34.692943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1873 10:34:34.783281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1874 10:34:34.784070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1876 10:34:34.868267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1877 10:34:34.869033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1879 10:34:34.954484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1880 10:34:34.955238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1882 10:34:35.036177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1883 10:34:35.036952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1885 10:34:35.121627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1886 10:34:35.122397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1888 10:34:35.205681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1889 10:34:35.206443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1891 10:34:35.292553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1892 10:34:35.293331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1894 10:34:35.377485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1895 10:34:35.378280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1897 10:34:35.470583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1898 10:34:35.471347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1900 10:34:35.556760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1901 10:34:35.557532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1903 10:34:35.642815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1904 10:34:35.643425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1906 10:34:35.738241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1907 10:34:35.738838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1909 10:34:35.830640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1910 10:34:35.831254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1912 10:34:35.915001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1913 10:34:35.915604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1915 10:34:36.001742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1916 10:34:36.002351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1918 10:34:36.092054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1919 10:34:36.092648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1921 10:34:36.180404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1922 10:34:36.181016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1924 10:34:36.265778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1925 10:34:36.266393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1927 10:34:36.350738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1928 10:34:36.351346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1930 10:34:36.436277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1931 10:34:36.436872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1933 10:34:36.521091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1934 10:34:36.521701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1936 10:34:36.607387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1937 10:34:36.608295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1939 10:34:36.700221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1940 10:34:36.701006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1942 10:34:36.792437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1943 10:34:36.793219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1945 10:34:36.878629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1946 10:34:36.879409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1948 10:34:36.970087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1949 10:34:36.970869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1951 10:34:37.056136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1952 10:34:37.056915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1954 10:34:37.147313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1955 10:34:37.148087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1957 10:34:37.231777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1959 10:34:37.234911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1960 10:34:37.318795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1962 10:34:37.321917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1963 10:34:37.407100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1965 10:34:37.410254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1966 10:34:37.495212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1967 10:34:37.496018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1969 10:34:37.588763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1970 10:34:37.589541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1972 10:34:37.684914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1973 10:34:37.685665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1975 10:34:37.782545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1976 10:34:37.783321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1978 10:34:37.880109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1979 10:34:37.880884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1981 10:34:37.975318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1982 10:34:37.976116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1984 10:34:38.067864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1985 10:34:38.068660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1987 10:34:38.163567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1988 10:34:38.164369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1990 10:34:38.256625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1991 10:34:38.257391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1993 10:34:38.345375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1994 10:34:38.346155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1996 10:34:38.459863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1997 10:34:38.460856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1999 10:34:38.591234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2000 10:34:38.592041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2002 10:34:38.681970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2003 10:34:38.682727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2005 10:34:38.775284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2006 10:34:38.776085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2008 10:34:38.864246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
2009 10:34:38.864995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
2011 10:34:38.955235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
2012 10:34:38.956142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
2014 10:34:39.057758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2015 10:34:39.058617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2017 10:34:39.171575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2018 10:34:39.172465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2020 10:34:39.267439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2021 10:34:39.268378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2023 10:34:39.361618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2024 10:34:39.362522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2026 10:34:39.449392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2027 10:34:39.450302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2029 10:34:39.539500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2030 10:34:39.540433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2032 10:34:39.628615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2033 10:34:39.629466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2035 10:34:39.721739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2036 10:34:39.722688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2038 10:34:39.813065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2039 10:34:39.813957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2041 10:34:39.902447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2042 10:34:39.903342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2044 10:34:39.995955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2045 10:34:39.996955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2047 10:34:40.083236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2048 10:34:40.084107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2050 10:34:40.171060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2051 10:34:40.171883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2053 10:34:40.258793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2054 10:34:40.259613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2056 10:34:40.352416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2057 10:34:40.353248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2059 10:34:40.439487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2060 10:34:40.440362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2062 10:34:40.532967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2063 10:34:40.533779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2065 10:34:40.626377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2066 10:34:40.627213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2068 10:34:40.714622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2069 10:34:40.715462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2071 10:34:40.804084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2072 10:34:40.804923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2074 10:34:40.897157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2075 10:34:40.898004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2077 10:34:40.989947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2078 10:34:40.990783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2080 10:34:41.083312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2081 10:34:41.084182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2083 10:34:41.171604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2084 10:34:41.172490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2086 10:34:41.258156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2087 10:34:41.258970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2089 10:34:41.345888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2090 10:34:41.346723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2092 10:34:41.438715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2093 10:34:41.439544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2095 10:34:41.531171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2096 10:34:41.532010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2098 10:34:41.623261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2099 10:34:41.624082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2101 10:34:41.711446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2102 10:34:41.712327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2104 10:34:41.798892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2105 10:34:41.799709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2107 10:34:41.892190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2108 10:34:41.892999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2110 10:34:41.979547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2111 10:34:41.980400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2113 10:34:42.073885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2114 10:34:42.074834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2116 10:34:42.166232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2117 10:34:42.167067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2119 10:34:42.255819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2120 10:34:42.256667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2122 10:34:42.341346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2123 10:34:42.342158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2125 10:34:42.435740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2126 10:34:42.436589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2128 10:34:42.529617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2129 10:34:42.530439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2131 10:34:42.617735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
2132 10:34:42.618600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
2134 10:34:42.712723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
2135 10:34:42.713882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
2137 10:34:42.798788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
2138 10:34:42.799601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
2140 10:34:42.887511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
2141 10:34:42.888283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
2143 10:34:42.974371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
2144 10:34:42.975125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
2146 10:34:43.068120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
2147 10:34:43.068939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
2149 10:34:43.155815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
2150 10:34:43.156713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
2152 10:34:43.245792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
2153 10:34:43.246564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
2155 10:34:43.337058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2156 10:34:43.337825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2158 10:34:43.430710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2159 10:34:43.431521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2161 10:34:43.541961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2162 10:34:43.542792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2164 10:34:43.634300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2165 10:34:43.635126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2167 10:34:43.720749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2168 10:34:43.721559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2170 10:34:43.815812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2171 10:34:43.816669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2173 10:34:43.908672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2174 10:34:43.909515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2176 10:34:44.000608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2177 10:34:44.001386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2179 10:34:44.088549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2180 10:34:44.089305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2182 10:34:44.182370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2183 10:34:44.183180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2185 10:34:44.276295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2186 10:34:44.277088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2188 10:34:44.365356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2189 10:34:44.366209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2191 10:34:44.449235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2192 10:34:44.450040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2194 10:34:44.544184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2195 10:34:44.544809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2197 10:34:44.633447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2198 10:34:44.634238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2200 10:34:44.718806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2201 10:34:44.719598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2203 10:34:44.812995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2204 10:34:44.813776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2206 10:34:44.901155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2207 10:34:44.901942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2209 10:34:44.988093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2210 10:34:44.988941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2212 10:34:45.075815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2213 10:34:45.076662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2215 10:34:45.164837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2216 10:34:45.165619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2218 10:34:45.260228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2219 10:34:45.260994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2221 10:34:45.354044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2222 10:34:45.354642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2224 10:34:45.437523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2225 10:34:45.438119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2227 10:34:45.523812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2228 10:34:45.524447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2230 10:34:45.619012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2231 10:34:45.619630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2233 10:34:45.706169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2234 10:34:45.706766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2236 10:34:45.794821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2237 10:34:45.795452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2239 10:34:45.885473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2240 10:34:45.886103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2242 10:34:45.972161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2243 10:34:45.972770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2245 10:34:46.060063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2246 10:34:46.060679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2248 10:34:46.154971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2249 10:34:46.155572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2251 10:34:46.240756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2252 10:34:46.241345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2254 10:34:46.334514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2255 10:34:46.335110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2257 10:34:46.429407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2258 10:34:46.430012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2260 10:34:46.519214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2261 10:34:46.519831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2263 10:34:46.614061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2264 10:34:46.614684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2266 10:34:46.708585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2267 10:34:46.709171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2269 10:34:46.801950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2270 10:34:46.802554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2272 10:34:46.889398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2273 10:34:46.889982 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2275 10:34:46.977828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2276 10:34:46.978425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2278 10:34:47.061540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2280 10:34:47.064103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2281 10:34:47.150306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2282 10:34:47.151177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2284 10:34:47.243725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2285 10:34:47.244538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2287 10:34:47.330329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2288 10:34:47.331167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2290 10:34:47.423485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2291 10:34:47.424383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2293 10:34:47.515104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2294 10:34:47.515935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2296 10:34:47.606592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2297 10:34:47.607414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2299 10:34:47.699506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2300 10:34:47.700330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2302 10:34:47.790871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2303 10:34:47.791678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2305 10:34:47.884926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2306 10:34:47.885695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2308 10:34:47.970355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2309 10:34:47.971117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2311 10:34:48.065579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2312 10:34:48.066359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2314 10:34:48.156339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2315 10:34:48.157107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2317 10:34:48.243605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2318 10:34:48.244421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2320 10:34:48.330342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2321 10:34:48.331127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2323 10:34:48.421939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2324 10:34:48.422786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2326 10:34:48.510102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2327 10:34:48.511079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2329 10:34:48.601911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2330 10:34:48.602742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2332 10:34:48.689274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2333 10:34:48.690118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2335 10:34:48.775946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2336 10:34:48.776825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2338 10:34:48.869166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2339 10:34:48.870000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2341 10:34:48.961224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2342 10:34:48.962064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2344 10:34:49.050426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2345 10:34:49.051387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2347 10:34:49.136770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2348 10:34:49.137599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2350 10:34:49.230854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2351 10:34:49.231649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2353 10:34:49.313680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2354 10:34:49.314479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2356 10:34:49.400340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2357 10:34:49.401182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2359 10:34:49.506091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2360 10:34:49.506972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2362 10:34:49.596465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2363 10:34:49.597249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2365 10:34:49.692268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2366 10:34:49.693062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2368 10:34:49.781659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2369 10:34:49.782435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2371 10:34:49.867605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2372 10:34:49.868176 + set +x
2373 10:34:49.868833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2375 10:34:49.871027 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 880499_1.6.2.4.5>
2376 10:34:49.871732 Received signal: <ENDRUN> 1_kselftest-dt 880499_1.6.2.4.5
2377 10:34:49.872208 Ending use of test pattern.
2378 10:34:49.872599 Ending test lava.1_kselftest-dt (880499_1.6.2.4.5), duration 82.17
2380 10:34:49.877202 <LAVA_TEST_RUNNER EXIT>
2381 10:34:49.877905 ok: lava_test_shell seems to have completed
2382 10:34:49.890869 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2383 10:34:49.892799 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2384 10:34:49.893329 end: 3 lava-test-retry (duration 00:01:24) [common]
2385 10:34:49.893863 start: 4 finalize (timeout 00:05:30) [common]
2386 10:34:49.894389 start: 4.1 power-off (timeout 00:00:30) [common]
2387 10:34:49.895322 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2388 10:34:49.930177 >> OK - accepted request
2389 10:34:49.932364 Returned 0 in 0 seconds
2390 10:34:50.033702 end: 4.1 power-off (duration 00:00:00) [common]
2392 10:34:50.035424 start: 4.2 read-feedback (timeout 00:05:30) [common]
2393 10:34:50.036932 Listened to connection for namespace 'common' for up to 1s
2394 10:34:50.037850 Listened to connection for namespace 'common' for up to 1s
2395 10:34:51.036725 Finalising connection for namespace 'common'
2396 10:34:51.037472 Disconnecting from shell: Finalise
2397 10:34:51.037980 / #
2398 10:34:51.139010 end: 4.2 read-feedback (duration 00:00:01) [common]
2399 10:34:51.139760 end: 4 finalize (duration 00:00:01) [common]
2400 10:34:51.140468 Cleaning after the job
2401 10:34:51.141136 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/ramdisk
2402 10:34:51.143799 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/kernel
2403 10:34:51.150984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/dtb
2404 10:34:51.152278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/nfsrootfs
2405 10:34:51.199188 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880499/tftp-deploy-v4sag_ox/modules
2406 10:34:51.203346 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/880499
2407 10:34:54.393401 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/880499
2408 10:34:54.393947 Job finished correctly