Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 10:02:01.215418 lava-dispatcher, installed at version: 2024.01
2 10:02:01.216161 start: 0 validate
3 10:02:01.216637 Start time: 2024-10-22 10:02:01.216606+00:00 (UTC)
4 10:02:01.217167 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 10:02:01.217706 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 10:02:01.250952 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 10:02:01.251478 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 10:02:01.276764 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 10:02:01.277333 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 10:02:01.301572 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 10:02:01.302115 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 10:02:01.326567 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 10:02:01.327018 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 10:02:01.356176 validate duration: 0.14
16 10:02:01.357067 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:02:01.357389 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:02:01.357680 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:02:01.358292 Not decompressing ramdisk as can be used compressed.
20 10:02:01.358704 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 10:02:01.358981 saving as /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/ramdisk/initrd.cpio.gz
22 10:02:01.359250 total size: 4775763 (4 MB)
23 10:02:01.387642 progress 0 % (0 MB)
24 10:02:01.391557 progress 5 % (0 MB)
25 10:02:01.394704 progress 10 % (0 MB)
26 10:02:01.397714 progress 15 % (0 MB)
27 10:02:01.401060 progress 20 % (0 MB)
28 10:02:01.404062 progress 25 % (1 MB)
29 10:02:01.407005 progress 30 % (1 MB)
30 10:02:01.410398 progress 35 % (1 MB)
31 10:02:01.413321 progress 40 % (1 MB)
32 10:02:01.416456 progress 45 % (2 MB)
33 10:02:01.419440 progress 50 % (2 MB)
34 10:02:01.422685 progress 55 % (2 MB)
35 10:02:01.425500 progress 60 % (2 MB)
36 10:02:01.428308 progress 65 % (2 MB)
37 10:02:01.431578 progress 70 % (3 MB)
38 10:02:01.434431 progress 75 % (3 MB)
39 10:02:01.437245 progress 80 % (3 MB)
40 10:02:01.440072 progress 85 % (3 MB)
41 10:02:01.443443 progress 90 % (4 MB)
42 10:02:01.446315 progress 95 % (4 MB)
43 10:02:01.449159 progress 100 % (4 MB)
44 10:02:01.449771 4 MB downloaded in 0.09 s (50.32 MB/s)
45 10:02:01.450387 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:02:01.451270 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:02:01.451577 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:02:01.451864 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:02:01.452350 downloading http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 10:02:01.452606 saving as /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/kernel/zImage
52 10:02:01.452824 total size: 11485696 (10 MB)
53 10:02:01.453043 No compression specified
54 10:02:01.485729 progress 0 % (0 MB)
55 10:02:01.492937 progress 5 % (0 MB)
56 10:02:01.500048 progress 10 % (1 MB)
57 10:02:01.506716 progress 15 % (1 MB)
58 10:02:01.513702 progress 20 % (2 MB)
59 10:02:01.520494 progress 25 % (2 MB)
60 10:02:01.527547 progress 30 % (3 MB)
61 10:02:01.534306 progress 35 % (3 MB)
62 10:02:01.541256 progress 40 % (4 MB)
63 10:02:01.548085 progress 45 % (4 MB)
64 10:02:01.555107 progress 50 % (5 MB)
65 10:02:01.561676 progress 55 % (6 MB)
66 10:02:01.568646 progress 60 % (6 MB)
67 10:02:01.575317 progress 65 % (7 MB)
68 10:02:01.582391 progress 70 % (7 MB)
69 10:02:01.588973 progress 75 % (8 MB)
70 10:02:01.596071 progress 80 % (8 MB)
71 10:02:01.602449 progress 85 % (9 MB)
72 10:02:01.609100 progress 90 % (9 MB)
73 10:02:01.615314 progress 95 % (10 MB)
74 10:02:01.621932 progress 100 % (10 MB)
75 10:02:01.622512 10 MB downloaded in 0.17 s (64.56 MB/s)
76 10:02:01.623020 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:02:01.623876 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:02:01.624180 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:02:01.624467 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:02:01.624953 downloading http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 10:02:01.625215 saving as /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/dtb/am335x-boneblack.dtb
83 10:02:01.625433 total size: 70544 (0 MB)
84 10:02:01.625651 No compression specified
85 10:02:01.654047 progress 46 % (0 MB)
86 10:02:01.654880 progress 92 % (0 MB)
87 10:02:01.655567 progress 100 % (0 MB)
88 10:02:01.655962 0 MB downloaded in 0.03 s (2.20 MB/s)
89 10:02:01.656430 end: 1.3.1 http-download (duration 00:00:00) [common]
91 10:02:01.657271 end: 1.3 download-retry (duration 00:00:00) [common]
92 10:02:01.657553 start: 1.4 download-retry (timeout 00:10:00) [common]
93 10:02:01.657849 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 10:02:01.658326 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 10:02:01.658585 saving as /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/nfsrootfs/full.rootfs.tar
96 10:02:01.658798 total size: 117747780 (112 MB)
97 10:02:01.659016 Using unxz to decompress xz
98 10:02:01.692935 progress 0 % (0 MB)
99 10:02:02.404135 progress 5 % (5 MB)
100 10:02:03.134259 progress 10 % (11 MB)
101 10:02:03.892534 progress 15 % (16 MB)
102 10:02:04.599352 progress 20 % (22 MB)
103 10:02:05.188289 progress 25 % (28 MB)
104 10:02:05.990316 progress 30 % (33 MB)
105 10:02:06.778044 progress 35 % (39 MB)
106 10:02:07.106067 progress 40 % (44 MB)
107 10:02:07.452090 progress 45 % (50 MB)
108 10:02:08.088970 progress 50 % (56 MB)
109 10:02:08.884624 progress 55 % (61 MB)
110 10:02:09.611343 progress 60 % (67 MB)
111 10:02:10.318291 progress 65 % (73 MB)
112 10:02:11.078191 progress 70 % (78 MB)
113 10:02:11.826968 progress 75 % (84 MB)
114 10:02:12.550516 progress 80 % (89 MB)
115 10:02:13.250407 progress 85 % (95 MB)
116 10:02:14.026475 progress 90 % (101 MB)
117 10:02:14.782505 progress 95 % (106 MB)
118 10:02:15.588272 progress 100 % (112 MB)
119 10:02:15.600620 112 MB downloaded in 13.94 s (8.05 MB/s)
120 10:02:15.601565 end: 1.4.1 http-download (duration 00:00:14) [common]
122 10:02:15.603413 end: 1.4 download-retry (duration 00:00:14) [common]
123 10:02:15.604001 start: 1.5 download-retry (timeout 00:09:46) [common]
124 10:02:15.604577 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 10:02:15.605541 downloading http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 10:02:15.606095 saving as /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/modules/modules.tar
127 10:02:15.606561 total size: 6625268 (6 MB)
128 10:02:15.607028 Using unxz to decompress xz
129 10:02:15.646346 progress 0 % (0 MB)
130 10:02:15.679881 progress 5 % (0 MB)
131 10:02:15.723737 progress 10 % (0 MB)
132 10:02:15.767842 progress 15 % (0 MB)
133 10:02:15.810937 progress 20 % (1 MB)
134 10:02:15.858008 progress 25 % (1 MB)
135 10:02:15.901173 progress 30 % (1 MB)
136 10:02:15.944547 progress 35 % (2 MB)
137 10:02:15.987239 progress 40 % (2 MB)
138 10:02:16.029727 progress 45 % (2 MB)
139 10:02:16.076057 progress 50 % (3 MB)
140 10:02:16.118691 progress 55 % (3 MB)
141 10:02:16.161646 progress 60 % (3 MB)
142 10:02:16.204604 progress 65 % (4 MB)
143 10:02:16.247623 progress 70 % (4 MB)
144 10:02:16.293976 progress 75 % (4 MB)
145 10:02:16.337713 progress 80 % (5 MB)
146 10:02:16.379882 progress 85 % (5 MB)
147 10:02:16.422908 progress 90 % (5 MB)
148 10:02:16.470658 progress 95 % (6 MB)
149 10:02:16.513083 progress 100 % (6 MB)
150 10:02:16.524386 6 MB downloaded in 0.92 s (6.88 MB/s)
151 10:02:16.525313 end: 1.5.1 http-download (duration 00:00:01) [common]
153 10:02:16.527160 end: 1.5 download-retry (duration 00:00:01) [common]
154 10:02:16.527754 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 10:02:16.528340 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 10:02:32.821580 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/880284/extract-nfsrootfs-hcsdta_m
157 10:02:32.822189 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 10:02:32.822518 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
159 10:02:32.823235 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge
160 10:02:32.823727 makedir: /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin
161 10:02:32.824134 makedir: /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/tests
162 10:02:32.824513 makedir: /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/results
163 10:02:32.824883 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-add-keys
164 10:02:32.825410 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-add-sources
165 10:02:32.825951 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-background-process-start
166 10:02:32.826473 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-background-process-stop
167 10:02:32.826995 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-common-functions
168 10:02:32.827489 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-echo-ipv4
169 10:02:32.827968 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-install-packages
170 10:02:32.828460 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-installed-packages
171 10:02:32.828994 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-os-build
172 10:02:32.829473 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-probe-channel
173 10:02:32.829994 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-probe-ip
174 10:02:32.830487 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-target-ip
175 10:02:32.831011 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-target-mac
176 10:02:32.831557 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-target-storage
177 10:02:32.832098 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-test-case
178 10:02:32.832653 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-test-event
179 10:02:32.833140 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-test-feedback
180 10:02:32.833621 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-test-raise
181 10:02:32.834167 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-test-reference
182 10:02:32.834661 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-test-runner
183 10:02:32.835154 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-test-set
184 10:02:32.835632 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-test-shell
185 10:02:32.836132 Updating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-add-keys (debian)
186 10:02:32.836672 Updating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-add-sources (debian)
187 10:02:32.837179 Updating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-install-packages (debian)
188 10:02:32.837679 Updating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-installed-packages (debian)
189 10:02:32.838209 Updating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/bin/lava-os-build (debian)
190 10:02:32.838652 Creating /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/environment
191 10:02:32.839031 LAVA metadata
192 10:02:32.839292 - LAVA_JOB_ID=880284
193 10:02:32.839506 - LAVA_DISPATCHER_IP=192.168.6.3
194 10:02:32.839875 start: 1.6.2.1 ssh-authorize (timeout 00:09:29) [common]
195 10:02:32.840815 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 10:02:32.841128 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:29) [common]
197 10:02:32.841334 skipped lava-vland-overlay
198 10:02:32.841574 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 10:02:32.841848 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:29) [common]
200 10:02:32.842058 skipped lava-multinode-overlay
201 10:02:32.842298 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 10:02:32.842549 start: 1.6.2.4 test-definition (timeout 00:09:29) [common]
203 10:02:32.842796 Loading test definitions
204 10:02:32.843070 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:29) [common]
205 10:02:32.843308 Using /lava-880284 at stage 0
206 10:02:32.844382 uuid=880284_1.6.2.4.1 testdef=None
207 10:02:32.844690 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 10:02:32.844950 start: 1.6.2.4.2 test-overlay (timeout 00:09:29) [common]
209 10:02:32.846580 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 10:02:32.847379 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:29) [common]
212 10:02:32.849334 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 10:02:32.850222 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:29) [common]
215 10:02:32.852098 runner path: /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/0/tests/0_timesync-off test_uuid 880284_1.6.2.4.1
216 10:02:32.852667 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 10:02:32.853481 start: 1.6.2.4.5 git-repo-action (timeout 00:09:29) [common]
219 10:02:32.853705 Using /lava-880284 at stage 0
220 10:02:32.854094 Fetching tests from https://github.com/kernelci/test-definitions.git
221 10:02:32.854391 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/0/tests/1_kselftest-dt'
222 10:02:36.236488 Running '/usr/bin/git checkout kernelci.org
223 10:02:36.476239 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 10:02:36.477704 uuid=880284_1.6.2.4.5 testdef=None
225 10:02:36.478286 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 10:02:36.479892 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 10:02:36.485868 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 10:02:36.487610 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 10:02:36.495666 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 10:02:36.497796 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 10:02:36.505600 runner path: /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/0/tests/1_kselftest-dt test_uuid 880284_1.6.2.4.5
235 10:02:36.506262 BOARD='beaglebone-black'
236 10:02:36.506719 BRANCH='next'
237 10:02:36.507154 SKIPFILE='/dev/null'
238 10:02:36.507587 SKIP_INSTALL='True'
239 10:02:36.508014 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 10:02:36.508451 TST_CASENAME=''
241 10:02:36.508881 TST_CMDFILES='dt'
242 10:02:36.510007 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 10:02:36.511709 Creating lava-test-runner.conf files
245 10:02:36.512151 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/880284/lava-overlay-n7p03oge/lava-880284/0 for stage 0
246 10:02:36.512881 - 0_timesync-off
247 10:02:36.513382 - 1_kselftest-dt
248 10:02:36.514101 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 10:02:36.514708 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 10:02:59.986368 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 10:02:59.986816 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 10:02:59.987109 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 10:02:59.987418 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 10:02:59.987711 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 10:03:00.340675 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 10:03:00.341236 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 10:03:00.341551 extracting modules file /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/modules/modules.tar to /var/lib/lava/dispatcher/tmp/880284/extract-nfsrootfs-hcsdta_m
258 10:03:01.323305 extracting modules file /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/modules/modules.tar to /var/lib/lava/dispatcher/tmp/880284/extract-overlay-ramdisk-hqp0858l/ramdisk
259 10:03:02.243900 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 10:03:02.244372 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 10:03:02.244660 [common] Applying overlay to NFS
262 10:03:02.244875 [common] Applying overlay /var/lib/lava/dispatcher/tmp/880284/compress-overlay-15__xto4/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/880284/extract-nfsrootfs-hcsdta_m
263 10:03:05.095600 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 10:03:05.096075 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 10:03:05.096385 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 10:03:05.096731 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 10:03:05.097020 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 10:03:05.097289 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 10:03:05.097561 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 10:03:05.097871 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 10:03:05.098139 Building ramdisk /var/lib/lava/dispatcher/tmp/880284/extract-overlay-ramdisk-hqp0858l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/880284/extract-overlay-ramdisk-hqp0858l/ramdisk
272 10:03:06.076095 >> 75166 blocks
273 10:03:10.910926 Adding RAMdisk u-boot header.
274 10:03:10.911688 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/880284/extract-overlay-ramdisk-hqp0858l/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/880284/extract-overlay-ramdisk-hqp0858l/ramdisk.cpio.gz.uboot
275 10:03:11.067009 output: Image Name:
276 10:03:11.067641 output: Created: Tue Oct 22 10:03:10 2024
277 10:03:11.068120 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 10:03:11.068583 output: Data Size: 14812065 Bytes = 14464.91 KiB = 14.13 MiB
279 10:03:11.069040 output: Load Address: 00000000
280 10:03:11.069491 output: Entry Point: 00000000
281 10:03:11.069985 output:
282 10:03:11.071276 rename /var/lib/lava/dispatcher/tmp/880284/extract-overlay-ramdisk-hqp0858l/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/ramdisk/ramdisk.cpio.gz.uboot
283 10:03:11.072075 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 10:03:11.072689 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 10:03:11.073285 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 10:03:11.073800 No LXC device requested
287 10:03:11.074426 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 10:03:11.075015 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 10:03:11.075581 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 10:03:11.076051 Checking files for TFTP limit of 4294967296 bytes.
291 10:03:11.079044 end: 1 tftp-deploy (duration 00:01:10) [common]
292 10:03:11.079688 start: 2 uboot-action (timeout 00:05:00) [common]
293 10:03:11.080282 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 10:03:11.080846 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 10:03:11.081418 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 10:03:11.082286 substitutions:
297 10:03:11.082766 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 10:03:11.083221 - {DTB_ADDR}: 0x88000000
299 10:03:11.083671 - {DTB}: 880284/tftp-deploy-qnwo8n43/dtb/am335x-boneblack.dtb
300 10:03:11.084121 - {INITRD}: 880284/tftp-deploy-qnwo8n43/ramdisk/ramdisk.cpio.gz.uboot
301 10:03:11.084569 - {KERNEL_ADDR}: 0x82000000
302 10:03:11.085008 - {KERNEL}: 880284/tftp-deploy-qnwo8n43/kernel/zImage
303 10:03:11.085454 - {LAVA_MAC}: None
304 10:03:11.085964 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/880284/extract-nfsrootfs-hcsdta_m
305 10:03:11.086419 - {NFS_SERVER_IP}: 192.168.6.3
306 10:03:11.086863 - {PRESEED_CONFIG}: None
307 10:03:11.087304 - {PRESEED_LOCAL}: None
308 10:03:11.087741 - {RAMDISK_ADDR}: 0x83000000
309 10:03:11.088178 - {RAMDISK}: 880284/tftp-deploy-qnwo8n43/ramdisk/ramdisk.cpio.gz.uboot
310 10:03:11.088617 - {ROOT_PART}: None
311 10:03:11.089048 - {ROOT}: None
312 10:03:11.089478 - {SERVER_IP}: 192.168.6.3
313 10:03:11.089937 - {TEE_ADDR}: 0x83000000
314 10:03:11.090376 - {TEE}: None
315 10:03:11.090811 Parsed boot commands:
316 10:03:11.091232 - setenv autoload no
317 10:03:11.091662 - setenv initrd_high 0xffffffff
318 10:03:11.092087 - setenv fdt_high 0xffffffff
319 10:03:11.092511 - dhcp
320 10:03:11.092936 - setenv serverip 192.168.6.3
321 10:03:11.093358 - tftp 0x82000000 880284/tftp-deploy-qnwo8n43/kernel/zImage
322 10:03:11.093786 - tftp 0x83000000 880284/tftp-deploy-qnwo8n43/ramdisk/ramdisk.cpio.gz.uboot
323 10:03:11.094250 - setenv initrd_size ${filesize}
324 10:03:11.094679 - tftp 0x88000000 880284/tftp-deploy-qnwo8n43/dtb/am335x-boneblack.dtb
325 10:03:11.095108 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/880284/extract-nfsrootfs-hcsdta_m,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 10:03:11.095552 - bootz 0x82000000 0x83000000 0x88000000
327 10:03:11.096100 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 10:03:11.097749 start: 2.3 connect-device (timeout 00:05:00) [common]
330 10:03:11.098256 [common] connect-device Connecting to device using 'telnet conserv3 3000'
331 10:03:11.114019 Setting prompt string to ['lava-test: # ']
332 10:03:11.115591 end: 2.3 connect-device (duration 00:00:00) [common]
333 10:03:11.116275 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 10:03:11.116888 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 10:03:11.117496 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 10:03:11.118873 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
337 10:03:11.156989 >> OK - accepted request
338 10:03:11.159017 Returned 0 in 0 seconds
339 10:03:11.260165 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 10:03:11.261920 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 10:03:11.262578 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 10:03:11.263164 Setting prompt string to ['Hit any key to stop autoboot']
344 10:03:11.263681 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 10:03:11.265374 Trying 192.168.56.22...
346 10:03:11.265934 Connected to conserv3.
347 10:03:11.266420 Escape character is '^]'.
348 10:03:11.266894
349 10:03:11.267365 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 10:03:11.267833
351 10:03:20.234676
352 10:03:20.241637 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
353 10:03:20.242198 Trying to boot from MMC1
354 10:03:20.827174
355 10:03:20.827617
356 10:03:20.832647 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
357 10:03:20.833082
358 10:03:20.833416 CPU : AM335X-GP rev 2.0
359 10:03:20.837893 Model: TI AM335x BeagleBone Black
360 10:03:20.838205 DRAM: 512 MiB
361 10:03:24.290744
362 10:03:24.297713 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
363 10:03:24.298103 Trying to boot from MMC1
364 10:03:24.882800
365 10:03:24.883251
366 10:03:24.888396 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
367 10:03:24.888997
368 10:03:24.889478 CPU : AM335X-GP rev 2.0
369 10:03:24.893555 Model: TI AM335x BeagleBone Black
370 10:03:24.894135 DRAM: 512 MiB
371 10:03:26.984783
372 10:03:26.991734 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
373 10:03:26.992281 Trying to boot from MMC1
374 10:03:27.577183
375 10:03:27.577905
376 10:03:27.582721 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
377 10:03:27.583289
378 10:03:27.583749 CPU : AM335X-GP rev 2.0
379 10:03:27.587786 Model: TI AM335x BeagleBone Black
380 10:03:27.588344 DRAM: 512 MiB
381 10:03:27.672279 Core: 160 devices, 18 uclasses, devicetree: separate
382 10:03:27.686036 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
383 10:03:28.086849 NAND: 0 MiB
384 10:03:28.096821 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
385 10:03:28.171558 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
386 10:03:28.192919 <ethaddr> not set. Validating first E-fuse MAC
387 10:03:28.222669 Net: eth2: ethernet@4a100000, eth3: usb_ether
389 10:03:28.281268 Hit any key to stop autoboot: 2
390 10:03:28.282188 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
391 10:03:28.282895 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
392 10:03:28.283429 Setting prompt string to ['=>']
393 10:03:28.283953 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
394 10:03:28.290973 0
395 10:03:28.291924 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
396 10:03:28.292461 Sending with 10 millisecond of delay
398 10:03:29.427876 => setenv autoload no
399 10:03:29.438754 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
400 10:03:29.444148 setenv autoload no
401 10:03:29.444926 Sending with 10 millisecond of delay
403 10:03:31.241996 => setenv initrd_high 0xffffffff
404 10:03:31.252808 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
405 10:03:31.253701 setenv initrd_high 0xffffffff
406 10:03:31.254507 Sending with 10 millisecond of delay
408 10:03:32.870893 => setenv fdt_high 0xffffffff
409 10:03:32.881710 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
410 10:03:32.882617 setenv fdt_high 0xffffffff
411 10:03:32.883372 Sending with 10 millisecond of delay
413 10:03:33.175223 => dhcp
414 10:03:33.185882 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
415 10:03:33.186707 dhcp
416 10:03:33.188532 link up on port 0, speed 100, full duplex
417 10:03:33.189009 BOOTP broadcast 1
418 10:03:33.440937 BOOTP broadcast 2
419 10:03:33.943043 BOOTP broadcast 3
420 10:03:34.945083 BOOTP broadcast 4
421 10:03:36.946955 BOOTP broadcast 5
422 10:03:37.045837 DHCP client bound to address 192.168.6.23 (3854 ms)
423 10:03:37.046666 Sending with 10 millisecond of delay
425 10:03:38.723297 => setenv serverip 192.168.6.3
426 10:03:38.734085 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
427 10:03:38.734933 setenv serverip 192.168.6.3
428 10:03:38.735676 Sending with 10 millisecond of delay
430 10:03:42.218831 => tftp 0x82000000 880284/tftp-deploy-qnwo8n43/kernel/zImage
431 10:03:42.229699 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
432 10:03:42.230765 tftp 0x82000000 880284/tftp-deploy-qnwo8n43/kernel/zImage
433 10:03:42.231235 link up on port 0, speed 100, full duplex
434 10:03:42.234682 Using ethernet@4a100000 device
435 10:03:42.240141 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
436 10:03:42.240616 Filename '880284/tftp-deploy-qnwo8n43/kernel/zImage'.
437 10:03:42.247333 Load address: 0x82000000
438 10:03:44.372642 Loading: *################################################## 11 MiB
439 10:03:44.373290 5.2 MiB/s
440 10:03:44.373758 done
441 10:03:44.376762 Bytes transferred = 11485696 (af4200 hex)
442 10:03:44.377533 Sending with 10 millisecond of delay
444 10:03:48.823359 => tftp 0x83000000 880284/tftp-deploy-qnwo8n43/ramdisk/ramdisk.cpio.gz.uboot
445 10:03:48.834166 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
446 10:03:48.835072 tftp 0x83000000 880284/tftp-deploy-qnwo8n43/ramdisk/ramdisk.cpio.gz.uboot
447 10:03:48.835534 link up on port 0, speed 100, full duplex
448 10:03:48.838816 Using ethernet@4a100000 device
449 10:03:48.844496 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
450 10:03:48.853158 Filename '880284/tftp-deploy-qnwo8n43/ramdisk/ramdisk.cpio.gz.uboot'.
451 10:03:48.853686 Load address: 0x83000000
452 10:03:51.632600 Loading: *################################################## 14.1 MiB
453 10:03:51.633237 5.1 MiB/s
454 10:03:51.633705 done
455 10:03:51.637031 Bytes transferred = 14812129 (e203e1 hex)
456 10:03:51.637876 Sending with 10 millisecond of delay
458 10:03:53.494929 => setenv initrd_size ${filesize}
459 10:03:53.505739 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
460 10:03:53.506684 setenv initrd_size ${filesize}
461 10:03:53.507431 Sending with 10 millisecond of delay
463 10:03:57.671373 => tftp 0x88000000 880284/tftp-deploy-qnwo8n43/dtb/am335x-boneblack.dtb
464 10:03:57.682202 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
465 10:03:57.683100 tftp 0x88000000 880284/tftp-deploy-qnwo8n43/dtb/am335x-boneblack.dtb
466 10:03:57.683560 link up on port 0, speed 100, full duplex
467 10:03:57.687069 Using ethernet@4a100000 device
468 10:03:57.692542 TFTP from server 192.168.6.3; our IP address is 192.168.6.23
469 10:03:57.700871 Filename '880284/tftp-deploy-qnwo8n43/dtb/am335x-boneblack.dtb'.
470 10:03:57.701405 Load address: 0x88000000
471 10:03:57.713123 Loading: *################################################## 68.9 KiB
472 10:03:57.721951 4.5 MiB/s
473 10:03:57.722442 done
474 10:03:57.722876 Bytes transferred = 70544 (11390 hex)
475 10:03:57.723585 Sending with 10 millisecond of delay
477 10:04:10.900541 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/880284/extract-nfsrootfs-hcsdta_m,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 10:04:10.911382 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
479 10:04:10.912292 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/880284/extract-nfsrootfs-hcsdta_m,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 10:04:10.913044 Sending with 10 millisecond of delay
482 10:04:13.251799 => bootz 0x82000000 0x83000000 0x88000000
483 10:04:13.262629 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 10:04:13.263210 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
485 10:04:13.264271 bootz 0x82000000 0x83000000 0x88000000
486 10:04:13.264747 Kernel image @ 0x82000000 [ 0x000000 - 0xaf4200 ]
487 10:04:13.265277 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 10:04:13.270362 Image Name:
489 10:04:13.270843 Created: 2024-10-22 10:03:10 UTC
490 10:04:13.275951 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 10:04:13.281478 Data Size: 14812065 Bytes = 14.1 MiB
492 10:04:13.281986 Load Address: 00000000
493 10:04:13.287580 Entry Point: 00000000
494 10:04:13.456097 Verifying Checksum ... OK
495 10:04:13.456630 ## Flattened Device Tree blob at 88000000
496 10:04:13.462612 Booting using the fdt blob at 0x88000000
497 10:04:13.463080 Working FDT set to 88000000
498 10:04:13.468200 Using Device Tree in place at 88000000, end 8801438f
499 10:04:13.472548 Working FDT set to 88000000
500 10:04:13.485747
501 10:04:13.486256 Starting kernel ...
502 10:04:13.486700
503 10:04:13.487612 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
504 10:04:13.488235 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
505 10:04:13.488715 Setting prompt string to ['Linux version [0-9]']
506 10:04:13.489211 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
507 10:04:13.489715 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
508 10:04:14.329325 [ 0.000000] Booting Linux on physical CPU 0x0
509 10:04:14.335146 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
510 10:04:14.335706 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 10:04:14.336216 Setting prompt string to []
512 10:04:14.336752 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 10:04:14.337247 Using line separator: #'\n'#
514 10:04:14.337689 No login prompt set.
515 10:04:14.338190 Parsing kernel messages
516 10:04:14.338619 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 10:04:14.339463 [login-action] Waiting for messages, (timeout 00:03:57)
518 10:04:14.339931 Waiting using forced prompt support (timeout 00:01:58)
519 10:04:14.351925 [ 0.000000] Linux version 6.12.0-rc4-next-20241022 (KernelCI@build-j350922-arm-gcc-12-multi-v7-defconfig-k6mzw) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Tue Oct 22 09:01:51 UTC 2024
520 10:04:14.357681 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
521 10:04:14.369135 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
522 10:04:14.374768 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
523 10:04:14.380499 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
524 10:04:14.386037 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
525 10:04:14.392664 [ 0.000000] Memory policy: Data cache writeback
526 10:04:14.393128 [ 0.000000] efi: UEFI not found.
527 10:04:14.399435 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
528 10:04:14.405105 [ 0.000000] Zone ranges:
529 10:04:14.410897 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
530 10:04:14.416539 [ 0.000000] Normal empty
531 10:04:14.417006 [ 0.000000] HighMem empty
532 10:04:14.422249 [ 0.000000] Movable zone start for each node
533 10:04:14.422712 [ 0.000000] Early memory node ranges
534 10:04:14.433750 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
535 10:04:14.439112 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
536 10:04:14.460662 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
537 10:04:14.472931 [ 0.000000] CPU: All CPU(s) started in SVC mode.
538 10:04:14.478489 [ 0.000000] AM335X ES2.0 (sgx neon)
539 10:04:14.490178 [ 0.000000] percpu: Embedded 17 pages/cpu s40396 r8192 d21044 u69632
540 10:04:14.507626 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/880284/extract-nfsrootfs-hcsdta_m,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
541 10:04:14.519240 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
542 10:04:14.525112 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
543 10:04:14.536542 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
544 10:04:14.542274 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
545 10:04:14.548653 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
546 10:04:14.577601 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
547 10:04:14.583560 <6>[ 0.000000] trace event string verifier disabled
548 10:04:14.584045 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
549 10:04:14.591609 <6>[ 0.000000] rcu: RCU event tracing is enabled.
550 10:04:14.597347 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
551 10:04:14.603076 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
552 10:04:14.608794 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
553 10:04:14.620324 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
554 10:04:14.628767 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
555 10:04:14.643626 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
556 10:04:14.660931 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
557 10:04:14.667679 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
558 10:04:14.759103 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
559 10:04:14.770435 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
560 10:04:14.777137 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
561 10:04:14.790223 <6>[ 0.019136] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
562 10:04:14.797490 <6>[ 0.033914] Console: colour dummy device 80x30
563 10:04:14.803707 Matched prompt #6: WARNING:
564 10:04:14.804226 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
565 10:04:14.809026 <3>[ 0.038811] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
566 10:04:14.814773 <3>[ 0.045879] This ensures that you still see kernel messages. Please
567 10:04:14.818064 <3>[ 0.052605] update your kernel commandline.
568 10:04:14.858862 <6>[ 0.057219] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
569 10:04:14.864513 <6>[ 0.096144] CPU: Testing write buffer coherency: ok
570 10:04:14.870418 <6>[ 0.101513] CPU0: Spectre v2: using BPIALL workaround
571 10:04:14.870884 <6>[ 0.106976] pid_max: default: 32768 minimum: 301
572 10:04:14.881974 <6>[ 0.112176] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
573 10:04:14.888838 <6>[ 0.119998] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
574 10:04:14.896022 <6>[ 0.129357] CPU0: thread -1, cpu 0, socket -1, mpidr 0
575 10:04:14.903378 <6>[ 0.136463] Setting up static identity map for 0x80300000 - 0x803000ac
576 10:04:14.909721 <6>[ 0.146122] rcu: Hierarchical SRCU implementation.
577 10:04:14.917926 <6>[ 0.151406] rcu: Max phase no-delay instances is 1000.
578 10:04:14.926276 <6>[ 0.162419] EFI services will not be available.
579 10:04:14.932124 <6>[ 0.167693] smp: Bringing up secondary CPUs ...
580 10:04:14.937839 <6>[ 0.172736] smp: Brought up 1 node, 1 CPU
581 10:04:14.943632 <6>[ 0.177138] SMP: Total of 1 processors activated (996.14 BogoMIPS).
582 10:04:14.949535 <6>[ 0.183907] CPU: All CPU(s) started in SVC mode.
583 10:04:14.969942 <6>[ 0.189093] Memory: 405980K/522240K available (16384K kernel code, 2539K rwdata, 6804K rodata, 2048K init, 426K bss, 49064K reserved, 65536K cma-reserved, 0K highmem)
584 10:04:14.970429 <6>[ 0.205383] devtmpfs: initialized
585 10:04:14.992218 <6>[ 0.222542] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
586 10:04:15.003723 <6>[ 0.231107] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
587 10:04:15.009661 <6>[ 0.241561] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
588 10:04:15.020392 <6>[ 0.253911] pinctrl core: initialized pinctrl subsystem
589 10:04:15.029724 <6>[ 0.264536] DMI not present or invalid.
590 10:04:15.038032 <6>[ 0.270408] NET: Registered PF_NETLINK/PF_ROUTE protocol family
591 10:04:15.047499 <6>[ 0.279288] DMA: preallocated 256 KiB pool for atomic coherent allocations
592 10:04:15.062641 <6>[ 0.290824] thermal_sys: Registered thermal governor 'step_wise'
593 10:04:15.063104 <6>[ 0.290983] cpuidle: using governor menu
594 10:04:15.090192 <6>[ 0.326671] No ATAGs?
595 10:04:15.096412 <6>[ 0.329312] hw-breakpoint: debug architecture 0x4 unsupported.
596 10:04:15.106701 <6>[ 0.341338] Serial: AMBA PL011 UART driver
597 10:04:15.139127 <6>[ 0.375422] iommu: Default domain type: Translated
598 10:04:15.148196 <6>[ 0.380770] iommu: DMA domain TLB invalidation policy: strict mode
599 10:04:15.175248 <5>[ 0.410923] SCSI subsystem initialized
600 10:04:15.181057 <6>[ 0.415813] usbcore: registered new interface driver usbfs
601 10:04:15.186870 <6>[ 0.421875] usbcore: registered new interface driver hub
602 10:04:15.195617 <6>[ 0.427659] usbcore: registered new device driver usb
603 10:04:15.201529 <6>[ 0.434182] pps_core: LinuxPPS API ver. 1 registered
604 10:04:15.207277 <6>[ 0.439610] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
605 10:04:15.213064 <6>[ 0.449296] PTP clock support registered
606 10:04:15.218089 <6>[ 0.453753] EDAC MC: Ver: 3.0.0
607 10:04:15.268393 <6>[ 0.502170] scmi_core: SCMI protocol bus registered
608 10:04:15.284057 <6>[ 0.519699] vgaarb: loaded
609 10:04:15.290111 <6>[ 0.523488] clocksource: Switched to clocksource dmtimer
610 10:04:15.324092 <6>[ 0.560159] NET: Registered PF_INET protocol family
611 10:04:15.336694 <6>[ 0.565845] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
612 10:04:15.342456 <6>[ 0.574679] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
613 10:04:15.353895 <6>[ 0.583608] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
614 10:04:15.359676 <6>[ 0.591848] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
615 10:04:15.371312 <6>[ 0.600134] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
616 10:04:15.377107 <6>[ 0.607848] TCP: Hash tables configured (established 4096 bind 4096)
617 10:04:15.382925 <6>[ 0.614778] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
618 10:04:15.388764 <6>[ 0.621784] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
619 10:04:15.396312 <6>[ 0.629395] NET: Registered PF_UNIX/PF_LOCAL protocol family
620 10:04:15.482839 <6>[ 0.713580] RPC: Registered named UNIX socket transport module.
621 10:04:15.483392 <6>[ 0.719969] RPC: Registered udp transport module.
622 10:04:15.488608 <6>[ 0.725110] RPC: Registered tcp transport module.
623 10:04:15.494350 <6>[ 0.730214] RPC: Registered tcp-with-tls transport module.
624 10:04:15.507347 <6>[ 0.736139] RPC: Registered tcp NFSv4.1 backchannel transport module.
625 10:04:15.507825 <6>[ 0.743047] PCI: CLS 0 bytes, default 64
626 10:04:15.514532 <5>[ 0.748861] Initialise system trusted keyrings
627 10:04:15.535706 <6>[ 0.769073] Trying to unpack rootfs image as initramfs...
628 10:04:15.617091 <6>[ 0.847181] workingset: timestamp_bits=30 max_order=17 bucket_order=0
629 10:04:15.621876 <6>[ 0.854730] squashfs: version 4.0 (2009/01/31) Phillip Lougher
630 10:04:15.657292 <5>[ 0.893649] NFS: Registering the id_resolver key type
631 10:04:15.663107 <5>[ 0.899242] Key type id_resolver registered
632 10:04:15.668820 <5>[ 0.903862] Key type id_legacy registered
633 10:04:15.674656 <6>[ 0.908293] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
634 10:04:15.683873 <6>[ 0.915482] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
635 10:04:15.753764 <5>[ 0.990187] Key type asymmetric registered
636 10:04:15.759632 <5>[ 0.994761] Asymmetric key parser 'x509' registered
637 10:04:15.771148 <6>[ 1.000191] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
638 10:04:15.771627 <6>[ 1.008107] io scheduler mq-deadline registered
639 10:04:15.777055 <6>[ 1.013037] io scheduler kyber registered
640 10:04:15.782576 <6>[ 1.017521] io scheduler bfq registered
641 10:04:15.881781 <6>[ 1.114453] ledtrig-cpu: registered to indicate activity on CPUs
642 10:04:16.195817 <6>[ 1.428328] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
643 10:04:16.242188 <6>[ 1.478358] msm_serial: driver initialized
644 10:04:16.248184 <6>[ 1.483154] SuperH (H)SCI(F) driver initialized
645 10:04:16.254100 <6>[ 1.488455] STMicroelectronics ASC driver initialized
646 10:04:16.259344 <6>[ 1.494116] STM32 USART driver initialized
647 10:04:16.385721 <6>[ 1.621428] brd: module loaded
648 10:04:16.415212 <6>[ 1.650944] loop: module loaded
649 10:04:16.456149 <6>[ 1.691631] CAN device driver interface
650 10:04:16.462904 <6>[ 1.696944] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
651 10:04:16.468655 <6>[ 1.704052] e1000e: Intel(R) PRO/1000 Network Driver
652 10:04:16.474439 <6>[ 1.709439] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
653 10:04:16.480175 <6>[ 1.715905] igb: Intel(R) Gigabit Ethernet Network Driver
654 10:04:16.488566 <6>[ 1.721730] igb: Copyright (c) 2007-2014 Intel Corporation.
655 10:04:16.500566 <6>[ 1.731278] pegasus: Pegasus/Pegasus II USB Ethernet driver
656 10:04:16.506429 <6>[ 1.737448] usbcore: registered new interface driver pegasus
657 10:04:16.509243 <6>[ 1.743613] usbcore: registered new interface driver asix
658 10:04:16.514961 <6>[ 1.749463] usbcore: registered new interface driver ax88179_178a
659 10:04:16.520701 <6>[ 1.756053] usbcore: registered new interface driver cdc_ether
660 10:04:16.526542 <6>[ 1.762351] usbcore: registered new interface driver smsc75xx
661 10:04:16.538091 <6>[ 1.768582] usbcore: registered new interface driver smsc95xx
662 10:04:16.543858 <6>[ 1.774811] usbcore: registered new interface driver net1080
663 10:04:16.549617 <6>[ 1.780929] usbcore: registered new interface driver cdc_subset
664 10:04:16.555418 <6>[ 1.787354] usbcore: registered new interface driver zaurus
665 10:04:16.560370 <6>[ 1.793405] usbcore: registered new interface driver cdc_ncm
666 10:04:16.570407 <6>[ 1.803127] usbcore: registered new interface driver usb-storage
667 10:04:16.861922 <6>[ 2.096181] i2c_dev: i2c /dev entries driver
668 10:04:16.921704 <5>[ 2.150026] cpuidle: enable-method property 'ti,am3352' found operations
669 10:04:16.927634 <6>[ 2.159607] sdhci: Secure Digital Host Controller Interface driver
670 10:04:16.934984 <6>[ 2.166394] sdhci: Copyright(c) Pierre Ossman
671 10:04:16.942223 <6>[ 2.172794] Synopsys Designware Multimedia Card Interface Driver
672 10:04:16.946732 <6>[ 2.180718] sdhci-pltfm: SDHCI platform and OF driver helper
673 10:04:17.076100 <6>[ 2.304962] usbcore: registered new interface driver usbhid
674 10:04:17.076759 <6>[ 2.311002] usbhid: USB HID core driver
675 10:04:17.126435 <6>[ 2.359983] NET: Registered PF_INET6 protocol family
676 10:04:17.168481 <6>[ 2.404669] Segment Routing with IPv6
677 10:04:17.174202 <6>[ 2.408814] In-situ OAM (IOAM) with IPv6
678 10:04:17.180911 <6>[ 2.413203] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
679 10:04:17.186701 <6>[ 2.420559] NET: Registered PF_PACKET protocol family
680 10:04:17.192549 <6>[ 2.426123] can: controller area network core
681 10:04:17.198371 <6>[ 2.430953] NET: Registered PF_CAN protocol family
682 10:04:17.198988 <6>[ 2.436179] can: raw protocol
683 10:04:17.204182 <6>[ 2.439505] can: broadcast manager protocol
684 10:04:17.210702 <6>[ 2.444122] can: netlink gateway - max_hops=1
685 10:04:17.216767 <5>[ 2.449614] Key type dns_resolver registered
686 10:04:17.223056 <6>[ 2.454679] ThumbEE CPU extension supported.
687 10:04:17.223632 <5>[ 2.459368] Registering SWP/SWPB emulation handler
688 10:04:17.232361 <3>[ 2.465063] omap_voltage_late_init: Voltage driver support not added
689 10:04:17.410877 <5>[ 2.644588] Loading compiled-in X.509 certificates
690 10:04:17.546255 <6>[ 2.769394] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
691 10:04:17.553247 <6>[ 2.786107] pinctrl-single 44e10800.pinmux: 142 pins, size 568
692 10:04:17.579524 <3>[ 2.809762] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
693 10:04:17.762059 <3>[ 2.993368] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
694 10:04:17.969886 <6>[ 3.204530] OMAP GPIO hardware version 0.1
695 10:04:17.990393 <6>[ 3.223097] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
696 10:04:18.082691 <4>[ 3.315039] at24 2-0054: supply vcc not found, using dummy regulator
697 10:04:18.117445 <4>[ 3.349840] at24 2-0055: supply vcc not found, using dummy regulator
698 10:04:18.159572 <4>[ 3.392088] at24 2-0056: supply vcc not found, using dummy regulator
699 10:04:18.200566 <4>[ 3.433058] at24 2-0057: supply vcc not found, using dummy regulator
700 10:04:18.234849 <6>[ 3.468148] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
701 10:04:18.310135 <3>[ 3.539415] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
702 10:04:18.334740 <6>[ 3.560223] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
703 10:04:18.356867 <4>[ 3.586442] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
704 10:04:18.364674 <4>[ 3.595770] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
705 10:04:18.501763 <6>[ 3.734343] omap_rng 48310000.rng: Random Number Generator ver. 20
706 10:04:18.525089 <5>[ 3.760483] random: crng init done
707 10:04:18.563884 <6>[ 3.800082] Freeing initrd memory: 14468K
708 10:04:18.573715 <6>[ 3.804798] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
709 10:04:18.621033 <6>[ 3.851213] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
710 10:04:18.626842 <6>[ 3.861544] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
711 10:04:18.638657 <6>[ 3.868900] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
712 10:04:18.644546 <6>[ 3.876400] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
713 10:04:18.655919 <6>[ 3.884535] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
714 10:04:18.663406 <6>[ 3.896162] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
715 10:04:18.676266 <5>[ 3.905189] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
716 10:04:18.704067 <3>[ 3.934907] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
717 10:04:18.709911 <6>[ 3.943372] edma 49000000.dma: TI EDMA DMA engine driver
718 10:04:18.780906 <3>[ 4.010908] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
719 10:04:18.795315 <6>[ 4.025360] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
720 10:04:18.808675 <3>[ 4.042422] l3-aon-clkctrl:0000:0: failed to disable
721 10:04:18.854020 <6>[ 4.084681] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
722 10:04:18.859707 <6>[ 4.094136] printk: legacy console [ttyS0] enabled
723 10:04:18.862588 <6>[ 4.094136] printk: legacy console [ttyS0] enabled
724 10:04:18.868156 <6>[ 4.104463] printk: legacy bootconsole [omap8250] disabled
725 10:04:18.876930 <6>[ 4.104463] printk: legacy bootconsole [omap8250] disabled
726 10:04:18.914542 <4>[ 4.144258] tps65217-pmic: Failed to locate of_node [id: -1]
727 10:04:18.918121 <4>[ 4.151647] tps65217-bl: Failed to locate of_node [id: -1]
728 10:04:18.934757 <6>[ 4.171346] tps65217 0-0024: TPS65217 ID 0xe version 1.2
729 10:04:18.953071 <6>[ 4.178285] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
730 10:04:18.964741 <6>[ 4.192007] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
731 10:04:18.969580 <6>[ 4.203864] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
732 10:04:18.992434 <6>[ 4.223396] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
733 10:04:18.998261 <6>[ 4.232574] sdhci-omap 48060000.mmc: Got CD GPIO
734 10:04:19.005614 <4>[ 4.237716] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
735 10:04:19.020918 <4>[ 4.251337] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
736 10:04:19.027345 <4>[ 4.259971] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
737 10:04:19.036262 <4>[ 4.268633] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
738 10:04:19.135556 <6>[ 4.368323] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
739 10:04:19.183583 <6>[ 4.414294] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
740 10:04:19.189836 <6>[ 4.422694] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
741 10:04:19.198073 <6>[ 4.431441] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
742 10:04:19.250959 <6>[ 4.484637] mmc0: new high speed SDHC card at address 0001
743 10:04:19.259200 <6>[ 4.494608] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
744 10:04:19.268594 <6>[ 4.505920] mmcblk0: p1
745 10:04:19.286521 <6>[ 4.515338] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
746 10:04:19.308537 <6>[ 4.537005] mmc1: new high speed MMC card at address 0001
747 10:04:19.309028 <6>[ 4.543951] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
748 10:04:19.316709 <6>[ 4.552710] mmcblk1:
749 10:04:19.320920 <6>[ 4.556074] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
750 10:04:19.328233 <6>[ 4.563213] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
751 10:04:19.336900 <6>[ 4.570211] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
752 10:04:21.453388 <6>[ 6.684528] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
753 10:04:21.577311 <5>[ 6.713502] Sending DHCP requests ., OK
754 10:04:21.588577 <6>[ 6.817954] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.23
755 10:04:21.589034 <6>[ 6.826130] IP-Config: Complete:
756 10:04:21.599879 <6>[ 6.829668] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.6.23, mask=255.255.255.0, gw=192.168.6.1
757 10:04:21.605627 <6>[ 6.840181] host=192.168.6.23, domain=, nis-domain=(none)
758 10:04:21.617894 <6>[ 6.846421] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
759 10:04:21.618385 <6>[ 6.846457] nameserver0=10.255.253.1
760 10:04:21.624069 <6>[ 6.859000] clk: Disabling unused clocks
761 10:04:21.629572 <6>[ 6.863717] PM: genpd: Disabling unused power domains
762 10:04:21.648866 <6>[ 6.882506] Freeing unused kernel image (initmem) memory: 2048K
763 10:04:21.656390 <6>[ 6.892196] Run /init as init process
764 10:04:21.681230 Loading, please wait...
765 10:04:21.756781 Starting systemd-udevd version 252.22-1~deb12u1
766 10:04:24.798107 <4>[ 10.027238] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
767 10:04:24.921620 <4>[ 10.150695] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
768 10:04:25.082135 <6>[ 10.318813] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
769 10:04:25.092987 <6>[ 10.324614] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
770 10:04:25.330433 <6>[ 10.564095] hub 1-0:1.0: USB hub found
771 10:04:25.336252 <6>[ 10.571113] tda998x 0-0070: found TDA19988
772 10:04:25.387912 <6>[ 10.623024] hub 1-0:1.0: 1 port detected
773 10:04:28.381851 Begin: Loading essential drivers ... done.
774 10:04:28.387343 Begin: Running /scripts/init-premount ... done.
775 10:04:28.392912 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
776 10:04:28.403201 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
777 10:04:28.412246 Device /sys/class/net/eth0 found
778 10:04:28.412747 done.
779 10:04:28.471076 Begin: Waiting up to 180 secs for any network device to become available ... done.
780 10:04:28.550445 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
781 10:04:28.663359 IP-Config: eth0 guessed broadcast address 192.168.6.255
782 10:04:28.668712 IP-Config: eth0 complete (dhcp from 192.168.6.1):
783 10:04:28.674503 address: 192.168.6.23 broadcast: 192.168.6.255 netmask: 255.255.255.0
784 10:04:28.685514 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
785 10:04:28.686079 rootserver: 192.168.6.1 rootpath:
786 10:04:28.688999 filename :
787 10:04:28.726333 done.
788 10:04:28.735466 Begin: Running /scripts/nfs-bottom ... done.
789 10:04:28.808345 Begin: Running /scripts/init-bottom ... done.
790 10:04:30.237351 <30>[ 15.469695] systemd[1]: System time before build time, advancing clock.
791 10:04:30.458162 <30>[ 15.665106] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
792 10:04:30.466974 <30>[ 15.701869] systemd[1]: Detected architecture arm.
793 10:04:30.479105
794 10:04:30.479571 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
795 10:04:30.479988
796 10:04:30.509789 <30>[ 15.743890] systemd[1]: Hostname set to <debian-bookworm-armhf>.
797 10:04:32.630688 <30>[ 17.862701] systemd[1]: Queued start job for default target graphical.target.
798 10:04:32.647828 <30>[ 17.877678] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
799 10:04:32.655125 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
800 10:04:32.675993 <30>[ 17.906368] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
801 10:04:32.683790 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
802 10:04:32.706588 <30>[ 17.936934] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
803 10:04:32.714660 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
804 10:04:32.734919 <30>[ 17.965525] systemd[1]: Created slice user.slice - User and Session Slice.
805 10:04:32.740745 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
806 10:04:32.770058 <30>[ 17.994838] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
807 10:04:32.776134 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
808 10:04:32.794130 <30>[ 18.024618] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
809 10:04:32.802063 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
810 10:04:32.834980 <30>[ 18.054667] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
811 10:04:32.841515 <30>[ 18.075170] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
812 10:04:32.849049 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
813 10:04:32.873105 <30>[ 18.103989] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
814 10:04:32.880536 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
815 10:04:32.904625 <30>[ 18.135292] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
816 10:04:32.916211 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
817 10:04:32.943732 <30>[ 18.174398] systemd[1]: Reached target paths.target - Path Units.
818 10:04:32.947908 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
819 10:04:32.973368 <30>[ 18.204066] systemd[1]: Reached target remote-fs.target - Remote File Systems.
820 10:04:32.979821 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
821 10:04:33.003483 <30>[ 18.234082] systemd[1]: Reached target slices.target - Slice Units.
822 10:04:33.007922 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
823 10:04:33.033635 <30>[ 18.264294] systemd[1]: Reached target swap.target - Swaps.
824 10:04:33.037537 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
825 10:04:33.063729 <30>[ 18.294308] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
826 10:04:33.071844 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
827 10:04:33.094620 <30>[ 18.325151] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
828 10:04:33.103378 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
829 10:04:33.181443 <30>[ 18.408070] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
830 10:04:33.194979 <30>[ 18.425628] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
831 10:04:33.202982 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
832 10:04:33.226619 <30>[ 18.456255] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
833 10:04:33.232993 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
834 10:04:33.256165 <30>[ 18.486686] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
835 10:04:33.264903 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
836 10:04:33.289624 <30>[ 18.518620] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
837 10:04:33.295178 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
838 10:04:33.322933 <30>[ 18.555223] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
839 10:04:33.334511 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
840 10:04:33.360396 <30>[ 18.585289] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
841 10:04:33.379472 <30>[ 18.603811] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
842 10:04:33.427485 <30>[ 18.659450] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
843 10:04:33.452887 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
844 10:04:33.502205 <30>[ 18.734445] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
845 10:04:33.532027 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
846 10:04:33.596422 <30>[ 18.827064] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
847 10:04:33.611760 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
848 10:04:33.641549 <30>[ 18.872467] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
849 10:04:33.656044 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
850 10:04:33.693689 <30>[ 18.924887] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
851 10:04:33.703409 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
852 10:04:33.735191 <30>[ 18.967336] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
853 10:04:33.758074 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
854 10:04:33.823052 <30>[ 19.054586] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
855 10:04:33.850770 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
856 10:04:33.903640 <30>[ 19.135715] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
857 10:04:33.928596 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
858 10:04:33.982244 <30>[ 19.214758] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
859 10:04:34.001207 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
860 10:04:34.031188 <28>[ 19.255778] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
861 10:04:34.038739 <28>[ 19.270403] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
862 10:04:34.084066 <30>[ 19.317072] systemd[1]: Starting systemd-journald.service - Journal Service...
863 10:04:34.102178 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
864 10:04:34.174139 <30>[ 19.405719] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
865 10:04:34.202645 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
866 10:04:34.245309 <30>[ 19.476698] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
867 10:04:34.292145 Starting [0;1;39msystemd-network-g… units from Kernel command line...
868 10:04:34.370800 <30>[ 19.601742] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
869 10:04:34.432788 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
870 10:04:34.495032 <30>[ 19.726860] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
871 10:04:34.542671 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
872 10:04:34.603585 <30>[ 19.836261] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
873 10:04:34.648563 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
874 10:04:34.676012 <30>[ 19.908553] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
875 10:04:34.702909 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
876 10:04:34.735363 <30>[ 19.966559] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
877 10:04:34.766332 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
878 10:04:34.882611 <30>[ 20.115621] systemd[1]: modprobe@configfs.service: Deactivated successfully.
879 10:04:34.913491 <30>[ 20.145043] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
880 10:04:34.942283 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
881 10:04:34.953046 <30>[ 20.186389] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
882 10:04:34.992733 <30>[ 20.225195] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
883 10:04:35.013499 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
884 10:04:35.034279 <30>[ 20.265220] systemd[1]: Started systemd-journald.service - Journal Service.
885 10:04:35.040192 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
886 10:04:35.084404 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
887 10:04:35.108565 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
888 10:04:35.143499 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
889 10:04:35.168198 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
890 10:04:35.203207 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
891 10:04:35.232312 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
892 10:04:35.255623 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
893 10:04:35.287143 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
894 10:04:35.352887 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
895 10:04:35.417109 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
896 10:04:35.493238 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
897 10:04:35.598402 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
898 10:04:35.648946 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
899 10:04:35.742259 <46>[ 20.974351] systemd-journald[164]: Received client request to flush runtime journal.
900 10:04:35.778709 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
901 10:04:35.944373 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
902 10:04:36.744472 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
903 10:04:37.081957 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
904 10:04:37.145514 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
905 10:04:37.473291 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
906 10:04:37.685464 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
907 10:04:37.733294 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
908 10:04:37.752149 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
909 10:04:37.827097 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
910 10:04:37.876269 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
911 10:04:38.814791 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
912 10:04:38.879091 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
913 10:04:38.967508 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
914 10:04:39.093033 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
915 10:04:39.115374 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
916 10:04:41.218952 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
917 10:04:41.775040 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
918 10:04:41.904466 <5>[ 27.136660] cfg80211: Loading compiled-in X.509 certificates for regulatory database
919 10:04:42.647895 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
920 10:04:43.272404 <5>[ 28.506281] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
921 10:04:43.359018 <5>[ 28.587957] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
922 10:04:43.364845 <4>[ 28.598372] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
923 10:04:43.372739 <6>[ 28.607500] cfg80211: failed to load regulatory.db
924 10:04:43.703975 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
925 10:04:43.872503 <46>[ 29.095314] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
926 10:04:44.039637 <46>[ 29.264506] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
927 10:04:44.530125 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
928 10:04:53.251875 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
929 10:04:53.278453 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
930 10:04:53.304016 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
931 10:04:53.325092 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
932 10:04:53.398633 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
933 10:04:53.444884 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
934 10:04:53.525734 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
935 10:04:53.591629 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
936 10:04:53.636755 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
937 10:04:53.671765 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
938 10:04:53.699530 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
939 10:04:53.728484 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
940 10:04:53.768660 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
941 10:04:53.800343 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
942 10:04:53.836282 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
943 10:04:53.865745 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
944 10:04:53.894367 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
945 10:04:53.918217 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
946 10:04:53.943688 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
947 10:04:53.964646 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
948 10:04:54.013871 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
949 10:04:54.031662 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
950 10:04:54.054605 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
951 10:04:54.134030 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
952 10:04:54.168045 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
953 10:04:54.256978 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
954 10:04:54.359632 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
955 10:04:54.438306 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
956 10:04:54.479791 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
957 10:04:54.503347 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
958 10:04:54.710953 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
959 10:04:54.762886 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
960 10:04:54.823288 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
961 10:04:54.843078 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
962 10:04:54.880643 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
963 10:04:55.102388 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
964 10:04:55.444418 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
965 10:04:55.478753 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
966 10:04:55.512730 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
967 10:04:55.575792 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
968 10:04:55.749870 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
969 10:04:55.902233
970 10:04:55.906167 Debian GNU/Linux 12 debian-rm-armhf login: root (automatic login)
971 10:04:55.906754
972 10:04:56.231752 Linux debian-bookworm-armhf 6.12.0-rc4-next-20241022 #1 SMP Tue Oct 22 09:01:51 UTC 2024 armv7l
973 10:04:56.232327
974 10:04:56.237295 The programs included with the Debian GNU/Linux system are free software;
975 10:04:56.242880 the exact distribution terms for each program are described in the
976 10:04:56.248416 individual files in /usr/share/doc/*/copyright.
977 10:04:56.248871
978 10:04:56.254041 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
979 10:04:56.257672 permitted by applicable law.
980 10:05:00.906673 Unable to match end of the kernel message
982 10:05:00.908232 Setting prompt string to ['/ #']
983 10:05:00.908795 end: 2.4.4.1 login-action (duration 00:00:47) [common]
985 10:05:00.910183 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
986 10:05:00.910730 start: 2.4.5 expect-shell-connection (timeout 00:03:10) [common]
987 10:05:00.911209 Setting prompt string to ['/ #']
988 10:05:00.911643 Forcing a shell prompt, looking for ['/ #']
990 10:05:00.962590 / #
991 10:05:00.963276 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
992 10:05:00.963772 Waiting using forced prompt support (timeout 00:02:30)
993 10:05:00.967065
994 10:05:00.974397 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
995 10:05:00.974947 start: 2.4.6 export-device-env (timeout 00:03:10) [common]
996 10:05:00.975392 Sending with 10 millisecond of delay
998 10:05:05.963279 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/880284/extract-nfsrootfs-hcsdta_m'
999 10:05:05.974211 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/880284/extract-nfsrootfs-hcsdta_m'
1000 10:05:05.975505 Sending with 10 millisecond of delay
1002 10:05:08.073722 / # export NFS_SERVER_IP='192.168.6.3'
1003 10:05:08.084752 export NFS_SERVER_IP='192.168.6.3'
1004 10:05:08.086330 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1005 10:05:08.086963 end: 2.4 uboot-commands (duration 00:01:57) [common]
1006 10:05:08.087572 end: 2 uboot-action (duration 00:01:57) [common]
1007 10:05:08.088165 start: 3 lava-test-retry (timeout 00:06:53) [common]
1008 10:05:08.088777 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1009 10:05:08.089275 Using namespace: common
1011 10:05:08.190595 / # #
1012 10:05:08.191351 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1013 10:05:08.196022 #
1014 10:05:08.201965 Using /lava-880284
1016 10:05:08.303251 / # export SHELL=/bin/bash
1017 10:05:08.308253 export SHELL=/bin/bash
1019 10:05:08.415211 / # . /lava-880284/environment
1020 10:05:08.420668 . /lava-880284/environment
1022 10:05:08.533339 / # /lava-880284/bin/lava-test-runner /lava-880284/0
1023 10:05:08.534380 Test shell timeout: 10s (minimum of the action and connection timeout)
1024 10:05:08.539124 /lava-880284/bin/lava-test-runner /lava-880284/0
1025 10:05:08.923500 + export TESTRUN_ID=0_timesync-off
1026 10:05:08.930239 + TESTRUN_ID=0_timesync-off
1027 10:05:08.930889 + cd /lava-880284/0/tests/0_timesync-off
1028 10:05:08.931449 ++ cat uuid
1029 10:05:08.947475 + UUID=880284_1.6.2.4.1
1030 10:05:08.948012 + set +x
1031 10:05:08.956110 <LAVA_SIGNAL_STARTRUN 0_timesync-off 880284_1.6.2.4.1>
1032 10:05:08.956611 + systemctl stop systemd-timesyncd
1033 10:05:08.957374 Received signal: <STARTRUN> 0_timesync-off 880284_1.6.2.4.1
1034 10:05:08.957901 Starting test lava.0_timesync-off (880284_1.6.2.4.1)
1035 10:05:08.958524 Skipping test definition patterns.
1036 10:05:09.292696 + set +x
1037 10:05:09.293356 <LAVA_SIGNAL_ENDRUN 0_timesync-off 880284_1.6.2.4.1>
1038 10:05:09.294091 Received signal: <ENDRUN> 0_timesync-off 880284_1.6.2.4.1
1039 10:05:09.294634 Ending use of test pattern.
1040 10:05:09.295076 Ending test lava.0_timesync-off (880284_1.6.2.4.1), duration 0.34
1042 10:05:09.459972 + export TESTRUN_ID=1_kselftest-dt
1043 10:05:09.466777 + TESTRUN_ID=1_kselftest-dt
1044 10:05:09.467267 + cd /lava-880284/0/tests/1_kselftest-dt
1045 10:05:09.467717 ++ cat uuid
1046 10:05:09.490780 + UUID=880284_1.6.2.4.5
1047 10:05:09.491357 + set +x
1048 10:05:09.496285 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 880284_1.6.2.4.5>
1049 10:05:09.496829 + cd ./automated/linux/kselftest/
1050 10:05:09.497544 Received signal: <STARTRUN> 1_kselftest-dt 880284_1.6.2.4.5
1051 10:05:09.498055 Starting test lava.1_kselftest-dt (880284_1.6.2.4.5)
1052 10:05:09.498602 Skipping test definition patterns.
1053 10:05:09.521615 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1054 10:05:09.630843 INFO: install_deps skipped
1055 10:05:10.209083 --2024-10-22 10:05:10-- http://storage.kernelci.org/next/master/next-20241022/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1056 10:05:10.243990 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1057 10:05:10.390909 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1058 10:05:10.533208 HTTP request sent, awaiting response... 200 OK
1059 10:05:10.533851 Length: 3835488 (3.7M) [application/octet-stream]
1060 10:05:10.538690 Saving to: 'kselftest_armhf.tar.gz'
1061 10:05:10.539161
1062 10:05:12.125804
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 177KB/s
kselftest_armhf.tar 5%[> ] 194.76K 346KB/s
kselftest_armhf.tar 17%[==> ] 667.26K 815KB/s
kselftest_armhf.tar 39%[======> ] 1.43M 1.28MB/s
kselftest_armhf.tar 88%[================> ] 3.25M 2.25MB/s
kselftest_armhf.tar 100%[===================>] 3.66M 2.30MB/s in 1.6s
1063 10:05:12.127473
1064 10:05:12.613708 2024-10-22 10:05:12 (2.30 MB/s) - 'kselftest_armhf.tar.gz' saved [3835488/3835488]
1065 10:05:12.614417
1066 10:05:27.097518 skiplist:
1067 10:05:27.098114 ========================================
1068 10:05:27.103269 ========================================
1069 10:05:27.204926 dt:test_unprobed_devices.sh
1070 10:05:27.238999 ============== Tests to run ===============
1071 10:05:27.246849 dt:test_unprobed_devices.sh
1072 10:05:27.250101 ===========End Tests to run ===============
1073 10:05:27.261437 shardfile-dt pass
1074 10:05:27.498065 <12>[ 72.736156] kselftest: Running tests in dt
1075 10:05:27.527160 TAP version 13
1076 10:05:27.550038 1..1
1077 10:05:27.603186 # timeout set to 45
1078 10:05:27.603759 # selftests: dt: test_unprobed_devices.sh
1079 10:05:28.479461 # TAP version 13
1080 10:05:53.282121 # 1..257
1081 10:05:53.469370 # ok 1 / # SKIP
1082 10:05:53.496934 # ok 2 /clk_mcasp0
1083 10:05:53.564409 # ok 3 /clk_mcasp0_fixed # SKIP
1084 10:05:53.637688 # ok 4 /cpus/cpu@0 # SKIP
1085 10:05:53.709000 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1086 10:05:53.729232 # ok 6 /fixedregulator0
1087 10:05:53.749327 # ok 7 /leds
1088 10:05:53.765311 # ok 8 /ocp
1089 10:05:53.789840 # ok 9 /ocp/interconnect@44c00000
1090 10:05:53.815233 # ok 10 /ocp/interconnect@44c00000/segment@0
1091 10:05:53.836256 # ok 11 /ocp/interconnect@44c00000/segment@100000
1092 10:05:53.860636 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1093 10:05:53.936210 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1094 10:05:53.955581 # ok 14 /ocp/interconnect@44c00000/segment@200000
1095 10:05:53.981179 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1096 10:05:54.085285 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1097 10:05:54.157310 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1098 10:05:54.229052 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1099 10:05:54.299760 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1100 10:05:54.367507 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1101 10:05:54.439211 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1102 10:05:54.515213 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1103 10:05:54.586302 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1104 10:05:54.653435 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1105 10:05:54.724306 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1106 10:05:54.795021 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1107 10:05:54.866839 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1108 10:05:54.937646 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1109 10:05:55.013265 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1110 10:05:55.079356 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1111 10:05:55.157399 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1112 10:05:55.227214 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1113 10:05:55.298740 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1114 10:05:55.366189 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1115 10:05:55.440494 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1116 10:05:55.508269 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1117 10:05:55.582972 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1118 10:05:55.654557 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1119 10:05:55.726792 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1120 10:05:55.798238 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1121 10:05:55.869118 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1122 10:05:55.941188 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1123 10:05:56.013287 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1124 10:05:56.085070 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1125 10:05:56.156069 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1126 10:05:56.227822 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1127 10:05:56.298590 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1128 10:05:56.372763 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1129 10:05:56.447637 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1130 10:05:56.520926 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1131 10:05:56.597208 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1132 10:05:56.668090 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1133 10:05:56.739564 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1134 10:05:56.810458 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1135 10:05:56.878054 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1136 10:05:56.949985 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1137 10:05:57.021364 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1138 10:05:57.092144 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1139 10:05:57.163833 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1140 10:05:57.237204 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1141 10:05:57.308396 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1142 10:05:57.379677 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1143 10:05:57.452010 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1144 10:05:57.527821 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1145 10:05:57.597824 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1146 10:05:57.670266 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1147 10:05:57.738972 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1148 10:05:57.813332 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1149 10:05:57.886257 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1150 10:05:57.957879 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1151 10:05:58.030354 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1152 10:05:58.097783 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1153 10:05:58.176928 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1154 10:05:58.248937 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1155 10:05:58.320534 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1156 10:05:58.388126 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1157 10:05:58.460693 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1158 10:05:58.531146 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1159 10:05:58.608557 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1160 10:05:58.680338 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1161 10:05:58.747658 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1162 10:05:58.819193 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1163 10:05:59.150294 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1164 10:05:59.150929 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1165 10:05:59.151373 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1166 10:05:59.153418 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1167 10:05:59.178102 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1168 10:05:59.249896 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1169 10:05:59.329757 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1170 10:05:59.401669 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1171 10:05:59.466857 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1172 10:05:59.540242 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1173 10:05:59.616541 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1174 10:05:59.690472 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1175 10:05:59.707158 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1176 10:05:59.730181 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1177 10:05:59.754745 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1178 10:05:59.782496 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1179 10:05:59.807149 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1180 10:05:59.828397 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1181 10:05:59.850723 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1182 10:05:59.872619 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1183 10:05:59.976779 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1184 10:06:00.002193 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1185 10:06:00.026218 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1186 10:06:00.049844 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1187 10:06:00.154894 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1188 10:06:00.227999 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1189 10:06:00.300540 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1190 10:06:00.372518 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1191 10:06:00.444119 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1192 10:06:00.515887 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1193 10:06:00.587544 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1194 10:06:00.660482 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1195 10:06:00.732476 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1196 10:06:00.804524 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1197 10:06:00.876764 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1198 10:06:00.950157 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1199 10:06:01.022681 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1200 10:06:01.099677 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1201 10:06:01.168302 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1202 10:06:01.239928 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1203 10:06:01.266029 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1204 10:06:01.337139 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1205 10:06:01.405277 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1206 10:06:01.478430 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1207 10:06:01.500031 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1208 10:06:01.567599 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1209 10:06:01.591135 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1210 10:06:01.668051 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1211 10:06:01.688992 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1212 10:06:01.712907 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1213 10:06:01.735402 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1214 10:06:01.758951 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1215 10:06:01.786194 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1216 10:06:01.807546 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1217 10:06:01.831132 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
1218 10:06:01.904407 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
1219 10:06:01.926871 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1220 10:06:01.949634 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1221 10:06:02.020713 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1222 10:06:02.095927 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1223 10:06:02.116809 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1224 10:06:02.211337 # not ok 144 /ocp/interconnect@47c00000
1225 10:06:02.285474 # not ok 145 /ocp/interconnect@47c00000/segment@0
1226 10:06:02.308976 # ok 146 /ocp/interconnect@48000000
1227 10:06:02.331565 # ok 147 /ocp/interconnect@48000000/segment@0
1228 10:06:02.356902 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1229 10:06:02.375552 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1230 10:06:02.398783 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1231 10:06:02.421735 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1232 10:06:02.444647 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1233 10:06:02.473628 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1234 10:06:02.496317 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1235 10:06:02.567114 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1236 10:06:02.634952 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1237 10:06:02.659805 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1238 10:06:02.680287 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1239 10:06:02.703576 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1240 10:06:02.732639 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1241 10:06:02.750563 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1242 10:06:02.774611 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1243 10:06:02.800855 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1244 10:06:02.825788 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1245 10:06:02.846956 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1246 10:06:02.871657 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1247 10:06:02.890277 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1248 10:06:02.917300 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1249 10:06:02.937675 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1250 10:06:02.965806 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1251 10:06:02.986811 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1252 10:06:03.009024 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1253 10:06:03.035204 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1254 10:06:03.059440 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1255 10:06:03.074509 # ok 175 /ocp/interconnect@48000000/segment@100000
1256 10:06:03.100184 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1257 10:06:03.124114 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1258 10:06:03.196477 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
1259 10:06:03.270338 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
1260 10:06:03.338576 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
1261 10:06:03.412725 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
1262 10:06:03.482587 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
1263 10:06:03.555823 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
1264 10:06:03.625427 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
1265 10:06:03.698533 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
1266 10:06:04.016284 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1267 10:06:04.016852 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1268 10:06:04.017325 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1269 10:06:04.018232 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1270 10:06:04.018711 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1271 10:06:04.019156 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1272 10:06:04.019596 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1273 10:06:04.020034 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1274 10:06:04.020466 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1275 10:06:04.020897 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1276 10:06:04.021325 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1277 10:06:04.021753 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1278 10:06:04.022696 # ok 198 /ocp/interconnect@48000000/segment@200000
1279 10:06:04.026844 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1280 10:06:04.097100 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1281 10:06:04.117123 # ok 201 /ocp/interconnect@48000000/segment@300000
1282 10:06:04.141002 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1283 10:06:04.164368 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1284 10:06:04.188613 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1285 10:06:04.215404 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1286 10:06:04.237055 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1287 10:06:04.257770 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1288 10:06:04.332219 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1289 10:06:04.346024 # ok 209 /ocp/interconnect@4a000000
1290 10:06:04.373798 # ok 210 /ocp/interconnect@4a000000/segment@0
1291 10:06:04.394323 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1292 10:06:04.418486 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1293 10:06:04.447466 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1294 10:06:04.466750 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1295 10:06:04.537936 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1296 10:06:04.641725 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1297 10:06:04.717701 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1298 10:06:04.815628 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1299 10:06:04.886619 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1300 10:06:04.960326 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1301 10:06:05.056184 # not ok 221 /ocp/interconnect@4b140000
1302 10:06:05.127834 # not ok 222 /ocp/interconnect@4b140000/segment@0
1303 10:06:05.198098 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1304 10:06:05.222878 # ok 224 /ocp/target-module@40300000
1305 10:06:05.244769 # ok 225 /ocp/target-module@40300000/sram@0
1306 10:06:05.314988 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1307 10:06:05.386428 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1308 10:06:05.406037 # ok 228 /ocp/target-module@47400000
1309 10:06:05.434431 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1310 10:06:05.455229 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1311 10:06:05.480698 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1312 10:06:05.498139 # ok 232 /ocp/target-module@47400000/usb@1400
1313 10:06:05.520338 # ok 233 /ocp/target-module@47400000/usb@1800
1314 10:06:05.541698 # ok 234 /ocp/target-module@47810000
1315 10:06:05.568655 # ok 235 /ocp/target-module@49000000
1316 10:06:05.591483 # ok 236 /ocp/target-module@49000000/dma@0
1317 10:06:05.612914 # ok 237 /ocp/target-module@49800000
1318 10:06:05.630627 # ok 238 /ocp/target-module@49800000/dma@0
1319 10:06:05.654199 # ok 239 /ocp/target-module@49900000
1320 10:06:05.676328 # ok 240 /ocp/target-module@49900000/dma@0
1321 10:06:05.701015 # ok 241 /ocp/target-module@49a00000
1322 10:06:05.724689 # ok 242 /ocp/target-module@49a00000/dma@0
1323 10:06:05.742112 # ok 243 /ocp/target-module@4c000000
1324 10:06:05.815137 # not ok 244 /ocp/target-module@4c000000/emif@0
1325 10:06:05.838965 # ok 245 /ocp/target-module@50000000
1326 10:06:05.861064 # ok 246 /ocp/target-module@53100000
1327 10:06:05.931970 # not ok 247 /ocp/target-module@53100000/sham@0
1328 10:06:05.952764 # ok 248 /ocp/target-module@53500000
1329 10:06:06.020174 # not ok 249 /ocp/target-module@53500000/aes@0
1330 10:06:06.044182 # ok 250 /ocp/target-module@56000000
1331 10:06:06.148255 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1332 10:06:06.213784 # ok 252 /opp-table # SKIP
1333 10:06:06.283292 # ok 253 /soc # SKIP
1334 10:06:06.308508 # ok 254 /sound
1335 10:06:06.326775 # ok 255 /target-module@4b000000
1336 10:06:06.355486 # ok 256 /target-module@4b000000/target-module@140000
1337 10:06:06.372960 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1338 10:06:06.382954 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1339 10:06:06.390777 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1340 10:06:08.544766 dt_test_unprobed_devices_sh_ skip
1341 10:06:08.550175 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1342 10:06:08.555639 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1343 10:06:08.556189 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1344 10:06:08.561321 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1345 10:06:08.567053 dt_test_unprobed_devices_sh_fixedregulator0 pass
1346 10:06:08.572603 dt_test_unprobed_devices_sh_leds pass
1347 10:06:08.573098 dt_test_unprobed_devices_sh_ocp pass
1348 10:06:08.578752 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1349 10:06:08.583945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1350 10:06:08.589286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1351 10:06:08.600387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1352 10:06:08.606209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1353 10:06:08.611722 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1354 10:06:08.623103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1355 10:06:08.628591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1356 10:06:08.639817 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1357 10:06:08.650913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1358 10:06:08.662113 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1359 10:06:08.667797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1360 10:06:08.678940 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1361 10:06:08.690130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1362 10:06:08.701345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1363 10:06:08.712580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1364 10:06:08.718157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1365 10:06:08.729315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1366 10:06:08.740492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1367 10:06:08.751672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1368 10:06:08.762968 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1369 10:06:08.768566 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1370 10:06:08.779689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1371 10:06:08.790945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1372 10:06:08.802085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1373 10:06:08.807705 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1374 10:06:08.818859 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1375 10:06:08.830099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1376 10:06:08.841217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1377 10:06:08.852429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1378 10:06:08.858105 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1379 10:06:08.869213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1380 10:06:08.880412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1381 10:06:08.891596 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1382 10:06:08.902813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1383 10:06:08.914049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1384 10:06:08.925159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1385 10:06:08.936344 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1386 10:06:08.947560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1387 10:06:08.958743 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1388 10:06:08.970061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1389 10:06:08.981122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1390 10:06:08.992303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1391 10:06:09.003522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1392 10:06:09.014674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1393 10:06:09.025905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1394 10:06:09.037049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1395 10:06:09.048280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1396 10:06:09.059441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1397 10:06:09.070667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1398 10:06:09.081787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1399 10:06:09.093060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1400 10:06:09.104258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1401 10:06:09.115412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1402 10:06:09.126645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1403 10:06:09.137840 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1404 10:06:09.143456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1405 10:06:09.154589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1406 10:06:09.165784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1407 10:06:09.176997 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1408 10:06:09.188136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1409 10:06:09.199365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1410 10:06:09.210535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1411 10:06:09.221737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1412 10:06:09.232945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1413 10:06:09.244156 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1414 10:06:09.255349 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1415 10:06:09.266490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1416 10:06:09.277689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1417 10:06:09.288863 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1418 10:06:09.300062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1419 10:06:09.311251 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1420 10:06:09.322474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1421 10:06:09.333652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1422 10:06:09.339315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1423 10:06:09.350442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1424 10:06:09.361636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1425 10:06:09.372851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1426 10:06:09.384016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1427 10:06:09.389626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1428 10:06:09.406360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1429 10:06:09.417579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1430 10:06:09.423232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1431 10:06:09.440026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1432 10:06:09.451159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1433 10:06:09.462322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1434 10:06:09.467968 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1435 10:06:09.479129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1436 10:06:09.490296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1437 10:06:09.495955 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1438 10:06:09.507054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1439 10:06:09.518254 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1440 10:06:09.523906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1441 10:06:09.535077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1442 10:06:09.540691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1443 10:06:09.551834 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1444 10:06:09.563051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1445 10:06:09.574246 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1446 10:06:09.585408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1447 10:06:09.596622 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1448 10:06:09.607804 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1449 10:06:09.619046 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1450 10:06:09.630219 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1451 10:06:09.641368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1452 10:06:09.652578 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1453 10:06:09.663772 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1454 10:06:09.674958 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1455 10:06:09.691778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1456 10:06:09.702963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1457 10:06:09.714120 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1458 10:06:09.725354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1459 10:06:09.736520 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1460 10:06:09.753262 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1461 10:06:09.764485 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1462 10:06:09.775691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1463 10:06:09.786873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1464 10:06:09.792523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1465 10:06:09.803639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1466 10:06:09.814854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1467 10:06:09.820482 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1468 10:06:09.831645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1469 10:06:09.837267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1470 10:06:09.848450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1471 10:06:09.854135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1472 10:06:09.865208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1473 10:06:09.870913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1474 10:06:09.882099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1475 10:06:09.887682 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1476 10:06:09.898805 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
1477 10:06:09.910032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
1478 10:06:09.921208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1479 10:06:09.926849 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1480 10:06:09.938098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1481 10:06:09.949207 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1482 10:06:09.954931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1483 10:06:09.960560 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1484 10:06:09.971708 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1485 10:06:09.972282 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1486 10:06:09.982949 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1487 10:06:09.988673 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1488 10:06:09.994263 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1489 10:06:10.005409 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1490 10:06:10.011088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1491 10:06:10.022208 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1492 10:06:10.027901 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1493 10:06:10.038998 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1494 10:06:10.044675 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1495 10:06:10.050278 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1496 10:06:10.061389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1497 10:06:10.067044 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1498 10:06:10.078160 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1499 10:06:10.083839 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1500 10:06:10.094981 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1501 10:06:10.100608 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1502 10:06:10.111733 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1503 10:06:10.117420 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1504 10:06:10.128543 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1505 10:06:10.134241 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1506 10:06:10.145306 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1507 10:06:10.150917 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1508 10:06:10.156514 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1509 10:06:10.167649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1510 10:06:10.173311 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1511 10:06:10.184457 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1512 10:06:10.190188 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1513 10:06:10.201239 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1514 10:06:10.206888 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1515 10:06:10.218086 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1516 10:06:10.223693 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1517 10:06:10.234824 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
1518 10:06:10.246034 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
1519 10:06:10.257198 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
1520 10:06:10.268383 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
1521 10:06:10.274088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
1522 10:06:10.285170 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
1523 10:06:10.296333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
1524 10:06:10.307592 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
1525 10:06:10.313209 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1526 10:06:10.324330 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1527 10:06:10.330033 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1528 10:06:10.341147 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1529 10:06:10.346770 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1530 10:06:10.357950 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1531 10:06:10.363567 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1532 10:06:10.374707 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1533 10:06:10.380346 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1534 10:06:10.391480 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1535 10:06:10.397223 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1536 10:06:10.408280 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1537 10:06:10.413914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1538 10:06:10.425035 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1539 10:06:10.431262 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1540 10:06:10.436311 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1541 10:06:10.447427 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1542 10:06:10.453097 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1543 10:06:10.464212 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1544 10:06:10.469912 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1545 10:06:10.481006 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1546 10:06:10.486670 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1547 10:06:10.497801 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1548 10:06:10.503432 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1549 10:06:10.509028 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1550 10:06:10.514714 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1551 10:06:10.525732 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1552 10:06:10.531417 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1553 10:06:10.542546 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1554 10:06:10.548236 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1555 10:06:10.559322 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1556 10:06:10.570530 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1557 10:06:10.581659 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1558 10:06:10.592903 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1559 10:06:10.598547 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1560 10:06:10.604164 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1561 10:06:10.609748 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1562 10:06:10.615339 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1563 10:06:10.621005 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1564 10:06:10.626633 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1565 10:06:10.637877 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1566 10:06:10.643419 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1567 10:06:10.649015 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1568 10:06:10.654620 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1569 10:06:10.660267 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1570 10:06:10.671344 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1571 10:06:10.676993 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1572 10:06:10.682584 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1573 10:06:10.688264 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1574 10:06:10.693760 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1575 10:06:10.699401 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1576 10:06:10.704997 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1577 10:06:10.710595 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1578 10:06:10.716271 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1579 10:06:10.721796 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1580 10:06:10.727422 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1581 10:06:10.733022 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1582 10:06:10.738574 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1583 10:06:10.744275 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1584 10:06:10.749845 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1585 10:06:10.755420 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1586 10:06:10.761035 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1587 10:06:10.766619 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1588 10:06:10.772254 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1589 10:06:10.778376 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1590 10:06:10.783946 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1591 10:06:10.784444 dt_test_unprobed_devices_sh_opp-table skip
1592 10:06:10.789564 dt_test_unprobed_devices_sh_soc skip
1593 10:06:10.795168 dt_test_unprobed_devices_sh_sound pass
1594 10:06:10.795662 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1595 10:06:10.806364 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1596 10:06:10.812013 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1597 10:06:10.817630 dt_test_unprobed_devices_sh fail
1598 10:06:10.818156 + ../../utils/send-to-lava.sh ./output/result.txt
1599 10:06:10.825192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1600 10:06:10.826114 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1602 10:06:10.848311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1603 10:06:10.849103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1605 10:06:10.941712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1606 10:06:10.942530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1608 10:06:11.035904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1609 10:06:11.036700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1611 10:06:11.128926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1612 10:06:11.129722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1614 10:06:11.223347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1615 10:06:11.224112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1617 10:06:11.315829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1618 10:06:11.316608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1620 10:06:11.407610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1621 10:06:11.408381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1623 10:06:11.501388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1624 10:06:11.502205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1626 10:06:11.595981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1627 10:06:11.596751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1629 10:06:11.691742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1630 10:06:11.692588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1632 10:06:11.784771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1633 10:06:11.785614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1635 10:06:11.880984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1636 10:06:11.881843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1638 10:06:11.984459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1639 10:06:11.985283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1641 10:06:12.082127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1642 10:06:12.082958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1644 10:06:12.176860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1645 10:06:12.177695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1647 10:06:12.271583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1648 10:06:12.272399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1650 10:06:12.366394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1651 10:06:12.367215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1653 10:06:12.456031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1654 10:06:12.456845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1656 10:06:12.547832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1657 10:06:12.548645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1659 10:06:12.641747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1660 10:06:12.642612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1662 10:06:12.735827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1663 10:06:12.736636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1665 10:06:12.827308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1666 10:06:12.828119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1668 10:06:12.919929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1669 10:06:12.920744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1671 10:06:13.011527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1672 10:06:13.012334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1674 10:06:13.105860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1675 10:06:13.106686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1677 10:06:13.197624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1678 10:06:13.198493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1680 10:06:13.289961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1681 10:06:13.290800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1683 10:06:13.384058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1684 10:06:13.384891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1686 10:06:13.476491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1687 10:06:13.477313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1689 10:06:13.568218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1690 10:06:13.569047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1692 10:06:13.662852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1693 10:06:13.663713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1695 10:06:13.763391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1696 10:06:13.764184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1698 10:06:13.865694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1699 10:06:13.866537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1701 10:06:13.965450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1702 10:06:13.966289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1704 10:06:14.068406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1705 10:06:14.069194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1707 10:06:14.160071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1708 10:06:14.160877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1710 10:06:14.254066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1711 10:06:14.254859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1713 10:06:14.347086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1714 10:06:14.347901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1716 10:06:14.438218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1717 10:06:14.438997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1719 10:06:14.532904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1720 10:06:14.533688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1722 10:06:14.626117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1723 10:06:14.626962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1725 10:06:14.718350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1726 10:06:14.719161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1728 10:06:14.811367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1729 10:06:14.812176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1731 10:06:14.903564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1732 10:06:14.904448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1734 10:06:14.997096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1735 10:06:14.997987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1737 10:06:15.090298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1738 10:06:15.091197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1740 10:06:15.191632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1741 10:06:15.192524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1743 10:06:15.303866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1744 10:06:15.304750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1746 10:06:15.397488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1747 10:06:15.398428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1749 10:06:15.488927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1750 10:06:15.489872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1752 10:06:15.580800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1753 10:06:15.581682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1755 10:06:15.674426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1756 10:06:15.675290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1758 10:06:15.775942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1759 10:06:15.776753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1761 10:06:15.877443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1762 10:06:15.878283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1764 10:06:15.970174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1765 10:06:15.970963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1767 10:06:16.064477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1768 10:06:16.065265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1770 10:06:16.158110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1771 10:06:16.158908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1773 10:06:16.248937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1774 10:06:16.249715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1776 10:06:16.341716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1777 10:06:16.342548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1779 10:06:16.435757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1780 10:06:16.436539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1782 10:06:16.528404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1783 10:06:16.529189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1785 10:06:16.620752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1786 10:06:16.621548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1788 10:06:16.713513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1789 10:06:16.714335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1791 10:06:16.806915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1792 10:06:16.807708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1794 10:06:16.899439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1795 10:06:16.900240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1797 10:06:16.993541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1798 10:06:16.994386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1800 10:06:17.087167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1801 10:06:17.087948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1803 10:06:17.186265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1804 10:06:17.187071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1806 10:06:17.279551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1807 10:06:17.280336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1809 10:06:17.381202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1810 10:06:17.381991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1812 10:06:17.474803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1813 10:06:17.475582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1815 10:06:17.566865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1816 10:06:17.567661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1818 10:06:17.660189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1819 10:06:17.660979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1821 10:06:17.761735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1822 10:06:17.762555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1824 10:06:17.864385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1825 10:06:17.865168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1827 10:06:17.958683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1828 10:06:17.959472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1830 10:06:18.049618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1831 10:06:18.050433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1833 10:06:18.144646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1834 10:06:18.145447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1836 10:06:18.238307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1837 10:06:18.239121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1839 10:06:18.331181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1840 10:06:18.331981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1842 10:06:18.427044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1843 10:06:18.427835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1845 10:06:18.519936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1846 10:06:18.520725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1848 10:06:18.613185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1849 10:06:18.613993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1851 10:06:18.706231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1852 10:06:18.707046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1854 10:06:18.798471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1855 10:06:18.799250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1857 10:06:18.891734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1858 10:06:18.892545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1860 10:06:18.985499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1861 10:06:18.986323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1863 10:06:19.079720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1864 10:06:19.080517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1866 10:06:19.173563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1867 10:06:19.174404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1869 10:06:19.268498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1870 10:06:19.269297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1872 10:06:19.358399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1873 10:06:19.359204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1875 10:06:19.453942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1876 10:06:19.454737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1878 10:06:19.546696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1879 10:06:19.547497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1881 10:06:19.640058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1882 10:06:19.640851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1884 10:06:19.730352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1885 10:06:19.731142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1887 10:06:19.824157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1888 10:06:19.824938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1890 10:06:19.916372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1891 10:06:19.917154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1893 10:06:20.010009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1894 10:06:20.010801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1896 10:06:20.103818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1897 10:06:20.104599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1899 10:06:20.196034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1900 10:06:20.196802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1902 10:06:20.288512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1903 10:06:20.289302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1905 10:06:20.383699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1906 10:06:20.384513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1908 10:06:20.482418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1909 10:06:20.483217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1911 10:06:20.578142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1912 10:06:20.578937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1914 10:06:20.672040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1915 10:06:20.672827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1917 10:06:20.765852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1918 10:06:20.766640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1920 10:06:20.858807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1921 10:06:20.859596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1923 10:06:20.955119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1924 10:06:20.955924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1926 10:06:21.049905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1927 10:06:21.050684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1929 10:06:21.144015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1930 10:06:21.144843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1932 10:06:21.236603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1933 10:06:21.237408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1935 10:06:21.330189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1936 10:06:21.330984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1938 10:06:21.422581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1939 10:06:21.423424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1941 10:06:21.516941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1942 10:06:21.517730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1944 10:06:21.618709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1945 10:06:21.619506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1947 10:06:21.720662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1948 10:06:21.721442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1950 10:06:21.814361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1951 10:06:21.815178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1953 10:06:21.907641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1954 10:06:21.908428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1956 10:06:22.001259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1957 10:06:22.002039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1959 10:06:22.095854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1961 10:06:22.098994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1962 10:06:22.196084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1964 10:06:22.199247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1965 10:06:22.289950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1967 10:06:22.293085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1968 10:06:22.383864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1969 10:06:22.384669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1971 10:06:22.476404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1972 10:06:22.477180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1974 10:06:22.767935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1975 10:06:22.768618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1977 10:06:22.769374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1978 10:06:22.769798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1980 10:06:22.771515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1981 10:06:22.772023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1983 10:06:22.864289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1984 10:06:22.865179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1986 10:06:22.956280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1987 10:06:22.957122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1989 10:06:23.050104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1990 10:06:23.050742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1992 10:06:23.151906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1993 10:06:23.152520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1995 10:06:23.246378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1996 10:06:23.247012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1998 10:06:23.338248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1999 10:06:23.338882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2001 10:06:23.431272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2002 10:06:23.431883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2004 10:06:23.524553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2005 10:06:23.525778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2007 10:06:23.617551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2008 10:06:23.618460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2010 10:06:23.712405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
2011 10:06:23.713282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
2013 10:06:23.806812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
2014 10:06:23.807664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
2016 10:06:23.898354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2017 10:06:23.899270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2019 10:06:23.991771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2020 10:06:23.992668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2022 10:06:24.086099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2023 10:06:24.086991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2025 10:06:24.179546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2026 10:06:24.180425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2028 10:06:24.270053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2029 10:06:24.270910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2031 10:06:24.358086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2032 10:06:24.358932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2034 10:06:24.450673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2035 10:06:24.451507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2037 10:06:24.542688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2038 10:06:24.543491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2040 10:06:24.637708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2041 10:06:24.638631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2043 10:06:24.732955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2044 10:06:24.733862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2046 10:06:24.825359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2047 10:06:24.826265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2049 10:06:24.916102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2050 10:06:24.916985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2052 10:06:25.009164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2053 10:06:25.010011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2055 10:06:25.111438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2056 10:06:25.112251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2058 10:06:25.213479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2059 10:06:25.214318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2061 10:06:25.305265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2062 10:06:25.306041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2064 10:06:25.395844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2065 10:06:25.396621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2067 10:06:25.489457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2068 10:06:25.490410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2070 10:06:25.591034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2071 10:06:25.591941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2073 10:06:25.695318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2074 10:06:25.696106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2076 10:06:25.793566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2077 10:06:25.794386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2079 10:06:25.886990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2080 10:06:25.887777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2082 10:06:25.988096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2083 10:06:25.988878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2085 10:06:26.082466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2086 10:06:26.083258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2088 10:06:26.173709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2089 10:06:26.174629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2091 10:06:26.267670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2092 10:06:26.268443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2094 10:06:26.360555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2095 10:06:26.361336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2097 10:06:26.453737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2098 10:06:26.454504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2100 10:06:26.544706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2101 10:06:26.545397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2103 10:06:26.637414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2104 10:06:26.638125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2106 10:06:26.728966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2107 10:06:26.729650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2109 10:06:26.823413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2110 10:06:26.824116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2112 10:06:26.915495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2113 10:06:26.916198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2115 10:06:27.009387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2116 10:06:27.010197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2118 10:06:27.101324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2119 10:06:27.102119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2121 10:06:27.194843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2122 10:06:27.195552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2124 10:06:27.284713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2125 10:06:27.285440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2127 10:06:27.380281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2128 10:06:27.381031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2130 10:06:27.473669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2131 10:06:27.474471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2133 10:06:27.566429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
2134 10:06:27.567141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
2136 10:06:27.659385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
2137 10:06:27.660089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
2139 10:06:27.751257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
2140 10:06:27.751959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
2142 10:06:27.846477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
2143 10:06:27.847185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
2145 10:06:27.936964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
2146 10:06:27.937675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
2148 10:06:28.030500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
2149 10:06:28.031199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
2151 10:06:28.122938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
2152 10:06:28.123631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
2154 10:06:28.217174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
2155 10:06:28.217904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
2157 10:06:28.306221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2158 10:06:28.306934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2160 10:06:28.398520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2161 10:06:28.399239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2163 10:06:28.491205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2164 10:06:28.491949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2166 10:06:28.583122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2167 10:06:28.583890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2169 10:06:28.675687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2170 10:06:28.676394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2172 10:06:28.767223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2173 10:06:28.768004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2175 10:06:28.859225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2176 10:06:28.859918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2178 10:06:28.954111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2179 10:06:28.954881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2181 10:06:29.048113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2182 10:06:29.048823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2184 10:06:29.149901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2185 10:06:29.150633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2187 10:06:29.250586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2188 10:06:29.251345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2190 10:06:29.352823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2191 10:06:29.353549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2193 10:06:29.443033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2194 10:06:29.443786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2196 10:06:29.536275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2197 10:06:29.537078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2199 10:06:29.629488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2200 10:06:29.630350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2202 10:06:29.720079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2203 10:06:29.720851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2205 10:06:29.813083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2206 10:06:29.813862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2208 10:06:29.905345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2209 10:06:29.906119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2211 10:06:29.996866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2212 10:06:29.997572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2214 10:06:30.090326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2215 10:06:30.091020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2217 10:06:30.184539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2218 10:06:30.185238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2220 10:06:30.274888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2221 10:06:30.275596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2223 10:06:30.367713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2224 10:06:30.368431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2226 10:06:30.457178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2227 10:06:30.457971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2229 10:06:30.552612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2230 10:06:30.553321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2232 10:06:30.646235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2233 10:06:30.646935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2235 10:06:30.738931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2236 10:06:30.739627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2238 10:06:30.840856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2239 10:06:30.841573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2241 10:06:30.940259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2242 10:06:30.940959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2244 10:06:31.043658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2245 10:06:31.044381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2247 10:06:31.145021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2248 10:06:31.145863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2250 10:06:31.248309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2251 10:06:31.249255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2253 10:06:31.338926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2254 10:06:31.339760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2256 10:06:31.432125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2257 10:06:31.432966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2259 10:06:31.524726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2260 10:06:31.525553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2262 10:06:31.613029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2263 10:06:31.613908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2265 10:06:31.706175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2266 10:06:31.706996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2268 10:06:31.798269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2269 10:06:31.799099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2271 10:06:31.889650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2272 10:06:31.890530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2274 10:06:31.982585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2275 10:06:31.983407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2277 10:06:32.075152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2278 10:06:32.075963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2280 10:06:32.166149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2282 10:06:32.169169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2283 10:06:32.261066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2284 10:06:32.261885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2286 10:06:32.353689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2287 10:06:32.354544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2289 10:06:32.445419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2290 10:06:32.446270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2292 10:06:32.538910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2293 10:06:32.539729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2295 10:06:32.632545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2296 10:06:32.633362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2298 10:06:32.722893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2299 10:06:32.723729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2301 10:06:32.813303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2302 10:06:32.814161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2304 10:06:32.914502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2305 10:06:32.915315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2307 10:06:33.015905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2308 10:06:33.016728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2310 10:06:33.108601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2311 10:06:33.109411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2313 10:06:33.200858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2314 10:06:33.201671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2316 10:06:33.292342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2317 10:06:33.293165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2319 10:06:33.384564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2320 10:06:33.385411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2322 10:06:33.477353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2323 10:06:33.478229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2325 10:06:33.570476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2326 10:06:33.571341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2328 10:06:33.663500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2329 10:06:33.664329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2331 10:06:33.756602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2332 10:06:33.757432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2334 10:06:33.848492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2335 10:06:33.849332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2337 10:06:33.941306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2338 10:06:33.942160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2340 10:06:34.033330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2341 10:06:34.034185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2343 10:06:34.124326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2344 10:06:34.125151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2346 10:06:34.217628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2347 10:06:34.218501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2349 10:06:34.310748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2350 10:06:34.311564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2352 10:06:34.401895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2353 10:06:34.402724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2355 10:06:34.491980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2356 10:06:34.492780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2358 10:06:34.584950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2359 10:06:34.585764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2361 10:06:34.679512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2362 10:06:34.680317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2364 10:06:34.771505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2365 10:06:34.772314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2367 10:06:34.864697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2368 10:06:34.865516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2370 10:06:34.958247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2371 10:06:34.959050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2373 10:06:35.047138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2374 10:06:35.047704 + set +x
2375 10:06:35.048424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2377 10:06:35.051447 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 880284_1.6.2.4.5>
2378 10:06:35.052229 Received signal: <ENDRUN> 1_kselftest-dt 880284_1.6.2.4.5
2379 10:06:35.052718 Ending use of test pattern.
2380 10:06:35.053159 Ending test lava.1_kselftest-dt (880284_1.6.2.4.5), duration 85.56
2382 10:06:35.059065 <LAVA_TEST_RUNNER EXIT>
2383 10:06:35.059821 ok: lava_test_shell seems to have completed
2384 10:06:35.073944 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2385 10:06:35.076020 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2386 10:06:35.076650 end: 3 lava-test-retry (duration 00:01:27) [common]
2387 10:06:35.077247 start: 4 finalize (timeout 00:05:26) [common]
2388 10:06:35.077871 start: 4.1 power-off (timeout 00:00:30) [common]
2389 10:06:35.078905 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2390 10:06:35.112065 >> OK - accepted request
2391 10:06:35.114293 Returned 0 in 0 seconds
2392 10:06:35.215762 end: 4.1 power-off (duration 00:00:00) [common]
2394 10:06:35.217610 start: 4.2 read-feedback (timeout 00:05:26) [common]
2395 10:06:35.219310 Listened to connection for namespace 'common' for up to 1s
2396 10:06:35.220254 Listened to connection for namespace 'common' for up to 1s
2397 10:06:36.219645 Finalising connection for namespace 'common'
2398 10:06:36.220397 Disconnecting from shell: Finalise
2399 10:06:36.220946 / #
2400 10:06:36.322016 end: 4.2 read-feedback (duration 00:00:01) [common]
2401 10:06:36.322772 end: 4 finalize (duration 00:00:01) [common]
2402 10:06:36.323557 Cleaning after the job
2403 10:06:36.324246 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/ramdisk
2404 10:06:36.334056 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/kernel
2405 10:06:36.342315 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/dtb
2406 10:06:36.343633 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/nfsrootfs
2407 10:06:36.428020 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880284/tftp-deploy-qnwo8n43/modules
2408 10:06:36.432632 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/880284
2409 10:06:39.267206 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/880284
2410 10:06:39.267790 Job finished correctly