Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:20:17.646188 lava-dispatcher, installed at version: 2024.01
2 09:20:17.647005 start: 0 validate
3 09:20:17.647488 Start time: 2024-10-22 09:20:17.647458+00:00 (UTC)
4 09:20:17.648070 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:20:17.648628 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:20:17.686246 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:20:17.686837 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 09:20:17.715610 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:20:17.716272 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 09:20:18.758120 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:20:18.758638 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 09:20:18.813100 validate duration: 1.17
14 09:20:18.814046 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:20:18.814414 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:20:18.814761 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:20:18.815332 Not decompressing ramdisk as can be used compressed.
18 09:20:18.815760 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:20:18.816561 saving as /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/ramdisk/rootfs.cpio.gz
20 09:20:18.817177 total size: 8181887 (7 MB)
21 09:20:18.855418 progress 0 % (0 MB)
22 09:20:18.864108 progress 5 % (0 MB)
23 09:20:18.870290 progress 10 % (0 MB)
24 09:20:18.876340 progress 15 % (1 MB)
25 09:20:18.881817 progress 20 % (1 MB)
26 09:20:18.887596 progress 25 % (1 MB)
27 09:20:18.893128 progress 30 % (2 MB)
28 09:20:18.898919 progress 35 % (2 MB)
29 09:20:18.904309 progress 40 % (3 MB)
30 09:20:18.909998 progress 45 % (3 MB)
31 09:20:18.915366 progress 50 % (3 MB)
32 09:20:18.921235 progress 55 % (4 MB)
33 09:20:18.926595 progress 60 % (4 MB)
34 09:20:18.932349 progress 65 % (5 MB)
35 09:20:18.937835 progress 70 % (5 MB)
36 09:20:18.943724 progress 75 % (5 MB)
37 09:20:18.949190 progress 80 % (6 MB)
38 09:20:18.955302 progress 85 % (6 MB)
39 09:20:18.960926 progress 90 % (7 MB)
40 09:20:18.966493 progress 95 % (7 MB)
41 09:20:18.971409 progress 100 % (7 MB)
42 09:20:18.972113 7 MB downloaded in 0.15 s (50.37 MB/s)
43 09:20:18.972669 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:20:18.973553 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:20:18.973841 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:20:18.974112 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:20:18.974573 downloading http://storage.kernelci.org/next/master/next-20241022/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/kernel/Image
49 09:20:18.974820 saving as /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/kernel/Image
50 09:20:18.975029 total size: 47391232 (45 MB)
51 09:20:18.975240 No compression specified
52 09:20:19.022925 progress 0 % (0 MB)
53 09:20:19.052598 progress 5 % (2 MB)
54 09:20:19.088375 progress 10 % (4 MB)
55 09:20:19.125501 progress 15 % (6 MB)
56 09:20:19.163594 progress 20 % (9 MB)
57 09:20:19.200345 progress 25 % (11 MB)
58 09:20:19.234669 progress 30 % (13 MB)
59 09:20:19.267612 progress 35 % (15 MB)
60 09:20:19.297056 progress 40 % (18 MB)
61 09:20:19.326983 progress 45 % (20 MB)
62 09:20:19.356403 progress 50 % (22 MB)
63 09:20:19.386594 progress 55 % (24 MB)
64 09:20:19.416212 progress 60 % (27 MB)
65 09:20:19.446147 progress 65 % (29 MB)
66 09:20:19.476128 progress 70 % (31 MB)
67 09:20:19.505450 progress 75 % (33 MB)
68 09:20:19.536086 progress 80 % (36 MB)
69 09:20:19.567144 progress 85 % (38 MB)
70 09:20:19.596784 progress 90 % (40 MB)
71 09:20:19.627452 progress 95 % (42 MB)
72 09:20:19.661884 progress 100 % (45 MB)
73 09:20:19.662456 45 MB downloaded in 0.69 s (65.75 MB/s)
74 09:20:19.662938 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:20:19.663875 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:20:19.664186 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:20:19.664454 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:20:19.664934 downloading http://storage.kernelci.org/next/master/next-20241022/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 09:20:19.665209 saving as /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 09:20:19.665418 total size: 53209 (0 MB)
82 09:20:19.665627 No compression specified
83 09:20:19.705752 progress 61 % (0 MB)
84 09:20:19.706590 progress 100 % (0 MB)
85 09:20:19.707180 0 MB downloaded in 0.04 s (1.22 MB/s)
86 09:20:19.707752 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:20:19.708621 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:20:19.708884 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:20:19.709147 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:20:19.709604 downloading http://storage.kernelci.org/next/master/next-20241022/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/gcc-12/modules.tar.xz
92 09:20:19.709847 saving as /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/modules/modules.tar
93 09:20:19.710050 total size: 11628256 (11 MB)
94 09:20:19.710259 Using unxz to decompress xz
95 09:20:19.744451 progress 0 % (0 MB)
96 09:20:19.811357 progress 5 % (0 MB)
97 09:20:19.885852 progress 10 % (1 MB)
98 09:20:19.966095 progress 15 % (1 MB)
99 09:20:20.042497 progress 20 % (2 MB)
100 09:20:20.118356 progress 25 % (2 MB)
101 09:20:20.199633 progress 30 % (3 MB)
102 09:20:20.282558 progress 35 % (3 MB)
103 09:20:20.359957 progress 40 % (4 MB)
104 09:20:20.447686 progress 45 % (5 MB)
105 09:20:20.528622 progress 50 % (5 MB)
106 09:20:20.611740 progress 55 % (6 MB)
107 09:20:20.688661 progress 60 % (6 MB)
108 09:20:20.773145 progress 65 % (7 MB)
109 09:20:20.855552 progress 70 % (7 MB)
110 09:20:20.935917 progress 75 % (8 MB)
111 09:20:21.014743 progress 80 % (8 MB)
112 09:20:21.094941 progress 85 % (9 MB)
113 09:20:21.167798 progress 90 % (10 MB)
114 09:20:21.267788 progress 95 % (10 MB)
115 09:20:21.360503 progress 100 % (11 MB)
116 09:20:21.374702 11 MB downloaded in 1.66 s (6.66 MB/s)
117 09:20:21.375328 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:20:21.376382 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:20:21.376966 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 09:20:21.377532 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 09:20:21.378067 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:20:21.378617 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 09:20:21.379657 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq
125 09:20:21.380585 makedir: /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin
126 09:20:21.381273 makedir: /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/tests
127 09:20:21.381947 makedir: /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/results
128 09:20:21.382604 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-add-keys
129 09:20:21.383615 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-add-sources
130 09:20:21.384662 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-background-process-start
131 09:20:21.385689 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-background-process-stop
132 09:20:21.386754 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-common-functions
133 09:20:21.387748 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-echo-ipv4
134 09:20:21.388882 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-install-packages
135 09:20:21.389862 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-installed-packages
136 09:20:21.390813 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-os-build
137 09:20:21.391773 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-probe-channel
138 09:20:21.392777 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-probe-ip
139 09:20:21.393734 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-target-ip
140 09:20:21.394735 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-target-mac
141 09:20:21.395700 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-target-storage
142 09:20:21.396771 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-test-case
143 09:20:21.397790 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-test-event
144 09:20:21.398755 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-test-feedback
145 09:20:21.399723 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-test-raise
146 09:20:21.400758 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-test-reference
147 09:20:21.401754 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-test-runner
148 09:20:21.402742 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-test-set
149 09:20:21.403698 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-test-shell
150 09:20:21.404714 Updating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-install-packages (oe)
151 09:20:21.405797 Updating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/bin/lava-installed-packages (oe)
152 09:20:21.406697 Creating /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/environment
153 09:20:21.407461 LAVA metadata
154 09:20:21.408017 - LAVA_JOB_ID=880221
155 09:20:21.408509 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:20:21.409253 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 09:20:21.411212 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:20:21.411868 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 09:20:21.412375 skipped lava-vland-overlay
160 09:20:21.412873 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:20:21.413379 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 09:20:21.413805 skipped lava-multinode-overlay
163 09:20:21.414286 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:20:21.414784 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 09:20:21.415263 Loading test definitions
166 09:20:21.415809 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 09:20:21.416284 Using /lava-880221 at stage 0
168 09:20:21.418518 uuid=880221_1.5.2.4.1 testdef=None
169 09:20:21.419105 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:20:21.419618 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 09:20:21.421748 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:20:21.422575 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 09:20:21.424979 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:20:21.425824 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 09:20:21.428124 runner path: /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/0/tests/0_dmesg test_uuid 880221_1.5.2.4.1
178 09:20:21.428771 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:20:21.429547 Creating lava-test-runner.conf files
181 09:20:21.429751 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/880221/lava-overlay-n3m87igq/lava-880221/0 for stage 0
182 09:20:21.430107 - 0_dmesg
183 09:20:21.430471 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:20:21.430758 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 09:20:21.456349 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:20:21.456798 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 09:20:21.457067 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:20:21.457338 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:20:21.457603 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 09:20:22.398307 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:20:22.398770 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 09:20:22.399011 extracting modules file /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/880221/extract-overlay-ramdisk-vrf7vms1/ramdisk
193 09:20:23.752389 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 09:20:23.752844 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 09:20:23.753117 [common] Applying overlay /var/lib/lava/dispatcher/tmp/880221/compress-overlay-6turizna/overlay-1.5.2.5.tar.gz to ramdisk
196 09:20:23.753329 [common] Applying overlay /var/lib/lava/dispatcher/tmp/880221/compress-overlay-6turizna/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/880221/extract-overlay-ramdisk-vrf7vms1/ramdisk
197 09:20:23.783785 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:20:23.784242 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 09:20:23.784520 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 09:20:23.784749 Converting downloaded kernel to a uImage
201 09:20:23.785074 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/kernel/Image /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/kernel/uImage
202 09:20:24.273939 output: Image Name:
203 09:20:24.274353 output: Created: Tue Oct 22 09:20:23 2024
204 09:20:24.274563 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:20:24.274764 output: Data Size: 47391232 Bytes = 46280.50 KiB = 45.20 MiB
206 09:20:24.274961 output: Load Address: 01080000
207 09:20:24.275156 output: Entry Point: 01080000
208 09:20:24.275351 output:
209 09:20:24.275678 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 09:20:24.275937 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 09:20:24.276252 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 09:20:24.276507 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:20:24.276761 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 09:20:24.277012 Building ramdisk /var/lib/lava/dispatcher/tmp/880221/extract-overlay-ramdisk-vrf7vms1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/880221/extract-overlay-ramdisk-vrf7vms1/ramdisk
215 09:20:26.703379 >> 182390 blocks
216 09:20:35.902712 Adding RAMdisk u-boot header.
217 09:20:35.903145 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/880221/extract-overlay-ramdisk-vrf7vms1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/880221/extract-overlay-ramdisk-vrf7vms1/ramdisk.cpio.gz.uboot
218 09:20:36.201652 output: Image Name:
219 09:20:36.202065 output: Created: Tue Oct 22 09:20:35 2024
220 09:20:36.202271 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:20:36.202474 output: Data Size: 26096611 Bytes = 25484.97 KiB = 24.89 MiB
222 09:20:36.202672 output: Load Address: 00000000
223 09:20:36.202868 output: Entry Point: 00000000
224 09:20:36.203062 output:
225 09:20:36.203675 rename /var/lib/lava/dispatcher/tmp/880221/extract-overlay-ramdisk-vrf7vms1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/ramdisk/ramdisk.cpio.gz.uboot
226 09:20:36.204155 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 09:20:36.204708 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 09:20:36.205227 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 09:20:36.205669 No LXC device requested
230 09:20:36.206159 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:20:36.206655 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 09:20:36.207141 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:20:36.207545 Checking files for TFTP limit of 4294967296 bytes.
234 09:20:36.210191 end: 1 tftp-deploy (duration 00:00:17) [common]
235 09:20:36.210750 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:20:36.211261 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:20:36.211748 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:20:36.212295 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:20:36.212816 Using kernel file from prepare-kernel: 880221/tftp-deploy-znflckp3/kernel/uImage
240 09:20:36.213411 substitutions:
241 09:20:36.213811 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:20:36.214206 - {DTB_ADDR}: 0x01070000
243 09:20:36.214596 - {DTB}: 880221/tftp-deploy-znflckp3/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 09:20:36.214990 - {INITRD}: 880221/tftp-deploy-znflckp3/ramdisk/ramdisk.cpio.gz.uboot
245 09:20:36.215380 - {KERNEL_ADDR}: 0x01080000
246 09:20:36.215764 - {KERNEL}: 880221/tftp-deploy-znflckp3/kernel/uImage
247 09:20:36.216182 - {LAVA_MAC}: None
248 09:20:36.216611 - {PRESEED_CONFIG}: None
249 09:20:36.217000 - {PRESEED_LOCAL}: None
250 09:20:36.217415 - {RAMDISK_ADDR}: 0x08000000
251 09:20:36.217822 - {RAMDISK}: 880221/tftp-deploy-znflckp3/ramdisk/ramdisk.cpio.gz.uboot
252 09:20:36.218215 - {ROOT_PART}: None
253 09:20:36.218598 - {ROOT}: None
254 09:20:36.218979 - {SERVER_IP}: 192.168.6.2
255 09:20:36.219365 - {TEE_ADDR}: 0x83000000
256 09:20:36.219747 - {TEE}: None
257 09:20:36.220162 Parsed boot commands:
258 09:20:36.220536 - setenv autoload no
259 09:20:36.220917 - setenv initrd_high 0xffffffff
260 09:20:36.221299 - setenv fdt_high 0xffffffff
261 09:20:36.221676 - dhcp
262 09:20:36.222055 - setenv serverip 192.168.6.2
263 09:20:36.222436 - tftpboot 0x01080000 880221/tftp-deploy-znflckp3/kernel/uImage
264 09:20:36.222818 - tftpboot 0x08000000 880221/tftp-deploy-znflckp3/ramdisk/ramdisk.cpio.gz.uboot
265 09:20:36.223200 - tftpboot 0x01070000 880221/tftp-deploy-znflckp3/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 09:20:36.223579 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:20:36.223967 - bootm 0x01080000 0x08000000 0x01070000
268 09:20:36.224492 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:20:36.225953 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:20:36.226391 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 09:20:36.240587 Setting prompt string to ['lava-test: # ']
273 09:20:36.242057 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:20:36.242645 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:20:36.243178 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:20:36.243681 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:20:36.244824 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 09:20:36.278617 >> OK - accepted request
279 09:20:36.280513 Returned 0 in 0 seconds
280 09:20:36.381620 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:20:36.383196 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:20:36.383754 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:20:36.384315 Setting prompt string to ['Hit any key to stop autoboot']
285 09:20:36.384765 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:20:36.386297 Trying 192.168.56.21...
287 09:20:36.386763 Connected to conserv1.
288 09:20:36.387168 Escape character is '^]'.
289 09:20:36.387584
290 09:20:36.388024 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 09:20:36.388460
292 09:20:43.949199 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 09:20:43.949635 bl2_stage_init 0x01
294 09:20:43.949896 bl2_stage_init 0x81
295 09:20:43.954844 hw id: 0x0000 - pwm id 0x01
296 09:20:43.955148 bl2_stage_init 0xc1
297 09:20:43.959134 bl2_stage_init 0x02
298 09:20:43.959436
299 09:20:43.959679 L0:00000000
300 09:20:43.959917 L1:00000703
301 09:20:43.960184 L2:00008067
302 09:20:43.964828 L3:15000000
303 09:20:43.965137 S1:00000000
304 09:20:43.965365 B2:20282000
305 09:20:43.965589 B1:a0f83180
306 09:20:43.965813
307 09:20:43.966034 TE: 70726
308 09:20:43.966260
309 09:20:43.975943 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 09:20:43.976272
311 09:20:43.976505 Board ID = 1
312 09:20:43.976734 Set cpu clk to 24M
313 09:20:43.976956 Set clk81 to 24M
314 09:20:43.979292 Use GP1_pll as DSU clk.
315 09:20:43.984961 DSU clk: 1200 Mhz
316 09:20:43.985244 CPU clk: 1200 MHz
317 09:20:43.985472 Set clk81 to 166.6M
318 09:20:43.990509 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 09:20:43.996121 board id: 1
320 09:20:44.000053 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:20:44.011771 fw parse done
322 09:20:44.017813 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:20:44.060383 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:20:44.071324 PIEI prepare done
325 09:20:44.071640 fastboot data load
326 09:20:44.071878 fastboot data verify
327 09:20:44.076873 verify result: 266
328 09:20:44.082426 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 09:20:44.082698 LPDDR4 probe
330 09:20:44.082919 ddr clk to 1584MHz
331 09:20:44.090437 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:20:44.127688
333 09:20:44.128012 dmc_version 0001
334 09:20:44.134362 Check phy result
335 09:20:44.140247 INFO : End of CA training
336 09:20:44.140496 INFO : End of initialization
337 09:20:44.145860 INFO : Training has run successfully!
338 09:20:44.146141 Check phy result
339 09:20:44.151459 INFO : End of initialization
340 09:20:44.151735 INFO : End of read enable training
341 09:20:44.157053 INFO : End of fine write leveling
342 09:20:44.162758 INFO : End of Write leveling coarse delay
343 09:20:44.163039 INFO : Training has run successfully!
344 09:20:44.163239 Check phy result
345 09:20:44.168281 INFO : End of initialization
346 09:20:44.168719 INFO : End of read dq deskew training
347 09:20:44.173893 INFO : End of MPR read delay center optimization
348 09:20:44.179491 INFO : End of write delay center optimization
349 09:20:44.185080 INFO : End of read delay center optimization
350 09:20:44.185496 INFO : End of max read latency training
351 09:20:44.190681 INFO : Training has run successfully!
352 09:20:44.191093 1D training succeed
353 09:20:44.199906 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:20:44.247493 Check phy result
355 09:20:44.248040 INFO : End of initialization
356 09:20:44.269958 INFO : End of 2D read delay Voltage center optimization
357 09:20:44.289190 INFO : End of 2D read delay Voltage center optimization
358 09:20:44.340962 INFO : End of 2D write delay Voltage center optimization
359 09:20:44.390271 INFO : End of 2D write delay Voltage center optimization
360 09:20:44.395750 INFO : Training has run successfully!
361 09:20:44.396253
362 09:20:44.396651 channel==0
363 09:20:44.401326 RxClkDly_Margin_A0==78 ps 8
364 09:20:44.401749 TxDqDly_Margin_A0==98 ps 10
365 09:20:44.406958 RxClkDly_Margin_A1==88 ps 9
366 09:20:44.407385 TxDqDly_Margin_A1==88 ps 9
367 09:20:44.407783 TrainedVREFDQ_A0==74
368 09:20:44.412546 TrainedVREFDQ_A1==74
369 09:20:44.412963 VrefDac_Margin_A0==23
370 09:20:44.413350 DeviceVref_Margin_A0==40
371 09:20:44.418106 VrefDac_Margin_A1==23
372 09:20:44.418514 DeviceVref_Margin_A1==40
373 09:20:44.418905
374 09:20:44.419294
375 09:20:44.419683 channel==1
376 09:20:44.423656 RxClkDly_Margin_A0==78 ps 8
377 09:20:44.424087 TxDqDly_Margin_A0==98 ps 10
378 09:20:44.429269 RxClkDly_Margin_A1==88 ps 9
379 09:20:44.429680 TxDqDly_Margin_A1==88 ps 9
380 09:20:44.434550 TrainedVREFDQ_A0==78
381 09:20:44.437474 TrainedVREFDQ_A1==75
382 09:20:44.437897 VrefDac_Margin_A0==22
383 09:20:44.438287 DeviceVref_Margin_A0==36
384 09:20:44.443134 VrefDac_Margin_A1==23
385 09:20:44.443538 DeviceVref_Margin_A1==39
386 09:20:44.443922
387 09:20:44.448722 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:20:44.449195
389 09:20:44.480558 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000060
390 09:20:44.481111 2D training succeed
391 09:20:44.486127 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:20:44.491574 auto size-- 65535DDR cs0 size: 2048MB
393 09:20:44.492020 DDR cs1 size: 2048MB
394 09:20:44.495089 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:20:44.495493 cs0 DataBus test pass
396 09:20:44.500673 cs1 DataBus test pass
397 09:20:44.501091 cs0 AddrBus test pass
398 09:20:44.506309 cs1 AddrBus test pass
399 09:20:44.506770
400 09:20:44.507161 100bdlr_step_size ps== 478
401 09:20:44.507559 result report
402 09:20:44.512034 boot times 0Enable ddr reg access
403 09:20:44.518382 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:20:44.532231 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 09:20:45.187372 bl2z: ptr: 05129330, size: 00001e40
406 09:20:45.193501 0.0;M3 CHK:0;cm4_sp_mode 0
407 09:20:45.193947 MVN_1=0x00000000
408 09:20:45.194344 MVN_2=0x00000000
409 09:20:45.205059 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 09:20:45.205488 OPS=0x04
411 09:20:45.205882 ring efuse init
412 09:20:45.208075 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 09:20:45.214136 [0.017319 Inits done]
414 09:20:45.214556 secure task start!
415 09:20:45.214948 high task start!
416 09:20:45.215333 low task start!
417 09:20:45.218325 run into bl31
418 09:20:45.227048 NOTICE: BL31: v1.3(release):4fc40b1
419 09:20:45.234807 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 09:20:45.235279 NOTICE: BL31: G12A normal boot!
421 09:20:45.250339 NOTICE: BL31: BL33 decompress pass
422 09:20:45.256034 ERROR: Error initializing runtime service opteed_fast
423 09:20:47.997503 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 09:20:47.998128 bl2_stage_init 0x01
425 09:20:47.998553 bl2_stage_init 0x81
426 09:20:48.002983 hw id: 0x0000 - pwm id 0x01
427 09:20:48.003466 bl2_stage_init 0xc1
428 09:20:48.008585 bl2_stage_init 0x02
429 09:20:48.009074
430 09:20:48.009507 L0:00000000
431 09:20:48.009907 L1:00000703
432 09:20:48.010292 L2:00008067
433 09:20:48.010700 L3:15000000
434 09:20:48.014169 S1:00000000
435 09:20:48.014590 B2:20282000
436 09:20:48.014977 B1:a0f83180
437 09:20:48.015355
438 09:20:48.015739 TE: 68609
439 09:20:48.016171
440 09:20:48.019756 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 09:20:48.020203
442 09:20:48.025436 Board ID = 1
443 09:20:48.025854 Set cpu clk to 24M
444 09:20:48.026239 Set clk81 to 24M
445 09:20:48.030942 Use GP1_pll as DSU clk.
446 09:20:48.031351 DSU clk: 1200 Mhz
447 09:20:48.031733 CPU clk: 1200 MHz
448 09:20:48.036583 Set clk81 to 166.6M
449 09:20:48.042155 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 09:20:48.042568 board id: 1
451 09:20:48.049397 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 09:20:48.060048 fw parse done
453 09:20:48.065992 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 09:20:48.108639 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 09:20:48.119528 PIEI prepare done
456 09:20:48.120142 fastboot data load
457 09:20:48.120665 fastboot data verify
458 09:20:48.125231 verify result: 266
459 09:20:48.130791 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 09:20:48.131383 LPDDR4 probe
461 09:20:48.131895 ddr clk to 1584MHz
462 09:20:48.138765 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 09:20:48.176028
464 09:20:48.176590 dmc_version 0001
465 09:20:48.182728 Check phy result
466 09:20:48.188664 INFO : End of CA training
467 09:20:48.189270 INFO : End of initialization
468 09:20:48.194210 INFO : Training has run successfully!
469 09:20:48.194759 Check phy result
470 09:20:48.199811 INFO : End of initialization
471 09:20:48.200399 INFO : End of read enable training
472 09:20:48.205416 INFO : End of fine write leveling
473 09:20:48.211006 INFO : End of Write leveling coarse delay
474 09:20:48.211554 INFO : Training has run successfully!
475 09:20:48.212109 Check phy result
476 09:20:48.216613 INFO : End of initialization
477 09:20:48.217154 INFO : End of read dq deskew training
478 09:20:48.222213 INFO : End of MPR read delay center optimization
479 09:20:48.227801 INFO : End of write delay center optimization
480 09:20:48.233394 INFO : End of read delay center optimization
481 09:20:48.233923 INFO : End of max read latency training
482 09:20:48.239002 INFO : Training has run successfully!
483 09:20:48.239544 1D training succeed
484 09:20:48.248202 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 09:20:48.295799 Check phy result
486 09:20:48.296395 INFO : End of initialization
487 09:20:48.318157 INFO : End of 2D read delay Voltage center optimization
488 09:20:48.337308 INFO : End of 2D read delay Voltage center optimization
489 09:20:48.389290 INFO : End of 2D write delay Voltage center optimization
490 09:20:48.438420 INFO : End of 2D write delay Voltage center optimization
491 09:20:48.444014 INFO : Training has run successfully!
492 09:20:48.444574
493 09:20:48.445116 channel==0
494 09:20:48.449582 RxClkDly_Margin_A0==78 ps 8
495 09:20:48.450129 TxDqDly_Margin_A0==98 ps 10
496 09:20:48.455147 RxClkDly_Margin_A1==88 ps 9
497 09:20:48.455689 TxDqDly_Margin_A1==88 ps 9
498 09:20:48.456249 TrainedVREFDQ_A0==74
499 09:20:48.460756 TrainedVREFDQ_A1==74
500 09:20:48.461303 VrefDac_Margin_A0==24
501 09:20:48.461828 DeviceVref_Margin_A0==40
502 09:20:48.466340 VrefDac_Margin_A1==23
503 09:20:48.466882 DeviceVref_Margin_A1==40
504 09:20:48.467397
505 09:20:48.467909
506 09:20:48.468455 channel==1
507 09:20:48.471967 RxClkDly_Margin_A0==78 ps 8
508 09:20:48.472535 TxDqDly_Margin_A0==88 ps 9
509 09:20:48.477571 RxClkDly_Margin_A1==78 ps 8
510 09:20:48.478133 TxDqDly_Margin_A1==88 ps 9
511 09:20:48.483192 TrainedVREFDQ_A0==75
512 09:20:48.483778 TrainedVREFDQ_A1==75
513 09:20:48.484357 VrefDac_Margin_A0==22
514 09:20:48.488796 DeviceVref_Margin_A0==39
515 09:20:48.489377 VrefDac_Margin_A1==22
516 09:20:48.489899 DeviceVref_Margin_A1==38
517 09:20:48.494362
518 09:20:48.494910 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 09:20:48.495439
520 09:20:48.527973 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 09:20:48.528604 2D training succeed
522 09:20:48.533602 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 09:20:48.539148 auto size-- 65535DDR cs0 size: 2048MB
524 09:20:48.539687 DDR cs1 size: 2048MB
525 09:20:48.544764 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 09:20:48.545347 cs0 DataBus test pass
527 09:20:48.550358 cs1 DataBus test pass
528 09:20:48.550944 cs0 AddrBus test pass
529 09:20:48.551466 cs1 AddrBus test pass
530 09:20:48.552015
531 09:20:48.556066 100bdlr_step_size ps== 478
532 09:20:48.556637 result report
533 09:20:48.561622 boot times 0Enable ddr reg access
534 09:20:48.566715 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 09:20:48.580971 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 09:20:49.235469 bl2z: ptr: 05129330, size: 00001e40
537 09:20:49.241992 0.0;M3 CHK:0;cm4_sp_mode 0
538 09:20:49.242578 MVN_1=0x00000000
539 09:20:49.243096 MVN_2=0x00000000
540 09:20:49.253530 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 09:20:49.254046 OPS=0x04
542 09:20:49.254507 ring efuse init
543 09:20:49.259109 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 09:20:49.259616 [0.017319 Inits done]
545 09:20:49.260102 secure task start!
546 09:20:49.266744 high task start!
547 09:20:49.267229 low task start!
548 09:20:49.267708 run into bl31
549 09:20:49.275280 NOTICE: BL31: v1.3(release):4fc40b1
550 09:20:49.283056 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 09:20:49.283615 NOTICE: BL31: G12A normal boot!
552 09:20:49.298646 NOTICE: BL31: BL33 decompress pass
553 09:20:49.304238 ERROR: Error initializing runtime service opteed_fast
554 09:20:50.699665 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 09:20:50.700364 bl2_stage_init 0x01
556 09:20:50.700836 bl2_stage_init 0x81
557 09:20:50.705242 hw id: 0x0000 - pwm id 0x01
558 09:20:50.705821 bl2_stage_init 0xc1
559 09:20:50.706326 bl2_stage_init 0x02
560 09:20:50.706813
561 09:20:50.710851 L0:00000000
562 09:20:50.711354 L1:00000703
563 09:20:50.711804 L2:00008067
564 09:20:50.712279 L3:15000000
565 09:20:50.712719 S1:00000000
566 09:20:50.716391 B2:20282000
567 09:20:50.716874 B1:a0f83180
568 09:20:50.717316
569 09:20:50.717766 TE: 71088
570 09:20:50.718204
571 09:20:50.721987 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 09:20:50.722535
573 09:20:50.727556 Board ID = 1
574 09:20:50.728143 Set cpu clk to 24M
575 09:20:50.728598 Set clk81 to 24M
576 09:20:50.733243 Use GP1_pll as DSU clk.
577 09:20:50.733751 DSU clk: 1200 Mhz
578 09:20:50.734197 CPU clk: 1200 MHz
579 09:20:50.734633 Set clk81 to 166.6M
580 09:20:50.744485 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 09:20:50.745005 board id: 1
582 09:20:50.750928 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 09:20:50.761640 fw parse done
584 09:20:50.767591 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 09:20:50.809850 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 09:20:50.821922 PIEI prepare done
587 09:20:50.822473 fastboot data load
588 09:20:50.822932 fastboot data verify
589 09:20:50.827484 verify result: 266
590 09:20:50.833106 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 09:20:50.833651 LPDDR4 probe
592 09:20:50.834104 ddr clk to 1584MHz
593 09:20:50.840256 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 09:20:50.878789
595 09:20:50.879367 dmc_version 0001
596 09:20:50.885814 Check phy result
597 09:20:50.891804 INFO : End of CA training
598 09:20:50.892344 INFO : End of initialization
599 09:20:50.897414 INFO : Training has run successfully!
600 09:20:50.897909 Check phy result
601 09:20:50.902999 INFO : End of initialization
602 09:20:50.903546 INFO : End of read enable training
603 09:20:50.908572 INFO : End of fine write leveling
604 09:20:50.914176 INFO : End of Write leveling coarse delay
605 09:20:50.914676 INFO : Training has run successfully!
606 09:20:50.915124 Check phy result
607 09:20:50.919790 INFO : End of initialization
608 09:20:50.920309 INFO : End of read dq deskew training
609 09:20:50.925405 INFO : End of MPR read delay center optimization
610 09:20:50.930968 INFO : End of write delay center optimization
611 09:20:50.936571 INFO : End of read delay center optimization
612 09:20:50.937110 INFO : End of max read latency training
613 09:20:50.942198 INFO : Training has run successfully!
614 09:20:50.942690 1D training succeed
615 09:20:50.951401 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 09:20:50.999703 Check phy result
617 09:20:51.000329 INFO : End of initialization
618 09:20:51.027063 INFO : End of 2D read delay Voltage center optimization
619 09:20:51.051245 INFO : End of 2D read delay Voltage center optimization
620 09:20:51.108008 INFO : End of 2D write delay Voltage center optimization
621 09:20:51.162066 INFO : End of 2D write delay Voltage center optimization
622 09:20:51.167552 INFO : Training has run successfully!
623 09:20:51.168138
624 09:20:51.168606 channel==0
625 09:20:51.173132 RxClkDly_Margin_A0==78 ps 8
626 09:20:51.173712 TxDqDly_Margin_A0==98 ps 10
627 09:20:51.178733 RxClkDly_Margin_A1==88 ps 9
628 09:20:51.179290 TxDqDly_Margin_A1==98 ps 10
629 09:20:51.179757 TrainedVREFDQ_A0==74
630 09:20:51.184376 TrainedVREFDQ_A1==74
631 09:20:51.184881 VrefDac_Margin_A0==23
632 09:20:51.185334 DeviceVref_Margin_A0==40
633 09:20:51.189998 VrefDac_Margin_A1==23
634 09:20:51.190490 DeviceVref_Margin_A1==40
635 09:20:51.190933
636 09:20:51.191383
637 09:20:51.195615 channel==1
638 09:20:51.196149 RxClkDly_Margin_A0==88 ps 9
639 09:20:51.196643 TxDqDly_Margin_A0==98 ps 10
640 09:20:51.201135 RxClkDly_Margin_A1==88 ps 9
641 09:20:51.201628 TxDqDly_Margin_A1==78 ps 8
642 09:20:51.206742 TrainedVREFDQ_A0==78
643 09:20:51.207314 TrainedVREFDQ_A1==75
644 09:20:51.207776 VrefDac_Margin_A0==22
645 09:20:51.212330 DeviceVref_Margin_A0==36
646 09:20:51.212823 VrefDac_Margin_A1==22
647 09:20:51.217969 DeviceVref_Margin_A1==39
648 09:20:51.218462
649 09:20:51.218911 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 09:20:51.219355
651 09:20:51.251518 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
652 09:20:51.252200 2D training succeed
653 09:20:51.257163 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 09:20:51.262724 auto size-- 65535DDR cs0 size: 2048MB
655 09:20:51.263231 DDR cs1 size: 2048MB
656 09:20:51.268318 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 09:20:51.268812 cs0 DataBus test pass
658 09:20:51.273995 cs1 DataBus test pass
659 09:20:51.274486 cs0 AddrBus test pass
660 09:20:51.274933 cs1 AddrBus test pass
661 09:20:51.275368
662 09:20:51.279430 100bdlr_step_size ps== 471
663 09:20:51.279958 result report
664 09:20:51.285012 boot times 0Enable ddr reg access
665 09:20:51.290251 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 09:20:51.304313 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 09:20:51.964433 bl2z: ptr: 05129330, size: 00001e40
668 09:20:51.972896 0.0;M3 CHK:0;cm4_sp_mode 0
669 09:20:51.973444 MVN_1=0x00000000
670 09:20:51.973915 MVN_2=0x00000000
671 09:20:51.984363 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 09:20:51.984867 OPS=0x04
673 09:20:51.985327 ring efuse init
674 09:20:51.987251 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 09:20:51.993544 [0.017354 Inits done]
676 09:20:51.994030 secure task start!
677 09:20:51.994480 high task start!
678 09:20:51.994923 low task start!
679 09:20:51.997848 run into bl31
680 09:20:52.006581 NOTICE: BL31: v1.3(release):4fc40b1
681 09:20:52.014364 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 09:20:52.014883 NOTICE: BL31: G12A normal boot!
683 09:20:52.029851 NOTICE: BL31: BL33 decompress pass
684 09:20:52.035626 ERROR: Error initializing runtime service opteed_fast
685 09:20:52.831000
686 09:20:52.831663
687 09:20:52.836408 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 09:20:52.836976
689 09:20:52.839902 Model: Libre Computer AML-S905D3-CC Solitude
690 09:20:52.986978 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 09:20:53.002434 DRAM: 2 GiB (effective 3.8 GiB)
692 09:20:53.103379 Core: 406 devices, 33 uclasses, devicetree: separate
693 09:20:53.109188 WDT: Not starting watchdog@f0d0
694 09:20:53.134222 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 09:20:53.146499 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 09:20:53.151468 ** Bad device specification mmc 0 **
697 09:20:53.161511 Card did not respond to voltage select! : -110
698 09:20:53.169153 ** Bad device specification mmc 0 **
699 09:20:53.169691 Couldn't find partition mmc 0
700 09:20:53.177497 Card did not respond to voltage select! : -110
701 09:20:53.182995 ** Bad device specification mmc 0 **
702 09:20:53.183533 Couldn't find partition mmc 0
703 09:20:53.188083 Error: could not access storage.
704 09:20:53.484444 Net: eth0: ethernet@ff3f0000
705 09:20:53.485048 starting USB...
706 09:20:53.729103 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 09:20:53.729682 Starting the controller
708 09:20:53.736140 USB XHCI 1.10
709 09:20:55.292221 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 09:20:55.300576 scanning usb for storage devices... 0 Storage Device(s) found
712 09:20:55.351836 Hit any key to stop autoboot: 1
713 09:20:55.352610 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 09:20:55.353013 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 09:20:55.353330 Setting prompt string to ['=>']
716 09:20:55.353645 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 09:20:55.366513 0
718 09:20:55.367196 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 09:20:55.468125 => setenv autoload no
721 09:20:55.469020 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 09:20:55.473290 setenv autoload no
724 09:20:55.574544 => setenv initrd_high 0xffffffff
725 09:20:55.575178 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 09:20:55.579347 setenv initrd_high 0xffffffff
728 09:20:55.680635 => setenv fdt_high 0xffffffff
729 09:20:55.681532 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 09:20:55.685769 setenv fdt_high 0xffffffff
732 09:20:55.786964 => dhcp
733 09:20:55.787782 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 09:20:55.791901 dhcp
735 09:20:56.446322 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 09:20:56.446904 Speed: 1000, full duplex
737 09:20:56.447258 BOOTP broadcast 1
738 09:20:56.480934 DHCP client bound to address 192.168.6.21 (33 ms)
740 09:20:56.582289 => setenv serverip 192.168.6.2
741 09:20:56.582824 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 09:20:56.587541 setenv serverip 192.168.6.2
744 09:20:56.688719 => tftpboot 0x01080000 880221/tftp-deploy-znflckp3/kernel/uImage
745 09:20:56.689376 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 09:20:56.695886 tftpboot 0x01080000 880221/tftp-deploy-znflckp3/kernel/uImage
747 09:20:56.696302 Speed: 1000, full duplex
748 09:20:56.696567 Using ethernet@ff3f0000 device
749 09:20:56.701552 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 09:20:56.706918 Filename '880221/tftp-deploy-znflckp3/kernel/uImage'.
751 09:20:56.711054 Load address: 0x1080000
752 09:21:00.255840 Loading: *################################################## 45.2 MiB
753 09:21:00.256311 13.7 MiB/s
754 09:21:00.256533 done
755 09:21:00.258992 Bytes transferred = 47391296 (2d32240 hex)
757 09:21:00.360112 => tftpboot 0x08000000 880221/tftp-deploy-znflckp3/ramdisk/ramdisk.cpio.gz.uboot
758 09:21:00.360689 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
759 09:21:00.367582 tftpboot 0x08000000 880221/tftp-deploy-znflckp3/ramdisk/ramdisk.cpio.gz.uboot
760 09:21:00.367974 Speed: 1000, full duplex
761 09:21:00.368380 Using ethernet@ff3f0000 device
762 09:21:00.373031 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 09:21:00.382686 Filename '880221/tftp-deploy-znflckp3/ramdisk/ramdisk.cpio.gz.uboot'.
764 09:21:00.383042 Load address: 0x8000000
765 09:21:07.263315 Loading: *#######################################T ########## UDP wrong checksum 00000005 00001a1d
766 09:21:12.264680 T UDP wrong checksum 00000005 00001a1d
767 09:21:15.819166 UDP wrong checksum 00000005 0000b8d5
768 09:21:22.265834 T T UDP wrong checksum 00000005 00001a1d
769 09:21:25.802430 UDP wrong checksum 000000ff 00000030
770 09:21:25.815636 UDP wrong checksum 000000ff 00009622
771 09:21:42.270726 T T T T UDP wrong checksum 00000005 00001a1d
772 09:21:57.273354 T T
773 09:21:57.273762 Retry count exceeded; starting again
775 09:21:57.275874 end: 2.4.3 bootloader-commands (duration 00:01:02) [common]
778 09:21:57.279069 end: 2.4 uboot-commands (duration 00:01:21) [common]
780 09:21:57.280611 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
782 09:21:57.281702 end: 2 uboot-action (duration 00:01:21) [common]
784 09:21:57.285471 Cleaning after the job
785 09:21:57.286904 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/ramdisk
786 09:21:57.289533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/kernel
787 09:21:57.303627 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/dtb
788 09:21:57.304618 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880221/tftp-deploy-znflckp3/modules
789 09:21:57.308018 start: 4.1 power-off (timeout 00:00:30) [common]
790 09:21:57.308638 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
791 09:21:57.339726 >> OK - accepted request
792 09:21:57.341617 Returned 0 in 0 seconds
793 09:21:57.442768 end: 4.1 power-off (duration 00:00:00) [common]
795 09:21:57.443802 start: 4.2 read-feedback (timeout 00:10:00) [common]
796 09:21:57.444604 Listened to connection for namespace 'common' for up to 1s
797 09:21:58.445570 Finalising connection for namespace 'common'
798 09:21:58.446416 Disconnecting from shell: Finalise
799 09:21:58.446980 =>
800 09:21:58.548069 end: 4.2 read-feedback (duration 00:00:01) [common]
801 09:21:58.548836 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/880221
802 09:21:59.157604 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/880221
803 09:21:59.158199 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.