Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:17:57.333120 lava-dispatcher, installed at version: 2024.01
2 09:17:57.333914 start: 0 validate
3 09:17:57.334378 Start time: 2024-10-22 09:17:57.334347+00:00 (UTC)
4 09:17:57.334944 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:17:57.335551 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:17:57.375336 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:17:57.375913 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:17:57.408449 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:17:57.409066 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 09:17:58.459542 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:17:58.460072 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 09:17:58.500832 validate duration: 1.17
14 09:17:58.501693 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:17:58.502020 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:17:58.502332 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:17:58.502931 Not decompressing ramdisk as can be used compressed.
18 09:17:58.503353 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:17:58.503621 saving as /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/ramdisk/rootfs.cpio.gz
20 09:17:58.503904 total size: 8181887 (7 MB)
21 09:17:58.538756 progress 0 % (0 MB)
22 09:17:58.551000 progress 5 % (0 MB)
23 09:17:58.562656 progress 10 % (0 MB)
24 09:17:58.573233 progress 15 % (1 MB)
25 09:17:58.578620 progress 20 % (1 MB)
26 09:17:58.584542 progress 25 % (1 MB)
27 09:17:58.590016 progress 30 % (2 MB)
28 09:17:58.595690 progress 35 % (2 MB)
29 09:17:58.601041 progress 40 % (3 MB)
30 09:17:58.606747 progress 45 % (3 MB)
31 09:17:58.612306 progress 50 % (3 MB)
32 09:17:58.617911 progress 55 % (4 MB)
33 09:17:58.623166 progress 60 % (4 MB)
34 09:17:58.628928 progress 65 % (5 MB)
35 09:17:58.634273 progress 70 % (5 MB)
36 09:17:58.640169 progress 75 % (5 MB)
37 09:17:58.645565 progress 80 % (6 MB)
38 09:17:58.651299 progress 85 % (6 MB)
39 09:17:58.656623 progress 90 % (7 MB)
40 09:17:58.662488 progress 95 % (7 MB)
41 09:17:58.667568 progress 100 % (7 MB)
42 09:17:58.668261 7 MB downloaded in 0.16 s (47.48 MB/s)
43 09:17:58.668817 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:17:58.669706 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:17:58.669998 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:17:58.670271 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:17:58.670734 downloading http://storage.kernelci.org/next/master/next-20241022/arm64/defconfig/gcc-12/kernel/Image
49 09:17:58.670981 saving as /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/kernel/Image
50 09:17:58.671191 total size: 45910528 (43 MB)
51 09:17:58.671403 No compression specified
52 09:17:58.708858 progress 0 % (0 MB)
53 09:17:58.736884 progress 5 % (2 MB)
54 09:17:58.764995 progress 10 % (4 MB)
55 09:17:58.793176 progress 15 % (6 MB)
56 09:17:58.821568 progress 20 % (8 MB)
57 09:17:58.849531 progress 25 % (10 MB)
58 09:17:58.877767 progress 30 % (13 MB)
59 09:17:58.907811 progress 35 % (15 MB)
60 09:17:58.935813 progress 40 % (17 MB)
61 09:17:58.963816 progress 45 % (19 MB)
62 09:17:58.993102 progress 50 % (21 MB)
63 09:17:59.022766 progress 55 % (24 MB)
64 09:17:59.050901 progress 60 % (26 MB)
65 09:17:59.078814 progress 65 % (28 MB)
66 09:17:59.106727 progress 70 % (30 MB)
67 09:17:59.134898 progress 75 % (32 MB)
68 09:17:59.162825 progress 80 % (35 MB)
69 09:17:59.190640 progress 85 % (37 MB)
70 09:17:59.218349 progress 90 % (39 MB)
71 09:17:59.246696 progress 95 % (41 MB)
72 09:17:59.274227 progress 100 % (43 MB)
73 09:17:59.274777 43 MB downloaded in 0.60 s (72.54 MB/s)
74 09:17:59.275275 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:17:59.276132 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:17:59.276417 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:17:59.276682 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:17:59.277165 downloading http://storage.kernelci.org/next/master/next-20241022/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 09:17:59.277417 saving as /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 09:17:59.277627 total size: 53209 (0 MB)
82 09:17:59.277839 No compression specified
83 09:17:59.318806 progress 61 % (0 MB)
84 09:17:59.319674 progress 100 % (0 MB)
85 09:17:59.320268 0 MB downloaded in 0.04 s (1.19 MB/s)
86 09:17:59.320762 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:17:59.321596 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:17:59.321878 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:17:59.322146 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:17:59.322621 downloading http://storage.kernelci.org/next/master/next-20241022/arm64/defconfig/gcc-12/modules.tar.xz
92 09:17:59.322869 saving as /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/modules/modules.tar
93 09:17:59.323075 total size: 11636672 (11 MB)
94 09:17:59.323287 Using unxz to decompress xz
95 09:17:59.362203 progress 0 % (0 MB)
96 09:17:59.434546 progress 5 % (0 MB)
97 09:17:59.512055 progress 10 % (1 MB)
98 09:17:59.595898 progress 15 % (1 MB)
99 09:17:59.678448 progress 20 % (2 MB)
100 09:17:59.751814 progress 25 % (2 MB)
101 09:17:59.832104 progress 30 % (3 MB)
102 09:17:59.910313 progress 35 % (3 MB)
103 09:17:59.996950 progress 40 % (4 MB)
104 09:18:00.079245 progress 45 % (5 MB)
105 09:18:00.161234 progress 50 % (5 MB)
106 09:18:00.245315 progress 55 % (6 MB)
107 09:18:00.327667 progress 60 % (6 MB)
108 09:18:00.408029 progress 65 % (7 MB)
109 09:18:00.489577 progress 70 % (7 MB)
110 09:18:00.578122 progress 75 % (8 MB)
111 09:18:00.668491 progress 80 % (8 MB)
112 09:18:00.745384 progress 85 % (9 MB)
113 09:18:00.818662 progress 90 % (10 MB)
114 09:18:00.917719 progress 95 % (10 MB)
115 09:18:01.015797 progress 100 % (11 MB)
116 09:18:01.028021 11 MB downloaded in 1.70 s (6.51 MB/s)
117 09:18:01.029052 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:18:01.030808 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:18:01.031389 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 09:18:01.031966 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 09:18:01.032560 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:18:01.033121 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 09:18:01.034203 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx
125 09:18:01.035078 makedir: /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin
126 09:18:01.035759 makedir: /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/tests
127 09:18:01.036488 makedir: /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/results
128 09:18:01.037159 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-add-keys
129 09:18:01.038175 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-add-sources
130 09:18:01.039190 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-background-process-start
131 09:18:01.040253 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-background-process-stop
132 09:18:01.041331 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-common-functions
133 09:18:01.042355 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-echo-ipv4
134 09:18:01.043372 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-install-packages
135 09:18:01.044484 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-installed-packages
136 09:18:01.045477 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-os-build
137 09:18:01.046443 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-probe-channel
138 09:18:01.047415 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-probe-ip
139 09:18:01.048545 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-target-ip
140 09:18:01.049533 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-target-mac
141 09:18:01.050507 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-target-storage
142 09:18:01.051496 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-test-case
143 09:18:01.052522 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-test-event
144 09:18:01.053506 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-test-feedback
145 09:18:01.054473 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-test-raise
146 09:18:01.055453 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-test-reference
147 09:18:01.056493 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-test-runner
148 09:18:01.057502 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-test-set
149 09:18:01.058481 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-test-shell
150 09:18:01.059486 Updating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-install-packages (oe)
151 09:18:01.060579 Updating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/bin/lava-installed-packages (oe)
152 09:18:01.061492 Creating /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/environment
153 09:18:01.062261 LAVA metadata
154 09:18:01.062793 - LAVA_JOB_ID=880152
155 09:18:01.063268 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:18:01.064031 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 09:18:01.065996 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:18:01.066648 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 09:18:01.067107 skipped lava-vland-overlay
160 09:18:01.067651 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:18:01.068254 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 09:18:01.068691 skipped lava-multinode-overlay
163 09:18:01.069176 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:18:01.069677 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 09:18:01.070155 Loading test definitions
166 09:18:01.070697 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 09:18:01.071136 Using /lava-880152 at stage 0
168 09:18:01.073374 uuid=880152_1.5.2.4.1 testdef=None
169 09:18:01.073951 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:18:01.074468 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 09:18:01.077021 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:18:01.077840 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 09:18:01.080166 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:18:01.081014 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 09:18:01.083217 runner path: /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/0/tests/0_dmesg test_uuid 880152_1.5.2.4.1
178 09:18:01.083785 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:18:01.084594 Creating lava-test-runner.conf files
181 09:18:01.084801 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/880152/lava-overlay-djlvq9yx/lava-880152/0 for stage 0
182 09:18:01.085151 - 0_dmesg
183 09:18:01.085508 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:18:01.085791 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 09:18:01.109640 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:18:01.110054 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 09:18:01.110322 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:18:01.110591 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:18:01.110860 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 09:18:02.025614 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:18:02.026078 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 09:18:02.026330 extracting modules file /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/880152/extract-overlay-ramdisk-b4pcbndq/ramdisk
193 09:18:03.366993 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 09:18:03.367476 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 09:18:03.367754 [common] Applying overlay /var/lib/lava/dispatcher/tmp/880152/compress-overlay-0h3dcasb/overlay-1.5.2.5.tar.gz to ramdisk
196 09:18:03.367966 [common] Applying overlay /var/lib/lava/dispatcher/tmp/880152/compress-overlay-0h3dcasb/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/880152/extract-overlay-ramdisk-b4pcbndq/ramdisk
197 09:18:03.398514 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:18:03.398942 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 09:18:03.399213 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 09:18:03.399443 Converting downloaded kernel to a uImage
201 09:18:03.399745 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/kernel/Image /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/kernel/uImage
202 09:18:03.915466 output: Image Name:
203 09:18:03.915888 output: Created: Tue Oct 22 09:18:03 2024
204 09:18:03.916147 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:18:03.916364 output: Data Size: 45910528 Bytes = 44834.50 KiB = 43.78 MiB
206 09:18:03.916569 output: Load Address: 01080000
207 09:18:03.916769 output: Entry Point: 01080000
208 09:18:03.916968 output:
209 09:18:03.917315 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 09:18:03.917623 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 09:18:03.917905 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 09:18:03.918167 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:18:03.918430 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 09:18:03.918687 Building ramdisk /var/lib/lava/dispatcher/tmp/880152/extract-overlay-ramdisk-b4pcbndq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/880152/extract-overlay-ramdisk-b4pcbndq/ramdisk
215 09:18:06.345959 >> 182363 blocks
216 09:18:15.497131 Adding RAMdisk u-boot header.
217 09:18:15.497776 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/880152/extract-overlay-ramdisk-b4pcbndq/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/880152/extract-overlay-ramdisk-b4pcbndq/ramdisk.cpio.gz.uboot
218 09:18:15.780627 output: Image Name:
219 09:18:15.781041 output: Created: Tue Oct 22 09:18:15 2024
220 09:18:15.781251 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:18:15.781455 output: Data Size: 26121957 Bytes = 25509.72 KiB = 24.91 MiB
222 09:18:15.781656 output: Load Address: 00000000
223 09:18:15.781853 output: Entry Point: 00000000
224 09:18:15.782049 output:
225 09:18:15.782719 rename /var/lib/lava/dispatcher/tmp/880152/extract-overlay-ramdisk-b4pcbndq/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/ramdisk/ramdisk.cpio.gz.uboot
226 09:18:15.783138 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 09:18:15.783424 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 09:18:15.783695 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 09:18:15.783935 No LXC device requested
230 09:18:15.784434 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:18:15.784951 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 09:18:15.785444 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:18:15.785884 Checking files for TFTP limit of 4294967296 bytes.
234 09:18:15.788725 end: 1 tftp-deploy (duration 00:00:17) [common]
235 09:18:15.789324 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:18:15.789842 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:18:15.790337 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:18:15.790836 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:18:15.791366 Using kernel file from prepare-kernel: 880152/tftp-deploy-ejhvbgbx/kernel/uImage
240 09:18:15.791967 substitutions:
241 09:18:15.792413 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:18:15.792816 - {DTB_ADDR}: 0x01070000
243 09:18:15.793211 - {DTB}: 880152/tftp-deploy-ejhvbgbx/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 09:18:15.793605 - {INITRD}: 880152/tftp-deploy-ejhvbgbx/ramdisk/ramdisk.cpio.gz.uboot
245 09:18:15.794002 - {KERNEL_ADDR}: 0x01080000
246 09:18:15.794393 - {KERNEL}: 880152/tftp-deploy-ejhvbgbx/kernel/uImage
247 09:18:15.794786 - {LAVA_MAC}: None
248 09:18:15.795220 - {PRESEED_CONFIG}: None
249 09:18:15.795613 - {PRESEED_LOCAL}: None
250 09:18:15.796023 - {RAMDISK_ADDR}: 0x08000000
251 09:18:15.796415 - {RAMDISK}: 880152/tftp-deploy-ejhvbgbx/ramdisk/ramdisk.cpio.gz.uboot
252 09:18:15.796809 - {ROOT_PART}: None
253 09:18:15.797200 - {ROOT}: None
254 09:18:15.797591 - {SERVER_IP}: 192.168.6.2
255 09:18:15.797985 - {TEE_ADDR}: 0x83000000
256 09:18:15.798376 - {TEE}: None
257 09:18:15.798767 Parsed boot commands:
258 09:18:15.799145 - setenv autoload no
259 09:18:15.799533 - setenv initrd_high 0xffffffff
260 09:18:15.799923 - setenv fdt_high 0xffffffff
261 09:18:15.800340 - dhcp
262 09:18:15.800731 - setenv serverip 192.168.6.2
263 09:18:15.801119 - tftpboot 0x01080000 880152/tftp-deploy-ejhvbgbx/kernel/uImage
264 09:18:15.801506 - tftpboot 0x08000000 880152/tftp-deploy-ejhvbgbx/ramdisk/ramdisk.cpio.gz.uboot
265 09:18:15.801892 - tftpboot 0x01070000 880152/tftp-deploy-ejhvbgbx/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 09:18:15.802277 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:18:15.802666 - bootm 0x01080000 0x08000000 0x01070000
268 09:18:15.803155 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:18:15.804693 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:18:15.805167 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 09:18:15.819431 Setting prompt string to ['lava-test: # ']
273 09:18:15.820928 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:18:15.821509 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:18:15.822052 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:18:15.822560 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:18:15.823653 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 09:18:15.860327 >> OK - accepted request
279 09:18:15.862630 Returned 0 in 0 seconds
280 09:18:15.963699 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:18:15.965347 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:18:15.965910 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:18:15.966444 Setting prompt string to ['Hit any key to stop autoboot']
285 09:18:15.966910 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:18:15.968515 Trying 192.168.56.21...
287 09:18:15.969002 Connected to conserv1.
288 09:18:15.969423 Escape character is '^]'.
289 09:18:15.969847
290 09:18:15.970276 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 09:18:15.970697
292 09:18:23.134896 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 09:18:23.135333 bl2_stage_init 0x01
294 09:18:23.135607 bl2_stage_init 0x81
295 09:18:23.140362 hw id: 0x0000 - pwm id 0x01
296 09:18:23.140696 bl2_stage_init 0xc1
297 09:18:23.145860 bl2_stage_init 0x02
298 09:18:23.146174
299 09:18:23.146419 L0:00000000
300 09:18:23.146667 L1:00000703
301 09:18:23.146895 L2:00008067
302 09:18:23.147124 L3:15000000
303 09:18:23.151536 S1:00000000
304 09:18:23.151848 B2:20282000
305 09:18:23.152126 B1:a0f83180
306 09:18:23.152362
307 09:18:23.152602 TE: 67848
308 09:18:23.152837
309 09:18:23.156934 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 09:18:23.157235
311 09:18:23.162668 Board ID = 1
312 09:18:23.162970 Set cpu clk to 24M
313 09:18:23.163207 Set clk81 to 24M
314 09:18:23.168241 Use GP1_pll as DSU clk.
315 09:18:23.168545 DSU clk: 1200 Mhz
316 09:18:23.168784 CPU clk: 1200 MHz
317 09:18:23.173833 Set clk81 to 166.6M
318 09:18:23.179497 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 09:18:23.179830 board id: 1
320 09:18:23.186532 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:18:23.197148 fw parse done
322 09:18:23.203128 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:18:23.245795 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:18:23.256735 PIEI prepare done
325 09:18:23.257118 fastboot data load
326 09:18:23.257367 fastboot data verify
327 09:18:23.262263 verify result: 266
328 09:18:23.267928 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 09:18:23.268315 LPDDR4 probe
330 09:18:23.268561 ddr clk to 1584MHz
331 09:18:23.275877 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:18:23.313151
333 09:18:23.313753 dmc_version 0001
334 09:18:23.319795 Check phy result
335 09:18:23.325713 INFO : End of CA training
336 09:18:23.326166 INFO : End of initialization
337 09:18:23.331281 INFO : Training has run successfully!
338 09:18:23.331725 Check phy result
339 09:18:23.336895 INFO : End of initialization
340 09:18:23.337337 INFO : End of read enable training
341 09:18:23.342491 INFO : End of fine write leveling
342 09:18:23.348118 INFO : End of Write leveling coarse delay
343 09:18:23.348574 INFO : Training has run successfully!
344 09:18:23.348970 Check phy result
345 09:18:23.354495 INFO : End of initialization
346 09:18:23.355000 INFO : End of read dq deskew training
347 09:18:23.359304 INFO : End of MPR read delay center optimization
348 09:18:23.364949 INFO : End of write delay center optimization
349 09:18:23.370752 INFO : End of read delay center optimization
350 09:18:23.371386 INFO : End of max read latency training
351 09:18:23.376318 INFO : Training has run successfully!
352 09:18:23.376937 1D training succeed
353 09:18:23.385329 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:18:23.432716 Check phy result
355 09:18:23.433159 INFO : End of initialization
356 09:18:23.457814 INFO : End of 2D read delay Voltage center optimization
357 09:18:23.474333 INFO : End of 2D read delay Voltage center optimization
358 09:18:23.526412 INFO : End of 2D write delay Voltage center optimization
359 09:18:23.575533 INFO : End of 2D write delay Voltage center optimization
360 09:18:23.580926 INFO : Training has run successfully!
361 09:18:23.581173
362 09:18:23.581380 channel==0
363 09:18:23.586508 RxClkDly_Margin_A0==78 ps 8
364 09:18:23.586745 TxDqDly_Margin_A0==98 ps 10
365 09:18:23.592224 RxClkDly_Margin_A1==88 ps 9
366 09:18:23.592670 TxDqDly_Margin_A1==98 ps 10
367 09:18:23.593086 TrainedVREFDQ_A0==76
368 09:18:23.597831 TrainedVREFDQ_A1==75
369 09:18:23.598282 VrefDac_Margin_A0==22
370 09:18:23.598677 DeviceVref_Margin_A0==38
371 09:18:23.603391 VrefDac_Margin_A1==23
372 09:18:23.603846 DeviceVref_Margin_A1==39
373 09:18:23.604296
374 09:18:23.604693
375 09:18:23.609000 channel==1
376 09:18:23.609450 RxClkDly_Margin_A0==78 ps 8
377 09:18:23.609842 TxDqDly_Margin_A0==98 ps 10
378 09:18:23.614672 RxClkDly_Margin_A1==88 ps 9
379 09:18:23.615123 TxDqDly_Margin_A1==78 ps 8
380 09:18:23.620310 TrainedVREFDQ_A0==78
381 09:18:23.620787 TrainedVREFDQ_A1==75
382 09:18:23.621182 VrefDac_Margin_A0==22
383 09:18:23.625831 DeviceVref_Margin_A0==36
384 09:18:23.626265 VrefDac_Margin_A1==22
385 09:18:23.631418 DeviceVref_Margin_A1==39
386 09:18:23.631844
387 09:18:23.632278 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:18:23.632671
389 09:18:23.665060 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000016 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000017 dram_vref_reg_value 0x 00000062
390 09:18:23.665645 2D training succeed
391 09:18:23.670574 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:18:23.676223 auto size-- 65535DDR cs0 size: 2048MB
393 09:18:23.676659 DDR cs1 size: 2048MB
394 09:18:23.681736 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:18:23.682180 cs0 DataBus test pass
396 09:18:23.687370 cs1 DataBus test pass
397 09:18:23.687790 cs0 AddrBus test pass
398 09:18:23.688214 cs1 AddrBus test pass
399 09:18:23.688602
400 09:18:23.692933 100bdlr_step_size ps== 478
401 09:18:23.693371 result report
402 09:18:23.698538 boot times 0Enable ddr reg access
403 09:18:23.703445 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:18:23.716753 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 09:18:24.373517 bl2z: ptr: 05129330, size: 00001e40
406 09:18:24.379919 0.0;M3 CHK:0;cm4_sp_mode 0
407 09:18:24.380250 MVN_1=0x00000000
408 09:18:24.380470 MVN_2=0x00000000
409 09:18:24.391396 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 09:18:24.391695 OPS=0x04
411 09:18:24.391912 ring efuse init
412 09:18:24.396999 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 09:18:24.397269 [0.017319 Inits done]
414 09:18:24.397481 secure task start!
415 09:18:24.404858 high task start!
416 09:18:24.405153 low task start!
417 09:18:24.405365 run into bl31
418 09:18:24.413434 NOTICE: BL31: v1.3(release):4fc40b1
419 09:18:24.421190 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 09:18:24.421517 NOTICE: BL31: G12A normal boot!
421 09:18:24.436848 NOTICE: BL31: BL33 decompress pass
422 09:18:24.442481 ERROR: Error initializing runtime service opteed_fast
423 09:18:27.186641 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 09:18:27.187075 bl2_stage_init 0x01
425 09:18:27.187296 bl2_stage_init 0x81
426 09:18:27.192274 hw id: 0x0000 - pwm id 0x01
427 09:18:27.192571 bl2_stage_init 0xc1
428 09:18:27.192779 bl2_stage_init 0x02
429 09:18:27.192984
430 09:18:27.197853 L0:00000000
431 09:18:27.198131 L1:00000703
432 09:18:27.198338 L2:00008067
433 09:18:27.198537 L3:15000000
434 09:18:27.198735 S1:00000000
435 09:18:27.200376 B2:20282000
436 09:18:27.200624 B1:a0f83180
437 09:18:27.200828
438 09:18:27.205978 TE: 69408
439 09:18:27.206249
440 09:18:27.211494 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 09:18:27.211779
442 09:18:27.212035 Board ID = 1
443 09:18:27.212252 Set cpu clk to 24M
444 09:18:27.217220 Set clk81 to 24M
445 09:18:27.217489 Use GP1_pll as DSU clk.
446 09:18:27.217698 DSU clk: 1200 Mhz
447 09:18:27.222747 CPU clk: 1200 MHz
448 09:18:27.223010 Set clk81 to 166.6M
449 09:18:27.228304 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 09:18:27.228575 board id: 1
451 09:18:27.237630 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 09:18:27.248558 fw parse done
453 09:18:27.253479 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 09:18:27.296642 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 09:18:27.308086 PIEI prepare done
456 09:18:27.308376 fastboot data load
457 09:18:27.308588 fastboot data verify
458 09:18:27.313593 verify result: 266
459 09:18:27.319188 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 09:18:27.319448 LPDDR4 probe
461 09:18:27.319654 ddr clk to 1584MHz
462 09:18:27.326919 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 09:18:27.363786
464 09:18:27.364207 dmc_version 0001
465 09:18:27.370558 Check phy result
466 09:18:27.376971 INFO : End of CA training
467 09:18:27.377257 INFO : End of initialization
468 09:18:27.382539 INFO : Training has run successfully!
469 09:18:27.382812 Check phy result
470 09:18:27.388137 INFO : End of initialization
471 09:18:27.388411 INFO : End of read enable training
472 09:18:27.393727 INFO : End of fine write leveling
473 09:18:27.399315 INFO : End of Write leveling coarse delay
474 09:18:27.399589 INFO : Training has run successfully!
475 09:18:27.399802 Check phy result
476 09:18:27.405023 INFO : End of initialization
477 09:18:27.405290 INFO : End of read dq deskew training
478 09:18:27.410540 INFO : End of MPR read delay center optimization
479 09:18:27.416254 INFO : End of write delay center optimization
480 09:18:27.421860 INFO : End of read delay center optimization
481 09:18:27.422140 INFO : End of max read latency training
482 09:18:27.427426 INFO : Training has run successfully!
483 09:18:27.427734 1D training succeed
484 09:18:27.436623 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 09:18:27.483452 Check phy result
486 09:18:27.483808 INFO : End of initialization
487 09:18:27.505844 INFO : End of 2D read delay Voltage center optimization
488 09:18:27.525171 INFO : End of 2D read delay Voltage center optimization
489 09:18:27.577565 INFO : End of 2D write delay Voltage center optimization
490 09:18:27.626822 INFO : End of 2D write delay Voltage center optimization
491 09:18:27.632352 INFO : Training has run successfully!
492 09:18:27.632653
493 09:18:27.632868 channel==0
494 09:18:27.637981 RxClkDly_Margin_A0==88 ps 9
495 09:18:27.638250 TxDqDly_Margin_A0==88 ps 9
496 09:18:27.641283 RxClkDly_Margin_A1==78 ps 8
497 09:18:27.641553 TxDqDly_Margin_A1==88 ps 9
498 09:18:27.646779 TrainedVREFDQ_A0==74
499 09:18:27.647059 TrainedVREFDQ_A1==74
500 09:18:27.647274 VrefDac_Margin_A0==23
501 09:18:27.652376 DeviceVref_Margin_A0==40
502 09:18:27.652689 VrefDac_Margin_A1==23
503 09:18:27.658048 DeviceVref_Margin_A1==40
504 09:18:27.658369
505 09:18:27.658582
506 09:18:27.658788 channel==1
507 09:18:27.658993 RxClkDly_Margin_A0==78 ps 8
508 09:18:27.663622 TxDqDly_Margin_A0==98 ps 10
509 09:18:27.663947 RxClkDly_Margin_A1==88 ps 9
510 09:18:27.669285 TxDqDly_Margin_A1==78 ps 8
511 09:18:27.669606 TrainedVREFDQ_A0==78
512 09:18:27.669822 TrainedVREFDQ_A1==75
513 09:18:27.674831 VrefDac_Margin_A0==23
514 09:18:27.675151 DeviceVref_Margin_A0==36
515 09:18:27.680414 VrefDac_Margin_A1==20
516 09:18:27.680746 DeviceVref_Margin_A1==39
517 09:18:27.680959
518 09:18:27.686042 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 09:18:27.686357
520 09:18:27.714039 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000018 00000019 00000016 00000018 00000014 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
521 09:18:27.719600 2D training succeed
522 09:18:27.725299 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 09:18:27.725576 auto size-- 65535DDR cs0 size: 2048MB
524 09:18:27.730796 DDR cs1 size: 2048MB
525 09:18:27.731067 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 09:18:27.736450 cs0 DataBus test pass
527 09:18:27.736726 cs1 DataBus test pass
528 09:18:27.736932 cs0 AddrBus test pass
529 09:18:27.742070 cs1 AddrBus test pass
530 09:18:27.742347
531 09:18:27.742557 100bdlr_step_size ps== 478
532 09:18:27.742761 result report
533 09:18:27.747591 boot times 0Enable ddr reg access
534 09:18:27.754462 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 09:18:27.768185 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 09:18:28.424548 bl2z: ptr: 05129330, size: 00001e40
537 09:18:28.430038 0.0;M3 CHK:0;cm4_sp_mode 0
538 09:18:28.430379 MVN_1=0x00000000
539 09:18:28.430624 MVN_2=0x00000000
540 09:18:28.435596 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 09:18:28.435929 OPS=0x04
542 09:18:28.442525 ring efuse init
543 09:18:28.442872 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 09:18:28.448214 [0.017310 Inits done]
545 09:18:28.448561 secure task start!
546 09:18:28.448799 high task start!
547 09:18:28.453244 low task start!
548 09:18:28.453875 run into bl31
549 09:18:28.461853 NOTICE: BL31: v1.3(release):4fc40b1
550 09:18:28.468789 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 09:18:28.469377 NOTICE: BL31: G12A normal boot!
552 09:18:28.485315 NOTICE: BL31: BL33 decompress pass
553 09:18:28.489862 ERROR: Error initializing runtime service opteed_fast
554 09:18:29.886600 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 09:18:29.887063 bl2_stage_init 0x01
556 09:18:29.887295 bl2_stage_init 0x81
557 09:18:29.892155 hw id: 0x0000 - pwm id 0x01
558 09:18:29.892662 bl2_stage_init 0xc1
559 09:18:29.897524 bl2_stage_init 0x02
560 09:18:29.897872
561 09:18:29.898100 L0:00000000
562 09:18:29.898425 L1:00000703
563 09:18:29.898690 L2:00008067
564 09:18:29.898902 L3:15000000
565 09:18:29.903062 S1:00000000
566 09:18:29.903492 B2:20282000
567 09:18:29.903747 B1:a0f83180
568 09:18:29.903957
569 09:18:29.904225 TE: 69851
570 09:18:29.904450
571 09:18:29.908675 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 09:18:29.909066
573 09:18:29.914301 Board ID = 1
574 09:18:29.914645 Set cpu clk to 24M
575 09:18:29.914961 Set clk81 to 24M
576 09:18:29.919935 Use GP1_pll as DSU clk.
577 09:18:29.920370 DSU clk: 1200 Mhz
578 09:18:29.920603 CPU clk: 1200 MHz
579 09:18:29.925622 Set clk81 to 166.6M
580 09:18:29.931089 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 09:18:29.931883 board id: 1
582 09:18:29.937860 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 09:18:29.949165 fw parse done
584 09:18:29.954691 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 09:18:29.997503 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 09:18:30.008754 PIEI prepare done
587 09:18:30.009160 fastboot data load
588 09:18:30.009401 fastboot data verify
589 09:18:30.014345 verify result: 266
590 09:18:30.019887 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 09:18:30.020284 LPDDR4 probe
592 09:18:30.020537 ddr clk to 1584MHz
593 09:18:30.026969 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 09:18:30.064363
595 09:18:30.064911 dmc_version 0001
596 09:18:30.070949 Check phy result
597 09:18:30.077684 INFO : End of CA training
598 09:18:30.078030 INFO : End of initialization
599 09:18:30.083369 INFO : Training has run successfully!
600 09:18:30.083799 Check phy result
601 09:18:30.088920 INFO : End of initialization
602 09:18:30.089294 INFO : End of read enable training
603 09:18:30.094655 INFO : End of fine write leveling
604 09:18:30.100091 INFO : End of Write leveling coarse delay
605 09:18:30.100500 INFO : Training has run successfully!
606 09:18:30.100713 Check phy result
607 09:18:30.105724 INFO : End of initialization
608 09:18:30.106080 INFO : End of read dq deskew training
609 09:18:30.111380 INFO : End of MPR read delay center optimization
610 09:18:30.116878 INFO : End of write delay center optimization
611 09:18:30.122567 INFO : End of read delay center optimization
612 09:18:30.122947 INFO : End of max read latency training
613 09:18:30.128057 INFO : Training has run successfully!
614 09:18:30.128541 1D training succeed
615 09:18:30.136585 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 09:18:30.184028 Check phy result
617 09:18:30.184440 INFO : End of initialization
618 09:18:30.207185 INFO : End of 2D read delay Voltage center optimization
619 09:18:30.226431 INFO : End of 2D read delay Voltage center optimization
620 09:18:30.277817 INFO : End of 2D write delay Voltage center optimization
621 09:18:30.327589 INFO : End of 2D write delay Voltage center optimization
622 09:18:30.333261 INFO : Training has run successfully!
623 09:18:30.333640
624 09:18:30.333865 channel==0
625 09:18:30.338883 RxClkDly_Margin_A0==78 ps 8
626 09:18:30.339236 TxDqDly_Margin_A0==98 ps 10
627 09:18:30.344425 RxClkDly_Margin_A1==78 ps 8
628 09:18:30.344837 TxDqDly_Margin_A1==88 ps 9
629 09:18:30.345070 TrainedVREFDQ_A0==76
630 09:18:30.350642 TrainedVREFDQ_A1==74
631 09:18:30.351474 VrefDac_Margin_A0==22
632 09:18:30.351930 DeviceVref_Margin_A0==38
633 09:18:30.356683 VrefDac_Margin_A1==22
634 09:18:30.357116 DeviceVref_Margin_A1==40
635 09:18:30.357344
636 09:18:30.357565
637 09:18:30.357775 channel==1
638 09:18:30.361035 RxClkDly_Margin_A0==78 ps 8
639 09:18:30.361353 TxDqDly_Margin_A0==98 ps 10
640 09:18:30.366706 RxClkDly_Margin_A1==78 ps 8
641 09:18:30.367025 TxDqDly_Margin_A1==78 ps 8
642 09:18:30.372263 TrainedVREFDQ_A0==78
643 09:18:30.372575 TrainedVREFDQ_A1==75
644 09:18:30.372790 VrefDac_Margin_A0==22
645 09:18:30.377862 DeviceVref_Margin_A0==36
646 09:18:30.378177 VrefDac_Margin_A1==22
647 09:18:30.383448 DeviceVref_Margin_A1==39
648 09:18:30.383782
649 09:18:30.384031 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 09:18:30.384252
651 09:18:30.417040 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 09:18:30.417410 2D training succeed
653 09:18:30.422622 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 09:18:30.428276 auto size-- 65535DDR cs0 size: 2048MB
655 09:18:30.428592 DDR cs1 size: 2048MB
656 09:18:30.433830 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 09:18:30.434129 cs0 DataBus test pass
658 09:18:30.439421 cs1 DataBus test pass
659 09:18:30.439720 cs0 AddrBus test pass
660 09:18:30.439940 cs1 AddrBus test pass
661 09:18:30.440183
662 09:18:30.445043 100bdlr_step_size ps== 478
663 09:18:30.445321 result report
664 09:18:30.450632 boot times 0Enable ddr reg access
665 09:18:30.454909 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 09:18:30.468796 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 09:18:31.123547 bl2z: ptr: 05129330, size: 00001e40
668 09:18:31.131369 0.0;M3 CHK:0;cm4_sp_mode 0
669 09:18:31.131809 MVN_1=0x00000000
670 09:18:31.132092 MVN_2=0x00000000
671 09:18:31.142862 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 09:18:31.143173 OPS=0x04
673 09:18:31.143390 ring efuse init
674 09:18:31.148444 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 09:18:31.148721 [0.017319 Inits done]
676 09:18:31.148936 secure task start!
677 09:18:31.154861 high task start!
678 09:18:31.155135 low task start!
679 09:18:31.155343 run into bl31
680 09:18:31.164458 NOTICE: BL31: v1.3(release):4fc40b1
681 09:18:31.172140 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 09:18:31.172454 NOTICE: BL31: G12A normal boot!
683 09:18:31.187736 NOTICE: BL31: BL33 decompress pass
684 09:18:31.193277 ERROR: Error initializing runtime service opteed_fast
685 09:18:31.987600
686 09:18:31.988076
687 09:18:31.992998 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 09:18:31.993360
689 09:18:31.996495 Model: Libre Computer AML-S905D3-CC Solitude
690 09:18:32.143307 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 09:18:32.158679 DRAM: 2 GiB (effective 3.8 GiB)
692 09:18:32.259699 Core: 406 devices, 33 uclasses, devicetree: separate
693 09:18:32.265745 WDT: Not starting watchdog@f0d0
694 09:18:32.290637 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 09:18:32.302919 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 09:18:32.307965 ** Bad device specification mmc 0 **
697 09:18:32.317901 Card did not respond to voltage select! : -110
698 09:18:32.325556 ** Bad device specification mmc 0 **
699 09:18:32.325895 Couldn't find partition mmc 0
700 09:18:32.333874 Card did not respond to voltage select! : -110
701 09:18:32.339380 ** Bad device specification mmc 0 **
702 09:18:32.339702 Couldn't find partition mmc 0
703 09:18:32.344453 Error: could not access storage.
704 09:18:32.640875 Net: eth0: ethernet@ff3f0000
705 09:18:32.641304 starting USB...
706 09:18:32.885493 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 09:18:32.886057 Starting the controller
708 09:18:32.892402 USB XHCI 1.10
709 09:18:34.446642 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 09:18:34.454938 scanning usb for storage devices... 0 Storage Device(s) found
712 09:18:34.506317 Hit any key to stop autoboot: 1
713 09:18:34.507169 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 09:18:34.507748 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 09:18:34.508088 Setting prompt string to ['=>']
716 09:18:34.508382 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 09:18:34.520918 0
718 09:18:34.521726 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 09:18:34.622551 => setenv autoload no
721 09:18:34.623233 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 09:18:34.627633 setenv autoload no
724 09:18:34.728757 => setenv initrd_high 0xffffffff
725 09:18:34.729253 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 09:18:34.733817 setenv initrd_high 0xffffffff
728 09:18:34.835035 => setenv fdt_high 0xffffffff
729 09:18:34.835689 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 09:18:34.840303 setenv fdt_high 0xffffffff
732 09:18:34.941369 => dhcp
733 09:18:34.942011 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 09:18:34.945156 dhcp
735 09:18:35.801271 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 09:18:35.801644 Speed: 1000, full duplex
737 09:18:35.801862 BOOTP broadcast 1
738 09:18:35.814389 DHCP client bound to address 192.168.6.21 (12 ms)
740 09:18:35.915715 => setenv serverip 192.168.6.2
741 09:18:35.916480 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 09:18:35.921006 setenv serverip 192.168.6.2
744 09:18:36.022430 => tftpboot 0x01080000 880152/tftp-deploy-ejhvbgbx/kernel/uImage
745 09:18:36.023090 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 09:18:36.029813 tftpboot 0x01080000 880152/tftp-deploy-ejhvbgbx/kernel/uImage
747 09:18:36.030294 Speed: 1000, full duplex
748 09:18:36.030713 Using ethernet@ff3f0000 device
749 09:18:36.035370 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 09:18:36.040889 Filename '880152/tftp-deploy-ejhvbgbx/kernel/uImage'.
751 09:18:36.045055 Load address: 0x1080000
752 09:18:38.850678 Loading: *################################################## 43.8 MiB
753 09:18:38.851357 15.6 MiB/s
754 09:18:38.851856 done
755 09:18:38.855276 Bytes transferred = 45910592 (2bc8a40 hex)
757 09:18:38.956855 => tftpboot 0x08000000 880152/tftp-deploy-ejhvbgbx/ramdisk/ramdisk.cpio.gz.uboot
758 09:18:38.957739 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
759 09:18:38.964582 tftpboot 0x08000000 880152/tftp-deploy-ejhvbgbx/ramdisk/ramdisk.cpio.gz.uboot
760 09:18:38.965090 Speed: 1000, full duplex
761 09:18:38.965489 Using ethernet@ff3f0000 device
762 09:18:38.969995 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 09:18:38.979892 Filename '880152/tftp-deploy-ejhvbgbx/ramdisk/ramdisk.cpio.gz.uboot'.
764 09:18:38.980620 Load address: 0x8000000
765 09:18:40.707692 Loading: *################################################# UDP wrong checksum 00000005 0000b8d5
766 09:18:45.707916 T UDP wrong checksum 00000005 0000b8d5
767 09:18:53.442719 T UDP wrong checksum 000000ff 00008b5c
768 09:18:53.479166 UDP wrong checksum 000000ff 0000104f
769 09:18:54.430406 UDP wrong checksum 000000ff 000024b5
770 09:18:54.444213 UDP wrong checksum 000000ff 0000bba7
771 09:18:55.710953 T UDP wrong checksum 00000005 0000b8d5
772 09:18:58.633987 UDP wrong checksum 000000ff 0000ed13
773 09:18:58.644575 UDP wrong checksum 000000ff 00008106
774 09:19:15.715022 T T T T UDP wrong checksum 00000005 0000b8d5
775 09:19:25.908685 T T UDP wrong checksum 000000ff 0000b2c4
776 09:19:25.918660 UDP wrong checksum 000000ff 000048b7
777 09:19:35.719899 T
778 09:19:35.720616 Retry count exceeded; starting again
780 09:19:35.722134 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
783 09:19:35.724182 end: 2.4 uboot-commands (duration 00:01:20) [common]
785 09:19:35.725694 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
787 09:19:35.726825 end: 2 uboot-action (duration 00:01:20) [common]
789 09:19:35.728565 Cleaning after the job
790 09:19:35.729193 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/ramdisk
791 09:19:35.730802 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/kernel
792 09:19:35.763402 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/dtb
793 09:19:35.764920 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880152/tftp-deploy-ejhvbgbx/modules
794 09:19:35.786813 start: 4.1 power-off (timeout 00:00:30) [common]
795 09:19:35.787962 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
796 09:19:35.824356 >> OK - accepted request
797 09:19:35.826608 Returned 0 in 0 seconds
798 09:19:35.927828 end: 4.1 power-off (duration 00:00:00) [common]
800 09:19:35.929704 start: 4.2 read-feedback (timeout 00:10:00) [common]
801 09:19:35.930920 Listened to connection for namespace 'common' for up to 1s
802 09:19:36.931332 Finalising connection for namespace 'common'
803 09:19:36.931857 Disconnecting from shell: Finalise
804 09:19:36.932227 =>
805 09:19:37.033026 end: 4.2 read-feedback (duration 00:00:01) [common]
806 09:19:37.033794 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/880152
807 09:19:37.339107 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/880152
808 09:19:37.339727 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.