Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:29:39.789763 lava-dispatcher, installed at version: 2024.01
2 10:29:39.790555 start: 0 validate
3 10:29:39.791026 Start time: 2024-10-22 10:29:39.790998+00:00 (UTC)
4 10:29:39.791565 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:29:39.792132 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 10:29:39.839771 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:29:39.840318 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 10:29:39.871070 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:29:39.871659 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 10:29:39.906291 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:29:39.906773 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:29:39.942894 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 10:29:39.943378 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241022%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 10:29:39.988752 validate duration: 0.20
16 10:29:39.990263 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:29:39.990881 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:29:39.991475 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:29:39.992444 Not decompressing ramdisk as can be used compressed.
20 10:29:39.993349 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 10:29:39.993689 saving as /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/ramdisk/initrd.cpio.gz
22 10:29:39.993973 total size: 5628169 (5 MB)
23 10:29:40.038953 progress 0 % (0 MB)
24 10:29:40.049130 progress 5 % (0 MB)
25 10:29:40.059148 progress 10 % (0 MB)
26 10:29:40.068408 progress 15 % (0 MB)
27 10:29:40.073835 progress 20 % (1 MB)
28 10:29:40.078512 progress 25 % (1 MB)
29 10:29:40.083882 progress 30 % (1 MB)
30 10:29:40.089200 progress 35 % (1 MB)
31 10:29:40.093896 progress 40 % (2 MB)
32 10:29:40.099133 progress 45 % (2 MB)
33 10:29:40.103912 progress 50 % (2 MB)
34 10:29:40.109516 progress 55 % (2 MB)
35 10:29:40.114788 progress 60 % (3 MB)
36 10:29:40.119532 progress 65 % (3 MB)
37 10:29:40.124961 progress 70 % (3 MB)
38 10:29:40.129821 progress 75 % (4 MB)
39 10:29:40.135136 progress 80 % (4 MB)
40 10:29:40.139855 progress 85 % (4 MB)
41 10:29:40.145074 progress 90 % (4 MB)
42 10:29:40.149835 progress 95 % (5 MB)
43 10:29:40.154241 progress 100 % (5 MB)
44 10:29:40.155116 5 MB downloaded in 0.16 s (33.32 MB/s)
45 10:29:40.155921 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:29:40.157298 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:29:40.157833 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:29:40.158265 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:29:40.158972 downloading http://storage.kernelci.org/next/master/next-20241022/arm64/defconfig/gcc-12/kernel/Image
51 10:29:40.159351 saving as /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/kernel/Image
52 10:29:40.159657 total size: 45910528 (43 MB)
53 10:29:40.160016 No compression specified
54 10:29:40.198194 progress 0 % (0 MB)
55 10:29:40.227066 progress 5 % (2 MB)
56 10:29:40.255916 progress 10 % (4 MB)
57 10:29:40.285080 progress 15 % (6 MB)
58 10:29:40.314549 progress 20 % (8 MB)
59 10:29:40.343719 progress 25 % (10 MB)
60 10:29:40.372744 progress 30 % (13 MB)
61 10:29:40.401163 progress 35 % (15 MB)
62 10:29:40.429987 progress 40 % (17 MB)
63 10:29:40.458333 progress 45 % (19 MB)
64 10:29:40.486659 progress 50 % (21 MB)
65 10:29:40.522296 progress 55 % (24 MB)
66 10:29:40.559832 progress 60 % (26 MB)
67 10:29:40.598446 progress 65 % (28 MB)
68 10:29:40.627004 progress 70 % (30 MB)
69 10:29:40.655933 progress 75 % (32 MB)
70 10:29:40.684641 progress 80 % (35 MB)
71 10:29:40.713485 progress 85 % (37 MB)
72 10:29:40.742459 progress 90 % (39 MB)
73 10:29:40.771491 progress 95 % (41 MB)
74 10:29:40.799549 progress 100 % (43 MB)
75 10:29:40.800110 43 MB downloaded in 0.64 s (68.36 MB/s)
76 10:29:40.800595 end: 1.2.1 http-download (duration 00:00:01) [common]
78 10:29:40.801422 end: 1.2 download-retry (duration 00:00:01) [common]
79 10:29:40.801698 start: 1.3 download-retry (timeout 00:09:59) [common]
80 10:29:40.801964 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 10:29:40.802437 downloading http://storage.kernelci.org/next/master/next-20241022/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 10:29:40.802689 saving as /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/dtb/meson-g12b-a311d-libretech-cc.dtb
83 10:29:40.802896 total size: 54703 (0 MB)
84 10:29:40.803106 No compression specified
85 10:29:40.842190 progress 59 % (0 MB)
86 10:29:40.843032 progress 100 % (0 MB)
87 10:29:40.843578 0 MB downloaded in 0.04 s (1.28 MB/s)
88 10:29:40.844082 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:29:40.844920 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:29:40.845183 start: 1.4 download-retry (timeout 00:09:59) [common]
92 10:29:40.845445 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 10:29:40.845905 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 10:29:40.846174 saving as /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/nfsrootfs/full.rootfs.tar
95 10:29:40.846382 total size: 120894716 (115 MB)
96 10:29:40.846594 Using unxz to decompress xz
97 10:29:40.886885 progress 0 % (0 MB)
98 10:29:41.676284 progress 5 % (5 MB)
99 10:29:42.518800 progress 10 % (11 MB)
100 10:29:43.326783 progress 15 % (17 MB)
101 10:29:44.074500 progress 20 % (23 MB)
102 10:29:44.667137 progress 25 % (28 MB)
103 10:29:45.495480 progress 30 % (34 MB)
104 10:29:46.291736 progress 35 % (40 MB)
105 10:29:46.661185 progress 40 % (46 MB)
106 10:29:47.037711 progress 45 % (51 MB)
107 10:29:47.759046 progress 50 % (57 MB)
108 10:29:48.658978 progress 55 % (63 MB)
109 10:29:49.445512 progress 60 % (69 MB)
110 10:29:50.218942 progress 65 % (74 MB)
111 10:29:51.019172 progress 70 % (80 MB)
112 10:29:51.851532 progress 75 % (86 MB)
113 10:29:52.634840 progress 80 % (92 MB)
114 10:29:53.388321 progress 85 % (98 MB)
115 10:29:54.234423 progress 90 % (103 MB)
116 10:29:55.002754 progress 95 % (109 MB)
117 10:29:55.831353 progress 100 % (115 MB)
118 10:29:55.843702 115 MB downloaded in 15.00 s (7.69 MB/s)
119 10:29:55.844597 end: 1.4.1 http-download (duration 00:00:15) [common]
121 10:29:55.846177 end: 1.4 download-retry (duration 00:00:15) [common]
122 10:29:55.846692 start: 1.5 download-retry (timeout 00:09:44) [common]
123 10:29:55.847196 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 10:29:55.848015 downloading http://storage.kernelci.org/next/master/next-20241022/arm64/defconfig/gcc-12/modules.tar.xz
125 10:29:55.848471 saving as /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/modules/modules.tar
126 10:29:55.848875 total size: 11636672 (11 MB)
127 10:29:55.849288 Using unxz to decompress xz
128 10:29:55.892786 progress 0 % (0 MB)
129 10:29:55.959578 progress 5 % (0 MB)
130 10:29:56.033118 progress 10 % (1 MB)
131 10:29:56.113323 progress 15 % (1 MB)
132 10:29:56.191861 progress 20 % (2 MB)
133 10:29:56.262928 progress 25 % (2 MB)
134 10:29:56.340931 progress 30 % (3 MB)
135 10:29:56.417482 progress 35 % (3 MB)
136 10:29:56.496543 progress 40 % (4 MB)
137 10:29:56.576868 progress 45 % (5 MB)
138 10:29:56.656340 progress 50 % (5 MB)
139 10:29:56.739666 progress 55 % (6 MB)
140 10:29:56.820085 progress 60 % (6 MB)
141 10:29:56.899623 progress 65 % (7 MB)
142 10:29:56.979485 progress 70 % (7 MB)
143 10:29:57.061269 progress 75 % (8 MB)
144 10:29:57.143733 progress 80 % (8 MB)
145 10:29:57.221160 progress 85 % (9 MB)
146 10:29:57.293426 progress 90 % (10 MB)
147 10:29:57.390404 progress 95 % (10 MB)
148 10:29:57.487494 progress 100 % (11 MB)
149 10:29:57.498233 11 MB downloaded in 1.65 s (6.73 MB/s)
150 10:29:57.498833 end: 1.5.1 http-download (duration 00:00:02) [common]
152 10:29:57.499670 end: 1.5 download-retry (duration 00:00:02) [common]
153 10:29:57.499943 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 10:29:57.500490 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 10:30:13.828026 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/880178/extract-nfsrootfs-sef0_wx5
156 10:30:13.828616 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 10:30:13.828904 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 10:30:13.829523 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86
159 10:30:13.829958 makedir: /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin
160 10:30:13.830286 makedir: /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/tests
161 10:30:13.830597 makedir: /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/results
162 10:30:13.830934 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-add-keys
163 10:30:13.831466 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-add-sources
164 10:30:13.832008 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-background-process-start
165 10:30:13.832562 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-background-process-stop
166 10:30:13.833160 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-common-functions
167 10:30:13.833698 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-echo-ipv4
168 10:30:13.834212 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-install-packages
169 10:30:13.834788 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-installed-packages
170 10:30:13.835280 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-os-build
171 10:30:13.835761 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-probe-channel
172 10:30:13.836297 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-probe-ip
173 10:30:13.836821 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-target-ip
174 10:30:13.837327 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-target-mac
175 10:30:13.837809 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-target-storage
176 10:30:13.838301 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-test-case
177 10:30:13.838780 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-test-event
178 10:30:13.839252 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-test-feedback
179 10:30:13.839731 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-test-raise
180 10:30:13.840234 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-test-reference
181 10:30:13.840754 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-test-runner
182 10:30:13.841261 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-test-set
183 10:30:13.841742 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-test-shell
184 10:30:13.842239 Updating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-add-keys (debian)
185 10:30:13.842778 Updating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-add-sources (debian)
186 10:30:13.843294 Updating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-install-packages (debian)
187 10:30:13.843798 Updating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-installed-packages (debian)
188 10:30:13.844352 Updating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/bin/lava-os-build (debian)
189 10:30:13.844796 Creating /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/environment
190 10:30:13.845173 LAVA metadata
191 10:30:13.845435 - LAVA_JOB_ID=880178
192 10:30:13.845650 - LAVA_DISPATCHER_IP=192.168.6.2
193 10:30:13.846015 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 10:30:13.846989 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 10:30:13.847308 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 10:30:13.847515 skipped lava-vland-overlay
197 10:30:13.847759 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 10:30:13.848056 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 10:30:13.848284 skipped lava-multinode-overlay
200 10:30:13.848527 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 10:30:13.848778 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 10:30:13.849029 Loading test definitions
203 10:30:13.849304 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 10:30:13.849524 Using /lava-880178 at stage 0
205 10:30:13.850653 uuid=880178_1.6.2.4.1 testdef=None
206 10:30:13.850968 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 10:30:13.851235 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 10:30:13.852822 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 10:30:13.853620 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 10:30:13.855558 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 10:30:13.856410 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 10:30:13.858244 runner path: /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/0/tests/0_timesync-off test_uuid 880178_1.6.2.4.1
215 10:30:13.858802 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 10:30:13.859623 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 10:30:13.859847 Using /lava-880178 at stage 0
219 10:30:13.860258 Fetching tests from https://github.com/kernelci/test-definitions.git
220 10:30:13.860552 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/0/tests/1_kselftest-alsa'
221 10:30:17.321203 Running '/usr/bin/git checkout kernelci.org
222 10:30:17.610742 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 10:30:17.612454 uuid=880178_1.6.2.4.5 testdef=None
224 10:30:17.613064 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 10:30:17.614512 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 10:30:17.619843 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 10:30:17.621445 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 10:30:17.628511 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 10:30:17.630150 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 10:30:17.637046 runner path: /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/0/tests/1_kselftest-alsa test_uuid 880178_1.6.2.4.5
234 10:30:17.637563 BOARD='meson-g12b-a311d-libretech-cc'
235 10:30:17.637964 BRANCH='next'
236 10:30:17.638351 SKIPFILE='/dev/null'
237 10:30:17.638742 SKIP_INSTALL='True'
238 10:30:17.639127 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241022/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 10:30:17.639520 TST_CASENAME=''
240 10:30:17.639908 TST_CMDFILES='alsa'
241 10:30:17.640788 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 10:30:17.641586 Creating lava-test-runner.conf files
244 10:30:17.641791 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/880178/lava-overlay-ja5yxd86/lava-880178/0 for stage 0
245 10:30:17.642144 - 0_timesync-off
246 10:30:17.642382 - 1_kselftest-alsa
247 10:30:17.642708 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 10:30:17.642987 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 10:30:41.018865 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 10:30:41.019296 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 10:30:41.019587 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 10:30:41.019893 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 10:30:41.020223 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 10:30:41.635387 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 10:30:41.635856 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 10:30:41.636160 extracting modules file /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/880178/extract-nfsrootfs-sef0_wx5
257 10:30:43.017790 extracting modules file /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/880178/extract-overlay-ramdisk-0xxz0a2k/ramdisk
258 10:30:44.460224 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 10:30:44.460721 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 10:30:44.461019 [common] Applying overlay to NFS
261 10:30:44.461238 [common] Applying overlay /var/lib/lava/dispatcher/tmp/880178/compress-overlay-3vxe_cxn/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/880178/extract-nfsrootfs-sef0_wx5
262 10:30:47.355513 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 10:30:47.356016 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 10:30:47.356301 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 10:30:47.356534 Converting downloaded kernel to a uImage
266 10:30:47.356844 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/kernel/Image /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/kernel/uImage
267 10:30:47.963530 output: Image Name:
268 10:30:47.963954 output: Created: Tue Oct 22 10:30:47 2024
269 10:30:47.964204 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 10:30:47.964413 output: Data Size: 45910528 Bytes = 44834.50 KiB = 43.78 MiB
271 10:30:47.964616 output: Load Address: 01080000
272 10:30:47.964817 output: Entry Point: 01080000
273 10:30:47.965017 output:
274 10:30:47.965356 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 10:30:47.965630 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 10:30:47.965901 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 10:30:47.966271 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 10:30:47.966607 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 10:30:47.966878 Building ramdisk /var/lib/lava/dispatcher/tmp/880178/extract-overlay-ramdisk-0xxz0a2k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/880178/extract-overlay-ramdisk-0xxz0a2k/ramdisk
280 10:30:50.245706 >> 167580 blocks
281 10:30:57.980062 Adding RAMdisk u-boot header.
282 10:30:57.980519 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/880178/extract-overlay-ramdisk-0xxz0a2k/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/880178/extract-overlay-ramdisk-0xxz0a2k/ramdisk.cpio.gz.uboot
283 10:30:58.221811 output: Image Name:
284 10:30:58.222231 output: Created: Tue Oct 22 10:30:57 2024
285 10:30:58.222443 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 10:30:58.222649 output: Data Size: 23490829 Bytes = 22940.26 KiB = 22.40 MiB
287 10:30:58.222853 output: Load Address: 00000000
288 10:30:58.223052 output: Entry Point: 00000000
289 10:30:58.223253 output:
290 10:30:58.223870 rename /var/lib/lava/dispatcher/tmp/880178/extract-overlay-ramdisk-0xxz0a2k/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/ramdisk/ramdisk.cpio.gz.uboot
291 10:30:58.224630 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 10:30:58.225257 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 10:30:58.225889 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 10:30:58.226388 No LXC device requested
295 10:30:58.226937 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 10:30:58.227499 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 10:30:58.228090 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 10:30:58.228615 Checking files for TFTP limit of 4294967296 bytes.
299 10:30:58.231638 end: 1 tftp-deploy (duration 00:01:18) [common]
300 10:30:58.232321 start: 2 uboot-action (timeout 00:05:00) [common]
301 10:30:58.232902 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 10:30:58.233451 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 10:30:58.234011 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 10:30:58.234595 Using kernel file from prepare-kernel: 880178/tftp-deploy-mwyevngn/kernel/uImage
305 10:30:58.235292 substitutions:
306 10:30:58.235740 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 10:30:58.236236 - {DTB_ADDR}: 0x01070000
308 10:30:58.236685 - {DTB}: 880178/tftp-deploy-mwyevngn/dtb/meson-g12b-a311d-libretech-cc.dtb
309 10:30:58.237136 - {INITRD}: 880178/tftp-deploy-mwyevngn/ramdisk/ramdisk.cpio.gz.uboot
310 10:30:58.237577 - {KERNEL_ADDR}: 0x01080000
311 10:30:58.238019 - {KERNEL}: 880178/tftp-deploy-mwyevngn/kernel/uImage
312 10:30:58.238459 - {LAVA_MAC}: None
313 10:30:58.238935 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/880178/extract-nfsrootfs-sef0_wx5
314 10:30:58.239376 - {NFS_SERVER_IP}: 192.168.6.2
315 10:30:58.239810 - {PRESEED_CONFIG}: None
316 10:30:58.240277 - {PRESEED_LOCAL}: None
317 10:30:58.240719 - {RAMDISK_ADDR}: 0x08000000
318 10:30:58.241153 - {RAMDISK}: 880178/tftp-deploy-mwyevngn/ramdisk/ramdisk.cpio.gz.uboot
319 10:30:58.241586 - {ROOT_PART}: None
320 10:30:58.242012 - {ROOT}: None
321 10:30:58.242438 - {SERVER_IP}: 192.168.6.2
322 10:30:58.242864 - {TEE_ADDR}: 0x83000000
323 10:30:58.243292 - {TEE}: None
324 10:30:58.243722 Parsed boot commands:
325 10:30:58.244172 - setenv autoload no
326 10:30:58.244606 - setenv initrd_high 0xffffffff
327 10:30:58.245035 - setenv fdt_high 0xffffffff
328 10:30:58.245465 - dhcp
329 10:30:58.245888 - setenv serverip 192.168.6.2
330 10:30:58.246317 - tftpboot 0x01080000 880178/tftp-deploy-mwyevngn/kernel/uImage
331 10:30:58.246749 - tftpboot 0x08000000 880178/tftp-deploy-mwyevngn/ramdisk/ramdisk.cpio.gz.uboot
332 10:30:58.247177 - tftpboot 0x01070000 880178/tftp-deploy-mwyevngn/dtb/meson-g12b-a311d-libretech-cc.dtb
333 10:30:58.247605 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/880178/extract-nfsrootfs-sef0_wx5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 10:30:58.248072 - bootm 0x01080000 0x08000000 0x01070000
335 10:30:58.248647 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 10:30:58.250293 start: 2.3 connect-device (timeout 00:05:00) [common]
338 10:30:58.250758 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 10:30:58.266701 Setting prompt string to ['lava-test: # ']
340 10:30:58.268375 end: 2.3 connect-device (duration 00:00:00) [common]
341 10:30:58.269055 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 10:30:58.269682 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 10:30:58.270282 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 10:30:58.271536 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 10:30:58.324697 >> OK - accepted request
346 10:30:58.326969 Returned 0 in 0 seconds
347 10:30:58.427881 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 10:30:58.429716 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 10:30:58.430319 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 10:30:58.430879 Setting prompt string to ['Hit any key to stop autoboot']
352 10:30:58.431378 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 10:30:58.433130 Trying 192.168.56.21...
354 10:30:58.433653 Connected to conserv1.
355 10:30:58.434114 Escape character is '^]'.
356 10:30:58.434569
357 10:30:58.435025 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 10:30:58.435491
359 10:31:10.428016 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 10:31:10.428442 bl2_stage_init 0x01
361 10:31:10.428661 bl2_stage_init 0x81
362 10:31:10.433363 hw id: 0x0000 - pwm id 0x01
363 10:31:10.433654 bl2_stage_init 0xc1
364 10:31:10.433872 bl2_stage_init 0x02
365 10:31:10.434081
366 10:31:10.438999 L0:00000000
367 10:31:10.439273 L1:20000703
368 10:31:10.439485 L2:00008067
369 10:31:10.439690 L3:14000000
370 10:31:10.441891 B2:00402000
371 10:31:10.442133 B1:e0f83180
372 10:31:10.442343
373 10:31:10.442543 TE: 58167
374 10:31:10.442743
375 10:31:10.452956 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 10:31:10.453226
377 10:31:10.453430 Board ID = 1
378 10:31:10.453627 Set A53 clk to 24M
379 10:31:10.453824 Set A73 clk to 24M
380 10:31:10.458631 Set clk81 to 24M
381 10:31:10.458870 A53 clk: 1200 MHz
382 10:31:10.459070 A73 clk: 1200 MHz
383 10:31:10.462117 CLK81: 166.6M
384 10:31:10.462351 smccc: 00012abd
385 10:31:10.467660 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 10:31:10.473257 board id: 1
387 10:31:10.478476 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 10:31:10.489099 fw parse done
389 10:31:10.495101 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 10:31:10.537579 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 10:31:10.548502 PIEI prepare done
392 10:31:10.548825 fastboot data load
393 10:31:10.549056 fastboot data verify
394 10:31:10.554114 verify result: 266
395 10:31:10.559726 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 10:31:10.560149 LPDDR4 probe
397 10:31:10.560386 ddr clk to 1584MHz
398 10:31:10.567669 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 10:31:10.604989
400 10:31:10.605356 dmc_version 0001
401 10:31:10.611583 Check phy result
402 10:31:10.617464 INFO : End of CA training
403 10:31:10.617754 INFO : End of initialization
404 10:31:10.623050 INFO : Training has run successfully!
405 10:31:10.623335 Check phy result
406 10:31:10.628659 INFO : End of initialization
407 10:31:10.628948 INFO : End of read enable training
408 10:31:10.634251 INFO : End of fine write leveling
409 10:31:10.639918 INFO : End of Write leveling coarse delay
410 10:31:10.640212 INFO : Training has run successfully!
411 10:31:10.640429 Check phy result
412 10:31:10.645468 INFO : End of initialization
413 10:31:10.645738 INFO : End of read dq deskew training
414 10:31:10.651043 INFO : End of MPR read delay center optimization
415 10:31:10.656623 INFO : End of write delay center optimization
416 10:31:10.662211 INFO : End of read delay center optimization
417 10:31:10.662463 INFO : End of max read latency training
418 10:31:10.667819 INFO : Training has run successfully!
419 10:31:10.668103 1D training succeed
420 10:31:10.677095 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 10:31:10.724747 Check phy result
422 10:31:10.725278 INFO : End of initialization
423 10:31:10.746452 INFO : End of 2D read delay Voltage center optimization
424 10:31:10.766667 INFO : End of 2D read delay Voltage center optimization
425 10:31:10.820480 INFO : End of 2D write delay Voltage center optimization
426 10:31:10.868117 INFO : End of 2D write delay Voltage center optimization
427 10:31:10.873594 INFO : Training has run successfully!
428 10:31:10.873849
429 10:31:10.874059 channel==0
430 10:31:10.879407 RxClkDly_Margin_A0==88 ps 9
431 10:31:10.879953 TxDqDly_Margin_A0==98 ps 10
432 10:31:10.884921 RxClkDly_Margin_A1==88 ps 9
433 10:31:10.885410 TxDqDly_Margin_A1==98 ps 10
434 10:31:10.885820 TrainedVREFDQ_A0==74
435 10:31:10.890438 TrainedVREFDQ_A1==74
436 10:31:10.890942 VrefDac_Margin_A0==25
437 10:31:10.891355 DeviceVref_Margin_A0==40
438 10:31:10.896077 VrefDac_Margin_A1==25
439 10:31:10.896571 DeviceVref_Margin_A1==40
440 10:31:10.896974
441 10:31:10.897376
442 10:31:10.901665 channel==1
443 10:31:10.902153 RxClkDly_Margin_A0==98 ps 10
444 10:31:10.902558 TxDqDly_Margin_A0==88 ps 9
445 10:31:10.907257 RxClkDly_Margin_A1==88 ps 9
446 10:31:10.907747 TxDqDly_Margin_A1==88 ps 9
447 10:31:10.912925 TrainedVREFDQ_A0==77
448 10:31:10.913436 TrainedVREFDQ_A1==77
449 10:31:10.913842 VrefDac_Margin_A0==22
450 10:31:10.918452 DeviceVref_Margin_A0==37
451 10:31:10.918952 VrefDac_Margin_A1==24
452 10:31:10.924106 DeviceVref_Margin_A1==37
453 10:31:10.924627
454 10:31:10.925035 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 10:31:10.925432
456 10:31:10.957632 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 10:31:10.958264 2D training succeed
458 10:31:10.963260 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 10:31:10.968877 auto size-- 65535DDR cs0 size: 2048MB
460 10:31:10.969408 DDR cs1 size: 2048MB
461 10:31:10.974401 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 10:31:10.974914 cs0 DataBus test pass
463 10:31:10.980057 cs1 DataBus test pass
464 10:31:10.980564 cs0 AddrBus test pass
465 10:31:10.980969 cs1 AddrBus test pass
466 10:31:10.981364
467 10:31:10.985625 100bdlr_step_size ps== 420
468 10:31:10.986134 result report
469 10:31:10.991219 boot times 0Enable ddr reg access
470 10:31:10.996479 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 10:31:11.010065 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 10:31:11.583647 0.0;M3 CHK:0;cm4_sp_mode 0
473 10:31:11.584111 MVN_1=0x00000000
474 10:31:11.589143 MVN_2=0x00000000
475 10:31:11.594906 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 10:31:11.595243 OPS=0x10
477 10:31:11.595475 ring efuse init
478 10:31:11.595688 chipver efuse init
479 10:31:11.600495 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 10:31:11.606107 [0.018961 Inits done]
481 10:31:11.606446 secure task start!
482 10:31:11.606686 high task start!
483 10:31:11.610707 low task start!
484 10:31:11.611058 run into bl31
485 10:31:11.617361 NOTICE: BL31: v1.3(release):4fc40b1
486 10:31:11.625190 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 10:31:11.625544 NOTICE: BL31: G12A normal boot!
488 10:31:11.650511 NOTICE: BL31: BL33 decompress pass
489 10:31:11.656170 ERROR: Error initializing runtime service opteed_fast
490 10:31:12.889143
491 10:31:12.889793
492 10:31:12.897519 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 10:31:12.898060
494 10:31:12.898514 Model: Libre Computer AML-A311D-CC Alta
495 10:31:13.105877 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 10:31:13.129366 DRAM: 2 GiB (effective 3.8 GiB)
497 10:31:13.272351 Core: 408 devices, 31 uclasses, devicetree: separate
498 10:31:13.278186 WDT: Not starting watchdog@f0d0
499 10:31:13.310458 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 10:31:13.322856 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 10:31:13.327821 ** Bad device specification mmc 0 **
502 10:31:13.338304 Card did not respond to voltage select! : -110
503 10:31:13.345828 ** Bad device specification mmc 0 **
504 10:31:13.346338 Couldn't find partition mmc 0
505 10:31:13.354168 Card did not respond to voltage select! : -110
506 10:31:13.359700 ** Bad device specification mmc 0 **
507 10:31:13.360250 Couldn't find partition mmc 0
508 10:31:13.364729 Error: could not access storage.
509 10:31:14.628302 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 10:31:14.628920 bl2_stage_init 0x01
511 10:31:14.629368 bl2_stage_init 0x81
512 10:31:14.633868 hw id: 0x0000 - pwm id 0x01
513 10:31:14.634381 bl2_stage_init 0xc1
514 10:31:14.634812 bl2_stage_init 0x02
515 10:31:14.635226
516 10:31:14.639461 L0:00000000
517 10:31:14.639953 L1:20000703
518 10:31:14.640417 L2:00008067
519 10:31:14.640869 L3:14000000
520 10:31:14.642350 B2:00402000
521 10:31:14.642828 B1:e0f83180
522 10:31:14.643249
523 10:31:14.643659 TE: 58159
524 10:31:14.644104
525 10:31:14.653508 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 10:31:14.654029
527 10:31:14.654452 Board ID = 1
528 10:31:14.654910 Set A53 clk to 24M
529 10:31:14.655334 Set A73 clk to 24M
530 10:31:14.659126 Set clk81 to 24M
531 10:31:14.659630 A53 clk: 1200 MHz
532 10:31:14.660106 A73 clk: 1200 MHz
533 10:31:14.664804 CLK81: 166.6M
534 10:31:14.665323 smccc: 00012ab5
535 10:31:14.670354 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 10:31:14.670857 board id: 1
537 10:31:14.678936 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 10:31:14.689613 fw parse done
539 10:31:14.695556 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 10:31:14.738190 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 10:31:14.749085 PIEI prepare done
542 10:31:14.749596 fastboot data load
543 10:31:14.750019 fastboot data verify
544 10:31:14.754783 verify result: 266
545 10:31:14.760362 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 10:31:14.760877 LPDDR4 probe
547 10:31:14.761291 ddr clk to 1584MHz
548 10:31:14.768322 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 10:31:14.805676
550 10:31:14.806241 dmc_version 0001
551 10:31:14.812269 Check phy result
552 10:31:14.818106 INFO : End of CA training
553 10:31:14.818595 INFO : End of initialization
554 10:31:14.823732 INFO : Training has run successfully!
555 10:31:14.824278 Check phy result
556 10:31:14.829350 INFO : End of initialization
557 10:31:14.829842 INFO : End of read enable training
558 10:31:14.834929 INFO : End of fine write leveling
559 10:31:14.840568 INFO : End of Write leveling coarse delay
560 10:31:14.841076 INFO : Training has run successfully!
561 10:31:14.841502 Check phy result
562 10:31:14.846143 INFO : End of initialization
563 10:31:14.846643 INFO : End of read dq deskew training
564 10:31:14.851676 INFO : End of MPR read delay center optimization
565 10:31:14.857351 INFO : End of write delay center optimization
566 10:31:14.862951 INFO : End of read delay center optimization
567 10:31:14.863446 INFO : End of max read latency training
568 10:31:14.868573 INFO : Training has run successfully!
569 10:31:14.869076 1D training succeed
570 10:31:14.877701 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 10:31:14.925308 Check phy result
572 10:31:14.925907 INFO : End of initialization
573 10:31:14.946943 INFO : End of 2D read delay Voltage center optimization
574 10:31:14.967053 INFO : End of 2D read delay Voltage center optimization
575 10:31:15.019003 INFO : End of 2D write delay Voltage center optimization
576 10:31:15.068312 INFO : End of 2D write delay Voltage center optimization
577 10:31:15.073759 INFO : Training has run successfully!
578 10:31:15.074268
579 10:31:15.074701 channel==0
580 10:31:15.079377 RxClkDly_Margin_A0==88 ps 9
581 10:31:15.079883 TxDqDly_Margin_A0==98 ps 10
582 10:31:15.084937 RxClkDly_Margin_A1==88 ps 9
583 10:31:15.085468 TxDqDly_Margin_A1==98 ps 10
584 10:31:15.085912 TrainedVREFDQ_A0==74
585 10:31:15.090639 TrainedVREFDQ_A1==74
586 10:31:15.091141 VrefDac_Margin_A0==25
587 10:31:15.091558 DeviceVref_Margin_A0==40
588 10:31:15.096229 VrefDac_Margin_A1==25
589 10:31:15.096728 DeviceVref_Margin_A1==40
590 10:31:15.097143
591 10:31:15.097555
592 10:31:15.101789 channel==1
593 10:31:15.102278 RxClkDly_Margin_A0==98 ps 10
594 10:31:15.102708 TxDqDly_Margin_A0==88 ps 9
595 10:31:15.107393 RxClkDly_Margin_A1==88 ps 9
596 10:31:15.107888 TxDqDly_Margin_A1==88 ps 9
597 10:31:15.112978 TrainedVREFDQ_A0==77
598 10:31:15.113478 TrainedVREFDQ_A1==77
599 10:31:15.113931 VrefDac_Margin_A0==22
600 10:31:15.118641 DeviceVref_Margin_A0==37
601 10:31:15.119144 VrefDac_Margin_A1==24
602 10:31:15.124235 DeviceVref_Margin_A1==37
603 10:31:15.124729
604 10:31:15.125148 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 10:31:15.125563
606 10:31:15.157737 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 10:31:15.158305 2D training succeed
608 10:31:15.163399 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 10:31:15.168961 auto size-- 65535DDR cs0 size: 2048MB
610 10:31:15.169494 DDR cs1 size: 2048MB
611 10:31:15.174662 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 10:31:15.175165 cs0 DataBus test pass
613 10:31:15.180238 cs1 DataBus test pass
614 10:31:15.180733 cs0 AddrBus test pass
615 10:31:15.181167 cs1 AddrBus test pass
616 10:31:15.181583
617 10:31:15.185765 100bdlr_step_size ps== 420
618 10:31:15.186277 result report
619 10:31:15.191376 boot times 0Enable ddr reg access
620 10:31:15.196717 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 10:31:15.210073 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 10:31:15.782128 0.0;M3 CHK:0;cm4_sp_mode 0
623 10:31:15.782547 MVN_1=0x00000000
624 10:31:15.787800 MVN_2=0x00000000
625 10:31:15.793312 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 10:31:15.793770 OPS=0x10
627 10:31:15.794010 ring efuse init
628 10:31:15.794276 chipver efuse init
629 10:31:15.798873 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 10:31:15.804615 [0.018961 Inits done]
631 10:31:15.804912 secure task start!
632 10:31:15.805125 high task start!
633 10:31:15.809109 low task start!
634 10:31:15.809388 run into bl31
635 10:31:15.815802 NOTICE: BL31: v1.3(release):4fc40b1
636 10:31:15.823711 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 10:31:15.824080 NOTICE: BL31: G12A normal boot!
638 10:31:15.849432 NOTICE: BL31: BL33 decompress pass
639 10:31:15.855095 ERROR: Error initializing runtime service opteed_fast
640 10:31:17.088115
641 10:31:17.088731
642 10:31:17.097474 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 10:31:17.097999
644 10:31:17.098429 Model: Libre Computer AML-A311D-CC Alta
645 10:31:17.304938 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 10:31:17.328229 DRAM: 2 GiB (effective 3.8 GiB)
647 10:31:17.471262 Core: 408 devices, 31 uclasses, devicetree: separate
648 10:31:17.477096 WDT: Not starting watchdog@f0d0
649 10:31:17.509267 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 10:31:17.521721 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 10:31:17.526833 ** Bad device specification mmc 0 **
652 10:31:17.537114 Card did not respond to voltage select! : -110
653 10:31:17.544864 ** Bad device specification mmc 0 **
654 10:31:17.545163 Couldn't find partition mmc 0
655 10:31:17.553093 Card did not respond to voltage select! : -110
656 10:31:17.558611 ** Bad device specification mmc 0 **
657 10:31:17.558930 Couldn't find partition mmc 0
658 10:31:17.563750 Error: could not access storage.
659 10:31:17.907415 Net: eth0: ethernet@ff3f0000
660 10:31:17.907834 starting USB...
661 10:31:18.159113 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 10:31:18.159531 Starting the controller
663 10:31:18.166034 USB XHCI 1.10
664 10:31:19.878524 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 10:31:19.878959 bl2_stage_init 0x01
666 10:31:19.879211 bl2_stage_init 0x81
667 10:31:19.883975 hw id: 0x0000 - pwm id 0x01
668 10:31:19.884359 bl2_stage_init 0xc1
669 10:31:19.884604 bl2_stage_init 0x02
670 10:31:19.884827
671 10:31:19.889584 L0:00000000
672 10:31:19.889934 L1:20000703
673 10:31:19.890170 L2:00008067
674 10:31:19.890413 L3:14000000
675 10:31:19.895362 B2:00402000
676 10:31:19.895846 B1:e0f83180
677 10:31:19.896246
678 10:31:19.896517 TE: 58124
679 10:31:19.897070
680 10:31:19.900818 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 10:31:19.901161
682 10:31:19.901399 Board ID = 1
683 10:31:19.906572 Set A53 clk to 24M
684 10:31:19.907067 Set A73 clk to 24M
685 10:31:19.907414 Set clk81 to 24M
686 10:31:19.912071 A53 clk: 1200 MHz
687 10:31:19.912399 A73 clk: 1200 MHz
688 10:31:19.912615 CLK81: 166.6M
689 10:31:19.912840 smccc: 00012a92
690 10:31:19.917593 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 10:31:19.923349 board id: 1
692 10:31:19.929353 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 10:31:19.939683 fw parse done
694 10:31:19.946695 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 10:31:19.988242 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 10:31:19.999239 PIEI prepare done
697 10:31:19.999736 fastboot data load
698 10:31:20.000010 fastboot data verify
699 10:31:20.004725 verify result: 266
700 10:31:20.010376 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 10:31:20.010699 LPDDR4 probe
702 10:31:20.010915 ddr clk to 1584MHz
703 10:31:20.018406 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 10:31:20.055642
705 10:31:20.056070 dmc_version 0001
706 10:31:20.062308 Check phy result
707 10:31:20.068224 INFO : End of CA training
708 10:31:20.068677 INFO : End of initialization
709 10:31:20.073735 INFO : Training has run successfully!
710 10:31:20.074070 Check phy result
711 10:31:20.079348 INFO : End of initialization
712 10:31:20.079791 INFO : End of read enable training
713 10:31:20.084928 INFO : End of fine write leveling
714 10:31:20.090532 INFO : End of Write leveling coarse delay
715 10:31:20.090862 INFO : Training has run successfully!
716 10:31:20.091072 Check phy result
717 10:31:20.096222 INFO : End of initialization
718 10:31:20.096652 INFO : End of read dq deskew training
719 10:31:20.101691 INFO : End of MPR read delay center optimization
720 10:31:20.107315 INFO : End of write delay center optimization
721 10:31:20.112935 INFO : End of read delay center optimization
722 10:31:20.113246 INFO : End of max read latency training
723 10:31:20.118578 INFO : Training has run successfully!
724 10:31:20.119011 1D training succeed
725 10:31:20.127794 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 10:31:20.175415 Check phy result
727 10:31:20.175830 INFO : End of initialization
728 10:31:20.197855 INFO : End of 2D read delay Voltage center optimization
729 10:31:20.218113 INFO : End of 2D read delay Voltage center optimization
730 10:31:20.270146 INFO : End of 2D write delay Voltage center optimization
731 10:31:20.319488 INFO : End of 2D write delay Voltage center optimization
732 10:31:20.325036 INFO : Training has run successfully!
733 10:31:20.325362
734 10:31:20.325573 channel==0
735 10:31:20.330641 RxClkDly_Margin_A0==88 ps 9
736 10:31:20.330963 TxDqDly_Margin_A0==98 ps 10
737 10:31:20.336248 RxClkDly_Margin_A1==88 ps 9
738 10:31:20.336556 TxDqDly_Margin_A1==98 ps 10
739 10:31:20.336776 TrainedVREFDQ_A0==74
740 10:31:20.341794 TrainedVREFDQ_A1==75
741 10:31:20.342108 VrefDac_Margin_A0==24
742 10:31:20.342319 DeviceVref_Margin_A0==40
743 10:31:20.347394 VrefDac_Margin_A1==24
744 10:31:20.347690 DeviceVref_Margin_A1==39
745 10:31:20.347910
746 10:31:20.348149
747 10:31:20.353015 channel==1
748 10:31:20.353324 RxClkDly_Margin_A0==98 ps 10
749 10:31:20.353531 TxDqDly_Margin_A0==88 ps 9
750 10:31:20.358617 RxClkDly_Margin_A1==98 ps 10
751 10:31:20.358922 TxDqDly_Margin_A1==98 ps 10
752 10:31:20.364273 TrainedVREFDQ_A0==76
753 10:31:20.364592 TrainedVREFDQ_A1==78
754 10:31:20.364805 VrefDac_Margin_A0==22
755 10:31:20.369814 DeviceVref_Margin_A0==38
756 10:31:20.370125 VrefDac_Margin_A1==24
757 10:31:20.375424 DeviceVref_Margin_A1==36
758 10:31:20.375874
759 10:31:20.376239 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 10:31:20.381004
761 10:31:20.409008 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000018 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 10:31:20.409391 2D training succeed
763 10:31:20.414616 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 10:31:20.420245 auto size-- 65535DDR cs0 size: 2048MB
765 10:31:20.420546 DDR cs1 size: 2048MB
766 10:31:20.425806 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 10:31:20.426095 cs0 DataBus test pass
768 10:31:20.431389 cs1 DataBus test pass
769 10:31:20.431680 cs0 AddrBus test pass
770 10:31:20.431889 cs1 AddrBus test pass
771 10:31:20.432121
772 10:31:20.437001 100bdlr_step_size ps== 420
773 10:31:20.437304 result report
774 10:31:20.442623 boot times 0Enable ddr reg access
775 10:31:20.448053 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 10:31:20.461526 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 10:31:21.035264 0.0;M3 CHK:0;cm4_sp_mode 0
778 10:31:21.035687 MVN_1=0x00000000
779 10:31:21.040732 MVN_2=0x00000000
780 10:31:21.046452 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 10:31:21.046750 OPS=0x10
782 10:31:21.046959 ring efuse init
783 10:31:21.047158 chipver efuse init
784 10:31:21.052046 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 10:31:21.057596 [0.018961 Inits done]
786 10:31:21.057858 secure task start!
787 10:31:21.058060 high task start!
788 10:31:21.062284 low task start!
789 10:31:21.062537 run into bl31
790 10:31:21.068972 NOTICE: BL31: v1.3(release):4fc40b1
791 10:31:21.374874 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 10:31:21.375309 NOTICE: BL31: G12A normal boot!
793 10:31:21.375544 NOTICE: BL31: BL33 decompress pass
794 10:31:21.377947 ERROR: Error initializing runtime service opteed_fast
795 10:31:22.340801
796 10:31:22.341422
797 10:31:22.349235 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 10:31:22.349764
799 10:31:22.350187 Model: Libre Computer AML-A311D-CC Alta
800 10:31:22.557686 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 10:31:22.581000 DRAM: 2 GiB (effective 3.8 GiB)
802 10:31:22.724073 Core: 408 devices, 31 uclasses, devicetree: separate
803 10:31:22.729922 WDT: Not starting watchdog@f0d0
804 10:31:22.762181 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 10:31:22.774570 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 10:31:22.779632 ** Bad device specification mmc 0 **
807 10:31:22.789971 Card did not respond to voltage select! : -110
808 10:31:22.797653 ** Bad device specification mmc 0 **
809 10:31:22.798154 Couldn't find partition mmc 0
810 10:31:22.805946 Card did not respond to voltage select! : -110
811 10:31:22.811440 ** Bad device specification mmc 0 **
812 10:31:22.811935 Couldn't find partition mmc 0
813 10:31:22.816521 Error: could not access storage.
814 10:31:23.158958 Net: eth0: ethernet@ff3f0000
815 10:31:23.159564 starting USB...
816 10:31:23.410818 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 10:31:23.411384 Starting the controller
818 10:31:23.417750 USB XHCI 1.10
819 10:31:25.578822 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 10:31:25.579253 bl2_stage_init 0x01
821 10:31:25.579487 bl2_stage_init 0x81
822 10:31:25.584232 hw id: 0x0000 - pwm id 0x01
823 10:31:25.584557 bl2_stage_init 0xc1
824 10:31:25.584787 bl2_stage_init 0x02
825 10:31:25.585010
826 10:31:25.589825 L0:00000000
827 10:31:25.590135 L1:20000703
828 10:31:25.590363 L2:00008067
829 10:31:25.590583 L3:14000000
830 10:31:25.592825 B2:00402000
831 10:31:25.593402 B1:e0f83180
832 10:31:25.593881
833 10:31:25.594345 TE: 58124
834 10:31:25.594805
835 10:31:25.603805 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 10:31:25.604356
837 10:31:25.604829 Board ID = 1
838 10:31:25.605290 Set A53 clk to 24M
839 10:31:25.605740 Set A73 clk to 24M
840 10:31:25.609467 Set clk81 to 24M
841 10:31:25.609963 A53 clk: 1200 MHz
842 10:31:25.610418 A73 clk: 1200 MHz
843 10:31:25.613008 CLK81: 166.6M
844 10:31:25.613506 smccc: 00012a91
845 10:31:25.618736 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 10:31:25.624161 board id: 1
847 10:31:25.629260 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 10:31:25.640075 fw parse done
849 10:31:25.645966 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 10:31:25.688398 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 10:31:25.699300 PIEI prepare done
852 10:31:25.699840 fastboot data load
853 10:31:25.700357 fastboot data verify
854 10:31:25.704916 verify result: 266
855 10:31:25.710480 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 10:31:25.710996 LPDDR4 probe
857 10:31:25.711465 ddr clk to 1584MHz
858 10:31:25.718467 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 10:31:25.755916
860 10:31:25.756490 dmc_version 0001
861 10:31:25.762615 Check phy result
862 10:31:25.768271 INFO : End of CA training
863 10:31:25.768780 INFO : End of initialization
864 10:31:25.773879 INFO : Training has run successfully!
865 10:31:25.774397 Check phy result
866 10:31:25.779446 INFO : End of initialization
867 10:31:25.779952 INFO : End of read enable training
868 10:31:25.785046 INFO : End of fine write leveling
869 10:31:25.790645 INFO : End of Write leveling coarse delay
870 10:31:25.791156 INFO : Training has run successfully!
871 10:31:25.791625 Check phy result
872 10:31:25.796234 INFO : End of initialization
873 10:31:25.796745 INFO : End of read dq deskew training
874 10:31:25.801872 INFO : End of MPR read delay center optimization
875 10:31:25.807449 INFO : End of write delay center optimization
876 10:31:25.813074 INFO : End of read delay center optimization
877 10:31:25.813582 INFO : End of max read latency training
878 10:31:25.818651 INFO : Training has run successfully!
879 10:31:25.819159 1D training succeed
880 10:31:25.827845 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 10:31:25.875494 Check phy result
882 10:31:25.876092 INFO : End of initialization
883 10:31:25.897227 INFO : End of 2D read delay Voltage center optimization
884 10:31:25.917462 INFO : End of 2D read delay Voltage center optimization
885 10:31:25.969490 INFO : End of 2D write delay Voltage center optimization
886 10:31:26.018884 INFO : End of 2D write delay Voltage center optimization
887 10:31:26.024419 INFO : Training has run successfully!
888 10:31:26.024936
889 10:31:26.025405 channel==0
890 10:31:26.029964 RxClkDly_Margin_A0==88 ps 9
891 10:31:26.030471 TxDqDly_Margin_A0==98 ps 10
892 10:31:26.035559 RxClkDly_Margin_A1==88 ps 9
893 10:31:26.036111 TxDqDly_Margin_A1==98 ps 10
894 10:31:26.036619 TrainedVREFDQ_A0==74
895 10:31:26.041215 TrainedVREFDQ_A1==74
896 10:31:26.041798 VrefDac_Margin_A0==25
897 10:31:26.042270 DeviceVref_Margin_A0==40
898 10:31:26.046811 VrefDac_Margin_A1==25
899 10:31:26.047385 DeviceVref_Margin_A1==40
900 10:31:26.047822
901 10:31:26.048303
902 10:31:26.052363 channel==1
903 10:31:26.052861 RxClkDly_Margin_A0==98 ps 10
904 10:31:26.053295 TxDqDly_Margin_A0==88 ps 9
905 10:31:26.057922 RxClkDly_Margin_A1==88 ps 9
906 10:31:26.058410 TxDqDly_Margin_A1==88 ps 9
907 10:31:26.063541 TrainedVREFDQ_A0==75
908 10:31:26.064080 TrainedVREFDQ_A1==77
909 10:31:26.064531 VrefDac_Margin_A0==22
910 10:31:26.069198 DeviceVref_Margin_A0==38
911 10:31:26.069678 VrefDac_Margin_A1==24
912 10:31:26.074804 DeviceVref_Margin_A1==37
913 10:31:26.075287
914 10:31:26.075725 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 10:31:26.076196
916 10:31:26.108384 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
917 10:31:26.108913 2D training succeed
918 10:31:26.113968 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 10:31:26.119554 auto size-- 65535DDR cs0 size: 2048MB
920 10:31:26.120073 DDR cs1 size: 2048MB
921 10:31:26.125184 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 10:31:26.125664 cs0 DataBus test pass
923 10:31:26.130783 cs1 DataBus test pass
924 10:31:26.131262 cs0 AddrBus test pass
925 10:31:26.131695 cs1 AddrBus test pass
926 10:31:26.132174
927 10:31:26.136388 100bdlr_step_size ps== 420
928 10:31:26.136884 result report
929 10:31:26.141979 boot times 0Enable ddr reg access
930 10:31:26.147247 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 10:31:26.160728 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 10:31:26.734430 0.0;M3 CHK:0;cm4_sp_mode 0
933 10:31:26.734849 MVN_1=0x00000000
934 10:31:26.740076 MVN_2=0x00000000
935 10:31:26.745674 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 10:31:26.746119 OPS=0x10
937 10:31:26.746384 ring efuse init
938 10:31:26.746604 chipver efuse init
939 10:31:26.753901 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 10:31:26.754379 [0.018961 Inits done]
941 10:31:26.760549 secure task start!
942 10:31:26.760996 high task start!
943 10:31:26.761357 low task start!
944 10:31:26.761614 run into bl31
945 10:31:26.768173 NOTICE: BL31: v1.3(release):4fc40b1
946 10:31:26.774981 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 10:31:26.775307 NOTICE: BL31: G12A normal boot!
948 10:31:26.801843 NOTICE: BL31: BL33 decompress pass
949 10:31:26.807532 ERROR: Error initializing runtime service opteed_fast
950 10:31:28.040454
951 10:31:28.040900
952 10:31:28.048813 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 10:31:28.049143
954 10:31:28.049383 Model: Libre Computer AML-A311D-CC Alta
955 10:31:28.257258 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 10:31:28.280651 DRAM: 2 GiB (effective 3.8 GiB)
957 10:31:28.423654 Core: 408 devices, 31 uclasses, devicetree: separate
958 10:31:28.429499 WDT: Not starting watchdog@f0d0
959 10:31:28.461748 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 10:31:28.474222 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 10:31:28.479168 ** Bad device specification mmc 0 **
962 10:31:28.489519 Card did not respond to voltage select! : -110
963 10:31:28.497179 ** Bad device specification mmc 0 **
964 10:31:28.497491 Couldn't find partition mmc 0
965 10:31:28.505504 Card did not respond to voltage select! : -110
966 10:31:28.511009 ** Bad device specification mmc 0 **
967 10:31:28.511441 Couldn't find partition mmc 0
968 10:31:28.516085 Error: could not access storage.
969 10:31:28.858601 Net: eth0: ethernet@ff3f0000
970 10:31:28.859270 starting USB...
971 10:31:29.110477 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 10:31:29.111040 Starting the controller
973 10:31:29.117338 USB XHCI 1.10
974 10:31:30.918340 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 10:31:30.918833 bl2_stage_init 0x01
976 10:31:30.919080 bl2_stage_init 0x81
977 10:31:30.923844 hw id: 0x0000 - pwm id 0x01
978 10:31:30.924291 bl2_stage_init 0xc1
979 10:31:30.924623 bl2_stage_init 0x02
980 10:31:30.924930
981 10:31:30.929417 L0:00000000
982 10:31:30.929707 L1:20000703
983 10:31:30.929922 L2:00008067
984 10:31:30.930126 L3:14000000
985 10:31:30.932320 B2:00402000
986 10:31:30.932612 B1:e0f83180
987 10:31:30.932826
988 10:31:30.933036 TE: 58124
989 10:31:30.933255
990 10:31:30.943513 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 10:31:30.943969
992 10:31:30.944341 Board ID = 1
993 10:31:30.944581 Set A53 clk to 24M
994 10:31:30.944788 Set A73 clk to 24M
995 10:31:30.949111 Set clk81 to 24M
996 10:31:30.949526 A53 clk: 1200 MHz
997 10:31:30.949853 A73 clk: 1200 MHz
998 10:31:30.952452 CLK81: 166.6M
999 10:31:30.952853 smccc: 00012a92
1000 10:31:30.958043 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 10:31:30.963641 board id: 1
1002 10:31:30.968938 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 10:31:30.979608 fw parse done
1004 10:31:30.985548 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 10:31:31.028131 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 10:31:31.039038 PIEI prepare done
1007 10:31:31.039338 fastboot data load
1008 10:31:31.039558 fastboot data verify
1009 10:31:31.044587 verify result: 266
1010 10:31:31.050187 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 10:31:31.050507 LPDDR4 probe
1012 10:31:31.050732 ddr clk to 1584MHz
1013 10:31:31.057594 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 10:31:31.094603
1015 10:31:31.095244 dmc_version 0001
1016 10:31:31.101216 Check phy result
1017 10:31:31.107965 INFO : End of CA training
1018 10:31:31.108501 INFO : End of initialization
1019 10:31:31.113573 INFO : Training has run successfully!
1020 10:31:31.114073 Check phy result
1021 10:31:31.119178 INFO : End of initialization
1022 10:31:31.119662 INFO : End of read enable training
1023 10:31:31.122456 INFO : End of fine write leveling
1024 10:31:31.128020 INFO : End of Write leveling coarse delay
1025 10:31:31.133620 INFO : Training has run successfully!
1026 10:31:31.134106 Check phy result
1027 10:31:31.134545 INFO : End of initialization
1028 10:31:31.139347 INFO : End of read dq deskew training
1029 10:31:31.144799 INFO : End of MPR read delay center optimization
1030 10:31:31.145279 INFO : End of write delay center optimization
1031 10:31:31.150384 INFO : End of read delay center optimization
1032 10:31:31.156362 INFO : End of max read latency training
1033 10:31:31.157013 INFO : Training has run successfully!
1034 10:31:31.161761 1D training succeed
1035 10:31:31.166793 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 10:31:31.215234 Check phy result
1037 10:31:31.215756 INFO : End of initialization
1038 10:31:31.236973 INFO : End of 2D read delay Voltage center optimization
1039 10:31:31.257231 INFO : End of 2D read delay Voltage center optimization
1040 10:31:31.309260 INFO : End of 2D write delay Voltage center optimization
1041 10:31:31.358644 INFO : End of 2D write delay Voltage center optimization
1042 10:31:31.364181 INFO : Training has run successfully!
1043 10:31:31.364687
1044 10:31:31.365150 channel==0
1045 10:31:31.369729 RxClkDly_Margin_A0==88 ps 9
1046 10:31:31.370222 TxDqDly_Margin_A0==98 ps 10
1047 10:31:31.375336 RxClkDly_Margin_A1==88 ps 9
1048 10:31:31.375832 TxDqDly_Margin_A1==88 ps 9
1049 10:31:31.376344 TrainedVREFDQ_A0==74
1050 10:31:31.380923 TrainedVREFDQ_A1==74
1051 10:31:31.381424 VrefDac_Margin_A0==25
1052 10:31:31.381874 DeviceVref_Margin_A0==40
1053 10:31:31.386623 VrefDac_Margin_A1==25
1054 10:31:31.387125 DeviceVref_Margin_A1==40
1055 10:31:31.387583
1056 10:31:31.388072
1057 10:31:31.388536 channel==1
1058 10:31:31.392137 RxClkDly_Margin_A0==98 ps 10
1059 10:31:31.392658 TxDqDly_Margin_A0==98 ps 10
1060 10:31:31.397712 RxClkDly_Margin_A1==88 ps 9
1061 10:31:31.398209 TxDqDly_Margin_A1==88 ps 9
1062 10:31:31.403314 TrainedVREFDQ_A0==77
1063 10:31:31.403803 TrainedVREFDQ_A1==77
1064 10:31:31.404307 VrefDac_Margin_A0==22
1065 10:31:31.408910 DeviceVref_Margin_A0==37
1066 10:31:31.409397 VrefDac_Margin_A1==24
1067 10:31:31.414582 DeviceVref_Margin_A1==37
1068 10:31:31.415064
1069 10:31:31.415520 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 10:31:31.415968
1071 10:31:31.448340 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 10:31:31.448876 2D training succeed
1073 10:31:31.453818 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 10:31:31.459390 auto size-- 65535DDR cs0 size: 2048MB
1075 10:31:31.459961 DDR cs1 size: 2048MB
1076 10:31:31.464959 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 10:31:31.465465 cs0 DataBus test pass
1078 10:31:31.470584 cs1 DataBus test pass
1079 10:31:31.471102 cs0 AddrBus test pass
1080 10:31:31.471555 cs1 AddrBus test pass
1081 10:31:31.472036
1082 10:31:31.476184 100bdlr_step_size ps== 420
1083 10:31:31.476706 result report
1084 10:31:31.481784 boot times 0Enable ddr reg access
1085 10:31:31.487030 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 10:31:31.500529 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 10:31:32.074225 0.0;M3 CHK:0;cm4_sp_mode 0
1088 10:31:32.074914 MVN_1=0x00000000
1089 10:31:32.079655 MVN_2=0x00000000
1090 10:31:32.085338 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 10:31:32.085857 OPS=0x10
1092 10:31:32.086324 ring efuse init
1093 10:31:32.086785 chipver efuse init
1094 10:31:32.090954 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 10:31:32.096526 [0.018961 Inits done]
1096 10:31:32.097029 secure task start!
1097 10:31:32.097487 high task start!
1098 10:31:32.101125 low task start!
1099 10:31:32.101624 run into bl31
1100 10:31:32.107790 NOTICE: BL31: v1.3(release):4fc40b1
1101 10:31:32.115604 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 10:31:32.116146 NOTICE: BL31: G12A normal boot!
1103 10:31:32.140981 NOTICE: BL31: BL33 decompress pass
1104 10:31:32.146647 ERROR: Error initializing runtime service opteed_fast
1105 10:31:33.379626
1106 10:31:33.380313
1107 10:31:33.388043 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 10:31:33.388580
1109 10:31:33.389037 Model: Libre Computer AML-A311D-CC Alta
1110 10:31:33.596456 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 10:31:33.619818 DRAM: 2 GiB (effective 3.8 GiB)
1112 10:31:33.762806 Core: 408 devices, 31 uclasses, devicetree: separate
1113 10:31:33.767652 WDT: Not starting watchdog@f0d0
1114 10:31:33.801027 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 10:31:33.813327 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 10:31:33.817408 ** Bad device specification mmc 0 **
1117 10:31:33.828698 Card did not respond to voltage select! : -110
1118 10:31:33.835377 ** Bad device specification mmc 0 **
1119 10:31:33.835858 Couldn't find partition mmc 0
1120 10:31:33.844682 Card did not respond to voltage select! : -110
1121 10:31:33.850164 ** Bad device specification mmc 0 **
1122 10:31:33.850622 Couldn't find partition mmc 0
1123 10:31:33.854359 Error: could not access storage.
1124 10:31:34.197756 Net: eth0: ethernet@ff3f0000
1125 10:31:34.198346 starting USB...
1126 10:31:34.449592 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 10:31:34.450149 Starting the controller
1128 10:31:34.456470 USB XHCI 1.10
1129 10:31:36.010633 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 10:31:36.018947 scanning usb for storage devices... 0 Storage Device(s) found
1132 10:31:36.070520 Hit any key to stop autoboot: 1
1133 10:31:36.071602 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1134 10:31:36.072284 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1135 10:31:36.072769 Setting prompt string to ['=>']
1136 10:31:36.073238 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1137 10:31:36.086554 0
1138 10:31:36.087421 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 10:31:36.087903 Sending with 10 millisecond of delay
1141 10:31:37.223198 => setenv autoload no
1142 10:31:37.234207 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 10:31:37.238893 setenv autoload no
1144 10:31:37.239506 Sending with 10 millisecond of delay
1146 10:31:39.038367 => setenv initrd_high 0xffffffff
1147 10:31:39.049231 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1148 10:31:39.050220 setenv initrd_high 0xffffffff
1149 10:31:39.050990 Sending with 10 millisecond of delay
1151 10:31:40.670466 => setenv fdt_high 0xffffffff
1152 10:31:40.681198 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 10:31:40.681771 setenv fdt_high 0xffffffff
1154 10:31:40.682334 Sending with 10 millisecond of delay
1156 10:31:40.973832 => dhcp
1157 10:31:40.984428 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1158 10:31:40.985123 dhcp
1159 10:31:40.985451 Speed: 1000, full duplex
1160 10:31:40.985699 BOOTP broadcast 1
1161 10:31:40.993251 DHCP client bound to address 192.168.6.27 (9 ms)
1162 10:31:40.994007 Sending with 10 millisecond of delay
1164 10:31:42.670332 => setenv serverip 192.168.6.2
1165 10:31:42.680946 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 10:31:42.681583 setenv serverip 192.168.6.2
1167 10:31:42.682130 Sending with 10 millisecond of delay
1169 10:31:46.405523 => tftpboot 0x01080000 880178/tftp-deploy-mwyevngn/kernel/uImage
1170 10:31:46.416551 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 10:31:46.417533 tftpboot 0x01080000 880178/tftp-deploy-mwyevngn/kernel/uImage
1172 10:31:46.418052 Speed: 1000, full duplex
1173 10:31:46.418497 Using ethernet@ff3f0000 device
1174 10:31:46.419033 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 10:31:46.424652 Filename '880178/tftp-deploy-mwyevngn/kernel/uImage'.
1176 10:31:46.428431 Load address: 0x1080000
1177 10:31:49.544577 Loading: *################################################## 43.8 MiB
1178 10:31:49.545246 14 MiB/s
1179 10:31:49.545733 done
1180 10:31:49.548749 Bytes transferred = 45910592 (2bc8a40 hex)
1181 10:31:49.549601 Sending with 10 millisecond of delay
1183 10:31:54.236534 => tftpboot 0x08000000 880178/tftp-deploy-mwyevngn/ramdisk/ramdisk.cpio.gz.uboot
1184 10:31:54.247383 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 10:31:54.248350 tftpboot 0x08000000 880178/tftp-deploy-mwyevngn/ramdisk/ramdisk.cpio.gz.uboot
1186 10:31:54.248854 Speed: 1000, full duplex
1187 10:31:54.249318 Using ethernet@ff3f0000 device
1188 10:31:54.250104 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 10:31:54.258617 Filename '880178/tftp-deploy-mwyevngn/ramdisk/ramdisk.cpio.gz.uboot'.
1190 10:31:54.259124 Load address: 0x8000000
1191 10:32:00.757573 Loading: *##########T ####################################### UDP wrong checksum 00000005 0000e3be
1192 10:32:03.010642 UDP wrong checksum 000000ff 00003e26
1193 10:32:03.065227 UDP wrong checksum 000000ff 0000d918
1194 10:32:05.760149 T UDP wrong checksum 00000005 0000e3be
1195 10:32:15.762026 T T UDP wrong checksum 00000005 0000e3be
1196 10:32:26.844792 T T UDP wrong checksum 000000ff 00003928
1197 10:32:26.862725 UDP wrong checksum 000000ff 0000cf1a
1198 10:32:35.766430 T T UDP wrong checksum 00000005 0000e3be
1199 10:32:50.769609 T T
1200 10:32:50.770229 Retry count exceeded; starting again
1202 10:32:50.771724 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1205 10:32:50.773688 end: 2.4 uboot-commands (duration 00:01:53) [common]
1207 10:32:50.775158 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1209 10:32:50.776246 end: 2 uboot-action (duration 00:01:53) [common]
1211 10:32:50.777780 Cleaning after the job
1212 10:32:50.778335 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/ramdisk
1213 10:32:50.779729 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/kernel
1214 10:32:50.805411 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/dtb
1215 10:32:50.806718 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/nfsrootfs
1216 10:32:50.841436 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/880178/tftp-deploy-mwyevngn/modules
1217 10:32:50.848610 start: 4.1 power-off (timeout 00:00:30) [common]
1218 10:32:50.849231 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1219 10:32:50.880622 >> OK - accepted request
1220 10:32:50.882605 Returned 0 in 0 seconds
1221 10:32:50.983421 end: 4.1 power-off (duration 00:00:00) [common]
1223 10:32:50.984553 start: 4.2 read-feedback (timeout 00:10:00) [common]
1224 10:32:50.985251 Listened to connection for namespace 'common' for up to 1s
1225 10:32:51.985504 Finalising connection for namespace 'common'
1226 10:32:51.986486 Disconnecting from shell: Finalise
1227 10:32:51.987222 =>
1228 10:32:52.088694 end: 4.2 read-feedback (duration 00:00:01) [common]
1229 10:32:52.089657 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/880178
1230 10:32:55.874530 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/880178
1231 10:32:55.875143 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.