Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 11:23:54.671526 lava-dispatcher, installed at version: 2024.01
2 11:23:54.672344 start: 0 validate
3 11:23:54.672838 Start time: 2024-10-30 11:23:54.672806+00:00 (UTC)
4 11:23:54.673400 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 11:23:54.673958 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 11:23:54.714322 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 11:23:54.714884 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 11:23:54.749233 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 11:23:54.749871 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 11:23:54.786124 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 11:23:54.786832 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 11:23:54.822411 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 11:23:54.822933 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 11:23:54.868204 validate duration: 0.20
16 11:23:54.869908 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:23:54.870556 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:23:54.871173 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:23:54.872298 Not decompressing ramdisk as can be used compressed.
20 11:23:54.873200 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 11:23:54.873744 saving as /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/ramdisk/initrd.cpio.gz
22 11:23:54.874293 total size: 4775763 (4 MB)
23 11:23:54.920887 progress 0 % (0 MB)
24 11:23:54.929719 progress 5 % (0 MB)
25 11:23:54.938210 progress 10 % (0 MB)
26 11:23:54.946567 progress 15 % (0 MB)
27 11:23:54.955878 progress 20 % (0 MB)
28 11:23:54.960026 progress 25 % (1 MB)
29 11:23:54.964025 progress 30 % (1 MB)
30 11:23:54.968368 progress 35 % (1 MB)
31 11:23:54.972428 progress 40 % (1 MB)
32 11:23:54.976409 progress 45 % (2 MB)
33 11:23:54.980364 progress 50 % (2 MB)
34 11:23:54.984854 progress 55 % (2 MB)
35 11:23:54.988827 progress 60 % (2 MB)
36 11:23:54.992881 progress 65 % (2 MB)
37 11:23:54.997296 progress 70 % (3 MB)
38 11:23:55.001183 progress 75 % (3 MB)
39 11:23:55.005234 progress 80 % (3 MB)
40 11:23:55.009205 progress 85 % (3 MB)
41 11:23:55.013714 progress 90 % (4 MB)
42 11:23:55.018512 progress 95 % (4 MB)
43 11:23:55.021833 progress 100 % (4 MB)
44 11:23:55.022494 4 MB downloaded in 0.15 s (30.73 MB/s)
45 11:23:55.023037 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:23:55.023940 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:23:55.024269 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:23:55.024554 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:23:55.025149 downloading http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 11:23:55.025428 saving as /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/kernel/zImage
52 11:23:55.025648 total size: 11502080 (10 MB)
53 11:23:55.025872 No compression specified
54 11:23:55.065598 progress 0 % (0 MB)
55 11:23:55.074324 progress 5 % (0 MB)
56 11:23:55.083417 progress 10 % (1 MB)
57 11:23:55.092072 progress 15 % (1 MB)
58 11:23:55.101207 progress 20 % (2 MB)
59 11:23:55.109744 progress 25 % (2 MB)
60 11:23:55.118783 progress 30 % (3 MB)
61 11:23:55.127524 progress 35 % (3 MB)
62 11:23:55.136591 progress 40 % (4 MB)
63 11:23:55.145200 progress 45 % (4 MB)
64 11:23:55.154177 progress 50 % (5 MB)
65 11:23:55.163207 progress 55 % (6 MB)
66 11:23:55.171809 progress 60 % (6 MB)
67 11:23:55.180954 progress 65 % (7 MB)
68 11:23:55.189530 progress 70 % (7 MB)
69 11:23:55.198799 progress 75 % (8 MB)
70 11:23:55.207430 progress 80 % (8 MB)
71 11:23:55.216535 progress 85 % (9 MB)
72 11:23:55.225166 progress 90 % (9 MB)
73 11:23:55.234150 progress 95 % (10 MB)
74 11:23:55.242701 progress 100 % (10 MB)
75 11:23:55.243247 10 MB downloaded in 0.22 s (50.42 MB/s)
76 11:23:55.243835 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:23:55.244880 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:23:55.245232 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:23:55.245568 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:23:55.246139 downloading http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 11:23:55.246438 saving as /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/dtb/am335x-boneblack.dtb
83 11:23:55.246712 total size: 70544 (0 MB)
84 11:23:55.246995 No compression specified
85 11:23:55.281207 progress 46 % (0 MB)
86 11:23:55.282024 progress 92 % (0 MB)
87 11:23:55.282673 progress 100 % (0 MB)
88 11:23:55.283052 0 MB downloaded in 0.04 s (1.85 MB/s)
89 11:23:55.283505 end: 1.3.1 http-download (duration 00:00:00) [common]
91 11:23:55.284363 end: 1.3 download-retry (duration 00:00:00) [common]
92 11:23:55.284629 start: 1.4 download-retry (timeout 00:10:00) [common]
93 11:23:55.284893 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 11:23:55.285396 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 11:23:55.285645 saving as /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/nfsrootfs/full.rootfs.tar
96 11:23:55.285849 total size: 117747780 (112 MB)
97 11:23:55.286058 Using unxz to decompress xz
98 11:23:55.326575 progress 0 % (0 MB)
99 11:23:56.141234 progress 5 % (5 MB)
100 11:23:56.910242 progress 10 % (11 MB)
101 11:23:57.683957 progress 15 % (16 MB)
102 11:23:58.402931 progress 20 % (22 MB)
103 11:23:58.983050 progress 25 % (28 MB)
104 11:23:59.791023 progress 30 % (33 MB)
105 11:24:00.597558 progress 35 % (39 MB)
106 11:24:00.931974 progress 40 % (44 MB)
107 11:24:01.310611 progress 45 % (50 MB)
108 11:24:01.972849 progress 50 % (56 MB)
109 11:24:02.785201 progress 55 % (61 MB)
110 11:24:03.535143 progress 60 % (67 MB)
111 11:24:04.254097 progress 65 % (73 MB)
112 11:24:05.014687 progress 70 % (78 MB)
113 11:24:05.763921 progress 75 % (84 MB)
114 11:24:06.491538 progress 80 % (89 MB)
115 11:24:07.200116 progress 85 % (95 MB)
116 11:24:07.979495 progress 90 % (101 MB)
117 11:24:08.733878 progress 95 % (106 MB)
118 11:24:09.544426 progress 100 % (112 MB)
119 11:24:09.557631 112 MB downloaded in 14.27 s (7.87 MB/s)
120 11:24:09.558496 end: 1.4.1 http-download (duration 00:00:14) [common]
122 11:24:09.560173 end: 1.4 download-retry (duration 00:00:14) [common]
123 11:24:09.560702 start: 1.5 download-retry (timeout 00:09:45) [common]
124 11:24:09.561232 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 11:24:09.562066 downloading http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 11:24:09.562531 saving as /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/modules/modules.tar
127 11:24:09.562951 total size: 6616988 (6 MB)
128 11:24:09.563376 Using unxz to decompress xz
129 11:24:09.609889 progress 0 % (0 MB)
130 11:24:09.647473 progress 5 % (0 MB)
131 11:24:09.693559 progress 10 % (0 MB)
132 11:24:09.737382 progress 15 % (0 MB)
133 11:24:09.782132 progress 20 % (1 MB)
134 11:24:09.824863 progress 25 % (1 MB)
135 11:24:09.868411 progress 30 % (1 MB)
136 11:24:09.911501 progress 35 % (2 MB)
137 11:24:09.954910 progress 40 % (2 MB)
138 11:24:09.998284 progress 45 % (2 MB)
139 11:24:10.040889 progress 50 % (3 MB)
140 11:24:10.087604 progress 55 % (3 MB)
141 11:24:10.130687 progress 60 % (3 MB)
142 11:24:10.172515 progress 65 % (4 MB)
143 11:24:10.215476 progress 70 % (4 MB)
144 11:24:10.259831 progress 75 % (4 MB)
145 11:24:10.306186 progress 80 % (5 MB)
146 11:24:10.352078 progress 85 % (5 MB)
147 11:24:10.395915 progress 90 % (5 MB)
148 11:24:10.442150 progress 95 % (6 MB)
149 11:24:10.484852 progress 100 % (6 MB)
150 11:24:10.500021 6 MB downloaded in 0.94 s (6.73 MB/s)
151 11:24:10.500943 end: 1.5.1 http-download (duration 00:00:01) [common]
153 11:24:10.502531 end: 1.5 download-retry (duration 00:00:01) [common]
154 11:24:10.503042 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 11:24:10.503554 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 11:24:27.116671 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/913245/extract-nfsrootfs-gqz_loyv
157 11:24:27.117274 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 11:24:27.117568 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 11:24:27.118192 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l
160 11:24:27.118619 makedir: /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin
161 11:24:27.118939 makedir: /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/tests
162 11:24:27.119243 makedir: /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/results
163 11:24:27.119567 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-add-keys
164 11:24:27.120129 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-add-sources
165 11:24:27.120644 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-background-process-start
166 11:24:27.121206 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-background-process-stop
167 11:24:27.121833 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-common-functions
168 11:24:27.122341 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-echo-ipv4
169 11:24:27.122835 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-install-packages
170 11:24:27.123320 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-installed-packages
171 11:24:27.123807 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-os-build
172 11:24:27.124332 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-probe-channel
173 11:24:27.124820 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-probe-ip
174 11:24:27.125307 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-target-ip
175 11:24:27.125782 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-target-mac
176 11:24:27.126268 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-target-storage
177 11:24:27.126748 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-test-case
178 11:24:27.127299 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-test-event
179 11:24:27.127782 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-test-feedback
180 11:24:27.128288 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-test-raise
181 11:24:27.128764 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-test-reference
182 11:24:27.129269 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-test-runner
183 11:24:27.129785 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-test-set
184 11:24:27.130283 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-test-shell
185 11:24:27.130785 Updating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-add-keys (debian)
186 11:24:27.131322 Updating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-add-sources (debian)
187 11:24:27.131840 Updating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-install-packages (debian)
188 11:24:27.132388 Updating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-installed-packages (debian)
189 11:24:27.132897 Updating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/bin/lava-os-build (debian)
190 11:24:27.133331 Creating /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/environment
191 11:24:27.133696 LAVA metadata
192 11:24:27.133956 - LAVA_JOB_ID=913245
193 11:24:27.134170 - LAVA_DISPATCHER_IP=192.168.6.2
194 11:24:27.134523 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 11:24:27.135467 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 11:24:27.135776 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 11:24:27.136022 skipped lava-vland-overlay
198 11:24:27.136272 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 11:24:27.136534 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 11:24:27.136757 skipped lava-multinode-overlay
201 11:24:27.137000 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 11:24:27.137253 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 11:24:27.137502 Loading test definitions
204 11:24:27.137775 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 11:24:27.137997 Using /lava-913245 at stage 0
206 11:24:27.139079 uuid=913245_1.6.2.4.1 testdef=None
207 11:24:27.139384 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 11:24:27.139645 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 11:24:27.141219 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 11:24:27.142012 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 11:24:27.143923 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 11:24:27.144769 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 11:24:27.146591 runner path: /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/0/tests/0_timesync-off test_uuid 913245_1.6.2.4.1
216 11:24:27.147130 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 11:24:27.147933 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 11:24:27.148185 Using /lava-913245 at stage 0
220 11:24:27.148533 Fetching tests from https://github.com/kernelci/test-definitions.git
221 11:24:27.148818 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/0/tests/1_kselftest-dt'
222 11:24:30.598712 Running '/usr/bin/git checkout kernelci.org
223 11:24:31.043677 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 11:24:31.045108 uuid=913245_1.6.2.4.5 testdef=None
225 11:24:31.045450 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 11:24:31.046197 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 11:24:31.049035 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 11:24:31.049846 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 11:24:31.053497 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 11:24:31.054345 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 11:24:31.057875 runner path: /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/0/tests/1_kselftest-dt test_uuid 913245_1.6.2.4.5
235 11:24:31.058155 BOARD='beaglebone-black'
236 11:24:31.058375 BRANCH='next'
237 11:24:31.058606 SKIPFILE='/dev/null'
238 11:24:31.058810 SKIP_INSTALL='True'
239 11:24:31.059007 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 11:24:31.059207 TST_CASENAME=''
241 11:24:31.059404 TST_CMDFILES='dt'
242 11:24:31.059957 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 11:24:31.060767 Creating lava-test-runner.conf files
245 11:24:31.060971 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/913245/lava-overlay-zw0fta5l/lava-913245/0 for stage 0
246 11:24:31.061321 - 0_timesync-off
247 11:24:31.061558 - 1_kselftest-dt
248 11:24:31.061883 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 11:24:31.062158 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 11:24:54.342691 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 11:24:54.343130 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 11:24:54.343422 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 11:24:54.343725 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 11:24:54.344048 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 11:24:54.701235 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 11:24:54.701806 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 11:24:54.702097 extracting modules file /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/913245/extract-nfsrootfs-gqz_loyv
258 11:24:55.675150 extracting modules file /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/913245/extract-overlay-ramdisk-h9g88vt3/ramdisk
259 11:24:56.635701 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 11:24:56.636211 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 11:24:56.636510 [common] Applying overlay to NFS
262 11:24:56.636738 [common] Applying overlay /var/lib/lava/dispatcher/tmp/913245/compress-overlay-qtv_age0/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/913245/extract-nfsrootfs-gqz_loyv
263 11:24:59.493885 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 11:24:59.494353 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 11:24:59.494658 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 11:24:59.494968 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 11:24:59.495248 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 11:24:59.495524 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 11:24:59.495792 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 11:24:59.496121 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 11:24:59.496395 Building ramdisk /var/lib/lava/dispatcher/tmp/913245/extract-overlay-ramdisk-h9g88vt3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/913245/extract-overlay-ramdisk-h9g88vt3/ramdisk
272 11:25:00.496337 >> 75293 blocks
273 11:25:05.083262 Adding RAMdisk u-boot header.
274 11:25:05.084082 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/913245/extract-overlay-ramdisk-h9g88vt3/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/913245/extract-overlay-ramdisk-h9g88vt3/ramdisk.cpio.gz.uboot
275 11:25:05.264906 output: Image Name:
276 11:25:05.265311 output: Created: Wed Oct 30 11:25:05 2024
277 11:25:05.265523 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 11:25:05.265730 output: Data Size: 14829640 Bytes = 14482.07 KiB = 14.14 MiB
279 11:25:05.265935 output: Load Address: 00000000
280 11:25:05.266136 output: Entry Point: 00000000
281 11:25:05.266335 output:
282 11:25:05.267065 rename /var/lib/lava/dispatcher/tmp/913245/extract-overlay-ramdisk-h9g88vt3/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/ramdisk/ramdisk.cpio.gz.uboot
283 11:25:05.267504 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 11:25:05.267793 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 11:25:05.268327 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 11:25:05.268862 No LXC device requested
287 11:25:05.269429 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 11:25:05.269987 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 11:25:05.270532 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 11:25:05.270987 Checking files for TFTP limit of 4294967296 bytes.
291 11:25:05.273912 end: 1 tftp-deploy (duration 00:01:10) [common]
292 11:25:05.274546 start: 2 uboot-action (timeout 00:05:00) [common]
293 11:25:05.275118 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 11:25:05.275665 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 11:25:05.276243 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 11:25:05.277056 substitutions:
297 11:25:05.277514 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 11:25:05.277954 - {DTB_ADDR}: 0x88000000
299 11:25:05.278390 - {DTB}: 913245/tftp-deploy-yjcudzpf/dtb/am335x-boneblack.dtb
300 11:25:05.278823 - {INITRD}: 913245/tftp-deploy-yjcudzpf/ramdisk/ramdisk.cpio.gz.uboot
301 11:25:05.279258 - {KERNEL_ADDR}: 0x82000000
302 11:25:05.279687 - {KERNEL}: 913245/tftp-deploy-yjcudzpf/kernel/zImage
303 11:25:05.280152 - {LAVA_MAC}: None
304 11:25:05.280630 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/913245/extract-nfsrootfs-gqz_loyv
305 11:25:05.281070 - {NFS_SERVER_IP}: 192.168.6.2
306 11:25:05.281501 - {PRESEED_CONFIG}: None
307 11:25:05.281928 - {PRESEED_LOCAL}: None
308 11:25:05.282356 - {RAMDISK_ADDR}: 0x83000000
309 11:25:05.282783 - {RAMDISK}: 913245/tftp-deploy-yjcudzpf/ramdisk/ramdisk.cpio.gz.uboot
310 11:25:05.283214 - {ROOT_PART}: None
311 11:25:05.283638 - {ROOT}: None
312 11:25:05.284092 - {SERVER_IP}: 192.168.6.2
313 11:25:05.284518 - {TEE_ADDR}: 0x83000000
314 11:25:05.284942 - {TEE}: None
315 11:25:05.285368 Parsed boot commands:
316 11:25:05.285780 - setenv autoload no
317 11:25:05.286202 - setenv initrd_high 0xffffffff
318 11:25:05.286625 - setenv fdt_high 0xffffffff
319 11:25:05.287045 - dhcp
320 11:25:05.287465 - setenv serverip 192.168.6.2
321 11:25:05.287888 - tftp 0x82000000 913245/tftp-deploy-yjcudzpf/kernel/zImage
322 11:25:05.288341 - tftp 0x83000000 913245/tftp-deploy-yjcudzpf/ramdisk/ramdisk.cpio.gz.uboot
323 11:25:05.288765 - setenv initrd_size ${filesize}
324 11:25:05.289185 - tftp 0x88000000 913245/tftp-deploy-yjcudzpf/dtb/am335x-boneblack.dtb
325 11:25:05.289607 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/913245/extract-nfsrootfs-gqz_loyv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 11:25:05.290041 - bootz 0x82000000 0x83000000 0x88000000
327 11:25:05.290575 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 11:25:05.292213 start: 2.3 connect-device (timeout 00:05:00) [common]
330 11:25:05.292674 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 11:25:05.308277 Setting prompt string to ['lava-test: # ']
332 11:25:05.309884 end: 2.3 connect-device (duration 00:00:00) [common]
333 11:25:05.310530 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 11:25:05.311125 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 11:25:05.311899 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 11:25:05.313256 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 11:25:05.351508 >> OK - accepted request
338 11:25:05.353625 Returned 0 in 0 seconds
339 11:25:05.454789 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 11:25:05.456680 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 11:25:05.457303 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 11:25:05.457867 Setting prompt string to ['Hit any key to stop autoboot']
344 11:25:05.458375 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 11:25:05.460102 Trying 192.168.56.21...
346 11:25:05.460640 Connected to conserv1.
347 11:25:05.461101 Escape character is '^]'.
348 11:25:05.461559
349 11:25:05.462021 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 11:25:05.462482
351 11:25:13.734548
352 11:25:13.735196 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 11:25:13.739647 Trying to boot from MMC1
354 11:25:14.312164
355 11:25:14.312737
356 11:25:14.313188 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 11:25:14.313631
358 11:25:14.317754 CPU : AM335X-GP rev 2.1
359 11:25:14.318251 Model: TI AM335x BeagleBone Black
360 11:25:14.321755 DRAM: 512 MiB
361 11:25:14.404568 Core: 160 devices, 18 uclasses, devicetree: separate
362 11:25:14.414277 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 11:25:17.782226 7[r[999;999H[6n8NAND:
364 11:25:17.782895 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 11:25:17.787454 Trying to boot from MMC1
366 11:25:18.359554
367 11:25:18.360195
368 11:25:18.360652 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 11:25:18.361098
370 11:25:18.365006 CPU : AM335X-GP rev 2.1
371 11:25:18.365483 Model: TI AM335x BeagleBone Black
372 11:25:18.369094 DRAM: 512 MiB
373 11:25:18.451866 Core: 160 devices, 18 uclasses, devicetree: separate
374 11:25:18.461464 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 11:25:20.485237 7[r[999;999H[6n8NAND:
376 11:25:20.485911 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 11:25:20.490451 Trying to boot from MMC1
378 11:25:21.062722
379 11:25:21.063355
380 11:25:21.063790 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 11:25:21.064275
382 11:25:21.068104 CPU : AM335X-GP rev 2.1
383 11:25:21.068579 Model: TI AM335x BeagleBone Black
384 11:25:21.072226 DRAM: 512 MiB
385 11:25:21.154986 Core: 160 devices, 18 uclasses, devicetree: separate
386 11:25:21.164651 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 11:25:21.669801 7[r[999;999H[6n8NAND: 0 MiB
388 11:25:21.679930 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 11:25:21.752849 Loading Environment from FAT... Unable to use mmc 0:1...
390 11:25:21.774087 <ethaddr> not set. Validating first E-fuse MAC
391 11:25:21.804590 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 11:25:21.863106 Hit any key to stop autoboot: 2
394 11:25:21.864149 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 11:25:21.864785 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
396 11:25:21.865269 Setting prompt string to ['=>']
397 11:25:21.865755 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
398 11:25:21.873021 0
399 11:25:21.873892 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 11:25:21.874381 Sending with 10 millisecond of delay
402 11:25:23.009247 => setenv autoload no
403 11:25:23.020073 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
404 11:25:23.025014 setenv autoload no
405 11:25:23.025739 Sending with 10 millisecond of delay
407 11:25:24.822655 => setenv initrd_high 0xffffffff
408 11:25:24.833448 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
409 11:25:24.834301 setenv initrd_high 0xffffffff
410 11:25:24.835017 Sending with 10 millisecond of delay
412 11:25:26.451594 => setenv fdt_high 0xffffffff
413 11:25:26.462406 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 11:25:26.463061 setenv fdt_high 0xffffffff
415 11:25:26.463525 Sending with 10 millisecond of delay
417 11:25:26.754914 => dhcp
418 11:25:26.765702 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 11:25:26.766490 dhcp
420 11:25:26.768288 link up on port 0, speed 100, full duplex
421 11:25:26.768727 BOOTP broadcast 1
422 11:25:26.789065 DHCP client bound to address 192.168.6.12 (17 ms)
423 11:25:26.789754 Sending with 10 millisecond of delay
425 11:25:28.466137 => setenv serverip 192.168.6.2
426 11:25:28.476946 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 11:25:28.477888 setenv serverip 192.168.6.2
428 11:25:28.478594 Sending with 10 millisecond of delay
430 11:25:31.961597 => tftp 0x82000000 913245/tftp-deploy-yjcudzpf/kernel/zImage
431 11:25:31.972365 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
432 11:25:31.972930 tftp 0x82000000 913245/tftp-deploy-yjcudzpf/kernel/zImage
433 11:25:31.973188 link up on port 0, speed 100, full duplex
434 11:25:31.976911 Using ethernet@4a100000 device
435 11:25:31.982540 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 11:25:31.989857 Filename '913245/tftp-deploy-yjcudzpf/kernel/zImage'.
437 11:25:31.990196 Load address: 0x82000000
438 11:25:34.320102 Loading: *################################################## 11 MiB
439 11:25:34.320693 4.7 MiB/s
440 11:25:34.321117 done
441 11:25:34.324267 Bytes transferred = 11502080 (af8200 hex)
442 11:25:34.325060 Sending with 10 millisecond of delay
444 11:25:38.770887 => tftp 0x83000000 913245/tftp-deploy-yjcudzpf/ramdisk/ramdisk.cpio.gz.uboot
445 11:25:38.781881 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
446 11:25:38.782933 tftp 0x83000000 913245/tftp-deploy-yjcudzpf/ramdisk/ramdisk.cpio.gz.uboot
447 11:25:38.783522 link up on port 0, speed 100, full duplex
448 11:25:38.786773 Using ethernet@4a100000 device
449 11:25:38.792314 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 11:25:38.801041 Filename '913245/tftp-deploy-yjcudzpf/ramdisk/ramdisk.cpio.gz.uboot'.
451 11:25:38.801447 Load address: 0x83000000
452 11:25:41.733737 Loading: *################################################## 14.1 MiB
453 11:25:41.734426 4.8 MiB/s
454 11:25:41.734907 done
455 11:25:41.738062 Bytes transferred = 14829704 (e24888 hex)
456 11:25:41.738948 Sending with 10 millisecond of delay
458 11:25:43.596858 => setenv initrd_size ${filesize}
459 11:25:43.607700 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 11:25:43.608667 setenv initrd_size ${filesize}
461 11:25:43.609429 Sending with 10 millisecond of delay
463 11:25:47.756797 => tftp 0x88000000 913245/tftp-deploy-yjcudzpf/dtb/am335x-boneblack.dtb
464 11:25:47.767661 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 11:25:47.768638 tftp 0x88000000 913245/tftp-deploy-yjcudzpf/dtb/am335x-boneblack.dtb
466 11:25:47.769108 link up on port 0, speed 100, full duplex
467 11:25:47.772475 Using ethernet@4a100000 device
468 11:25:47.778009 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 11:25:47.791279 Filename '913245/tftp-deploy-yjcudzpf/dtb/am335x-boneblack.dtb'.
470 11:25:47.791857 Load address: 0x88000000
471 11:25:47.802948 Loading: *################################################## 68.9 KiB
472 11:25:47.803566 4.5 MiB/s
473 11:25:47.804217 done
474 11:25:47.809417 Bytes transferred = 70544 (11390 hex)
475 11:25:47.810323 Sending with 10 millisecond of delay
477 11:26:00.989448 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/913245/extract-nfsrootfs-gqz_loyv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 11:26:01.000316 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
479 11:26:01.001302 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/913245/extract-nfsrootfs-gqz_loyv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 11:26:01.002071 Sending with 10 millisecond of delay
482 11:26:03.341126 => bootz 0x82000000 0x83000000 0x88000000
483 11:26:03.352029 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 11:26:03.352668 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 11:26:03.353780 bootz 0x82000000 0x83000000 0x88000000
486 11:26:03.354269 Kernel image @ 0x82000000 [ 0x000000 - 0xaf8200 ]
487 11:26:03.354815 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 11:26:03.359741 Image Name:
489 11:26:03.360267 Created: 2024-10-30 11:25:05 UTC
490 11:26:03.365215 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 11:26:03.370769 Data Size: 14829640 Bytes = 14.1 MiB
492 11:26:03.371252 Load Address: 00000000
493 11:26:03.376949 Entry Point: 00000000
494 11:26:03.545800 Verifying Checksum ... OK
495 11:26:03.546330 ## Flattened Device Tree blob at 88000000
496 11:26:03.552342 Booting using the fdt blob at 0x88000000
497 11:26:03.557294 Using Device Tree in place at 88000000, end 8801438f
498 11:26:03.570849
499 11:26:03.571340 Starting kernel ...
500 11:26:03.571792
501 11:26:03.572768 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 11:26:03.573414 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 11:26:03.573920 Setting prompt string to ['Linux version [0-9]']
504 11:26:03.574422 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 11:26:03.574938 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 11:26:04.417598 [ 0.000000] Booting Linux on physical CPU 0x0
507 11:26:04.423674 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 11:26:04.424327 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 11:26:04.424841 Setting prompt string to []
510 11:26:04.425376 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 11:26:04.425883 Using line separator: #'\n'#
512 11:26:04.426331 No login prompt set.
513 11:26:04.426799 Parsing kernel messages
514 11:26:04.427233 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 11:26:04.428108 [login-action] Waiting for messages, (timeout 00:04:01)
516 11:26:04.428608 Waiting using forced prompt support (timeout 00:02:00)
517 11:26:04.440272 [ 0.000000] Linux version 6.12.0-rc5-next-20241030 (KernelCI@build-j357063-arm-gcc-12-multi-v7-defconfig-gp9k8) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Wed Oct 30 10:53:25 UTC 2024
518 11:26:04.445900 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 11:26:04.457504 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 11:26:04.463049 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 11:26:04.468705 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 11:26:04.474443 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 11:26:04.481144 [ 0.000000] Memory policy: Data cache writeback
524 11:26:04.481619 [ 0.000000] efi: UEFI not found.
525 11:26:04.489881 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 11:26:04.495620 [ 0.000000] Zone ranges:
527 11:26:04.501371 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 11:26:04.501869 [ 0.000000] Normal empty
529 11:26:04.507126 [ 0.000000] HighMem empty
530 11:26:04.507617 [ 0.000000] Movable zone start for each node
531 11:26:04.512835 [ 0.000000] Early memory node ranges
532 11:26:04.518565 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 11:26:04.527555 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 11:26:04.549128 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
535 11:26:04.561368 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 11:26:04.566979 [ 0.000000] AM335X ES2.1 (sgx neon)
537 11:26:04.578635 [ 0.000000] percpu: Embedded 17 pages/cpu s40396 r8192 d21044 u69632
538 11:26:04.596114 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/913245/extract-nfsrootfs-gqz_loyv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 11:26:04.607767 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
540 11:26:04.613588 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
541 11:26:04.625068 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
542 11:26:04.630768 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
543 11:26:04.637153 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
544 11:26:04.666262 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
545 11:26:04.672212 <6>[ 0.000000] trace event string verifier disabled
546 11:26:04.672684 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
547 11:26:04.677950 <6>[ 0.000000] rcu: RCU event tracing is enabled.
548 11:26:04.689397 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
549 11:26:04.689898 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
550 11:26:04.700855 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
551 11:26:04.706650 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
552 11:26:04.717391 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
553 11:26:04.732351 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
554 11:26:04.749736 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
555 11:26:04.756480 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
556 11:26:04.848085 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
557 11:26:04.859461 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
558 11:26:04.866188 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
559 11:26:04.879270 <6>[ 0.019143] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
560 11:26:04.886706 <6>[ 0.033954] Console: colour dummy device 80x30
561 11:26:04.892857 Matched prompt #6: WARNING:
562 11:26:04.893408 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
563 11:26:04.898181 <3>[ 0.038856] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
564 11:26:04.903892 <3>[ 0.045923] This ensures that you still see kernel messages. Please
565 11:26:04.907136 <3>[ 0.052654] update your kernel commandline.
566 11:26:04.947766 <6>[ 0.057271] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
567 11:26:04.953515 <6>[ 0.096148] CPU: Testing write buffer coherency: ok
568 11:26:04.959464 <6>[ 0.101515] CPU0: Spectre v2: using BPIALL workaround
569 11:26:04.959955 <6>[ 0.106980] pid_max: default: 32768 minimum: 301
570 11:26:04.970939 <6>[ 0.112185] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
571 11:26:04.977904 <6>[ 0.120009] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
572 11:26:04.985204 <6>[ 0.129383] CPU0: thread -1, cpu 0, socket -1, mpidr 0
573 11:26:04.993602 <6>[ 0.136573] Setting up static identity map for 0x80300000 - 0x803000ac
574 11:26:04.999438 <6>[ 0.146258] rcu: Hierarchical SRCU implementation.
575 11:26:05.007064 <6>[ 0.151540] rcu: Max phase no-delay instances is 1000.
576 11:26:05.015554 <6>[ 0.162642] EFI services will not be available.
577 11:26:05.021405 <6>[ 0.167929] smp: Bringing up secondary CPUs ...
578 11:26:05.027144 <6>[ 0.172976] smp: Brought up 1 node, 1 CPU
579 11:26:05.035342 <6>[ 0.177377] SMP: Total of 1 processors activated (996.14 BogoMIPS).
580 11:26:05.041241 <6>[ 0.184147] CPU: All CPU(s) started in SVC mode.
581 11:26:05.056190 <6>[ 0.189329] Memory: 405960K/522240K available (16384K kernel code, 2543K rwdata, 6824K rodata, 2048K init, 426K bss, 49084K reserved, 65536K cma-reserved, 0K highmem)
582 11:26:05.056683 <6>[ 0.205633] devtmpfs: initialized
583 11:26:05.081651 <6>[ 0.222942] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
584 11:26:05.093176 <6>[ 0.231525] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
585 11:26:05.099159 <6>[ 0.241980] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
586 11:26:05.109793 <6>[ 0.254241] pinctrl core: initialized pinctrl subsystem
587 11:26:05.119132 <6>[ 0.264895] DMI not present or invalid.
588 11:26:05.127515 <6>[ 0.270785] NET: Registered PF_NETLINK/PF_ROUTE protocol family
589 11:26:05.137037 <6>[ 0.279783] DMA: preallocated 256 KiB pool for atomic coherent allocations
590 11:26:05.152207 <6>[ 0.291315] thermal_sys: Registered thermal governor 'step_wise'
591 11:26:05.152702 <6>[ 0.291480] cpuidle: using governor menu
592 11:26:05.179519 <6>[ 0.326844] No ATAGs?
593 11:26:05.185718 <6>[ 0.329580] hw-breakpoint: debug architecture 0x4 unsupported.
594 11:26:05.195921 <6>[ 0.341546] Serial: AMBA PL011 UART driver
595 11:26:05.227756 <6>[ 0.375048] iommu: Default domain type: Translated
596 11:26:05.236880 <6>[ 0.380395] iommu: DMA domain TLB invalidation policy: strict mode
597 11:26:05.264031 <5>[ 0.410683] SCSI subsystem initialized
598 11:26:05.269890 <6>[ 0.415588] usbcore: registered new interface driver usbfs
599 11:26:05.275620 <6>[ 0.421620] usbcore: registered new interface driver hub
600 11:26:05.284382 <6>[ 0.427403] usbcore: registered new device driver usb
601 11:26:05.290143 <6>[ 0.433917] pps_core: LinuxPPS API ver. 1 registered
602 11:26:05.295904 <6>[ 0.439305] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
603 11:26:05.301794 <6>[ 0.449034] PTP clock support registered
604 11:26:05.306858 <6>[ 0.453493] EDAC MC: Ver: 3.0.0
605 11:26:05.356859 <6>[ 0.501648] scmi_core: SCMI protocol bus registered
606 11:26:05.372434 <6>[ 0.519064] vgaarb: loaded
607 11:26:05.378515 <6>[ 0.522905] clocksource: Switched to clocksource dmtimer
608 11:26:05.412490 <6>[ 0.559515] NET: Registered PF_INET protocol family
609 11:26:05.425144 <6>[ 0.565223] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
610 11:26:05.430869 <6>[ 0.574071] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
611 11:26:05.442320 <6>[ 0.582992] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
612 11:26:05.448156 <6>[ 0.591234] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
613 11:26:05.459664 <6>[ 0.599524] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
614 11:26:05.465523 <6>[ 0.607242] TCP: Hash tables configured (established 4096 bind 4096)
615 11:26:05.471274 <6>[ 0.614163] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
616 11:26:05.477174 <6>[ 0.621172] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
617 11:26:05.484743 <6>[ 0.628791] NET: Registered PF_UNIX/PF_LOCAL protocol family
618 11:26:05.571211 <6>[ 0.712936] RPC: Registered named UNIX socket transport module.
619 11:26:05.571719 <6>[ 0.719323] RPC: Registered udp transport module.
620 11:26:05.576978 <6>[ 0.724455] RPC: Registered tcp transport module.
621 11:26:05.582729 <6>[ 0.729560] RPC: Registered tcp-with-tls transport module.
622 11:26:05.595721 <6>[ 0.735490] RPC: Registered tcp NFSv4.1 backchannel transport module.
623 11:26:05.596243 <6>[ 0.742399] PCI: CLS 0 bytes, default 64
624 11:26:05.602914 <5>[ 0.748199] Initialise system trusted keyrings
625 11:26:05.624236 <6>[ 0.768470] Trying to unpack rootfs image as initramfs...
626 11:26:05.705463 <6>[ 0.846528] workingset: timestamp_bits=30 max_order=17 bucket_order=0
627 11:26:05.710250 <6>[ 0.854094] squashfs: version 4.0 (2009/01/31) Phillip Lougher
628 11:26:05.746466 <5>[ 0.893827] NFS: Registering the id_resolver key type
629 11:26:05.752279 <5>[ 0.899405] Key type id_resolver registered
630 11:26:05.758055 <5>[ 0.904064] Key type id_legacy registered
631 11:26:05.766484 <6>[ 0.908503] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
632 11:26:05.773411 <6>[ 0.915693] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
633 11:26:05.841581 <5>[ 0.988960] Key type asymmetric registered
634 11:26:05.847443 <5>[ 0.993531] Asymmetric key parser 'x509' registered
635 11:26:05.858940 <6>[ 0.998952] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
636 11:26:05.859417 <6>[ 1.006884] io scheduler mq-deadline registered
637 11:26:05.864786 <6>[ 1.011816] io scheduler kyber registered
638 11:26:05.870365 <6>[ 1.016305] io scheduler bfq registered
639 11:26:05.959578 <6>[ 1.103257] ledtrig-cpu: registered to indicate activity on CPUs
640 11:26:06.254983 <6>[ 1.398411] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
641 11:26:06.290771 <6>[ 1.437908] msm_serial: driver initialized
642 11:26:06.296835 <6>[ 1.442694] SuperH (H)SCI(F) driver initialized
643 11:26:06.302780 <6>[ 1.448044] STMicroelectronics ASC driver initialized
644 11:26:06.308062 <6>[ 1.453730] STM32 USART driver initialized
645 11:26:06.409325 <6>[ 1.555863] brd: module loaded
646 11:26:06.443281 <6>[ 1.589916] loop: module loaded
647 11:26:06.484526 <6>[ 1.630866] CAN device driver interface
648 11:26:06.491251 <6>[ 1.636210] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
649 11:26:06.496960 <6>[ 1.643327] e1000e: Intel(R) PRO/1000 Network Driver
650 11:26:06.502794 <6>[ 1.648715] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
651 11:26:06.508523 <6>[ 1.655168] igb: Intel(R) Gigabit Ethernet Network Driver
652 11:26:06.516776 <6>[ 1.660993] igb: Copyright (c) 2007-2014 Intel Corporation.
653 11:26:06.528559 <6>[ 1.670201] pegasus: Pegasus/Pegasus II USB Ethernet driver
654 11:26:06.534345 <6>[ 1.676384] usbcore: registered new interface driver pegasus
655 11:26:06.540199 <6>[ 1.682515] usbcore: registered new interface driver asix
656 11:26:06.545920 <6>[ 1.688414] usbcore: registered new interface driver ax88179_178a
657 11:26:06.551705 <6>[ 1.695009] usbcore: registered new interface driver cdc_ether
658 11:26:06.557512 <6>[ 1.701308] usbcore: registered new interface driver smsc75xx
659 11:26:06.563278 <6>[ 1.707537] usbcore: registered new interface driver smsc95xx
660 11:26:06.569038 <6>[ 1.713765] usbcore: registered new interface driver net1080
661 11:26:06.574811 <6>[ 1.719889] usbcore: registered new interface driver cdc_subset
662 11:26:06.580588 <6>[ 1.726297] usbcore: registered new interface driver zaurus
663 11:26:06.588231 <6>[ 1.732339] usbcore: registered new interface driver cdc_ncm
664 11:26:06.598025 <6>[ 1.741777] usbcore: registered new interface driver usb-storage
665 11:26:06.607170 <6>[ 1.752697] i2c_dev: i2c /dev entries driver
666 11:26:06.630968 <5>[ 1.770440] cpuidle: enable-method property 'ti,am3352' found operations
667 11:26:06.636806 <6>[ 1.779920] sdhci: Secure Digital Host Controller Interface driver
668 11:26:06.644761 <6>[ 1.786687] sdhci: Copyright(c) Pierre Ossman
669 11:26:06.651789 <6>[ 1.793191] Synopsys Designware Multimedia Card Interface Driver
670 11:26:06.656831 <6>[ 1.800945] sdhci-pltfm: SDHCI platform and OF driver helper
671 11:26:06.670754 <6>[ 1.810650] usbcore: registered new interface driver usbhid
672 11:26:06.671219 <6>[ 1.816760] usbhid: USB HID core driver
673 11:26:06.683383 <6>[ 1.828138] NET: Registered PF_INET6 protocol family
674 11:26:07.156574 <6>[ 2.303756] Segment Routing with IPv6
675 11:26:07.162142 <6>[ 2.307905] In-situ OAM (IOAM) with IPv6
676 11:26:07.168936 <6>[ 2.312295] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
677 11:26:07.174731 <6>[ 2.319711] NET: Registered PF_PACKET protocol family
678 11:26:07.180565 <6>[ 2.325275] can: controller area network core
679 11:26:07.186386 <6>[ 2.330104] NET: Registered PF_CAN protocol family
680 11:26:07.186873 <6>[ 2.335339] can: raw protocol
681 11:26:07.192148 <6>[ 2.338665] can: broadcast manager protocol
682 11:26:07.198697 <6>[ 2.343265] can: netlink gateway - max_hops=1
683 11:26:07.204819 <5>[ 2.348864] Key type dns_resolver registered
684 11:26:07.211157 <6>[ 2.353938] ThumbEE CPU extension supported.
685 11:26:07.211466 <5>[ 2.358626] Registering SWP/SWPB emulation handler
686 11:26:07.220953 <3>[ 2.364319] omap_voltage_late_init: Voltage driver support not added
687 11:26:07.418919 <5>[ 2.563737] Loading compiled-in X.509 certificates
688 11:26:07.557325 <6>[ 2.691730] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
689 11:26:07.564644 <6>[ 2.708415] pinctrl-single 44e10800.pinmux: 142 pins, size 568
690 11:26:07.590720 <3>[ 2.732025] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
691 11:26:07.791640 <3>[ 2.932805] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
692 11:26:07.998572 <6>[ 3.144138] OMAP GPIO hardware version 0.1
693 11:26:08.019027 <6>[ 3.162677] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
694 11:26:08.112508 <4>[ 3.255892] at24 2-0054: supply vcc not found, using dummy regulator
695 11:26:08.178951 <4>[ 3.322342] at24 2-0055: supply vcc not found, using dummy regulator
696 11:26:08.214727 <4>[ 3.358126] at24 2-0056: supply vcc not found, using dummy regulator
697 11:26:08.255168 <4>[ 3.398560] at24 2-0057: supply vcc not found, using dummy regulator
698 11:26:08.293478 <6>[ 3.437681] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
699 11:26:08.369094 <3>[ 3.509275] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
700 11:26:08.393935 <6>[ 3.530415] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
701 11:26:08.415042 <4>[ 3.557178] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
702 11:26:08.451469 <4>[ 3.593594] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
703 11:26:08.569777 <6>[ 3.713301] omap_rng 48310000.rng: Random Number Generator ver. 20
704 11:26:08.593053 <5>[ 3.739417] random: crng init done
705 11:26:08.641918 <6>[ 3.783998] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
706 11:26:08.676593 <6>[ 3.822360] Freeing initrd memory: 14484K
707 11:26:08.724020 <6>[ 3.865229] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
708 11:26:08.729732 <6>[ 3.875564] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
709 11:26:08.741486 <6>[ 3.882838] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
710 11:26:08.747330 <6>[ 3.890390] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
711 11:26:08.758911 <6>[ 3.898519] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
712 11:26:08.766375 <6>[ 3.910154] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
713 11:26:08.779396 <5>[ 3.919227] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
714 11:26:08.807205 <3>[ 3.948964] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
715 11:26:08.812962 <6>[ 3.957551] edma 49000000.dma: TI EDMA DMA engine driver
716 11:26:08.884066 <3>[ 4.024648] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
717 11:26:08.898376 <6>[ 4.038961] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
718 11:26:08.911561 <3>[ 4.056037] l3-aon-clkctrl:0000:0: failed to disable
719 11:26:08.959650 <6>[ 4.101323] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
720 11:26:08.965384 <6>[ 4.110829] printk: legacy console [ttyS0] enabled
721 11:26:08.971007 <6>[ 4.110829] printk: legacy console [ttyS0] enabled
722 11:26:08.976833 <6>[ 4.121167] printk: legacy bootconsole [omap8250] disabled
723 11:26:08.982609 <6>[ 4.121167] printk: legacy bootconsole [omap8250] disabled
724 11:26:09.023192 <4>[ 4.163676] tps65217-pmic: Failed to locate of_node [id: -1]
725 11:26:09.026829 <4>[ 4.171070] tps65217-bl: Failed to locate of_node [id: -1]
726 11:26:09.043112 <6>[ 4.190628] tps65217 0-0024: TPS65217 ID 0xe version 1.2
727 11:26:09.061679 <6>[ 4.197566] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
728 11:26:09.075059 <6>[ 4.211303] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
729 11:26:09.080241 <6>[ 4.223172] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
730 11:26:09.101603 <6>[ 4.243666] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
731 11:26:09.107579 <6>[ 4.252722] sdhci-omap 48060000.mmc: Got CD GPIO
732 11:26:09.115604 <4>[ 4.257935] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
733 11:26:09.131355 <4>[ 4.271050] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
734 11:26:09.138235 <4>[ 4.281206] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
735 11:26:09.148037 <4>[ 4.290388] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
736 11:26:09.270279 <6>[ 4.413312] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
737 11:26:09.318800 <6>[ 4.459627] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
738 11:26:09.325300 <6>[ 4.468978] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
739 11:26:09.334425 <6>[ 4.477897] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
740 11:26:09.384615 <6>[ 4.522826] mmc0: new high speed SDHC card at address 1234
741 11:26:09.385230 <6>[ 4.530214] mmcblk0: mmc0:1234 SA32G 29.1 GiB
742 11:26:09.391617 <6>[ 4.538991] mmcblk0: p1
743 11:26:09.414940 <6>[ 4.554091] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
744 11:26:09.438633 <6>[ 4.572696] mmc1: new high speed MMC card at address 0001
745 11:26:09.439334 <6>[ 4.580304] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
746 11:26:09.445015 <6>[ 4.588840] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
747 11:26:09.452000 <6>[ 4.597102] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
748 11:26:09.461570 <6>[ 4.605365] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
749 11:26:11.542350 <6>[ 6.683960] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
750 11:26:11.615749 <5>[ 6.722911] Sending DHCP requests ., OK
751 11:26:11.626946 <6>[ 6.767375] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
752 11:26:11.627439 <6>[ 6.775543] IP-Config: Complete:
753 11:26:11.641088 <6>[ 6.779083] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
754 11:26:11.646801 <6>[ 6.789604] host=192.168.6.12, domain=, nis-domain=(none)
755 11:26:11.652496 <6>[ 6.795816] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
756 11:26:11.659095 <6>[ 6.795851] nameserver0=10.255.253.1
757 11:26:11.668163 <6>[ 6.808396] clk: Disabling unused clocks
758 11:26:11.668633 <6>[ 6.813114] PM: genpd: Disabling unused power domains
759 11:26:11.687472 <6>[ 6.831568] Freeing unused kernel image (initmem) memory: 2048K
760 11:26:11.694941 <6>[ 6.841324] Run /init as init process
761 11:26:11.720210 Loading, please wait...
762 11:26:11.795761 Starting systemd-udevd version 252.22-1~deb12u1
763 11:26:14.876739 <4>[ 10.016994] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
764 11:26:15.014029 <4>[ 10.154426] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
765 11:26:15.194195 <6>[ 10.342150] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
766 11:26:15.205225 <6>[ 10.348019] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
767 11:26:15.375565 <6>[ 10.521921] hub 1-0:1.0: USB hub found
768 11:26:15.420101 <6>[ 10.566104] tda998x 0-0070: found TDA19988
769 11:26:15.436806 <6>[ 10.583099] hub 1-0:1.0: 1 port detected
770 11:26:18.812149 Begin: Loading essential drivers ... done.
771 11:26:18.817619 Begin: Running /scripts/init-premount ... done.
772 11:26:18.823177 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
773 11:26:18.838206 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
774 11:26:18.838686 Device /sys/class/net/eth0 found
775 11:26:18.839126 done.
776 11:26:18.897888 Begin: Waiting up to 180 secs for any network device to become available ... done.
777 11:26:18.968412 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
778 11:26:18.996090 IP-Config: eth0 guessed broadcast address 192.168.6.255
779 11:26:19.002327 IP-Config: eth0 complete (dhcp from 192.168.6.1):
780 11:26:19.007303 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
781 11:26:19.018301 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
782 11:26:19.018791 rootserver: 192.168.6.1 rootpath:
783 11:26:19.021826 filename :
784 11:26:19.143443 done.
785 11:26:19.149547 Begin: Running /scripts/nfs-bottom ... done.
786 11:26:19.218912 Begin: Running /scripts/init-bottom ... done.
787 11:26:20.620169 <30>[ 15.764022] systemd[1]: System time before build time, advancing clock.
788 11:26:20.795815 <30>[ 15.913444] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
789 11:26:20.805166 <30>[ 15.950796] systemd[1]: Detected architecture arm.
790 11:26:20.817838
791 11:26:20.818147 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
792 11:26:20.818383
793 11:26:20.846875 <30>[ 15.992374] systemd[1]: Hostname set to <debian-bookworm-armhf>.
794 11:26:23.028675 <30>[ 18.172066] systemd[1]: Queued start job for default target graphical.target.
795 11:26:23.045688 <30>[ 18.187069] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
796 11:26:23.053225 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
797 11:26:23.073966 <30>[ 18.215742] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
798 11:26:23.082418 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
799 11:26:23.104709 <30>[ 18.246359] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
800 11:26:23.113077 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
801 11:26:23.133130 <30>[ 18.274959] systemd[1]: Created slice user.slice - User and Session Slice.
802 11:26:23.139790 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
803 11:26:23.168227 <30>[ 18.304308] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
804 11:26:23.174227 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
805 11:26:23.192096 <30>[ 18.334063] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
806 11:26:23.201127 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
807 11:26:23.233126 <30>[ 18.364079] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
808 11:26:23.239596 <30>[ 18.384610] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
809 11:26:23.248086 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
810 11:26:23.271238 <30>[ 18.413423] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
811 11:26:23.279481 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
812 11:26:23.302050 <30>[ 18.443894] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
813 11:26:23.310472 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
814 11:26:23.331796 <30>[ 18.473900] systemd[1]: Reached target paths.target - Path Units.
815 11:26:23.336888 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
816 11:26:23.361640 <30>[ 18.503644] systemd[1]: Reached target remote-fs.target - Remote File Systems.
817 11:26:23.368904 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
818 11:26:23.391360 <30>[ 18.533496] systemd[1]: Reached target slices.target - Slice Units.
819 11:26:23.396821 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
820 11:26:23.421616 <30>[ 18.563669] systemd[1]: Reached target swap.target - Swaps.
821 11:26:23.425594 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
822 11:26:23.451832 <30>[ 18.593777] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
823 11:26:23.460791 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
824 11:26:23.482719 <30>[ 18.624506] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
825 11:26:23.490991 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
826 11:26:23.573436 <30>[ 18.710493] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
827 11:26:23.586144 <30>[ 18.727940] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
828 11:26:23.594619 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
829 11:26:23.623467 <30>[ 18.764704] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
830 11:26:23.630824 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
831 11:26:23.654912 <30>[ 18.796556] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
832 11:26:23.663108 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
833 11:26:23.686417 <30>[ 18.828063] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
834 11:26:23.692057 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
835 11:26:23.725570 <30>[ 18.866392] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
836 11:26:23.733084 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
837 11:26:23.758691 <30>[ 18.894539] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
838 11:26:23.775190 <30>[ 18.911071] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
839 11:26:23.825931 <30>[ 18.968717] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
840 11:26:23.851757 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
841 11:26:23.903386 <30>[ 19.046044] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
842 11:26:23.922981 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
843 11:26:23.986921 <30>[ 19.128640] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
844 11:26:24.022219 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
845 11:26:24.073329 <30>[ 19.215614] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
846 11:26:24.100945 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
847 11:26:24.152192 <30>[ 19.294838] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
848 11:26:24.172340 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
849 11:26:24.221810 <30>[ 19.364927] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
850 11:26:24.241167 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
851 11:26:24.270607 <30>[ 19.412602] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
852 11:26:24.300282 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
853 11:26:24.353382 <30>[ 19.496424] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
854 11:26:24.380531 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
855 11:26:24.433170 <30>[ 19.576225] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
856 11:26:24.459511 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
857 11:26:24.488227 <28>[ 19.625254] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
858 11:26:24.496636 <28>[ 19.638848] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
859 11:26:24.542437 <30>[ 19.684268] systemd[1]: Starting systemd-journald.service - Journal Service...
860 11:26:24.548849 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
861 11:26:24.620678 <30>[ 19.764428] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
862 11:26:24.640261 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
863 11:26:24.668604 <30>[ 19.811603] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
864 11:26:24.710587 Starting [0;1;39msystemd-network-g… units from Kernel command line...
865 11:26:24.766016 <30>[ 19.908351] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
866 11:26:24.829443 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
867 11:26:24.904219 <30>[ 20.047332] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
868 11:26:24.951351 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
869 11:26:25.034095 <30>[ 20.177263] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
870 11:26:25.071039 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
871 11:26:25.091305 <30>[ 20.235195] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
872 11:26:25.131388 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
873 11:26:25.154870 <30>[ 20.297729] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
874 11:26:25.188202 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
875 11:26:25.301267 <30>[ 20.444930] systemd[1]: modprobe@configfs.service: Deactivated successfully.
876 11:26:25.331554 <30>[ 20.474104] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
877 11:26:25.360710 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
878 11:26:25.371971 <30>[ 20.515788] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
879 11:26:25.401782 <30>[ 20.544701] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
880 11:26:25.431125 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
881 11:26:25.441728 <30>[ 20.585869] systemd[1]: modprobe@drm.service: Deactivated successfully.
882 11:26:25.471390 <30>[ 20.614840] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
883 11:26:25.499557 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
884 11:26:25.512338 <30>[ 20.654654] systemd[1]: Started systemd-journald.service - Journal Service.
885 11:26:25.519190 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
886 11:26:25.561332 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
887 11:26:25.586935 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
888 11:26:25.622466 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
889 11:26:25.644074 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
890 11:26:25.664519 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
891 11:26:25.693783 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
892 11:26:25.722185 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
893 11:26:25.790109 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
894 11:26:25.811879 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
895 11:26:25.872344 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
896 11:26:25.934625 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
897 11:26:25.990800 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
898 11:26:26.142704 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
899 11:26:26.284077 <46>[ 21.426942] systemd-journald[164]: Received client request to flush runtime journal.
900 11:26:26.334540 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
901 11:26:26.421171 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
902 11:26:27.192433 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
903 11:26:27.286883 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
904 11:26:28.006214 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
905 11:26:28.123953 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
906 11:26:28.150884 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
907 11:26:28.170917 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
908 11:26:28.241368 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
909 11:26:28.296217 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
910 11:26:29.264611 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
911 11:26:29.332262 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
912 11:26:29.391029 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
913 11:26:29.465081 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
914 11:26:29.531169 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
915 11:26:30.416666 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
916 11:26:31.872451 <5>[ 27.015884] cfg80211: Loading compiled-in X.509 certificates for regulatory database
917 11:26:32.417936 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
918 11:26:33.043205 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
919 11:26:33.069547 <5>[ 28.215025] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
920 11:26:33.192682 <5>[ 28.333454] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
921 11:26:33.198321 <4>[ 28.343487] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
922 11:26:33.206047 <6>[ 28.352465] cfg80211: failed to load regulatory.db
923 11:26:33.711080 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
924 11:26:34.001865 <46>[ 29.136178] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
925 11:26:34.184879 <46>[ 29.321263] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
926 11:26:34.663333 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
927 11:26:43.666305 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
928 11:26:43.697032 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
929 11:26:43.722694 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
930 11:26:43.743082 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
931 11:26:43.801049 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
932 11:26:43.843005 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
933 11:26:43.902525 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
934 11:26:43.981705 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
935 11:26:44.034199 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
936 11:26:44.068519 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
937 11:26:44.098845 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
938 11:26:44.126319 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
939 11:26:44.167616 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
940 11:26:44.198743 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
941 11:26:44.234295 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
942 11:26:44.274745 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
943 11:26:44.312352 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
944 11:26:44.335615 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
945 11:26:44.362554 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
946 11:26:44.383362 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
947 11:26:44.421304 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
948 11:26:44.446226 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
949 11:26:44.473457 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
950 11:26:44.540953 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
951 11:26:44.582739 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
952 11:26:44.670703 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
953 11:26:44.751227 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
954 11:26:44.805460 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
955 11:26:44.846851 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
956 11:26:44.874028 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
957 11:26:45.056286 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
958 11:26:45.130725 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
959 11:26:45.183132 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
960 11:26:45.200948 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
961 11:26:45.235870 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
962 11:26:45.483711 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
963 11:26:45.878016 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
964 11:26:45.933902 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
965 11:26:45.976568 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
966 11:26:46.052268 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
967 11:26:46.229127 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
968 11:26:46.360878
969 11:26:46.364303 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
970 11:26:46.364808
971 11:26:46.671525 Linux debian-bookworm-armhf 6.12.0-rc5-next-20241030 #1 SMP Wed Oct 30 10:53:25 UTC 2024 armv7l
972 11:26:46.672165
973 11:26:46.677238 The programs included with the Debian GNU/Linux system are free software;
974 11:26:46.682742 the exact distribution terms for each program are described in the
975 11:26:46.688328 individual files in /usr/share/doc/*/copyright.
976 11:26:46.688826
977 11:26:46.693932 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
978 11:26:46.697646 permitted by applicable law.
979 11:26:51.407312 Unable to match end of the kernel message
981 11:26:51.409069 Setting prompt string to ['/ #']
982 11:26:51.409691 end: 2.4.4.1 login-action (duration 00:00:47) [common]
984 11:26:51.411203 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
985 11:26:51.411784 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
986 11:26:51.412370 Setting prompt string to ['/ #']
987 11:26:51.412839 Forcing a shell prompt, looking for ['/ #']
989 11:26:51.463961 / #
990 11:26:51.464749 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
991 11:26:51.465299 Waiting using forced prompt support (timeout 00:02:30)
992 11:26:51.469640
993 11:26:51.476215 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
994 11:26:51.476839 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
995 11:26:51.477342 Sending with 10 millisecond of delay
997 11:26:56.464929 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/913245/extract-nfsrootfs-gqz_loyv'
998 11:26:56.476029 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/913245/extract-nfsrootfs-gqz_loyv'
999 11:26:56.476891 Sending with 10 millisecond of delay
1001 11:26:58.574970 / # export NFS_SERVER_IP='192.168.6.2'
1002 11:26:58.586042 export NFS_SERVER_IP='192.168.6.2'
1003 11:26:58.587051 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1004 11:26:58.587704 end: 2.4 uboot-commands (duration 00:01:53) [common]
1005 11:26:58.588398 end: 2 uboot-action (duration 00:01:53) [common]
1006 11:26:58.589025 start: 3 lava-test-retry (timeout 00:06:56) [common]
1007 11:26:58.589654 start: 3.1 lava-test-shell (timeout 00:06:56) [common]
1008 11:26:58.590159 Using namespace: common
1010 11:26:58.691429 / # #
1011 11:26:58.692448 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1012 11:26:58.696408 #
1013 11:26:58.703450 Using /lava-913245
1015 11:26:58.804773 / # export SHELL=/bin/bash
1016 11:26:58.810155 export SHELL=/bin/bash
1018 11:26:58.916517 / # . /lava-913245/environment
1019 11:26:58.921330 . /lava-913245/environment
1021 11:26:59.030456 / # /lava-913245/bin/lava-test-runner /lava-913245/0
1022 11:26:59.031412 Test shell timeout: 10s (minimum of the action and connection timeout)
1023 11:26:59.035571 /lava-913245/bin/lava-test-runner /lava-913245/0
1024 11:26:59.428798 + export TESTRUN_ID=0_timesync-off
1025 11:26:59.436021 + TESTRUN_ID=0_timesync-off
1026 11:26:59.436558 + cd /lava-913245/0/tests/0_timesync-off
1027 11:26:59.437028 ++ cat uuid
1028 11:26:59.452452 + UUID=913245_1.6.2.4.1
1029 11:26:59.452969 + set +x
1030 11:26:59.460272 <LAVA_SIGNAL_STARTRUN 0_timesync-off 913245_1.6.2.4.1>
1031 11:26:59.460785 + systemctl stop systemd-timesyncd
1032 11:26:59.461549 Received signal: <STARTRUN> 0_timesync-off 913245_1.6.2.4.1
1033 11:26:59.462027 Starting test lava.0_timesync-off (913245_1.6.2.4.1)
1034 11:26:59.462591 Skipping test definition patterns.
1035 11:26:59.761052 + set +x
1036 11:26:59.761629 <LAVA_SIGNAL_ENDRUN 0_timesync-off 913245_1.6.2.4.1>
1037 11:26:59.762355 Received signal: <ENDRUN> 0_timesync-off 913245_1.6.2.4.1
1038 11:26:59.762890 Ending use of test pattern.
1039 11:26:59.763341 Ending test lava.0_timesync-off (913245_1.6.2.4.1), duration 0.30
1041 11:26:59.940451 + export TESTRUN_ID=1_kselftest-dt
1042 11:26:59.947434 + TESTRUN_ID=1_kselftest-dt
1043 11:26:59.947953 + cd /lava-913245/0/tests/1_kselftest-dt
1044 11:26:59.948482 ++ cat uuid
1045 11:26:59.964395 + UUID=913245_1.6.2.4.5
1046 11:26:59.964905 + set +x
1047 11:26:59.970101 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 913245_1.6.2.4.5>
1048 11:26:59.970599 + cd ./automated/linux/kselftest/
1049 11:26:59.971332 Received signal: <STARTRUN> 1_kselftest-dt 913245_1.6.2.4.5
1050 11:26:59.971799 Starting test lava.1_kselftest-dt (913245_1.6.2.4.5)
1051 11:26:59.972366 Skipping test definition patterns.
1052 11:26:59.995158 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1053 11:27:00.107273 INFO: install_deps skipped
1054 11:27:00.612487 --2024-10-30 11:27:00-- http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1055 11:27:00.641904 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1056 11:27:00.786416 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1057 11:27:00.931456 HTTP request sent, awaiting response... 200 OK
1058 11:27:00.931974 Length: 4169676 (4.0M) [application/octet-stream]
1059 11:27:00.937013 Saving to: 'kselftest_armhf.tar.gz'
1060 11:27:00.937515
1061 11:27:02.467412
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 44.73K 158KB/s
kselftest_armhf.tar 5%[> ] 218.67K 384KB/s
kselftest_armhf.tar 21%[===> ] 892.70K 1.02MB/s
kselftest_armhf.tar 36%[======> ] 1.45M 1.31MB/s
kselftest_armhf.tar 92%[=================> ] 3.67M 2.80MB/s
kselftest_armhf.tar 100%[===================>] 3.98M 2.61MB/s
kselftest_armhf.tar 100%[===================>] 3.98M 2.61MB/s in 1.5s
1062 11:27:02.468145
1063 11:27:02.948343 2024-10-30 11:27:02 (2.61 MB/s) - 'kselftest_armhf.tar.gz' saved [4169676/4169676]
1064 11:27:02.949016
1065 11:27:15.490384 skiplist:
1066 11:27:15.491043 ========================================
1067 11:27:15.496109 ========================================
1068 11:27:15.598457 dt:test_unprobed_devices.sh
1069 11:27:15.642888 ============== Tests to run ===============
1070 11:27:15.651030 dt:test_unprobed_devices.sh
1071 11:27:15.654813 ===========End Tests to run ===============
1072 11:27:15.664923 shardfile-dt pass
1073 11:27:15.896360 <12>[ 71.046103] kselftest: Running tests in dt
1074 11:27:15.925511 TAP version 13
1075 11:27:15.951405 1..1
1076 11:27:16.004061 # timeout set to 45
1077 11:27:16.004763 # selftests: dt: test_unprobed_devices.sh
1078 11:27:16.753973 # TAP version 13
1079 11:27:41.729187 # 1..257
1080 11:27:41.897779 # ok 1 / # SKIP
1081 11:27:41.925138 # ok 2 /clk_mcasp0
1082 11:27:41.997578 # ok 3 /clk_mcasp0_fixed # SKIP
1083 11:27:42.067618 # ok 4 /cpus/cpu@0 # SKIP
1084 11:27:42.141978 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1085 11:27:42.160641 # ok 6 /fixedregulator0
1086 11:27:42.181247 # ok 7 /leds
1087 11:27:42.206269 # ok 8 /ocp
1088 11:27:42.230286 # ok 9 /ocp/interconnect@44c00000
1089 11:27:42.252151 # ok 10 /ocp/interconnect@44c00000/segment@0
1090 11:27:42.279645 # ok 11 /ocp/interconnect@44c00000/segment@100000
1091 11:27:42.298167 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1092 11:27:42.370104 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1093 11:27:42.390435 # ok 14 /ocp/interconnect@44c00000/segment@200000
1094 11:27:42.414833 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1095 11:27:42.524534 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1096 11:27:42.596080 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1097 11:27:42.669573 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1098 11:27:42.737958 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1099 11:27:42.810712 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1100 11:27:42.882541 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1101 11:27:42.954359 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1102 11:27:43.029110 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1103 11:27:43.098117 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1104 11:27:43.170976 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1105 11:27:43.241615 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1106 11:27:43.313870 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1107 11:27:43.385683 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1108 11:27:43.458002 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1109 11:27:43.528635 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1110 11:27:43.600543 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1111 11:27:43.671367 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1112 11:27:43.743312 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1113 11:27:43.814630 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1114 11:27:43.890566 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1115 11:27:43.958600 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1116 11:27:44.030762 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1117 11:27:44.102840 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1118 11:27:44.174508 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1119 11:27:44.246640 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1120 11:27:44.318165 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1121 11:27:44.395359 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1122 11:27:44.467270 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1123 11:27:44.537625 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1124 11:27:44.605840 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1125 11:27:44.679058 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1126 11:27:44.751243 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1127 11:27:44.822984 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1128 11:27:44.895007 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1129 11:27:44.969773 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1130 11:27:45.039066 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1131 11:27:45.112134 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1132 11:27:45.183963 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1133 11:27:45.257298 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1134 11:27:45.332967 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1135 11:27:45.401918 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1136 11:27:45.473808 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1137 11:27:45.545261 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1138 11:27:45.625740 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1139 11:27:45.695752 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1140 11:27:45.767029 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1141 11:27:45.835318 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1142 11:27:45.909905 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1143 11:27:45.978589 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1144 11:27:46.050582 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1145 11:27:46.123325 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1146 11:27:46.195732 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1147 11:27:46.271026 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1148 11:27:46.340927 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1149 11:27:46.413775 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1150 11:27:46.488847 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1151 11:27:46.561431 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1152 11:27:46.633788 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1153 11:27:46.706305 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1154 11:27:46.782953 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1155 11:27:46.850882 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1156 11:27:46.923413 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1157 11:27:46.999560 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1158 11:27:47.071696 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1159 11:27:47.144108 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1160 11:27:47.216301 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1161 11:27:47.288484 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1162 11:27:47.360343 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1163 11:27:47.432888 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1164 11:27:47.505284 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1165 11:27:47.577563 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1166 11:27:47.650215 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1167 11:27:47.722395 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1168 11:27:47.796759 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1169 11:27:47.869869 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1170 11:27:47.939821 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1171 11:27:48.013912 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1172 11:27:48.085913 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1173 11:27:48.163909 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1174 11:27:48.180413 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1175 11:27:48.204220 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1176 11:27:48.232765 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1177 11:27:48.254900 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1178 11:27:48.276965 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1179 11:27:48.301364 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1180 11:27:48.329062 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1181 11:27:48.348714 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1182 11:27:48.455235 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1183 11:27:48.479724 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1184 11:27:48.504205 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1185 11:27:48.527970 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1186 11:27:48.633464 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1187 11:27:48.713907 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1188 11:27:48.781985 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1189 11:27:48.854429 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1190 11:27:48.926983 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1191 11:27:48.999448 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1192 11:27:49.072768 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1193 11:27:49.144770 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1194 11:27:49.217624 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1195 11:27:49.290215 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1196 11:27:49.363241 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1197 11:27:49.435430 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1198 11:27:49.507045 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1199 11:27:49.585872 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1200 11:27:49.659505 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1201 11:27:49.728800 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1202 11:27:49.750564 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1203 11:27:49.821001 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1204 11:27:49.890224 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1205 11:27:49.963426 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1206 11:27:49.985896 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1207 11:27:50.061543 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1208 11:27:50.083899 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1209 11:27:50.151704 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1210 11:27:50.174597 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1211 11:27:50.198926 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1212 11:27:50.223974 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1213 11:27:50.247014 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1214 11:27:50.269311 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1215 11:27:50.293409 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1216 11:27:50.318863 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
1217 11:27:50.393058 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
1218 11:27:50.419684 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1219 11:27:50.443925 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1220 11:27:50.513394 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1221 11:27:50.584570 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1222 11:27:50.610298 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1223 11:27:50.711272 # not ok 144 /ocp/interconnect@47c00000
1224 11:27:50.778141 # not ok 145 /ocp/interconnect@47c00000/segment@0
1225 11:27:50.798988 # ok 146 /ocp/interconnect@48000000
1226 11:27:50.822567 # ok 147 /ocp/interconnect@48000000/segment@0
1227 11:27:50.847452 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1228 11:27:50.873601 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1229 11:27:50.900566 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1230 11:27:50.916749 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1231 11:27:50.940445 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1232 11:27:50.969318 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1233 11:27:50.987679 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1234 11:27:51.058981 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1235 11:27:51.131240 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1236 11:27:51.157653 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1237 11:27:51.176814 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1238 11:27:51.199816 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1239 11:27:51.226665 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1240 11:27:51.245993 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1241 11:27:51.270805 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1242 11:27:51.295002 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1243 11:27:51.322167 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1244 11:27:51.343636 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1245 11:27:51.364992 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1246 11:27:51.387696 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1247 11:27:51.411614 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1248 11:27:51.439133 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1249 11:27:51.464026 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1250 11:27:51.486785 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1251 11:27:51.507200 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1252 11:27:51.530045 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1253 11:27:51.558098 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1254 11:27:51.579903 # ok 175 /ocp/interconnect@48000000/segment@100000
1255 11:27:51.603940 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1256 11:27:51.625240 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1257 11:27:51.696613 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
1258 11:27:51.769625 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
1259 11:27:51.838707 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
1260 11:27:51.911684 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
1261 11:27:51.980530 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
1262 11:27:52.053771 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
1263 11:27:52.122755 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
1264 11:27:52.196222 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
1265 11:27:52.216762 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1266 11:27:52.239908 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1267 11:27:52.263148 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1268 11:27:52.286743 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1269 11:27:52.309717 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1270 11:27:52.333813 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1271 11:27:52.356722 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1272 11:27:52.384433 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1273 11:27:52.405987 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1274 11:27:52.428818 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1275 11:27:52.452947 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1276 11:27:52.476338 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1277 11:27:52.496019 # ok 198 /ocp/interconnect@48000000/segment@200000
1278 11:27:52.523554 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1279 11:27:52.594461 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1280 11:27:52.619113 # ok 201 /ocp/interconnect@48000000/segment@300000
1281 11:27:52.639457 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1282 11:27:52.663942 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1283 11:27:52.692233 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1284 11:27:52.713880 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1285 11:27:52.738687 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1286 11:27:52.758044 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1287 11:27:52.830206 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1288 11:27:52.848293 # ok 209 /ocp/interconnect@4a000000
1289 11:27:52.875290 # ok 210 /ocp/interconnect@4a000000/segment@0
1290 11:27:52.901245 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1291 11:27:52.924341 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1292 11:27:52.951069 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1293 11:27:52.973465 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1294 11:27:53.041069 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1295 11:27:53.154297 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1296 11:27:53.220280 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1297 11:27:53.323720 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1298 11:27:53.394615 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1299 11:27:53.472903 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1300 11:27:53.569948 # not ok 221 /ocp/interconnect@4b140000
1301 11:27:53.641340 # not ok 222 /ocp/interconnect@4b140000/segment@0
1302 11:27:53.707951 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1303 11:27:53.730855 # ok 224 /ocp/target-module@40300000
1304 11:27:53.752211 # ok 225 /ocp/target-module@40300000/sram@0
1305 11:27:53.828929 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1306 11:27:53.901404 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1307 11:27:53.920850 # ok 228 /ocp/target-module@47400000
1308 11:27:53.941558 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1309 11:27:53.964150 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1310 11:27:53.986352 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1311 11:27:54.008303 # ok 232 /ocp/target-module@47400000/usb@1400
1312 11:27:54.030906 # ok 233 /ocp/target-module@47400000/usb@1800
1313 11:27:54.052712 # ok 234 /ocp/target-module@47810000
1314 11:27:54.078893 # ok 235 /ocp/target-module@49000000
1315 11:27:54.101456 # ok 236 /ocp/target-module@49000000/dma@0
1316 11:27:54.119666 # ok 237 /ocp/target-module@49800000
1317 11:27:54.147104 # ok 238 /ocp/target-module@49800000/dma@0
1318 11:27:54.168899 # ok 239 /ocp/target-module@49900000
1319 11:27:54.187703 # ok 240 /ocp/target-module@49900000/dma@0
1320 11:27:54.210874 # ok 241 /ocp/target-module@49a00000
1321 11:27:54.231964 # ok 242 /ocp/target-module@49a00000/dma@0
1322 11:27:54.258397 # ok 243 /ocp/target-module@4c000000
1323 11:27:54.330002 # not ok 244 /ocp/target-module@4c000000/emif@0
1324 11:27:54.347091 # ok 245 /ocp/target-module@50000000
1325 11:27:54.370954 # ok 246 /ocp/target-module@53100000
1326 11:27:54.441224 # not ok 247 /ocp/target-module@53100000/sham@0
1327 11:27:54.462676 # ok 248 /ocp/target-module@53500000
1328 11:27:54.538037 # not ok 249 /ocp/target-module@53500000/aes@0
1329 11:27:54.560046 # ok 250 /ocp/target-module@56000000
1330 11:27:54.660470 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1331 11:27:54.730136 # ok 252 /opp-table # SKIP
1332 11:27:54.798322 # ok 253 /soc # SKIP
1333 11:27:54.824378 # ok 254 /sound
1334 11:27:54.842335 # ok 255 /target-module@4b000000
1335 11:27:54.867478 # ok 256 /target-module@4b000000/target-module@140000
1336 11:27:54.887943 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1337 11:27:54.896491 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1338 11:27:54.904467 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1339 11:27:57.101863 dt_test_unprobed_devices_sh_ skip
1340 11:27:57.107518 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1341 11:27:57.112991 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1342 11:27:57.113553 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1343 11:27:57.118539 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1344 11:27:57.124200 dt_test_unprobed_devices_sh_fixedregulator0 pass
1345 11:27:57.129786 dt_test_unprobed_devices_sh_leds pass
1346 11:27:57.130286 dt_test_unprobed_devices_sh_ocp pass
1347 11:27:57.135365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1348 11:27:57.140893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1349 11:27:57.146611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1350 11:27:57.157798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1351 11:27:57.163364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1352 11:27:57.169023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1353 11:27:57.180028 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1354 11:27:57.185701 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1355 11:27:57.196987 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1356 11:27:57.208252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1357 11:27:57.219424 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1358 11:27:57.225045 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1359 11:27:57.236402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1360 11:27:57.247592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1361 11:27:57.258633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1362 11:27:57.270700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1363 11:27:57.275571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1364 11:27:57.287204 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1365 11:27:57.298237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1366 11:27:57.308998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1367 11:27:57.326494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1368 11:27:57.327182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1369 11:27:57.337136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1370 11:27:57.349883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1371 11:27:57.373074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1372 11:27:57.373733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1373 11:27:57.376535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1374 11:27:57.387500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1375 11:27:57.398567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1376 11:27:57.411504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1377 11:27:57.418108 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1378 11:27:57.427168 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1379 11:27:57.438827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1380 11:27:57.448837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1381 11:27:57.460048 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1382 11:27:57.473138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1383 11:27:57.482486 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1384 11:27:57.493742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1385 11:27:57.504744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1386 11:27:57.515936 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1387 11:27:57.527268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1388 11:27:57.541477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1389 11:27:57.565720 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1390 11:27:57.585660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1391 11:27:57.586332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1392 11:27:57.586654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1393 11:27:57.594309 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1394 11:27:57.605500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1395 11:27:57.616761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1396 11:27:57.627859 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1397 11:27:57.639355 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1398 11:27:57.650360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1399 11:27:57.661590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1400 11:27:57.672884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1401 11:27:57.684332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1402 11:27:57.695397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1403 11:27:57.700674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1404 11:27:57.711888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1405 11:27:57.725092 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1406 11:27:57.734640 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1407 11:27:57.745529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1408 11:27:57.765368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1409 11:27:57.767900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1410 11:27:57.779025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1411 11:27:57.790209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1412 11:27:57.801902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1413 11:27:57.813201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1414 11:27:57.823857 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1415 11:27:57.836592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1416 11:27:57.846191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1417 11:27:57.857446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1418 11:27:57.868566 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1419 11:27:57.879826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1420 11:27:57.891287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1421 11:27:57.896773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1422 11:27:57.907930 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1423 11:27:57.919130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1424 11:27:57.930390 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1425 11:27:57.941553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1426 11:27:57.947065 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1427 11:27:57.963822 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1428 11:27:57.975406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1429 11:27:57.980802 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1430 11:27:57.997503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1431 11:27:58.008737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1432 11:27:58.019899 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1433 11:27:58.025468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1434 11:27:58.036660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1435 11:27:58.047809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1436 11:27:58.053504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1437 11:27:58.064898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1438 11:27:58.075853 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1439 11:27:58.081920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1440 11:27:58.092597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1441 11:27:58.098466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1442 11:27:58.109431 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1443 11:27:58.120589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1444 11:27:58.131724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1445 11:27:58.142933 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1446 11:27:58.154261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1447 11:27:58.165419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1448 11:27:58.176755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1449 11:27:58.187758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1450 11:27:58.198946 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1451 11:27:58.210043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1452 11:27:58.221305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1453 11:27:58.232483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1454 11:27:58.249249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1455 11:27:58.260556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1456 11:27:58.271670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1457 11:27:58.282816 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1458 11:27:58.294029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1459 11:27:58.310906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1460 11:27:58.321982 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1461 11:27:58.333255 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1462 11:27:58.344362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1463 11:27:58.350116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1464 11:27:58.361311 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1465 11:27:58.372340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1466 11:27:58.378557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1467 11:27:58.390177 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1468 11:27:58.394788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1469 11:27:58.405914 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1470 11:27:58.411509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1471 11:27:58.422693 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1472 11:27:58.428329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1473 11:27:58.440453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1474 11:27:58.445063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1475 11:27:58.456424 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
1476 11:27:58.468843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
1477 11:27:58.481751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1478 11:27:58.484803 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1479 11:27:58.495542 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1480 11:27:58.506619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1481 11:27:58.514353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1482 11:27:58.517795 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1483 11:27:58.528979 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1484 11:27:58.529267 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1485 11:27:58.559387 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1486 11:27:58.559824 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1487 11:27:58.560185 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1488 11:27:58.562651 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1489 11:27:58.568321 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1490 11:27:58.591523 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1491 11:27:58.592060 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1492 11:27:58.600613 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1493 11:27:58.602550 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1494 11:27:58.609469 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1495 11:27:58.623827 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1496 11:27:58.624630 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1497 11:27:58.636781 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1498 11:27:58.646162 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1499 11:27:58.652287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1500 11:27:58.657812 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1501 11:27:58.669165 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1502 11:27:58.674517 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1503 11:27:58.685796 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1504 11:27:58.691322 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1505 11:27:58.702504 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1506 11:27:58.708120 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1507 11:27:58.713678 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1508 11:27:58.724874 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1509 11:27:58.730619 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1510 11:27:58.747231 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1511 11:27:58.747846 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1512 11:27:58.758490 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1513 11:27:58.764182 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1514 11:27:58.775285 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1515 11:27:58.780936 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1516 11:27:58.792206 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
1517 11:27:58.803207 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
1518 11:27:58.814430 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
1519 11:27:58.825626 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
1520 11:27:58.831333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
1521 11:27:58.842562 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
1522 11:27:58.853641 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
1523 11:27:58.864801 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
1524 11:27:58.870471 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1525 11:27:58.881579 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1526 11:27:58.887330 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1527 11:27:58.899331 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1528 11:27:58.905334 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1529 11:27:58.915316 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1530 11:27:58.921045 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1531 11:27:58.941035 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1532 11:27:58.941737 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1533 11:27:58.949418 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1534 11:27:58.955051 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1535 11:27:58.965490 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1536 11:27:58.971129 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1537 11:27:58.982246 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1538 11:27:58.987963 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1539 11:27:58.993532 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1540 11:27:59.004650 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1541 11:27:59.010301 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1542 11:27:59.021418 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1543 11:27:59.027104 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1544 11:27:59.038211 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1545 11:27:59.043912 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1546 11:27:59.055004 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1547 11:27:59.060654 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1548 11:27:59.066220 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1549 11:27:59.071848 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1550 11:27:59.083018 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1551 11:27:59.088610 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1552 11:27:59.099765 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1553 11:27:59.105395 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1554 11:27:59.116544 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1555 11:27:59.127774 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1556 11:27:59.138911 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1557 11:27:59.150188 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1558 11:27:59.155802 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1559 11:27:59.161408 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1560 11:27:59.167018 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1561 11:27:59.172663 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1562 11:27:59.178229 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1563 11:27:59.183856 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1564 11:27:59.195076 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1565 11:27:59.200738 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1566 11:27:59.206327 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1567 11:27:59.211970 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1568 11:27:59.217541 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1569 11:27:59.228664 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1570 11:27:59.234312 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1571 11:27:59.240009 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1572 11:27:59.245546 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1573 11:27:59.251175 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1574 11:27:59.256777 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1575 11:27:59.262376 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1576 11:27:59.268007 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1577 11:27:59.273588 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1578 11:27:59.279217 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1579 11:27:59.284825 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1580 11:27:59.290416 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1581 11:27:59.296041 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1582 11:27:59.301650 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1583 11:27:59.307273 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1584 11:27:59.312866 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1585 11:27:59.318496 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1586 11:27:59.324121 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1587 11:27:59.329657 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1588 11:27:59.335260 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1589 11:27:59.340864 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1590 11:27:59.341418 dt_test_unprobed_devices_sh_opp-table skip
1591 11:27:59.346444 dt_test_unprobed_devices_sh_soc skip
1592 11:27:59.352097 dt_test_unprobed_devices_sh_sound pass
1593 11:27:59.352656 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1594 11:27:59.363173 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1595 11:27:59.368862 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1596 11:27:59.374429 dt_test_unprobed_devices_sh fail
1597 11:27:59.374973 + ../../utils/send-to-lava.sh ./output/result.txt
1598 11:27:59.380100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1599 11:27:59.381147 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1601 11:27:59.385903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1603 11:27:59.388851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1604 11:27:59.477447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1605 11:27:59.478307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1607 11:27:59.562156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1608 11:27:59.563086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1610 11:27:59.654270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1611 11:27:59.655218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1613 11:27:59.745641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1614 11:27:59.746562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1616 11:27:59.835564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1617 11:27:59.836529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1619 11:27:59.925128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1620 11:27:59.926057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1622 11:28:00.017644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1623 11:28:00.018582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1625 11:28:00.104555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1626 11:28:00.105581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1628 11:28:00.196192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1629 11:28:00.197105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1631 11:28:00.288880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1632 11:28:00.289847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1634 11:28:00.379236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1635 11:28:00.380280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1637 11:28:00.464312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1638 11:28:00.465329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1640 11:28:00.548550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1641 11:28:00.549478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1643 11:28:00.641225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1644 11:28:00.642113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1646 11:28:00.731797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1647 11:28:00.732801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1649 11:28:00.817164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1650 11:28:00.818110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1652 11:28:00.909358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1653 11:28:00.910344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1655 11:28:00.996289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1656 11:28:00.997337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1658 11:28:01.087743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1659 11:28:01.088828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1661 11:28:01.174663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1662 11:28:01.175640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1664 11:28:01.259509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1665 11:28:01.260483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1667 11:28:01.353388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1668 11:28:01.354213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1670 11:28:01.442691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1671 11:28:01.443591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1673 11:28:01.535516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1674 11:28:01.536534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1676 11:28:01.628618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1677 11:28:01.629626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1679 11:28:01.714320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1680 11:28:01.715290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1682 11:28:01.800017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1683 11:28:01.800965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1685 11:28:01.893281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1686 11:28:01.894178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1688 11:28:01.977526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1689 11:28:01.978202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1691 11:28:02.068572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1692 11:28:02.069736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1694 11:28:02.249342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1695 11:28:02.250183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1697 11:28:02.349401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1698 11:28:02.350246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1700 11:28:02.433117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1701 11:28:02.434028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1703 11:28:02.518828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1704 11:28:02.519739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1706 11:28:02.602731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1707 11:28:02.603610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1709 11:28:02.687908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1710 11:28:02.688829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1712 11:28:02.774792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1713 11:28:02.775822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1715 11:28:02.864369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1716 11:28:02.865231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1718 11:28:02.947599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1719 11:28:02.948470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1721 11:28:03.031040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1722 11:28:03.031883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1724 11:28:03.123103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1725 11:28:03.124089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1727 11:28:03.206788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1728 11:28:03.207618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1730 11:28:03.289722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1731 11:28:03.290567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1733 11:28:03.373751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1734 11:28:03.374597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1736 11:28:03.463831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1737 11:28:03.464852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1739 11:28:03.548858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1740 11:28:03.549769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1742 11:28:03.634113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1743 11:28:03.634981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1745 11:28:03.724867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1746 11:28:03.725715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1748 11:28:03.809436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1749 11:28:03.810292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1751 11:28:03.900269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1752 11:28:03.901107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1754 11:28:03.986421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1755 11:28:03.987257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1757 11:28:04.077991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1758 11:28:04.078824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1760 11:28:04.170496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1761 11:28:04.171353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1763 11:28:04.255763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1764 11:28:04.256653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1766 11:28:04.349519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1767 11:28:04.350526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1769 11:28:04.440231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1770 11:28:04.441110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1772 11:28:04.525676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1773 11:28:04.526528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1775 11:28:04.616025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1776 11:28:04.616929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1778 11:28:04.706100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1779 11:28:04.706943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1781 11:28:04.790623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1782 11:28:04.791450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1784 11:28:04.879844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1785 11:28:04.880847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1787 11:28:04.967091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1788 11:28:04.967939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1790 11:28:05.058136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1791 11:28:05.059063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1793 11:28:05.143184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1794 11:28:05.143956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1796 11:28:05.234592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1797 11:28:05.235346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1799 11:28:05.319435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1800 11:28:05.320191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1802 11:28:05.412273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1803 11:28:05.413014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1805 11:28:05.505145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1806 11:28:05.505868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1808 11:28:05.592568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1809 11:28:05.593287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1811 11:28:05.682972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1812 11:28:05.683696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1814 11:28:05.773827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1815 11:28:05.774551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1817 11:28:05.864273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1818 11:28:05.864987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1820 11:28:05.949573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1821 11:28:05.950319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1823 11:28:06.035776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1824 11:28:06.036627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1826 11:28:06.126425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1827 11:28:06.127173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1829 11:28:06.212494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1830 11:28:06.213219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1832 11:28:06.303054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1833 11:28:06.303795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1835 11:28:06.394100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1836 11:28:06.394841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1838 11:28:06.484059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1839 11:28:06.484778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1841 11:28:06.569566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1842 11:28:06.570300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1844 11:28:06.654156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1845 11:28:06.654860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1847 11:28:06.743266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1848 11:28:06.744032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1850 11:28:06.827704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1851 11:28:06.828462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1853 11:28:06.919224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1854 11:28:06.919943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1856 11:28:07.004772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1857 11:28:07.005519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1859 11:28:07.095798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1860 11:28:07.096566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1862 11:28:07.182130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1863 11:28:07.182863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1865 11:28:07.276106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1866 11:28:07.276837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1868 11:28:07.366896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1869 11:28:07.367726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1871 11:28:07.449812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1872 11:28:07.450577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1874 11:28:07.544891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1875 11:28:07.545617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1877 11:28:07.635886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1878 11:28:07.636659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1880 11:28:07.721263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1881 11:28:07.722099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1883 11:28:07.812174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1884 11:28:07.812966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1886 11:28:07.897350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1887 11:28:07.898108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1889 11:28:07.987613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1890 11:28:07.988400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1892 11:28:08.078700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1893 11:28:08.079416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1895 11:28:08.170365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1896 11:28:08.171096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1898 11:28:08.262154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1899 11:28:08.262863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1901 11:28:08.352540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1902 11:28:08.353320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1904 11:28:08.436621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1905 11:28:08.437329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1907 11:28:08.528642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1908 11:28:08.529404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1910 11:28:08.621387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1911 11:28:08.622237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1913 11:28:08.712673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1914 11:28:08.713451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1916 11:28:08.802911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1917 11:28:08.803676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1919 11:28:08.893944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1920 11:28:08.894669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1922 11:28:08.984045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1923 11:28:08.984803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1925 11:28:09.074578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1926 11:28:09.075298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1928 11:28:09.165778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1929 11:28:09.166526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1931 11:28:09.251172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1932 11:28:09.251903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1934 11:28:09.343049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1935 11:28:09.343788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1937 11:28:09.435302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1938 11:28:09.436069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1940 11:28:09.524999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1941 11:28:09.525794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1943 11:28:09.615811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1944 11:28:09.616601 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1946 11:28:09.709496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1947 11:28:09.710135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1949 11:28:09.800966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1950 11:28:09.801621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1952 11:28:09.887090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1953 11:28:09.888083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1955 11:28:09.976703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1956 11:28:09.977559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1958 11:28:10.063388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1960 11:28:10.066718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1961 11:28:10.153264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1963 11:28:10.156445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1964 11:28:10.244503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1966 11:28:10.247679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1967 11:28:10.330629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1968 11:28:10.331461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1970 11:28:10.421174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1971 11:28:10.422002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1973 11:28:10.511339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1974 11:28:10.512159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1976 11:28:10.601698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1977 11:28:10.602569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1979 11:28:10.686921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1980 11:28:10.687753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1982 11:28:10.777095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1983 11:28:10.777914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1985 11:28:10.872348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1986 11:28:10.873181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1988 11:28:10.963435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1989 11:28:10.964286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1991 11:28:11.054360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1992 11:28:11.055191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1994 11:28:11.146434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1995 11:28:11.147260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1997 11:28:11.232485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1998 11:28:11.233302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2000 11:28:11.324450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2001 11:28:11.325279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2003 11:28:11.409915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2004 11:28:11.410728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2006 11:28:11.501915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2007 11:28:11.502746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2009 11:28:11.594231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
2010 11:28:11.595067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
2012 11:28:11.682974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
2013 11:28:11.683813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
2015 11:28:11.772358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2016 11:28:11.773208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2018 11:28:11.863084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2019 11:28:11.863900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2021 11:28:11.951097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2022 11:28:11.951915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2024 11:28:12.042391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2025 11:28:12.043206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2027 11:28:12.133621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2028 11:28:12.134482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2030 11:28:12.218841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2031 11:28:12.219686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2033 11:28:12.310759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2034 11:28:12.311617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2036 11:28:12.400934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2037 11:28:12.401756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2039 11:28:12.489399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2040 11:28:12.490220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2042 11:28:12.580353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2043 11:28:12.581194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2045 11:28:12.671071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2046 11:28:12.671917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2048 11:28:12.756341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2049 11:28:12.757187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2051 11:28:12.849706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2052 11:28:12.850546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2054 11:28:12.940534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2055 11:28:12.941362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2057 11:28:13.031732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2058 11:28:13.032615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2060 11:28:13.116058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2061 11:28:13.116897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2063 11:28:13.201164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2064 11:28:13.202013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2066 11:28:13.292097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2067 11:28:13.292935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2069 11:28:13.376107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2070 11:28:13.376937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2072 11:28:13.467685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2073 11:28:13.468566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2075 11:28:13.559897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2076 11:28:13.560766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2078 11:28:13.650254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2079 11:28:13.651126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2081 11:28:13.734721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2082 11:28:13.735557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2084 11:28:13.820353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2085 11:28:13.821194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2087 11:28:13.910593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2088 11:28:13.911426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2090 11:28:14.001386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2091 11:28:14.002229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2093 11:28:14.086262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2094 11:28:14.087101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2096 11:28:14.172576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2097 11:28:14.173419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2099 11:28:14.262763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2100 11:28:14.263602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2102 11:28:14.350110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2103 11:28:14.350950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2105 11:28:14.440100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2106 11:28:14.440946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2108 11:28:14.530021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2109 11:28:14.530873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2111 11:28:14.622176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2112 11:28:14.623028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2114 11:28:14.708116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2115 11:28:14.708958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2117 11:28:14.798655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2118 11:28:14.799487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2120 11:28:14.890457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2121 11:28:14.891298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2123 11:28:14.973326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2124 11:28:14.974161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2126 11:28:15.059817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2127 11:28:15.060691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2129 11:28:15.151467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2130 11:28:15.152321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2132 11:28:15.242230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
2133 11:28:15.243029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
2135 11:28:15.333079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
2136 11:28:15.333870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
2138 11:28:15.422436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
2139 11:28:15.423225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
2141 11:28:15.509052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
2142 11:28:15.509947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
2144 11:28:15.599001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
2145 11:28:15.599894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
2147 11:28:15.691469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
2148 11:28:15.692341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
2150 11:28:15.780771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
2151 11:28:15.781573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
2153 11:28:15.873576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
2154 11:28:15.874416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
2156 11:28:15.962655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2157 11:28:15.963468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2159 11:28:16.047603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2160 11:28:16.048426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2162 11:28:16.138726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2163 11:28:16.139510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2165 11:28:16.230868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2166 11:28:16.231649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2168 11:28:16.321074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2169 11:28:16.321856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2171 11:28:16.407854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2172 11:28:16.408683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2174 11:28:16.491039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2175 11:28:16.491811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2177 11:28:16.581603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2178 11:28:16.582403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2180 11:28:16.665874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2181 11:28:16.666652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2183 11:28:16.756575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2184 11:28:16.757355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2186 11:28:16.841344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2187 11:28:16.842121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2189 11:28:16.932824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2190 11:28:16.933602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2192 11:28:17.020590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2193 11:28:17.021362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2195 11:28:17.105845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2196 11:28:17.106618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2198 11:28:17.196323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2199 11:28:17.197101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2201 11:28:17.278903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2202 11:28:17.279676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2204 11:28:17.366148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2205 11:28:17.366923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2207 11:28:17.451316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2208 11:28:17.452120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2210 11:28:17.541938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2211 11:28:17.542708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2213 11:28:17.625908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2214 11:28:17.626701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2216 11:28:17.717773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2217 11:28:17.718551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2219 11:28:17.807484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2220 11:28:17.808308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2222 11:28:17.893364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2223 11:28:17.894149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2225 11:28:17.983509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2226 11:28:17.984324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2228 11:28:18.074459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2229 11:28:18.075238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2231 11:28:18.166752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2232 11:28:18.167544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2234 11:28:18.257956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2235 11:28:18.258736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2237 11:28:18.343836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2238 11:28:18.344665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2240 11:28:18.431948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2241 11:28:18.432756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2243 11:28:18.517303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2244 11:28:18.518116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2246 11:28:18.608383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2247 11:28:18.609183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2249 11:28:18.695418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2250 11:28:18.696199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2252 11:28:18.778707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2253 11:28:18.779482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2255 11:28:18.864360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2256 11:28:18.865143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2258 11:28:18.954249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2259 11:28:18.955031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2261 11:28:19.034530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2262 11:28:19.035305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2264 11:28:19.126290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2265 11:28:19.127083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2267 11:28:19.215451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2268 11:28:19.216231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2270 11:28:19.304988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2271 11:28:19.305763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2273 11:28:19.396409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2274 11:28:19.397185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2276 11:28:19.487940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2277 11:28:19.488776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2279 11:28:19.577431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2281 11:28:19.580584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2282 11:28:19.666729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2283 11:28:19.667514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2285 11:28:19.752921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2286 11:28:19.753694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2288 11:28:19.837153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2289 11:28:19.837935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2291 11:28:19.928108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2292 11:28:19.928886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2294 11:28:20.018123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2295 11:28:20.018898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2297 11:28:20.108122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2298 11:28:20.108913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2300 11:28:20.196937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2301 11:28:20.197717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2303 11:28:20.282313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2304 11:28:20.283086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2306 11:28:20.373260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2307 11:28:20.374029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2309 11:28:20.463168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2310 11:28:20.463937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2312 11:28:20.548019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2313 11:28:20.548796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2315 11:28:20.632125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2316 11:28:20.632917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2318 11:28:20.718051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2319 11:28:20.718827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2321 11:28:20.807972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2322 11:28:20.808779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2324 11:28:20.898469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2325 11:28:20.899243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2327 11:28:20.983039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2328 11:28:20.983846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2330 11:28:21.068512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2331 11:28:21.069326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2333 11:28:21.158419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2334 11:28:21.159247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2336 11:28:21.243117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2337 11:28:21.243961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2339 11:28:21.334752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2340 11:28:21.335663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2342 11:28:21.427568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2343 11:28:21.428455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2345 11:28:21.518554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2346 11:28:21.519437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2348 11:28:21.602822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2349 11:28:21.603733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2351 11:28:21.693578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2352 11:28:21.694457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2354 11:28:21.777160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2355 11:28:21.778043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2357 11:28:21.867840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2358 11:28:21.868767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2360 11:28:21.957275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2361 11:28:21.958120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2363 11:28:22.043377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2364 11:28:22.044227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2366 11:28:22.137993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2367 11:28:22.138871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2369 11:28:22.230201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2370 11:28:22.231039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2372 11:28:22.315463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2373 11:28:22.316092 + set +x
2374 11:28:22.316820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2376 11:28:22.325093 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 913245_1.6.2.4.5>
2377 11:28:22.325617 <LAVA_TEST_RUNNER EXIT>
2378 11:28:22.326327 Received signal: <ENDRUN> 1_kselftest-dt 913245_1.6.2.4.5
2379 11:28:22.326815 Ending use of test pattern.
2380 11:28:22.327261 Ending test lava.1_kselftest-dt (913245_1.6.2.4.5), duration 82.36
2382 11:28:22.328971 ok: lava_test_shell seems to have completed
2383 11:28:22.342967 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2384 11:28:22.345046 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2385 11:28:22.345681 end: 3 lava-test-retry (duration 00:01:24) [common]
2386 11:28:22.346306 start: 4 finalize (timeout 00:05:33) [common]
2387 11:28:22.346914 start: 4.1 power-off (timeout 00:00:30) [common]
2388 11:28:22.348024 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2389 11:28:22.384538 >> OK - accepted request
2390 11:28:22.386451 Returned 0 in 0 seconds
2391 11:28:22.487750 end: 4.1 power-off (duration 00:00:00) [common]
2393 11:28:22.489626 start: 4.2 read-feedback (timeout 00:05:32) [common]
2394 11:28:22.490780 Listened to connection for namespace 'common' for up to 1s
2395 11:28:23.491567 Finalising connection for namespace 'common'
2396 11:28:23.492417 Disconnecting from shell: Finalise
2397 11:28:23.492992 / #
2398 11:28:23.594104 end: 4.2 read-feedback (duration 00:00:01) [common]
2399 11:28:23.594966 end: 4 finalize (duration 00:00:01) [common]
2400 11:28:23.595704 Cleaning after the job
2401 11:28:23.596451 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/ramdisk
2402 11:28:23.606570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/kernel
2403 11:28:23.614070 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/dtb
2404 11:28:23.615548 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/nfsrootfs
2405 11:28:23.774356 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913245/tftp-deploy-yjcudzpf/modules
2406 11:28:23.784339 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/913245
2407 11:28:27.333915 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/913245
2408 11:28:27.334507 Job finished correctly