Boot log: beaglebone-black

    1 11:22:39.117330  lava-dispatcher, installed at version: 2023.08
    2 11:22:39.117736  start: 0 validate
    3 11:22:39.117974  Start time: 2024-10-30 11:22:39.117958+00:00 (UTC)
    4 11:22:39.118250  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
    5 11:22:39.447582  Validating that http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
    6 11:22:39.609273  Validating that http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
    7 11:22:39.771454  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
    8 11:22:39.934866  Validating that http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
    9 11:22:40.106308  validate duration: 0.99
   11 11:22:40.107412  start: 1 tftp-deploy (timeout 00:10:00) [common]
   12 11:22:40.107883  start: 1.1 download-retry (timeout 00:10:00) [common]
   13 11:22:40.108322  start: 1.1.1 http-download (timeout 00:10:00) [common]
   14 11:22:40.109082  Not decompressing ramdisk as can be used compressed.
   15 11:22:40.109521  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   16 11:22:40.109859  saving as /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/ramdisk/initrd.cpio.gz
   17 11:22:40.110207  total size: 4775763 (4 MB)
   18 11:22:40.438265  progress   0 % (0 MB)
   19 11:22:40.922566  progress   5 % (0 MB)
   20 11:22:41.117776  progress  10 % (0 MB)
   21 11:22:41.266371  progress  15 % (0 MB)
   22 11:22:41.279983  progress  20 % (0 MB)
   23 11:22:41.412047  progress  25 % (1 MB)
   24 11:22:41.439740  progress  30 % (1 MB)
   25 11:22:41.595163  progress  35 % (1 MB)
   26 11:22:41.745599  progress  40 % (1 MB)
   27 11:22:41.894195  progress  45 % (2 MB)
   28 11:22:41.921768  progress  50 % (2 MB)
   29 11:22:42.072743  progress  55 % (2 MB)
   30 11:22:42.220477  progress  60 % (2 MB)
   31 11:22:42.249731  progress  65 % (2 MB)
   32 11:22:42.397352  progress  70 % (3 MB)
   33 11:22:42.546288  progress  75 % (3 MB)
   34 11:22:42.571651  progress  80 % (3 MB)
   35 11:22:42.716400  progress  85 % (3 MB)
   36 11:22:42.865184  progress  90 % (4 MB)
   37 11:22:42.893073  progress  95 % (4 MB)
   38 11:22:43.062634  progress 100 % (4 MB)
   39 11:22:43.063684  4 MB downloaded in 2.95 s (1.54 MB/s)
   40 11:22:43.064382  end: 1.1.1 http-download (duration 00:00:03) [common]
   42 11:22:43.065568  end: 1.1 download-retry (duration 00:00:03) [common]
   43 11:22:43.065982  start: 1.2 download-retry (timeout 00:09:57) [common]
   44 11:22:43.066384  start: 1.2.1 http-download (timeout 00:09:57) [common]
   45 11:22:43.067031  downloading http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/kernel/zImage
   46 11:22:43.067346  saving as /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/kernel/zImage
   47 11:22:43.067647  total size: 11502080 (10 MB)
   48 11:22:43.067949  No compression specified
   49 11:22:43.234983  progress   0 % (0 MB)
   50 11:22:43.563961  progress   5 % (0 MB)
   51 11:22:44.050173  progress  10 % (1 MB)
   52 11:22:44.519211  progress  15 % (1 MB)
   53 11:22:44.863077  progress  20 % (2 MB)
   54 11:22:45.330586  progress  25 % (2 MB)
   55 11:22:45.672980  progress  30 % (3 MB)
   56 11:22:46.135507  progress  35 % (3 MB)
   57 11:22:46.477169  progress  40 % (4 MB)
   58 11:22:46.937843  progress  45 % (4 MB)
   59 11:22:47.280712  progress  50 % (5 MB)
   60 11:22:47.745248  progress  55 % (6 MB)
   61 11:22:48.084054  progress  60 % (6 MB)
   62 11:22:48.547732  progress  65 % (7 MB)
   63 11:22:48.888227  progress  70 % (7 MB)
   64 11:22:49.348053  progress  75 % (8 MB)
   65 11:22:49.685795  progress  80 % (8 MB)
   66 11:22:50.143778  progress  85 % (9 MB)
   67 11:22:50.479378  progress  90 % (9 MB)
   68 11:22:50.823019  progress  95 % (10 MB)
   69 11:22:51.173046  progress 100 % (10 MB)
   70 11:22:51.173964  10 MB downloaded in 8.11 s (1.35 MB/s)
   71 11:22:51.175959  end: 1.2.1 http-download (duration 00:00:08) [common]
   73 11:22:51.177423  end: 1.2 download-retry (duration 00:00:08) [common]
   74 11:22:51.177858  start: 1.3 download-retry (timeout 00:09:49) [common]
   75 11:22:51.178338  start: 1.3.1 http-download (timeout 00:09:49) [common]
   76 11:22:51.179268  downloading http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
   77 11:22:51.179584  saving as /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/dtb/am335x-boneblack.dtb
   78 11:22:51.179908  total size: 70544 (0 MB)
   79 11:22:51.180207  No compression specified
   80 11:22:51.350815  progress  46 % (0 MB)
   81 11:22:51.353704  progress  92 % (0 MB)
   82 11:22:51.354976  progress 100 % (0 MB)
   83 11:22:51.355511  0 MB downloaded in 0.18 s (0.38 MB/s)
   84 11:22:51.356101  end: 1.3.1 http-download (duration 00:00:00) [common]
   86 11:22:51.357219  end: 1.3 download-retry (duration 00:00:00) [common]
   87 11:22:51.357609  start: 1.4 download-retry (timeout 00:09:49) [common]
   88 11:22:51.358064  start: 1.4.1 http-download (timeout 00:09:49) [common]
   89 11:22:51.358597  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   90 11:22:51.358907  saving as /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/nfsrootfs/full.rootfs.tar
   91 11:22:51.359232  total size: 117747780 (112 MB)
   92 11:22:51.359578  Using unxz to decompress xz
   93 11:22:51.531784  progress   0 % (0 MB)
   94 11:22:57.972954  progress   5 % (5 MB)
   95 11:23:03.213217  progress  10 % (11 MB)
   96 11:23:05.564741  progress  15 % (16 MB)
   97 11:23:07.274163  progress  20 % (22 MB)
   98 11:23:08.933836  progress  25 % (28 MB)
   99 11:23:11.036512  progress  30 % (33 MB)
  100 11:23:13.476115  progress  35 % (39 MB)
  101 11:23:15.813257  progress  40 % (44 MB)
  102 11:23:18.097121  progress  45 % (50 MB)
  103 11:23:20.232541  progress  50 % (56 MB)
  104 11:23:22.444369  progress  55 % (61 MB)
  105 11:23:24.542947  progress  60 % (67 MB)
  106 11:23:26.408713  progress  65 % (73 MB)
  107 11:23:28.261521  progress  70 % (78 MB)
  108 11:23:30.361704  progress  75 % (84 MB)
  109 11:23:32.748853  progress  80 % (89 MB)
  110 11:23:36.004117  progress  85 % (95 MB)
  111 11:23:39.862038  progress  90 % (101 MB)
  112 11:23:43.446888  progress  95 % (106 MB)
  113 11:23:46.220616  progress 100 % (112 MB)
  114 11:23:46.222751  112 MB downloaded in 54.86 s (2.05 MB/s)
  115 11:23:46.223040  end: 1.4.1 http-download (duration 00:00:55) [common]
  117 11:23:46.223497  end: 1.4 download-retry (duration 00:00:55) [common]
  118 11:23:46.223657  start: 1.5 download-retry (timeout 00:08:54) [common]
  119 11:23:46.223815  start: 1.5.1 http-download (timeout 00:08:54) [common]
  120 11:23:46.224119  downloading http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
  121 11:23:46.224247  saving as /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/modules/modules.tar
  122 11:23:46.224365  total size: 6616988 (6 MB)
  123 11:23:46.224491  Using unxz to decompress xz
  124 11:23:46.389541  progress   0 % (0 MB)
  125 11:23:46.582327  progress   5 % (0 MB)
  126 11:23:46.605702  progress  10 % (0 MB)
  127 11:23:46.743098  progress  15 % (0 MB)
  128 11:23:46.905957  progress  20 % (1 MB)
  129 11:23:47.066816  progress  25 % (1 MB)
  130 11:23:47.226639  progress  30 % (1 MB)
  131 11:23:47.385172  progress  35 % (2 MB)
  132 11:23:47.543616  progress  40 % (2 MB)
  133 11:23:47.706939  progress  45 % (2 MB)
  134 11:23:47.864606  progress  50 % (3 MB)
  135 11:23:48.024495  progress  55 % (3 MB)
  136 11:23:48.176548  progress  60 % (3 MB)
  137 11:23:48.332084  progress  65 % (4 MB)
  138 11:23:48.487980  progress  70 % (4 MB)
  139 11:23:48.637938  progress  75 % (4 MB)
  140 11:23:48.679719  progress  80 % (5 MB)
  141 11:23:48.831853  progress  85 % (5 MB)
  142 11:23:48.982890  progress  90 % (5 MB)
  143 11:23:49.137197  progress  95 % (6 MB)
  144 11:23:49.324374  progress 100 % (6 MB)
  145 11:23:49.333852  6 MB downloaded in 3.11 s (2.03 MB/s)
  146 11:23:49.334138  end: 1.5.1 http-download (duration 00:00:03) [common]
  148 11:23:49.334594  end: 1.5 download-retry (duration 00:00:03) [common]
  149 11:23:49.334833  start: 1.6 prepare-tftp-overlay (timeout 00:08:51) [common]
  150 11:23:49.335083  start: 1.6.1 extract-nfsrootfs (timeout 00:08:51) [common]
  151 11:23:56.540596  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1213804/extract-nfsrootfs-z9lvv0_v
  152 11:23:56.540907  end: 1.6.1 extract-nfsrootfs (duration 00:00:07) [common]
  153 11:23:56.541057  start: 1.6.2 lava-overlay (timeout 00:08:44) [common]
  154 11:23:56.541361  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn
  155 11:23:56.541601  makedir: /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin
  156 11:23:56.541774  makedir: /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/tests
  157 11:23:56.541938  makedir: /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/results
  158 11:23:56.542097  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-add-keys
  159 11:23:56.542341  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-add-sources
  160 11:23:56.542557  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-background-process-start
  161 11:23:56.542776  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-background-process-stop
  162 11:23:56.543012  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-common-functions
  163 11:23:56.543231  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-echo-ipv4
  164 11:23:56.543447  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-install-packages
  165 11:23:56.543663  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-installed-packages
  166 11:23:56.543876  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-os-build
  167 11:23:56.544086  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-probe-channel
  168 11:23:56.544297  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-probe-ip
  169 11:23:56.544515  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-target-ip
  170 11:23:56.544725  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-target-mac
  171 11:23:56.545011  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-target-storage
  172 11:23:56.545229  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-test-case
  173 11:23:56.545442  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-test-event
  174 11:23:56.545649  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-test-feedback
  175 11:23:56.545857  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-test-raise
  176 11:23:56.546082  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-test-reference
  177 11:23:56.546297  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-test-runner
  178 11:23:56.546525  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-test-set
  179 11:23:56.546747  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-test-shell
  180 11:23:56.546962  Updating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-add-keys (debian)
  181 11:23:56.580184  Updating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-add-sources (debian)
  182 11:23:56.580548  Updating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-install-packages (debian)
  183 11:23:56.580876  Updating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-installed-packages (debian)
  184 11:23:56.581153  Updating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/bin/lava-os-build (debian)
  185 11:23:56.581365  Creating /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/environment
  186 11:23:56.581530  LAVA metadata
  187 11:23:56.581645  - LAVA_JOB_ID=1213804
  188 11:23:56.581755  - LAVA_DISPATCHER_IP=172.16.3.3
  189 11:23:56.581924  start: 1.6.2.1 ssh-authorize (timeout 00:08:44) [common]
  190 11:23:56.582357  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  191 11:23:56.582509  start: 1.6.2.2 lava-vland-overlay (timeout 00:08:44) [common]
  192 11:23:56.582615  skipped lava-vland-overlay
  193 11:23:56.582742  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  194 11:23:56.582875  start: 1.6.2.3 lava-multinode-overlay (timeout 00:08:44) [common]
  195 11:23:56.582985  skipped lava-multinode-overlay
  196 11:23:56.583112  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  197 11:23:56.583242  start: 1.6.2.4 test-definition (timeout 00:08:44) [common]
  198 11:23:56.583364  Loading test definitions
  199 11:23:56.583503  start: 1.6.2.4.1 inline-repo-action (timeout 00:08:44) [common]
  200 11:23:56.583614  Using /lava-1213804 at stage 0
  201 11:23:56.584169  uuid=1213804_1.6.2.4.1 testdef=None
  202 11:23:56.584325  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  203 11:23:56.584457  start: 1.6.2.4.2 test-overlay (timeout 00:08:44) [common]
  204 11:23:56.585241  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  206 11:23:56.585621  start: 1.6.2.4.3 test-install-overlay (timeout 00:08:44) [common]
  207 11:23:56.586539  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  209 11:23:56.586945  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:08:44) [common]
  210 11:23:56.603299  runner path: /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/0/tests/0_timesync-off test_uuid 1213804_1.6.2.4.1
  211 11:23:56.603578  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  213 11:23:56.603989  start: 1.6.2.4.5 git-repo-action (timeout 00:08:44) [common]
  214 11:23:56.604134  Using /lava-1213804 at stage 0
  215 11:23:56.604301  Fetching tests from https://github.com/kernelci/test-definitions.git
  216 11:23:56.604435  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/0/tests/1_kselftest-dt'
  217 11:24:04.437621  Running '/usr/bin/git checkout kernelci.org
  218 11:24:04.716918  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  219 11:24:04.718107  uuid=1213804_1.6.2.4.5 testdef=None
  220 11:24:04.718407  end: 1.6.2.4.5 git-repo-action (duration 00:00:08) [common]
  222 11:24:04.719068  start: 1.6.2.4.6 test-overlay (timeout 00:08:35) [common]
  223 11:24:04.721148  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  225 11:24:04.721842  start: 1.6.2.4.7 test-install-overlay (timeout 00:08:35) [common]
  226 11:24:04.724906  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  228 11:24:04.725560  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:08:35) [common]
  229 11:24:04.746562  runner path: /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/0/tests/1_kselftest-dt test_uuid 1213804_1.6.2.4.5
  230 11:24:04.746825  BOARD='beaglebone-black'
  231 11:24:04.747023  BRANCH='next'
  232 11:24:04.747216  SKIPFILE='/dev/null'
  233 11:24:04.747409  SKIP_INSTALL='True'
  234 11:24:04.747595  TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
  235 11:24:04.747783  TST_CASENAME=''
  236 11:24:04.747963  TST_CMDFILES='dt'
  237 11:24:04.748400  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  239 11:24:04.748986  Creating lava-test-runner.conf files
  240 11:24:04.749164  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1213804/lava-overlay-6_3s18cn/lava-1213804/0 for stage 0
  241 11:24:04.749450  - 0_timesync-off
  242 11:24:04.749649  - 1_kselftest-dt
  243 11:24:04.749944  end: 1.6.2.4 test-definition (duration 00:00:08) [common]
  244 11:24:04.750195  start: 1.6.2.5 compress-overlay (timeout 00:08:35) [common]
  245 11:24:14.271652  end: 1.6.2.5 compress-overlay (duration 00:00:10) [common]
  246 11:24:14.271865  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:26) [common]
  247 11:24:14.272008  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  248 11:24:14.272154  end: 1.6.2 lava-overlay (duration 00:00:18) [common]
  249 11:24:14.272300  start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:26) [common]
  250 11:24:14.412355  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  251 11:24:14.412613  start: 1.6.4 extract-modules (timeout 00:08:26) [common]
  252 11:24:14.412739  extracting modules file /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1213804/extract-nfsrootfs-z9lvv0_v
  253 11:24:14.798604  extracting modules file /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1213804/extract-overlay-ramdisk-w6__85p_/ramdisk
  254 11:24:15.181114  end: 1.6.4 extract-modules (duration 00:00:01) [common]
  255 11:24:15.181376  start: 1.6.5 apply-overlay-tftp (timeout 00:08:25) [common]
  256 11:24:15.181505  [common] Applying overlay to NFS
  257 11:24:15.181613  [common] Applying overlay /var/lib/lava/dispatcher/tmp/1213804/compress-overlay-a1iqoh49/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1213804/extract-nfsrootfs-z9lvv0_v
  258 11:24:16.492654  end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
  259 11:24:16.492921  start: 1.6.6 prepare-kernel (timeout 00:08:24) [common]
  260 11:24:16.493061  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:24) [common]
  261 11:24:16.493204  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  262 11:24:16.493335  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  263 11:24:16.493469  start: 1.6.7 configure-preseed-file (timeout 00:08:24) [common]
  264 11:24:16.493597  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  265 11:24:16.493727  start: 1.6.8 compress-ramdisk (timeout 00:08:24) [common]
  266 11:24:16.493837  Building ramdisk /var/lib/lava/dispatcher/tmp/1213804/extract-overlay-ramdisk-w6__85p_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1213804/extract-overlay-ramdisk-w6__85p_/ramdisk
  267 11:24:16.786419  >> 75293 blocks

  268 11:24:18.885855  Adding RAMdisk u-boot header.
  269 11:24:18.886187  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1213804/extract-overlay-ramdisk-w6__85p_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1213804/extract-overlay-ramdisk-w6__85p_/ramdisk.cpio.gz.uboot
  270 11:24:19.200912  output: Image Name:   
  271 11:24:19.201342  output: Created:      Wed Oct 30 11:24:18 2024
  272 11:24:19.201660  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  273 11:24:19.201964  output: Data Size:    14832654 Bytes = 14485.01 KiB = 14.15 MiB
  274 11:24:19.202257  output: Load Address: 00000000
  275 11:24:19.202543  output: Entry Point:  00000000
  276 11:24:19.202831  output: 
  277 11:24:19.203309  rename /var/lib/lava/dispatcher/tmp/1213804/extract-overlay-ramdisk-w6__85p_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/ramdisk/ramdisk.cpio.gz.uboot
  278 11:24:19.203804  end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
  279 11:24:19.204209  end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
  280 11:24:19.204608  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:21) [common]
  281 11:24:19.204889  No LXC device requested
  282 11:24:19.205066  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  283 11:24:19.205455  start: 1.8 deploy-device-env (timeout 00:08:21) [common]
  284 11:24:19.205827  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  285 11:24:19.206126  Checking files for TFTP limit of 4294967296 bytes.
  286 11:24:19.208027  end: 1 tftp-deploy (duration 00:01:39) [common]
  287 11:24:19.208445  start: 2 uboot-action (timeout 00:05:00) [common]
  288 11:24:19.208852  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  289 11:24:19.209019  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  290 11:24:19.209398  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  291 11:24:19.209945  substitutions:
  292 11:24:19.210255  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  293 11:24:19.210550  - {DTB_ADDR}: 0x88000000
  294 11:24:19.210839  - {DTB}: 1213804/tftp-deploy-qte23qrv/dtb/am335x-boneblack.dtb
  295 11:24:19.211123  - {INITRD}: 1213804/tftp-deploy-qte23qrv/ramdisk/ramdisk.cpio.gz.uboot
  296 11:24:19.211407  - {KERNEL_ADDR}: 0x82000000
  297 11:24:19.211688  - {KERNEL}: 1213804/tftp-deploy-qte23qrv/kernel/zImage
  298 11:24:19.211966  - {LAVA_MAC}: None
  299 11:24:19.212258  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1213804/extract-nfsrootfs-z9lvv0_v
  300 11:24:19.212538  - {NFS_SERVER_IP}: 172.16.3.3
  301 11:24:19.212845  - {PRESEED_CONFIG}: None
  302 11:24:19.212967  - {PRESEED_LOCAL}: None
  303 11:24:19.213173  - {RAMDISK_ADDR}: 0x83000000
  304 11:24:19.213450  - {RAMDISK}: 1213804/tftp-deploy-qte23qrv/ramdisk/ramdisk.cpio.gz.uboot
  305 11:24:19.213727  - {ROOT_PART}: None
  306 11:24:19.214000  - {ROOT}: None
  307 11:24:19.214270  - {SERVER_IP}: 172.16.3.3
  308 11:24:19.214540  - {TEE_ADDR}: 0x83000000
  309 11:24:19.214810  - {TEE}: None
  310 11:24:19.215082  Parsed boot commands:
  311 11:24:19.215350  - setenv autoload no
  312 11:24:19.215622  - setenv initrd_high 0xffffffff
  313 11:24:19.215896  - setenv fdt_high 0xffffffff
  314 11:24:19.216166  - dhcp
  315 11:24:19.216433  - setenv serverip 172.16.3.3
  316 11:24:19.216702  - tftp 0x82000000 1213804/tftp-deploy-qte23qrv/kernel/zImage
  317 11:24:19.216913  - tftp 0x83000000 1213804/tftp-deploy-qte23qrv/ramdisk/ramdisk.cpio.gz.uboot
  318 11:24:19.217032  - setenv initrd_size ${filesize}
  319 11:24:19.217316  - tftp 0x88000000 1213804/tftp-deploy-qte23qrv/dtb/am335x-boneblack.dtb
  320 11:24:19.217585  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1213804/extract-nfsrootfs-z9lvv0_v,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  321 11:24:19.217871  - bootz 0x82000000 0x83000000 0x88000000
  322 11:24:19.218224  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  324 11:24:19.219225  start: 2.3 connect-device (timeout 00:05:00) [common]
  325 11:24:19.219519  [common] connect-device Connecting to device using 'telnet ts5 2000'
  326 11:24:19.226751  Setting prompt string to ['lava-test: # ']
  327 11:24:19.227221  end: 2.3 connect-device (duration 00:00:00) [common]
  328 11:24:19.227421  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  329 11:24:19.227608  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  330 11:24:19.227790  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  331 11:24:19.228076  Calling: 'drpm' 'lf-bbb' 'powercycle'
  332 11:24:19.502920  >> OFF

  333 11:24:34.848730  >> ON

  334 11:24:34.849572  Returned 0 in 15 seconds
  335 11:24:34.950309  end: 2.4.1.1 pdu-reboot (duration 00:00:16) [common]
  337 11:24:34.951460  end: 2.4.1 reset-device (duration 00:00:16) [common]
  338 11:24:34.951889  start: 2.4.2 bootloader-interrupt (timeout 00:04:44) [common]
  339 11:24:34.952283  Setting prompt string to ['Hit any key to stop autoboot']
  340 11:24:34.952627  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  341 11:24:34.953592  Trying 192.168.1.205...
  342 11:24:34.953910  Connected to ts5.
  343 11:24:34.954205  Escape character is '^]'.
  344 11:24:34.954493  
  345 11:24:34.954784  ser2net port telnet,2000 device serialdev,/dev/ttyUSB-lf-bbb-01,115200n81,local [] (Debian GNU/Linux)
  346 11:24:34.955082  
  347 11:24:35.684120  
  348 11:24:35.692146  U-Boot SPL 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  349 11:24:35.692546  Trying to boot from MMC2
  350 11:24:36.206859  
  351 11:24:36.207254  
  352 11:24:36.213131  U-Boot 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  353 11:24:36.213530  
  354 11:24:36.213854  CPU  : AM335X-GP rev 2.1
  355 11:24:36.219971  Model: TI AM335x BeagleBone Black
  356 11:24:36.220370  DRAM:  512 MiB
  357 11:24:36.301006  WDT:   Started with servicing (60s timeout)
  358 11:24:36.705914  NAND:  0 MiB
  359 11:24:36.716918  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  360 11:24:36.750557  Loading Environment from FAT... <ethaddr> not set. Validating first E-fuse MAC
  361 11:24:36.779958  Net:   eth2: ethernet@4a100000, eth3: usb_ether
  362 11:24:36.837531  end: 2.4.2 bootloader-interrupt (duration 00:00:02) [common]
  363 11:24:36.838027  start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
  364 11:24:36.838401  Setting prompt string to ['=> ']
  365 11:24:36.838768  bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:42)
  366 11:24:36.848043  Hit any key to stop autoboot:  2   0 
  367 11:24:36.848828  Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  368 11:24:36.849221  Sending with 10 millisecond of delay
  370 11:24:37.985731  => setenv autoload no
  371 11:24:37.996283  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:41)
  372 11:24:37.999364  setenv autoload no
  373 11:24:37.999965  Sending with 10 millisecond of delay
  375 11:24:39.800018  => setenv initrd_high 0xffffffff
  376 11:24:39.810566  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:39)
  377 11:24:39.811188  setenv initrd_high 0xffffffff
  378 11:24:39.811750  Sending with 10 millisecond of delay
  380 11:24:41.430439  => setenv fdt_high 0xffffffff
  381 11:24:41.441143  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  382 11:24:41.441793  setenv fdt_high 0xffffffff
  383 11:24:41.442370  Sending with 10 millisecond of delay
  385 11:24:41.734415  => dhcp
  386 11:24:41.744959  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
  387 11:24:41.746506  dhcp
  388 11:24:41.746885  link up on port 0, speed 100, full duplex
  389 11:24:41.747197  BOOTP broadcast 1
  390 11:24:41.798990  DHCP client bound to address 172.16.3.208 (47 ms)
  391 11:24:41.799613  Sending with 10 millisecond of delay
  393 11:24:43.418785  => setenv serverip 172.16.3.3
  394 11:24:43.429381  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:36)
  395 11:24:43.430018  setenv serverip 172.16.3.3
  396 11:24:43.430586  Sending with 10 millisecond of delay
  398 11:24:46.979387  => tftp 0x82000000 1213804/tftp-deploy-qte23qrv/kernel/zImage
  399 11:24:46.990090  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
  400 11:24:46.991264  tftp 0x82000000 1213804/tftp-deploy-qte23qrv/kernel/zImage
  401 11:24:46.991596  link up on port 0, speed 100, full duplex
  402 11:24:46.996419  Using ethernet@4a100000 device
  403 11:24:47.002282  TFTP from server 172.16.3.3; our IP address is 172.16.3.208
  404 11:24:47.009035  Filename '1213804/tftp-deploy-qte23qrv/kernel/zImage'.
  405 11:24:47.009419  Load address: 0x82000000
  406 11:24:49.309340  Loading: *##################################################  11 MiB
  407 11:24:49.309739  	 4.8 MiB/s
  408 11:24:49.310048  done
  409 11:24:49.313558  Bytes transferred = 11502080 (af8200 hex)
  410 11:24:49.314195  Sending with 10 millisecond of delay
  412 11:24:53.827170  => tftp 0x83000000 1213804/tftp-deploy-qte23qrv/ramdisk/ramdisk.cpio.gz.uboot
  413 11:24:53.837868  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:25)
  414 11:24:53.838599  tftp 0x83000000 1213804/tftp-deploy-qte23qrv/ramdisk/ramdisk.cpio.gz.uboot
  415 11:24:53.838932  link up on port 0, speed 100, full duplex
  416 11:24:53.843859  Using ethernet@4a100000 device
  417 11:24:53.849963  TFTP from server 172.16.3.3; our IP address is 172.16.3.208
  418 11:24:53.857811  Filename '1213804/tftp-deploy-qte23qrv/ramdisk/ramdisk.cpio.gz.uboot'.
  419 11:24:53.858143  Load address: 0x83000000
  420 11:24:57.230568  Loading: *##################################################  14.1 MiB
  421 11:24:57.230988  	 4.2 MiB/s
  422 11:24:57.231300  done
  423 11:24:57.235635  Bytes transferred = 14832718 (e2544e hex)
  424 11:24:57.236286  Sending with 10 millisecond of delay
  426 11:24:59.096425  => setenv initrd_size ${filesize}
  427 11:24:59.107044  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:20)
  428 11:24:59.107665  setenv initrd_size ${filesize}
  429 11:24:59.108223  Sending with 10 millisecond of delay
  431 11:25:03.320761  => tftp 0x88000000 1213804/tftp-deploy-qte23qrv/dtb/am335x-boneblack.dtb
  432 11:25:03.331376  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:16)
  433 11:25:03.331990  tftp 0x88000000 1213804/tftp-deploy-qte23qrv/dtb/am335x-boneblack.dtb
  434 11:25:03.332318  link up on port 0, speed 100, full duplex
  435 11:25:03.338331  Using ethernet@4a100000 device
  436 11:25:03.343195  TFTP from server 172.16.3.3; our IP address is 172.16.3.208
  437 11:25:03.353900  Filename '1213804/tftp-deploy-qte23qrv/dtb/am335x-boneblack.dtb'.
  438 11:25:03.354104  Load address: 0x88000000
  439 11:25:03.366203  Loading: *##################################################  68.9 KiB
  440 11:25:03.366585  	 4.2 MiB/s
  441 11:25:03.375433  done
  442 11:25:03.375816  Bytes transferred = 70544 (11390 hex)
  443 11:25:03.376385  Sending with 10 millisecond of delay
  445 11:25:16.753331  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1213804/extract-nfsrootfs-z9lvv0_v,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  446 11:25:16.764004  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:02)
  447 11:25:16.764644  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1213804/extract-nfsrootfs-z9lvv0_v,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  448 11:25:16.765278  Sending with 10 millisecond of delay
  450 11:25:19.106260  => bootz 0x82000000 0x83000000 0x88000000
  451 11:25:19.116923  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  452 11:25:19.117352  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:00)
  453 11:25:19.118187  bootz 0x82000000 0x83000000 0x88000000
  454 11:25:19.118553  Kernel image @ 0x82000000 [ 0x000000 - 0xaf8200 ]
  455 11:25:19.121356  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  456 11:25:19.125132     Image Name:   
  457 11:25:19.125479     Created:      2024-10-30  11:24:18 UTC
  458 11:25:19.134927     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  459 11:25:19.135280     Data Size:    14832654 Bytes = 14.1 MiB
  460 11:25:19.142939     Load Address: 00000000
  461 11:25:19.143287     Entry Point:  00000000
  462 11:25:19.311983     Verifying Checksum ... OK
  463 11:25:19.312358  ## Flattened Device Tree blob at 88000000
  464 11:25:19.318360     Booting using the fdt blob at 0x88000000
  465 11:25:19.323845     Using Device Tree in place at 88000000, end 8801438f
  466 11:25:19.336987  
  467 11:25:19.337345  Starting kernel ...
  468 11:25:19.337687  
  469 11:25:19.338439  end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
  470 11:25:19.338913  start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
  471 11:25:19.339299  Setting prompt string to ['Linux version [0-9]']
  472 11:25:19.339698  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  473 11:25:19.340093  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
  474 11:25:20.184719  [    0.000000] Booting Linux on physical CPU 0x0
  475 11:25:20.191035  start: 2.4.4.1 login-action (timeout 00:03:59) [common]
  476 11:25:20.191470  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  477 11:25:20.191826  Setting prompt string to []
  478 11:25:20.192183  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  479 11:25:20.192525  Using line separator: #'\n'#
  480 11:25:20.192859  No login prompt set.
  481 11:25:20.193177  Parsing kernel messages
  482 11:25:20.193460  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  483 11:25:20.194033  [login-action] Waiting for messages, (timeout 00:03:59)
  484 11:25:20.210146  [    0.000000] Linux version 6.12.0-rc5-next-20241030 (KernelCI@build-j357063-arm-gcc-12-multi-v7-defconfig-gp9k8) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Wed Oct 30 10:53:25 UTC 2024
  485 11:25:20.216409  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  486 11:25:20.224893  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  487 11:25:20.231016  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  488 11:25:20.236913  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  489 11:25:20.240761  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  490 11:25:20.245728  [    0.000000] Memory policy: Data cache writeback
  491 11:25:20.253088  [    0.000000] efi: UEFI not found.
  492 11:25:20.253480  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  493 11:25:20.261624  [    0.000000] Zone ranges:
  494 11:25:20.266536  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  495 11:25:20.272714  [    0.000000]   Normal   empty
  496 11:25:20.272958  [    0.000000]   HighMem  empty
  497 11:25:20.275934  [    0.000000] Movable zone start for each node
  498 11:25:20.281163  [    0.000000] Early memory node ranges
  499 11:25:20.287446  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  500 11:25:20.295332  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  501 11:25:20.315657  [    0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
  502 11:25:20.329287  [    0.000000] CPU: All CPU(s) started in SVC mode.
  503 11:25:20.337968  [    0.000000] AM335X ES2.1 (sgx neon)
  504 11:25:20.342710  [    0.000000] percpu: Embedded 17 pages/cpu s40396 r8192 d21044 u69632
  505 11:25:20.363015  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1213804/extract-nfsrootfs-z9lvv0_v,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  506 11:25:20.374582  <6>[    0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
  507 11:25:20.380664  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  508 11:25:20.389429  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  509 11:25:20.395464  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  510 11:25:20.404968  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  511 11:25:20.435423  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  512 11:25:20.440245  <6>[    0.000000] trace event string verifier disabled
  513 11:25:20.440631  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  514 11:25:20.447705  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  515 11:25:20.453841  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  516 11:25:20.459975  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.
  517 11:25:20.468383  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  518 11:25:20.474588  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  519 11:25:20.484318  <6>[    0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
  520 11:25:20.501138  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  521 11:25:20.517969  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  522 11:25:20.524680  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  523 11:25:20.616386  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  524 11:25:20.624974  <6>[    0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  525 11:25:20.637202  <6>[    0.008340] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  526 11:25:20.645796  <6>[    0.019148] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  527 11:25:20.655400  <6>[    0.033962] Console: colour dummy device 80x30
  528 11:25:20.661813  Matched prompt #6: WARNING:
  529 11:25:20.662213  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  530 11:25:20.666458  <3>[    0.038860] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  531 11:25:20.669971  <3>[    0.045928] This ensures that you still see kernel messages. Please
  532 11:25:20.674486  <3>[    0.052658] update your kernel commandline.
  533 11:25:20.716404  <6>[    0.057273] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  534 11:25:20.721419  <6>[    0.096151] CPU: Testing write buffer coherency: ok
  535 11:25:20.724949  <6>[    0.101520] CPU0: Spectre v2: using BPIALL workaround
  536 11:25:20.730046  <6>[    0.106988] pid_max: default: 32768 minimum: 301
  537 11:25:20.736150  <6>[    0.112186] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  538 11:25:20.745742  <6>[    0.120010] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  539 11:25:20.753164  <6>[    0.129395] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  540 11:25:20.766406  <6>[    0.136574] Setting up static identity map for 0x80300000 - 0x803000ac
  541 11:25:20.771574  <6>[    0.146226] rcu: Hierarchical SRCU implementation.
  542 11:25:20.774939  <6>[    0.151509] rcu: 	Max phase no-delay instances is 1000.
  543 11:25:20.784426  <6>[    0.162615] EFI services will not be available.
  544 11:25:20.789410  <6>[    0.167904] smp: Bringing up secondary CPUs ...
  545 11:25:20.795455  <6>[    0.172950] smp: Brought up 1 node, 1 CPU
  546 11:25:20.802825  <6>[    0.177349] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  547 11:25:20.808926  <6>[    0.184117] CPU: All CPU(s) started in SVC mode.
  548 11:25:20.826434  <6>[    0.189304] Memory: 405956K/522240K available (16384K kernel code, 2543K rwdata, 6824K rodata, 2048K init, 426K bss, 49088K reserved, 65536K cma-reserved, 0K highmem)
  549 11:25:20.826835  <6>[    0.205609] devtmpfs: initialized
  550 11:25:20.849511  <6>[    0.222935] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  551 11:25:20.857931  <6>[    0.231519] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  552 11:25:20.867367  <6>[    0.241974] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  553 11:25:20.877102  <6>[    0.254291] pinctrl core: initialized pinctrl subsystem
  554 11:25:20.887737  <6>[    0.264956] DMI not present or invalid.
  555 11:25:20.894465  <6>[    0.270853] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  556 11:25:20.905247  <6>[    0.279851] DMA: preallocated 256 KiB pool for atomic coherent allocations
  557 11:25:20.919258  <6>[    0.291360] thermal_sys: Registered thermal governor 'step_wise'
  558 11:25:20.919456  <6>[    0.291528] cpuidle: using governor menu
  559 11:25:20.947783  <6>[    0.326907] No ATAGs?
  560 11:25:20.953287  <6>[    0.329644] hw-breakpoint: debug architecture 0x4 unsupported.
  561 11:25:20.963971  <6>[    0.341614] Serial: AMBA PL011 UART driver
  562 11:25:20.995674  <6>[    0.374951] iommu: Default domain type: Translated
  563 11:25:21.005160  <6>[    0.380292] iommu: DMA domain TLB invalidation policy: strict mode
  564 11:25:21.032680  <5>[    0.410784] SCSI subsystem initialized
  565 11:25:21.037756  <6>[    0.415694] usbcore: registered new interface driver usbfs
  566 11:25:21.043882  <6>[    0.421721] usbcore: registered new interface driver hub
  567 11:25:21.051423  <6>[    0.427501] usbcore: registered new device driver usb
  568 11:25:21.057623  <6>[    0.434012] pps_core: LinuxPPS API ver. 1 registered
  569 11:25:21.070158  <6>[    0.439446] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  570 11:25:21.070564  <6>[    0.449128] PTP clock support registered
  571 11:25:21.074427  <6>[    0.453591] EDAC MC: Ver: 3.0.0
  572 11:25:21.125205  <6>[    0.501759] scmi_core: SCMI protocol bus registered
  573 11:25:21.141290  <6>[    0.519184] vgaarb: loaded
  574 11:25:21.146803  <6>[    0.523040] clocksource: Switched to clocksource dmtimer
  575 11:25:21.180677  <6>[    0.559676] NET: Registered PF_INET protocol family
  576 11:25:21.193197  <6>[    0.565395] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  577 11:25:21.200588  <6>[    0.574253] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  578 11:25:21.206862  <6>[    0.583180] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  579 11:25:21.216741  <6>[    0.591422] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  580 11:25:21.228155  <6>[    0.599708] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  581 11:25:21.233293  <6>[    0.607423] TCP: Hash tables configured (established 4096 bind 4096)
  582 11:25:21.239378  <6>[    0.614348] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  583 11:25:21.244421  <6>[    0.621358] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  584 11:25:21.252597  <6>[    0.628980] NET: Registered PF_UNIX/PF_LOCAL protocol family
  585 11:25:21.340012  <6>[    0.713086] RPC: Registered named UNIX socket transport module.
  586 11:25:21.340406  <6>[    0.719473] RPC: Registered udp transport module.
  587 11:25:21.345076  <6>[    0.724602] RPC: Registered tcp transport module.
  588 11:25:21.353674  <6>[    0.729708] RPC: Registered tcp-with-tls transport module.
  589 11:25:21.359708  <6>[    0.735639] RPC: Registered tcp NFSv4.1 backchannel transport module.
  590 11:25:21.367280  <6>[    0.742544] PCI: CLS 0 bytes, default 64
  591 11:25:21.370495  <5>[    0.748349] Initialise system trusted keyrings
  592 11:25:21.392617  <6>[    0.768622] Trying to unpack rootfs image as initramfs...
  593 11:25:21.474813  <6>[    0.847205] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  594 11:25:21.479127  <6>[    0.854759] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  595 11:25:21.510920  <5>[    0.890102] NFS: Registering the id_resolver key type
  596 11:25:21.517076  <5>[    0.895786] Key type id_resolver registered
  597 11:25:21.523420  <5>[    0.900368] Key type id_legacy registered
  598 11:25:21.530926  <6>[    0.904844] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  599 11:25:21.537576  <6>[    0.912011] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  600 11:25:21.610471  <5>[    0.989951] Key type asymmetric registered
  601 11:25:21.616676  <5>[    0.994518] Asymmetric key parser 'x509' registered
  602 11:25:21.625143  <6>[    0.999946] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  603 11:25:21.630278  <6>[    1.007875] io scheduler mq-deadline registered
  604 11:25:21.635302  <6>[    1.012804] io scheduler kyber registered
  605 11:25:21.639582  <6>[    1.017292] io scheduler bfq registered
  606 11:25:21.737698  <6>[    1.113435] ledtrig-cpu: registered to indicate activity on CPUs
  607 11:25:22.014270  <6>[    1.388985] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  608 11:25:22.049496  <6>[    1.427790] msm_serial: driver initialized
  609 11:25:22.055486  <6>[    1.432579] SuperH (H)SCI(F) driver initialized
  610 11:25:22.060369  <6>[    1.437934] STMicroelectronics ASC driver initialized
  611 11:25:22.066090  <6>[    1.443611] STM32 USART driver initialized
  612 11:25:22.186922  <6>[    1.565644] brd: module loaded
  613 11:25:22.227662  <6>[    1.606731] loop: module loaded
  614 11:25:22.277363  <6>[    1.655282] CAN device driver interface
  615 11:25:22.283593  <6>[    1.660341] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  616 11:25:22.288613  <6>[    1.667435] e1000e: Intel(R) PRO/1000 Network Driver
  617 11:25:22.296123  <6>[    1.672823] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  618 11:25:22.302231  <6>[    1.679303] igb: Intel(R) Gigabit Ethernet Network Driver
  619 11:25:22.308956  <6>[    1.685149] igb: Copyright (c) 2007-2014 Intel Corporation.
  620 11:25:22.320411  <6>[    1.694741] pegasus: Pegasus/Pegasus II USB Ethernet driver
  621 11:25:22.326671  <6>[    1.700814] usbcore: registered new interface driver pegasus
  622 11:25:22.330145  <6>[    1.707020] usbcore: registered new interface driver asix
  623 11:25:22.335299  <6>[    1.712876] usbcore: registered new interface driver ax88179_178a
  624 11:25:22.340259  <6>[    1.719472] usbcore: registered new interface driver cdc_ether
  625 11:25:22.351262  <6>[    1.725791] usbcore: registered new interface driver smsc75xx
  626 11:25:22.356420  <6>[    1.731999] usbcore: registered new interface driver smsc95xx
  627 11:25:22.363931  <6>[    1.738227] usbcore: registered new interface driver net1080
  628 11:25:22.367450  <6>[    1.744373] usbcore: registered new interface driver cdc_subset
  629 11:25:22.373666  <6>[    1.750763] usbcore: registered new interface driver zaurus
  630 11:25:22.380578  <6>[    1.756832] usbcore: registered new interface driver cdc_ncm
  631 11:25:22.391659  <6>[    1.766566] usbcore: registered new interface driver usb-storage
  632 11:25:22.400872  <6>[    1.778073] i2c_dev: i2c /dev entries driver
  633 11:25:22.427443  <5>[    1.798196] cpuidle: enable-method property 'ti,am3352' found operations
  634 11:25:22.432411  <6>[    1.807758] sdhci: Secure Digital Host Controller Interface driver
  635 11:25:22.440901  <6>[    1.814529] sdhci: Copyright(c) Pierre Ossman
  636 11:25:22.448416  <6>[    1.821111] Synopsys Designware Multimedia Card Interface Driver
  637 11:25:22.453904  <6>[    1.829296] sdhci-pltfm: SDHCI platform and OF driver helper
  638 11:25:22.468422  <6>[    1.839487] usbcore: registered new interface driver usbhid
  639 11:25:22.468858  <6>[    1.845604] usbhid: USB HID core driver
  640 11:25:22.481252  <6>[    1.857843] NET: Registered PF_INET6 protocol family
  641 11:25:22.944504  <6>[    2.323926] Segment Routing with IPv6
  642 11:25:22.950500  <6>[    2.328077] In-situ OAM (IOAM) with IPv6
  643 11:25:22.957847  <6>[    2.332470] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  644 11:25:22.962711  <6>[    2.339882] NET: Registered PF_PACKET protocol family
  645 11:25:22.968876  <6>[    2.345456] can: controller area network core
  646 11:25:22.975094  <6>[    2.350281] NET: Registered PF_CAN protocol family
  647 11:25:22.975474  <6>[    2.355512] can: raw protocol
  648 11:25:22.981187  <6>[    2.358834] can: broadcast manager protocol
  649 11:25:22.987367  <6>[    2.363430] can: netlink gateway - max_hops=1
  650 11:25:22.992436  <5>[    2.368953] Key type dns_resolver registered
  651 11:25:22.999862  <6>[    2.374024] ThumbEE CPU extension supported.
  652 11:25:23.000243  <5>[    2.378717] Registering SWP/SWPB emulation handler
  653 11:25:23.008999  <3>[    2.384414] omap_voltage_late_init: Voltage driver support not added
  654 11:25:23.207468  <5>[    2.583602] Loading compiled-in X.509 certificates
  655 11:25:23.345293  <6>[    2.712067] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  656 11:25:23.353308  <6>[    2.728755] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  657 11:25:23.378968  <3>[    2.752396] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  658 11:25:23.584092  <3>[    2.957476] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  659 11:25:23.786438  <6>[    3.163919] OMAP GPIO hardware version 0.1
  660 11:25:23.806566  <6>[    3.182430] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  661 11:25:23.890881  <4>[    3.265778] at24 2-0054: supply vcc not found, using dummy regulator
  662 11:25:23.929245  <4>[    3.304601] at24 2-0055: supply vcc not found, using dummy regulator
  663 11:25:23.964240  <4>[    3.339096] at24 2-0056: supply vcc not found, using dummy regulator
  664 11:25:24.006533  <4>[    3.381114] at24 2-0057: supply vcc not found, using dummy regulator
  665 11:25:24.042526  <6>[    3.418456] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  666 11:25:24.116819  <3>[    3.489025] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  667 11:25:24.142139  <6>[    3.509799] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  668 11:25:24.164417  <4>[    3.536093] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  669 11:25:24.171432  <4>[    3.545381] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  670 11:25:24.327499  <6>[    3.703766] omap_rng 48310000.rng: Random Number Generator ver. 20
  671 11:25:24.352441  <5>[    3.729909] random: crng init done
  672 11:25:24.399376  <6>[    3.773344] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  673 11:25:24.451959  <6>[    3.829024] Freeing initrd memory: 14488K
  674 11:25:24.498392  <6>[    3.871144] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  675 11:25:24.504412  <6>[    3.881502] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  676 11:25:24.513058  <6>[    3.888864] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  677 11:25:24.523914  <6>[    3.896371] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  678 11:25:24.532648  <6>[    3.904509] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  679 11:25:24.541099  <6>[    3.916143] cpsw-switch 4a100000.switch: Detected MACID = 34:03:de:5e:2c:05
  680 11:25:24.554067  <5>[    3.925193] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  681 11:25:24.581250  <3>[    3.955010] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  682 11:25:24.586844  <6>[    3.963544] edma 49000000.dma: TI EDMA DMA engine driver
  683 11:25:24.657973  <3>[    4.031123] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  684 11:25:24.674401  <6>[    4.045849] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  685 11:25:24.685967  <3>[    4.062906] l3-aon-clkctrl:0000:0: failed to disable
  686 11:25:24.731305  <6>[    4.104212] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  687 11:25:24.738655  <6>[    4.113671] printk: legacy console [ttyS0] enabled
  688 11:25:24.739050  <6>[    4.113671] printk: legacy console [ttyS0] enabled
  689 11:25:24.744905  <6>[    4.124007] printk: legacy bootconsole [omap8250] disabled
  690 11:25:24.754146  <6>[    4.124007] printk: legacy bootconsole [omap8250] disabled
  691 11:25:24.792027  <4>[    4.163808] tps65217-pmic: Failed to locate of_node [id: -1]
  692 11:25:24.795254  <4>[    4.171192] tps65217-bl: Failed to locate of_node [id: -1]
  693 11:25:24.812268  <6>[    4.190852] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  694 11:25:24.829117  <6>[    4.197823] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  695 11:25:24.841395  <6>[    4.211556] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  696 11:25:24.847084  <6>[    4.223437] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  697 11:25:24.869831  <6>[    4.244008] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  698 11:25:24.875641  <6>[    4.253157] sdhci-omap 48060000.mmc: Got CD GPIO
  699 11:25:24.883641  <4>[    4.258279] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  700 11:25:24.898526  <4>[    4.271470] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  701 11:25:24.904607  <4>[    4.280427] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  702 11:25:24.915082  <4>[    4.289285] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  703 11:25:25.038638  <6>[    4.413449] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  704 11:25:25.086403  <6>[    4.460234] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  705 11:25:25.121059  <6>[    4.494017] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  706 11:25:25.127707  <6>[    4.502700] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  707 11:25:25.193997  <6>[    4.563481] mmc1: new high speed MMC card at address 0001
  708 11:25:25.194382  <6>[    4.571529] mmcblk1: mmc1:0001 M62704 3.56 GiB
  709 11:25:25.205783  <6>[    4.584232]  mmcblk1: p1
  710 11:25:25.219024  <6>[    4.587946] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  711 11:25:25.223432  <6>[    4.601087] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
  712 11:25:25.238404  <6>[    4.616325] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
  713 11:25:25.247759  <6>[    4.623957] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
  714 11:25:27.311348  <6>[    6.684099] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  715 11:25:27.413699  <5>[    6.713060] Sending DHCP requests ., OK
  716 11:25:27.424949  <6>[    6.797479] IP-Config: Got DHCP answer from 172.16.3.3, my address is 172.16.3.208
  717 11:25:27.425332  <6>[    6.805566] IP-Config: Complete:
  718 11:25:27.439573  <6>[    6.809104]      device=eth0, hwaddr=34:03:de:5e:2c:05, ipaddr=172.16.3.208, mask=255.255.255.0, gw=172.16.3.3
  719 11:25:27.444446  <6>[    6.819530]      host=172.16.3.208, domain=denx.de, nis-domain=(none)
  720 11:25:27.450524  <6>[    6.826354]      bootserver=172.16.3.33, rootserver=172.16.3.3, rootpath=
  721 11:25:27.458070  <6>[    6.826389]      nameserver0=172.16.3.3
  722 11:25:27.458450  <6>[    6.837697]      ntpserver0=172.16.3.3
  723 11:25:27.464188  <6>[    6.843268] clk: Disabling unused clocks
  724 11:25:27.470890  <6>[    6.847876] PM: genpd: Disabling unused power domains
  725 11:25:27.498253  <6>[    6.866679] Freeing unused kernel image (initmem) memory: 2048K
  726 11:25:27.498638  <6>[    6.876474] Run /init as init process
  727 11:25:27.520901  Loading, please wait...
  728 11:25:27.596650  Starting systemd-udevd version 252.22-1~deb12u1
  729 11:25:30.850017  <4>[   10.221629] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  730 11:25:30.982481  <4>[   10.354695] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  731 11:25:31.171182  <6>[   10.552026] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  732 11:25:31.182836  <6>[   10.557856] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  733 11:25:31.209218  <6>[   10.586416] tda998x 0-0070: found TDA19988
  734 11:25:31.496064  <6>[   10.873624] hub 1-0:1.0: USB hub found
  735 11:25:31.505292  <6>[   10.883459] hub 1-0:1.0: 1 port detected
  736 11:25:34.119551  Begin: Loading essential drivers ... done.
  737 11:25:34.124394  Begin: Running /scripts/init-premount ... done.
  738 11:25:34.130530  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  739 11:25:34.139064  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  740 11:25:34.144576  Device /sys/class/net/eth0 found
  741 11:25:34.144982  done.
  742 11:25:34.229398  Begin: Waiting up to 180 secs for any network device to become available ... done.
  743 11:25:34.326639  IP-Config: eth0 hardware address 34:03:de:5e:2c:05 mtu 1500 DHCP
  744 11:25:34.399318  IP-Config: eth0 complete (dhcp from 172.16.3.3):
  745 11:25:34.410314   address: 172.16.3.208     broadcast: 172.16.3.255     netmask: 255.255.255.0   
  746 11:25:34.415200   gateway: 172.16.3.3       dns0     : 172.16.3.3       dns1   : 0.0.0.0         
  747 11:25:34.419873   domain : denx.de                                                         
  748 11:25:34.424992   rootserver: 172.16.3.33 rootpath: 
  749 11:25:34.429237   filename  : this-host-is-not-configured.kpxe
  750 11:25:34.464537  done.
  751 11:25:34.475082  Begin: Running /scripts/nfs-bottom ... done.
  752 11:25:34.546217  Begin: Running /scripts/init-bottom ... done.
  753 11:25:35.864486  <30>[   15.240556] systemd[1]: System time before build time, advancing clock.
  754 11:25:36.022200  <30>[   15.372528] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  755 11:25:36.031560  <30>[   15.409395] systemd[1]: Detected architecture arm.
  756 11:25:36.104575  
  757 11:25:36.104994  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  758 11:25:36.105311  
  759 11:25:36.137223  <30>[   15.513243] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  760 11:25:38.376949  <30>[   17.752309] systemd[1]: Queued start job for default target graphical.target.
  761 11:25:38.394831  <30>[   17.767269] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  762 11:25:38.401977  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  763 11:25:38.422889  <30>[   17.795902] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  764 11:25:38.429933  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  765 11:25:38.454060  <30>[   17.826538] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  766 11:25:38.461296  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  767 11:25:38.482236  <30>[   17.855088] systemd[1]: Created slice user.slice - User and Session Slice.
  768 11:25:38.489066  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  769 11:25:38.517156  <30>[   17.884485] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  770 11:25:38.522893  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  771 11:25:38.540394  <30>[   17.914227] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  772 11:25:38.552137  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  773 11:25:38.579266  <30>[   17.944302] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  774 11:25:38.591688  <30>[   17.964813] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  775 11:25:38.597180           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  776 11:25:38.620298  <30>[   17.993540] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  777 11:25:38.627339  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  778 11:25:38.650402  <30>[   18.023850] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  779 11:25:38.658554  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  780 11:25:38.680507  <30>[   18.054041] systemd[1]: Reached target paths.target - Path Units.
  781 11:25:38.686077  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  782 11:25:38.710151  <30>[   18.083730] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  783 11:25:38.718132  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  784 11:25:38.740154  <30>[   18.113597] systemd[1]: Reached target slices.target - Slice Units.
  785 11:25:38.745669  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  786 11:25:38.769973  <30>[   18.143872] systemd[1]: Reached target swap.target - Swaps.
  787 11:25:38.774327  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  788 11:25:38.800583  <30>[   18.173895] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  789 11:25:38.807828  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  790 11:25:38.832008  <30>[   18.204684] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  791 11:25:38.839147  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  792 11:25:38.924365  <30>[   18.293880] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  793 11:25:38.937836  <30>[   18.311554] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  794 11:25:38.946367  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  795 11:25:38.972864  <30>[   18.347480] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  796 11:25:38.984531  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  797 11:25:39.013180  <30>[   18.385986] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  798 11:25:39.020489  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  799 11:25:39.045507  <30>[   18.418386] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  800 11:25:39.051636  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  801 11:25:39.081436  <30>[   18.456307] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  802 11:25:39.094367  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  803 11:25:39.128114  <30>[   18.494823] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  804 11:25:39.143424  <30>[   18.511473] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  805 11:25:39.193284  <30>[   18.568554] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  806 11:25:39.219786           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  807 11:25:39.269668  <30>[   18.644455] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  808 11:25:39.299522           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  809 11:25:39.354805  <30>[   18.728167] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  810 11:25:39.387871           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  811 11:25:39.441072  <30>[   18.814295] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  812 11:25:39.463463           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  813 11:25:39.510202  <30>[   18.884356] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  814 11:25:39.529275           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  815 11:25:39.580830  <30>[   18.954285] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  816 11:25:39.587493           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  817 11:25:39.623992  <30>[   18.997104] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  818 11:25:39.658789           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  819 11:25:39.709966  <30>[   19.084426] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  820 11:25:39.729213           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  821 11:25:39.761144  <30>[   19.135380] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  822 11:25:39.786602           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  823 11:25:39.805602  <28>[   19.175471] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  824 11:25:39.817506  <28>[   19.191791] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  825 11:25:39.859974  <30>[   19.234974] systemd[1]: Starting systemd-journald.service - Journal Service...
  826 11:25:39.872730           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  827 11:25:39.960957  <30>[   19.336503] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  828 11:25:39.987243           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  829 11:25:40.031384  <30>[   19.406262] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  830 11:25:40.078820           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  831 11:25:40.144903  <30>[   19.518662] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  832 11:25:40.208376           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  833 11:25:40.273207  <30>[   19.646246] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  834 11:25:40.330311           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  835 11:25:40.393972  <30>[   19.768897] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  836 11:25:40.431140  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  837 11:25:40.466298  <30>[   19.841647] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  838 11:25:40.494138  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  839 11:25:40.524373  <30>[   19.898032] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  840 11:25:40.551183  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  841 11:25:40.711622  <30>[   20.087497] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  842 11:25:40.751095  <30>[   20.124826] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  843 11:25:40.770531  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  844 11:25:40.790411  <30>[   20.164827] systemd[1]: Started systemd-journald.service - Journal Service.
  845 11:25:40.798411  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  846 11:25:40.830313  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  847 11:25:40.862219  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  848 11:25:40.885688  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  849 11:25:40.920876  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  850 11:25:40.954091  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  851 11:25:40.983906  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  852 11:25:41.002306  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  853 11:25:41.022824  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  854 11:25:41.048506  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  855 11:25:41.109237           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  856 11:25:41.181018           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  857 11:25:41.221325           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  858 11:25:41.301701           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  859 11:25:41.394816           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  860 11:25:41.534017  <46>[   20.907517] systemd-journald[163]: Received client request to flush runtime journal.
  861 11:25:41.542173  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  862 11:25:41.710515  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  863 11:25:41.771931  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  864 11:25:41.802752  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  865 11:25:41.852705           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  866 11:25:43.365450  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  867 11:25:43.391220  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  868 11:25:43.408969  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  869 11:25:43.482346           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  870 11:25:43.546801  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  871 11:25:43.612767           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  872 11:25:44.441653  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  873 11:25:44.516568           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  874 11:25:45.204279  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  875 11:25:45.462811           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  876 11:25:45.572917           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  877 11:25:47.093167  <5>[   26.469111] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  878 11:25:47.265428  [[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  879 11:25:47.681274  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  880 11:25:48.432244  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  881 11:25:48.542070  <5>[   27.918922] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  882 11:25:48.661453  <5>[   28.037709] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  883 11:25:48.674678  <4>[   28.049756] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  884 11:25:48.680263  <6>[   28.058918] cfg80211: failed to load regulatory.db
  885 11:25:50.014395  [[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  886 11:25:50.383016  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  887 11:25:57.809549  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  888 11:25:57.836204  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  889 11:25:57.861918  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  890 11:25:57.881169  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  891 11:25:57.954362           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  892 11:25:58.002157           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  893 11:25:58.081442           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  894 11:25:58.125992           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  895 11:25:58.172973  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  896 11:25:58.206989  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  897 11:25:58.234788  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  898 11:25:58.276241  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  899 11:25:58.302097  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  900 11:25:58.546771  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  901 11:25:58.654826  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  902 11:25:58.684813  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  903 11:25:58.840893  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  904 11:25:58.966976  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  905 11:25:58.990461  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  906 11:25:59.009619  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  907 11:25:59.039598  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  908 11:25:59.059784  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  909 11:25:59.086306  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  910 11:25:59.159419           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  911 11:25:59.210121           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  912 11:25:59.448850           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  913 11:25:59.599961           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  914 11:25:59.629800           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  915 11:25:59.651996  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  916 11:25:59.769478  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  917 11:25:59.799143  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  918 11:25:59.859603  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  919 11:25:59.920134  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  920 11:25:59.958506  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  921 11:25:59.979688  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  922 11:26:00.288224           Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
  923 11:26:00.319937  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  924 11:26:00.825783  [[0;32m  OK  [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
  925 11:26:00.914866  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  926 11:26:00.965778  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  927 11:26:00.993482  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  928 11:26:01.080118           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  929 11:26:01.380443  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  930 11:26:01.557728  
  931 11:26:01.561970  Debian GNU/Linux 12 debian-bookworworm-armhf login: root (automatic login)
  932 11:26:01.562357  
  933 11:26:01.931011  Linux debian-bookworm-armhf 6.12.0-rc5-next-20241030 #1 SMP Wed Oct 30 10:53:25 UTC 2024 armv7l
  934 11:26:01.931520  
  935 11:26:01.937106  The programs included with the Debian GNU/Linux system are free software;
  936 11:26:01.945735  the exact distribution terms for each program are described in the
  937 11:26:01.951890  individual files in /usr/share/doc/*/copyright.
  938 11:26:01.952274  
  939 11:26:01.957299  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  940 11:26:01.957682  permitted by applicable law.
  941 11:26:06.794234  Unable to match end of the kernel message
  943 11:26:06.795255  Setting prompt string to ['/ #']
  944 11:26:06.795677  end: 2.4.4.1 login-action (duration 00:00:47) [common]
  946 11:26:06.796628  end: 2.4.4 auto-login-action (duration 00:00:47) [common]
  947 11:26:06.797067  start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
  948 11:26:06.797411  Setting prompt string to ['/ #']
  949 11:26:06.797706  Forcing a shell prompt, looking for ['/ #']
  951 11:26:06.848464  / # 
  952 11:26:06.849002  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  953 11:26:06.849368  Waiting using forced prompt support (timeout 00:02:30)
  954 11:26:06.856063  
  955 11:26:06.861944  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  956 11:26:06.862424  start: 2.4.6 export-device-env (timeout 00:03:12) [common]
  957 11:26:06.862793  Sending with 10 millisecond of delay
  959 11:26:11.919054  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1213804/extract-nfsrootfs-z9lvv0_v'
  960 11:26:11.929791  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1213804/extract-nfsrootfs-z9lvv0_v'
  961 11:26:11.932822  Sending with 10 millisecond of delay
  963 11:26:13.974167  / # export NFS_SERVER_IP='172.16.3.3'
  964 11:26:13.984984  export NFS_SERVER_IP='172.16.3.3'
  965 11:26:13.988242  end: 2.4.6 export-device-env (duration 00:00:07) [common]
  966 11:26:13.988723  end: 2.4 uboot-commands (duration 00:01:55) [common]
  967 11:26:13.989200  end: 2 uboot-action (duration 00:01:55) [common]
  968 11:26:13.989637  start: 3 lava-test-retry (timeout 00:06:26) [common]
  969 11:26:13.990082  start: 3.1 lava-test-shell (timeout 00:06:26) [common]
  970 11:26:13.990430  Using namespace: common
  972 11:26:14.091439  / # #
  973 11:26:14.091954  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
  974 11:26:14.099160  #
  975 11:26:14.105100  Using /lava-1213804
  977 11:26:14.206133  / # export SHELL=/bin/bash
  978 11:26:14.213105  export SHELL=/bin/bash
  980 11:26:14.319678  / # . /lava-1213804/environment
  981 11:26:14.327097  . /lava-1213804/environment
  983 11:26:14.440040  / # /lava-1213804/bin/lava-test-runner /lava-1213804/0
  984 11:26:14.440550  Test shell timeout: 10s (minimum of the action and connection timeout)
  985 11:26:14.447749  /lava-1213804/bin/lava-test-runner /lava-1213804/0
  986 11:26:15.036757  + export TESTRUN_ID=0_timesync-off
  987 11:26:15.045881  + TESTRUN_ID=0_timesync-off
  988 11:26:15.046269  + cd /lava-1213804/0/tests/0_timesync-off
  989 11:26:15.046586  ++ cat uuid
  990 11:26:15.066854  + UUID=1213804_1.6.2.4.1
  991 11:26:15.067240  + set +x
  992 11:26:15.073114  <LAVA_SIGNAL_STARTRUN 0_timesync-off 1213804_1.6.2.4.1>
  993 11:26:15.073755  Received signal: <STARTRUN> 0_timesync-off 1213804_1.6.2.4.1
  994 11:26:15.074133  Starting test lava.0_timesync-off (1213804_1.6.2.4.1)
  995 11:26:15.074512  Skipping test definition patterns.
  996 11:26:15.076347  + systemctl stop systemd-timesyncd
  997 11:26:15.371902  + set +x
  998 11:26:15.372521  Received signal: <ENDRUN> 0_timesync-off 1213804_1.6.2.4.1
  999 11:26:15.372914  Ending use of test pattern.
 1000 11:26:15.373221  Ending test lava.0_timesync-off (1213804_1.6.2.4.1), duration 0.30
 1002 11:26:15.375040  <LAVA_SIGNAL_ENDRUN 0_timesync-off 1213804_1.6.2.4.1>
 1003 11:26:15.684392  + export TESTRUN_ID=1_kselftest-dt
 1004 11:26:15.692304  + TESTRUN_ID=1_kselftest-dt
 1005 11:26:15.692687  + cd /lava-1213804/0/tests/1_kselftest-dt
 1006 11:26:15.693051  ++ cat uuid
 1007 11:26:15.710252  + UUID=1213804_1.6.2.4.5
 1008 11:26:15.710636  + set +x
 1009 11:26:15.716521  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1213804_1.6.2.4.5>
 1010 11:26:15.716926  + cd ./automated/linux/kselftest/
 1011 11:26:15.717478  Received signal: <STARTRUN> 1_kselftest-dt 1213804_1.6.2.4.5
 1012 11:26:15.717792  Starting test lava.1_kselftest-dt (1213804_1.6.2.4.5)
 1013 11:26:15.718223  Skipping test definition patterns.
 1014 11:26:15.742889  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1015 11:26:15.912230  INFO: install_deps skipped
 1016 11:26:16.466114  --2024-01-26 21:49:16--  http://storage.kernelci.org/next/master/next-20241030/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
 1017 11:26:16.510875  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1018 11:26:16.677970  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1019 11:26:16.837371  HTTP request sent, awaiting response... 200 OK
 1020 11:26:16.837749  Length: 4169676 (4.0M) [application/octet-stream]
 1021 11:26:16.842194  Saving to: 'kselftest_armhf.tar.gz'
 1022 11:26:16.842578  
 1023 11:26:19.334998  kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               kselftest_armhf.tar   1%[                    ]  49.92K   156KB/s               kselftest_armhf.tar   5%[>                   ] 218.67K   338KB/s               kselftest_armhf.tar  10%[=>                  ] 428.20K   497KB/s               kselftest_armhf.tar  25%[====>               ]   1.02M   935KB/s               kselftest_armhf.tar  37%[======>             ]   1.49M  1.12MB/s               kselftest_armhf.tar  48%[========>           ]   1.94M  1.25MB/s               kselftest_armhf.tar  57%[==========>         ]   2.28M  1.29MB/s               kselftest_armhf.tar  70%[=============>      ]   2.80M  1.40MB/s               kselftest_armhf.tar  83%[===============>    ]   3.30M  1.47MB/s               kselftest_armhf.tar  97%[==================> ]   3.86M  1.56MB/s               kselftest_armhf.tar 100%[===================>]   3.98M  1.60MB/s    in 2.5s    
 1024 11:26:19.335435  
 1025 11:26:19.925296  2024-01-26 21:49:19 (1.60 MB/s) - 'kselftest_armhf.tar.gz' saved [4169676/4169676]
 1026 11:26:19.925748  
 1027 11:26:20.175948  tar: ./proc/fd-003-kthread: time stamp 2024-10-30 11:08:56 is 23980775.690724204 s in the future
 1028 11:26:20.319742  tar: ./proc/config: time stamp 2024-10-28 11:31:42 is 23809341.545173245 s in the future
 1029 11:26:20.449955  tar: ./proc/proc-tid0: time stamp 2024-10-30 11:08:57 is 23980776.415469745 s in the future
 1030 11:26:20.573826  tar: ./proc/proc-loadavg-001: time stamp 2024-10-30 11:08:56 is 23980775.291230412 s in the future
 1031 11:26:20.715732  tar: ./proc/proc-self-syscall: time stamp 2024-10-30 11:08:57 is 23980776.149346078 s in the future
 1032 11:26:20.846997  tar: ./proc/setns-dcache: time stamp 2024-10-30 11:08:58 is 23980777.018635328 s in the future
 1033 11:26:20.995008  tar: ./proc/setns-sysvipc: time stamp 2024-10-30 11:08:58 is 23980776.869610287 s in the future
 1034 11:26:21.115733  tar: ./proc/proc-uptime-001: time stamp 2024-10-30 11:08:57 is 23980775.749032203 s in the future
 1035 11:26:21.257420  tar: ./proc/fd-001-lookup: time stamp 2024-10-30 11:08:56 is 23980774.607025453 s in the future
 1036 11:26:21.383331  tar: ./proc/proc-uptime-002: time stamp 2024-10-30 11:08:57 is 23980775.481401787 s in the future
 1037 11:26:21.533370  tar: ./proc/fd-002-posix-eq: time stamp 2024-10-30 11:08:56 is 23980774.331174787 s in the future
 1038 11:26:21.658335  tar: ./proc/thread-self: time stamp 2024-10-30 11:08:58 is 23980776.206715078 s in the future
 1039 11:26:21.797985  tar: ./proc/read: time stamp 2024-10-30 11:08:57 is 23980775.06514687 s in the future
 1040 11:26:21.924896  tar: ./proc/self: time stamp 2024-10-30 11:08:57 is 23980774.939288703 s in the future
 1041 11:26:22.058078  tar: ./proc/proc-pid-vm: time stamp 2024-10-30 11:08:56 is 23980773.805830328 s in the future
 1042 11:26:22.184112  tar: ./proc/proc-multiple-procfs: time stamp 2024-10-30 11:08:58 is 23980775.681487203 s in the future
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 1344 11:27:02.562388  tar: ./net/lib.sh: time stamp 2024-10-28 11:31:42 is 23809299.299488198 s in the future
 1345 11:27:02.794046  tar: ./net/tcp_ao/bench-lookups_ipv4: time stamp 2024-10-30 11:08:38 is 23980715.06989824 s in the future
 1346 11:27:02.986438  tar: ./net/tcp_ao/connect_ipv4: time stamp 2024-10-30 11:08:39 is 23980715.87618499 s in the future
 1347 11:27:03.204419  tar: ./net/tcp_ao/self-connect_ipv4: time stamp 2024-10-30 11:08:43 is 23980719.659618823 s in the future
 1348 11:27:03.422298  tar: ./net/tcp_ao/connect_ipv6: time stamp 2024-10-30 11:08:46 is 23980722.440473115 s in the future
 1349 11:27:03.630474  tar: ./net/tcp_ao/key-management_ipv6: time stamp 2024-10-30 11:08:49 is 23980725.23320299 s in the future
 1350 11:27:03.822761  tar: ./net/tcp_ao/restore_ipv4: time stamp 2024-10-30 11:08:42 is 23980718.040013782 s in the future
 1351 11:27:04.032401  tar: ./net/tcp_ao/unsigned-md5_ipv6: time stamp 2024-10-30 11:08:53 is 23980728.831784907 s in the future
 1352 11:27:04.204925  tar: ./net/tcp_ao/restore_ipv6: time stamp 2024-10-30 11:08:49 is 23980724.658234698 s in the future
 1353 11:27:04.371246  tar: ./net/tcp_ao/icmps-accept_ipv6: time stamp 2024-10-30 11:08:48 is 23980723.491912865 s in the future
 1354 11:27:04.570140  tar: ./net/tcp_ao/seq-ext_ipv4: time stamp 2024-10-30 11:08:43 is 23980718.293389365 s in the future
 1355 11:27:04.698034  tar: ./net/tcp_ao/config: time stamp 2024-10-28 11:31:42 is 23809297.164447907 s in the future
 1356 11:27:04.898300  tar: ./net/tcp_ao/setsockopt-closed_ipv6: time stamp 2024-10-30 11:08:52 is 23980726.966451532 s in the future
 1357 11:27:05.097098  tar: ./net/tcp_ao/unsigned-md5_ipv4: time stamp 2024-10-30 11:08:45 is 23980719.766599698 s in the future
 1358 11:27:05.290585  tar: ./net/tcp_ao/icmps-discard_ipv4: time stamp 2024-10-30 11:08:40 is 23980714.572456407 s in the future
 1359 11:27:05.464274  tar: ./net/tcp_ao/connect-deny_ipv4: time stamp 2024-10-30 11:08:39 is 23980713.399009865 s in the future
 1360 11:27:05.664277  tar: ./net/tcp_ao/setsockopt-closed_ipv4: time stamp 2024-10-30 11:08:44 is 23980718.199140823 s in the future
 1361 11:27:05.873496  tar: ./net/tcp_ao/rst_ipv6: time stamp 2024-10-30 11:08:50 is 23980723.988975365 s in the future
 1362 11:27:06.066277  tar: ./net/tcp_ao/seq-ext_ipv6: time stamp 2024-10-30 11:08:51 is 23980724.796921615 s in the future
 1363 11:27:06.215357  tar: ./net/tcp_ao/settings: time stamp 2024-10-28 11:31:42 is 23809295.648056406 s in the future
 1364 11:27:06.392110  tar: ./net/tcp_ao/icmps-discard_ipv6: time stamp 2024-10-30 11:08:48 is 23980721.471431865 s in the future
 1365 11:27:06.592124  tar: ./net/tcp_ao/connect-deny_ipv6: time stamp 2024-10-30 11:08:47 is 23980720.27166999 s in the future
 1366 11:27:06.850124  tar: ./net/tcp_ao/key-management_ipv4: time stamp 2024-10-30 11:08:41 is 23980714.01325349 s in the future
 1367 11:27:07.034388  tar: ./net/tcp_ao/icmps-accept_ipv4: time stamp 2024-10-30 11:08:40 is 23980712.829842156 s in the future
 1368 11:27:07.208958  tar: ./net/tcp_ao/bench-lookups_ipv6: time stamp 2024-10-30 11:08:46 is 23980718.654626031 s in the future
 1369 11:27:07.392051  tar: ./net/tcp_ao/self-connect_ipv6: time stamp 2024-10-30 11:08:51 is 23980723.471281948 s in the future
 1370 11:27:07.575062  tar: ./net/tcp_ao/rst_ipv4: time stamp 2024-10-30 11:08:42 is 23980714.28786899 s in the future
 1371 11:27:07.630234  tar: ./net/tcp_ao: time stamp 2024-10-30 11:09:58 is 23980790.230647365 s in the future
 1372 11:27:07.825943  tar: ./net/forwarding/q_in_vni.sh: time stamp 2024-10-28 11:31:42 is 23809294.037136073 s in the future
 1373 11:27:07.952164  tar: ./net/forwarding/router_mpath_nh_res.sh: time stamp 2024-10-28 11:31:42 is 23809293.912072406 s in the future
 1374 11:27:08.084502  tar: ./net/forwarding/vxlan_bridge_1q.sh: time stamp 2024-10-28 11:31:42 is 23809293.778747323 s in the future
 1375 11:27:08.208356  tar: ./net/forwarding/sch_tbf_etsprio.sh: time stamp 2024-10-28 11:31:42 is 23809293.655552781 s in the future
 1376 11:27:08.344179  tar: ./net/forwarding/router_bridge.sh: time stamp 2024-10-28 11:31:42 is 23809293.520121281 s in the future
 1377 11:27:08.469232  tar: ./net/forwarding/vxlan_symmetric.sh: time stamp 2024-10-28 11:31:42 is 23809293.394956989 s in the future
 1378 11:27:08.592074  tar: ./net/forwarding/ip6gre_hier.sh: time stamp 2024-10-28 11:31:42 is 23809293.271584614 s in the future
 1379 11:27:08.742302  tar: ./net/forwarding/sch_tbf_prio.sh: time stamp 2024-10-28 11:31:42 is 23809293.121302198 s in the future
 1380 11:27:08.861130  tar: ./net/forwarding/tc_actions.sh: time stamp 2024-10-28 11:31:42 is 23809293.003059114 s in the future
 1381 11:27:08.974920  tar: ./net/forwarding/tc_flower_port_range.sh: time stamp 2024-10-28 11:31:42 is 23809292.889902781 s in the future
 1382 11:27:09.086500  tar: ./net/forwarding/vxlan_bridge_1d_port_8472_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809292.779242573 s in the future
 1383 11:27:09.220278  tar: ./net/forwarding/gre_multipath_nh_res.sh: time stamp 2024-10-28 11:31:42 is 23809292.644164156 s in the future
 1384 11:27:09.377917  tar: ./net/forwarding/devlink_lib.sh: time stamp 2024-10-28 11:31:42 is 23809292.485686114 s in the future
 1385 11:27:09.502007  tar: ./net/forwarding/ipip_hier_gre_key.sh: time stamp 2024-10-28 11:31:42 is 23809292.362370573 s in the future
 1386 11:27:09.620920  tar: ./net/forwarding/tc_flower_router.sh: time stamp 2024-10-28 11:31:42 is 23809292.243519989 s in the future
 1387 11:27:09.783899  tar: ./net/forwarding/lib.sh: time stamp 2024-10-28 11:31:42 is 23809292.078929531 s in the future
 1388 11:27:09.954481  tar: ./net/forwarding/mirror_gre_bridge_1q_lag.sh: time stamp 2024-10-28 11:31:42 is 23809291.910245948 s in the future
 1389 11:27:10.103648  tar: ./net/forwarding/router_bridge_lag.sh: time stamp 2024-10-28 11:31:42 is 23809291.760045031 s in the future
 1390 11:27:10.235047  tar: ./net/forwarding/ipip_flat_gre.sh: time stamp 2024-10-28 11:31:42 is 23809291.628680656 s in the future
 1391 11:27:10.362079  tar: ./net/forwarding/sch_tbf_root.sh: time stamp 2024-10-28 11:31:42 is 23809291.501533031 s in the future
 1392 11:27:10.479909  tar: ./net/forwarding/skbedit_priority.sh: time stamp 2024-10-28 11:31:42 is 23809291.384439114 s in the future
 1393 11:27:10.618628  tar: ./net/forwarding/bridge_mdb_max.sh: time stamp 2024-10-28 11:31:42 is 23809291.244503198 s in the future
 1394 11:27:10.748388  tar: ./net/forwarding/ip6gre_custom_multipath_hash.sh: time stamp 2024-10-28 11:31:42 is 23809291.117476656 s in the future
 1395 11:27:10.896734  tar: ./net/forwarding/router_multicast.sh: time stamp 2024-10-28 11:31:42 is 23809290.967594531 s in the future
 1396 11:27:11.022050  tar: ./net/forwarding/mirror_gre_flower.sh: time stamp 2024-10-28 11:31:42 is 23809290.842205656 s in the future
 1397 11:27:11.170370  tar: ./net/forwarding/router_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809290.694324031 s in the future
 1398 11:27:11.297492  tar: ./net/forwarding/vxlan_bridge_1d_port_8472.sh: time stamp 2024-10-28 11:31:42 is 23809290.567237364 s in the future
 1399 11:27:11.412978  tar: ./net/forwarding/tc_shblocks.sh: time stamp 2024-10-28 11:31:42 is 23809290.450119031 s in the future
 1400 11:27:11.544316  tar: ./net/forwarding/config: time stamp 2024-10-28 11:31:42 is 23809290.318608322 s in the future
 1401 11:27:11.670476  tar: ./net/forwarding/dual_vxlan_bridge.sh: time stamp 2024-10-28 11:31:42 is 23809290.193355697 s in the future
 1402 11:27:11.814641  tar: ./net/forwarding/mirror_gre_vlan_bridge_1q.sh: time stamp 2024-10-28 11:31:42 is 23809290.049830947 s in the future
 1403 11:27:11.948266  tar: ./net/forwarding/sch_ets_tests.sh: time stamp 2024-10-28 11:31:42 is 23809289.916193531 s in the future
 1404 11:27:12.096961  tar: ./net/forwarding/ip6gre_inner_v4_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809289.768133781 s in the future
 1405 11:27:12.246427  tar: ./net/forwarding/mirror_vlan.sh: time stamp 2024-10-28 11:31:42 is 23809289.617907031 s in the future
 1406 11:27:12.390510  tar: ./net/forwarding/fib_offload_lib.sh: time stamp 2024-10-28 11:31:42 is 23809289.474282947 s in the future
 1407 11:27:12.548326  tar: ./net/forwarding/bridge_mdb.sh: time stamp 2024-10-28 11:31:42 is 23809289.315719531 s in the future
 1408 11:27:12.679978  tar: ./net/forwarding/bridge_vlan_aware.sh: time stamp 2024-10-28 11:31:42 is 23809289.184428864 s in the future
 1409 11:27:12.812334  tar: ./net/forwarding/router_bridge_1d.sh: time stamp 2024-10-28 11:31:42 is 23809289.050936947 s in the future
 1410 11:27:12.959537  tar: ./net/forwarding/bridge_vlan_mcast.sh: time stamp 2024-10-28 11:31:42 is 23809288.903912864 s in the future
 1411 11:27:13.072858  tar: ./net/forwarding/router.sh: time stamp 2024-10-28 11:31:42 is 23809288.790391822 s in the future
 1412 11:27:13.199184  tar: ./net/forwarding/ipip_flat_gre_key.sh: time stamp 2024-10-28 11:31:42 is 23809288.665219406 s in the future
 1413 11:27:13.341351  tar: ./net/forwarding/vxlan_asymmetric_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809288.523584614 s in the future
 1414 11:27:13.482430  tar: ./net/forwarding/router_broadcast.sh: time stamp 2024-10-28 11:31:42 is 23809288.381605197 s in the future
 1415 11:27:13.604284  tar: ./net/forwarding/ip6gre_hier_key.sh: time stamp 2024-10-28 11:31:42 is 23809288.258603697 s in the future
 1416 11:27:13.756072  tar: ./net/forwarding/bridge_fdb_learning_limit.sh: time stamp 2024-10-28 11:31:42 is 23809288.108454405 s in the future
 1417 11:27:13.885197  tar: ./net/forwarding/ip6gre_flat_key.sh: time stamp 2024-10-28 11:31:42 is 23809287.978346822 s in the future
 1418 11:27:14.025064  tar: ./net/forwarding/tc_flower_l2_miss.sh: time stamp 2024-10-28 11:31:42 is 23809287.839322447 s in the future
 1419 11:27:14.167184  tar: ./net/forwarding/ip6gre_inner_v6_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809287.69751428 s in the future
 1420 11:27:14.298573  tar: ./net/forwarding/tc_tunnel_key.sh: time stamp 2024-10-28 11:31:42 is 23809287.56436578 s in the future
 1421 11:27:14.433194  tar: ./net/forwarding/no_forwarding.sh: time stamp 2024-10-28 11:31:42 is 23809287.43064353 s in the future
 1422 11:27:14.561470  tar: ./net/forwarding/router_mpath_seed.sh: time stamp 2024-10-28 11:31:42 is 23809287.302853614 s in the future
 1423 11:27:14.689825  tar: ./net/forwarding/vxlan_bridge_1q_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809287.174126947 s in the future
 1424 11:27:14.853161  tar: ./net/forwarding/vxlan_asymmetric.sh: time stamp 2024-10-28 11:31:42 is 23809287.010833114 s in the future
 1425 11:27:15.000387  tar: ./net/forwarding/sch_tbf_core.sh: time stamp 2024-10-28 11:31:42 is 23809286.863531489 s in the future
 1426 11:27:15.124571  tar: ./net/forwarding/gre_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809286.738266739 s in the future
 1427 11:27:15.278111  tar: ./net/forwarding/sch_ets_core.sh: time stamp 2024-10-28 11:31:42 is 23809286.585499072 s in the future
 1428 11:27:15.426488  tar: ./net/forwarding/gre_inner_v6_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809286.437849989 s in the future
 1429 11:27:15.541245  tar: ./net/forwarding/mirror_gre_lib.sh: time stamp 2024-10-28 11:31:42 is 23809286.323137155 s in the future
 1430 11:27:15.658681  tar: ./net/forwarding/sch_red.sh: time stamp 2024-10-28 11:31:42 is 23809286.204495864 s in the future
 1431 11:27:15.833394  tar: ./net/forwarding/ip6gre_flat_keys.sh: time stamp 2024-10-28 11:31:42 is 23809286.02940578 s in the future
 1432 11:27:15.951050  tar: ./net/forwarding/router_mpath_nh.sh: time stamp 2024-10-28 11:31:42 is 23809285.912446155 s in the future
 1433 11:27:16.065547  tar: ./net/forwarding/ipip_flat_gre_keys.sh: time stamp 2024-10-28 11:31:42 is 23809285.797902155 s in the future
 1434 11:27:16.209659  tar: ./net/forwarding/ip6gre_lib.sh: time stamp 2024-10-28 11:31:42 is 23809285.653838239 s in the future
 1435 11:27:16.343155  tar: ./net/forwarding/bridge_sticky_fdb.sh: time stamp 2024-10-28 11:31:42 is 23809285.52039628 s in the future
 1436 11:27:16.459883  tar: ./net/forwarding/vxlan_bridge_1q_port_8472_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809285.405014322 s in the future
 1437 11:27:16.579966  tar: ./net/forwarding/mirror_gre_bridge_1d_vlan.sh: time stamp 2024-10-28 11:31:42 is 23809285.28440378 s in the future
 1438 11:27:16.727354  tar: ./net/forwarding/tc_police.sh: time stamp 2024-10-28 11:31:42 is 23809285.136591072 s in the future
 1439 11:27:16.860838  tar: ./net/forwarding/gre_multipath_nh.sh: time stamp 2024-10-28 11:31:42 is 23809285.003047613 s in the future
 1440 11:27:17.004923  tar: ./net/forwarding/vxlan_bridge_1d_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809284.859099613 s in the future
 1441 11:27:17.145746  tar: ./net/forwarding/q_in_vni_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809284.717089488 s in the future
 1442 11:27:17.279293  tar: ./net/forwarding/vxlan_bridge_1q_port_8472.sh: time stamp 2024-10-28 11:31:42 is 23809284.585891363 s in the future
 1443 11:27:17.400160  tar: ./net/forwarding/mirror_lib.sh: time stamp 2024-10-28 11:31:42 is 23809284.462813363 s in the future
 1444 11:27:17.530742  tar: ./net/forwarding/vxlan_symmetric_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809284.333698113 s in the future
 1445 11:27:17.678114  tar: ./net/forwarding/pedit_dsfield.sh: time stamp 2024-10-28 11:31:42 is 23809284.185625072 s in the future
 1446 11:27:17.821006  tar: ./net/forwarding/settings: time stamp 2024-10-28 11:31:42 is 23809284.041512155 s in the future
 1447 11:27:17.934245  tar: ./net/forwarding/mirror_gre_nh.sh: time stamp 2024-10-28 11:31:42 is 23809283.92907478 s in the future
 1448 11:27:18.069784  tar: ./net/forwarding/ip6gre_flat.sh: time stamp 2024-10-28 11:31:42 is 23809283.793403655 s in the future
 1449 11:27:18.207481  tar: ./net/forwarding/tc_chains.sh: time stamp 2024-10-28 11:31:42 is 23809283.654927738 s in the future
 1450 11:27:18.328374  tar: ./net/forwarding/bridge_mdb_port_down.sh: time stamp 2024-10-28 11:31:42 is 23809283.534938488 s in the future
 1451 11:27:18.456613  tar: ./net/forwarding/gre_custom_multipath_hash.sh: time stamp 2024-10-28 11:31:42 is 23809283.407603155 s in the future
 1452 11:27:18.595588  tar: ./net/forwarding/mirror_gre_bound.sh: time stamp 2024-10-28 11:31:42 is 23809283.267584947 s in the future
 1453 11:27:18.719613  tar: ./net/forwarding/ip6_forward_instats_vrf.sh: time stamp 2024-10-28 11:31:42 is 23809283.14471628 s in the future
 1454 11:27:18.843681  tar: ./net/forwarding/tc_vlan_modify.sh: time stamp 2024-10-28 11:31:42 is 23809283.019611155 s in the future
 1455 11:27:18.968700  tar: ./net/forwarding/bridge_vlan_unaware.sh: time stamp 2024-10-28 11:31:42 is 23809282.894833572 s in the future
 1456 11:27:19.104445  tar: ./net/forwarding/bridge_mld.sh: time stamp 2024-10-28 11:31:42 is 23809282.758686905 s in the future
 1457 11:27:19.241326  tar: ./net/forwarding/gre_inner_v4_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809282.623683613 s in the future
 1458 11:27:19.365378  tar: ./net/forwarding/router_nh.sh: time stamp 2024-10-28 11:31:42 is 23809282.498612988 s in the future
 1459 11:27:19.489197  tar: ./net/forwarding/mirror_topo_lib.sh: time stamp 2024-10-28 11:31:42 is 23809282.373483988 s in the future
 1460 11:27:19.645024  tar: ./net/forwarding/bridge_port_isolation.sh: time stamp 2024-10-28 11:31:42 is 23809282.21917403 s in the future
 1461 11:27:19.781614  tar: ./net/forwarding/sch_tbf_ets.sh: time stamp 2024-10-28 11:31:42 is 23809282.081649113 s in the future
 1462 11:27:19.936220  tar: ./net/forwarding/router_bridge_vlan_upper.sh: time stamp 2024-10-28 11:31:42 is 23809281.927630696 s in the future
 1463 11:27:20.074121  tar: ./net/forwarding/router_bridge_1d_lag.sh: time stamp 2024-10-28 11:31:42 is 23809281.78968078 s in the future
 1464 11:27:20.213237  tar: ./net/forwarding/custom_multipath_hash.sh: time stamp 2024-10-28 11:31:42 is 23809281.651620196 s in the future
 1465 11:27:20.332898  tar: ./net/forwarding/mirror_gre_lag_lacp.sh: time stamp 2024-10-28 11:31:42 is 23809281.531248363 s in the future
 1466 11:27:20.464130  tar: ./net/forwarding/min_max_mtu.sh: time stamp 2024-10-28 11:31:42 is 23809281.39915453 s in the future
 1467 11:27:20.571096  tar: ./net/forwarding/sch_ets.sh: time stamp 2024-10-28 11:31:42 is 23809281.29086953 s in the future
 1468 11:27:20.708132  tar: ./net/forwarding/tc_flower_cfm.sh: time stamp 2024-10-28 11:31:42 is 23809281.155886863 s in the future
 1469 11:27:20.832327  tar: ./net/forwarding/router_bridge_vlan.sh: time stamp 2024-10-28 11:31:42 is 23809281.031825821 s in the future
 1470 11:27:20.970920  tar: ./net/forwarding/local_termination.sh: time stamp 2024-10-28 11:31:42 is 23809280.892547155 s in the future
 1471 11:27:21.090849  tar: ./net/forwarding/mirror_gre_vlan.sh: time stamp 2024-10-28 11:31:42 is 23809280.77227328 s in the future
 1472 11:27:21.232924  tar: ./net/forwarding/router_bridge_vlan_upper_pvid.sh: time stamp 2024-10-28 11:31:42 is 23809280.631567988 s in the future
 1473 11:27:21.356913  tar: ./net/forwarding/mirror_gre_changes.sh: time stamp 2024-10-28 11:31:42 is 23809280.50646828 s in the future
 1474 11:27:21.474547  tar: ./net/forwarding/tc_common.sh: time stamp 2024-10-28 11:31:42 is 23809280.388537155 s in the future
 1475 11:27:21.599321  tar: ./net/forwarding/router_vid_1.sh: time stamp 2024-10-28 11:31:42 is 23809280.263637821 s in the future
 1476 11:27:21.716052  tar: ./net/forwarding/bridge_mdb_host.sh: time stamp 2024-10-28 11:31:42 is 23809280.147647071 s in the future
 1477 11:27:21.824436  tar: ./net/forwarding/ipip_hier_gre_keys.sh: time stamp 2024-10-28 11:31:42 is 23809280.039023238 s in the future
 1478 11:27:21.976080  tar: ./net/forwarding/mirror_gre_topo_lib.sh: time stamp 2024-10-28 11:31:42 is 23809279.888280488 s in the future
 1479 11:27:22.091936  tar: ./net/forwarding/forwarding.config.sample: time stamp 2024-10-28 11:31:42 is 23809279.77225153 s in the future
 1480 11:27:22.213532  tar: ./net/forwarding/pedit_l4port.sh: time stamp 2024-10-28 11:31:42 is 23809279.649463196 s in the future
 1481 11:27:22.324908  tar: ./net/forwarding/lib_sh_test.sh: time stamp 2024-10-28 11:31:42 is 23809279.537934863 s in the future
 1482 11:27:22.458741  tar: ./net/forwarding/ip6gre_hier_keys.sh: time stamp 2024-10-28 11:31:42 is 23809279.404946988 s in the future
 1483 11:27:22.584965  tar: ./net/forwarding/router_mpath_nh_lib.sh: time stamp 2024-10-28 11:31:42 is 23809279.279262863 s in the future
 1484 11:27:22.717284  tar: ./net/forwarding/mirror_gre_bridge_1q.sh: time stamp 2024-10-28 11:31:42 is 23809279.145896113 s in the future
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 1533 11:27:28.894210  tar: ./net/packetdrill/tcp_slow_start_slow-start-app-limited-9-packets-out.pkt: time stamp 2024-10-28 11:31:42 is 23809272.972597279 s in the future
 1534 11:27:29.014187  tar: ./net/packetdrill/tcp_zerocopy_fastopen-server.pkt: time stamp 2024-10-28 11:31:42 is 23809272.84992707 s in the future
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 1541 11:27:29.873835  tar: ./net/packetdrill/tcp_zerocopy_maxfrags.pkt: time stamp 2024-10-28 11:31:42 is 23809271.989501237 s in the future
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 1543 11:27:30.136601  tar: ./net/packetdrill/tcp_slow_start_slow-start-fq-ack-per-2pkt.pkt: time stamp 2024-10-28 11:31:42 is 23809271.729232737 s in the future
 1544 11:27:30.235574  tar: ./net/packetdrill/tcp_slow_start_slow-start-ack-per-4pkt.pkt: time stamp 2024-10-28 11:31:42 is 23809271.629401612 s in the future
 1545 11:27:30.378050  tar: ./net/packetdrill/tcp_slow_start_slow-start-after-idle.pkt: time stamp 2024-10-28 11:31:42 is 23809271.487162404 s in the future
 1546 11:27:30.502112  tar: ./net/packetdrill/tcp_zerocopy_epoll_oneshot.pkt: time stamp 2024-10-28 11:31:42 is 23809271.362290362 s in the future
 1547 11:27:30.615635  tar: ./net/packetdrill/tcp_inq_server.pkt: time stamp 2024-10-28 11:31:42 is 23809271.24767657 s in the future
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 1550 11:27:30.984078  tar: ./net/packetdrill/tcp_zerocopy_epoll_edge.pkt: time stamp 2024-10-28 11:31:42 is 23809270.880581653 s in the future
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 1580 11:27:34.395856  tar: ./drivers/net/bonding/bond-arp-interval-causes-panic.sh: time stamp 2024-10-28 11:31:42 is 23809267.46867457 s in the future
 1581 11:27:34.520965  tar: ./drivers/net/bonding/bond-eth-type-change.sh: time stamp 2024-10-28 11:31:42 is 23809267.342395778 s in the future
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 1596 11:27:36.433148  tar: ./drivers/platform/x86/intel/ifs/test_ifs.sh: time stamp 2024-10-28 11:31:42 is 23809265.429473361 s in the future
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 2079 11:28:51.235612  tar: ./tc-testing/tc-tests/qdiscs/cbs.json: time stamp 2024-10-28 11:31:42 is 23809190.623623852 s in the future
 2080 11:28:51.359687  tar: ./tc-testing/tc-tests/qdiscs/htb.json: time stamp 2024-10-28 11:31:42 is 23809190.499221727 s in the future
 2081 11:28:51.513190  tar: ./tc-testing/tc-tests/qdiscs/ingress.json: time stamp 2024-10-28 11:31:42 is 23809190.346919727 s in the future
 2082 11:28:51.643637  tar: ./tc-testing/tc-tests/qdiscs/tbf.json: time stamp 2024-10-28 11:31:42 is 23809190.215087102 s in the future
 2083 11:28:51.787185  tar: ./tc-testing/tc-tests/qdiscs/skbprio.json: time stamp 2024-10-28 11:31:42 is 23809190.07322131 s in the future
 2084 11:28:51.919394  tar: ./tc-testing/tc-tests/qdiscs/hhf.json: time stamp 2024-10-28 11:31:42 is 23809189.940640477 s in the future
 2085 11:28:52.047562  tar: ./tc-testing/tc-tests/qdiscs/codel.json: time stamp 2024-10-28 11:31:42 is 23809189.81118556 s in the future
 2086 11:28:52.177028  tar: ./tc-testing/tc-tests/qdiscs/ets.json: time stamp 2024-10-28 11:31:42 is 23809189.681312769 s in the future
 2087 11:28:52.319748  tar: ./tc-testing/tc-tests/qdiscs/pfifo_fast.json: time stamp 2024-10-28 11:31:42 is 23809189.53963731 s in the future
 2088 11:28:52.443686  tar: ./tc-testing/tc-tests/qdiscs/qfq.json: time stamp 2024-10-28 11:31:42 is 23809189.415010519 s in the future
 2089 11:28:52.585537  tar: ./tc-testing/tc-tests/qdiscs/etf.json: time stamp 2024-10-28 11:31:42 is 23809189.273211977 s in the future
 2090 11:28:52.703344  tar: ./tc-testing/tc-tests/qdiscs/cake.json: time stamp 2024-10-28 11:31:42 is 23809189.155979894 s in the future
 2091 11:28:52.845557  tar: ./tc-testing/tc-tests/qdiscs/taprio.json: time stamp 2024-10-28 11:31:42 is 23809189.014273519 s in the future
 2092 11:28:52.961507  tar: ./tc-testing/tc-tests/qdiscs/drr.json: time stamp 2024-10-28 11:31:42 is 23809188.897890394 s in the future
 2093 11:28:53.106550  tar: ./tc-testing/tc-tests/qdiscs/prio.json: time stamp 2024-10-28 11:31:42 is 23809188.753905102 s in the future
 2094 11:28:53.228543  tar: ./tc-testing/tc-tests/qdiscs/fq_pie.json: time stamp 2024-10-28 11:31:42 is 23809188.630429894 s in the future
 2095 11:28:53.362993  tar: ./tc-testing/tc-tests/qdiscs/mq.json: time stamp 2024-10-28 11:31:42 is 23809188.496792352 s in the future
 2096 11:28:53.486939  tar: ./tc-testing/tc-tests/qdiscs/plug.json: time stamp 2024-10-28 11:31:42 is 23809188.37213681 s in the future
 2097 11:28:53.617280  tar: ./tc-testing/tc-tests/qdiscs/mqprio.json: time stamp 2024-10-28 11:31:42 is 23809188.241825894 s in the future
 2098 11:28:53.671740  tar: ./tc-testing/tc-tests/qdiscs: time stamp 2024-10-28 11:31:42 is 23809188.186670435 s in the future
 2099 11:28:53.830488  tar: ./tc-testing/tc-tests/actions/sample.json: time stamp 2024-10-28 11:31:42 is 23809188.029865935 s in the future
 2100 11:28:53.936815  tar: ./tc-testing/tc-tests/actions/connmark.json: time stamp 2024-10-28 11:31:42 is 23809187.922950977 s in the future
 2101 11:28:54.076590  tar: ./tc-testing/tc-tests/actions/tunnel_key.json: time stamp 2024-10-28 11:31:42 is 23809187.78308806 s in the future
 2102 11:28:54.256904  tar: ./tc-testing/tc-tests/actions/mpls.json: time stamp 2024-10-28 11:31:42 is 23809187.602848227 s in the future
 2103 11:28:54.402265  tar: ./tc-testing/tc-tests/actions/skbedit.json: time stamp 2024-10-28 11:31:42 is 23809187.457876685 s in the future
 2104 11:28:54.536745  tar: ./tc-testing/tc-tests/actions/skbmod.json: time stamp 2024-10-28 11:31:42 is 23809187.322788268 s in the future
 2105 11:28:54.673821  tar: ./tc-testing/tc-tests/actions/ife.json: time stamp 2024-10-28 11:31:42 is 23809187.185767643 s in the future
 2106 11:28:54.815371  tar: ./tc-testing/tc-tests/actions/gact.json: time stamp 2024-10-28 11:31:42 is 23809187.044041727 s in the future
 2107 11:28:54.931373  tar: ./tc-testing/tc-tests/actions/gate.json: time stamp 2024-10-28 11:31:42 is 23809186.927127435 s in the future
 2108 11:28:55.066194  tar: ./tc-testing/tc-tests/actions/pedit.json: time stamp 2024-10-28 11:31:42 is 23809186.793717227 s in the future
 2109 11:28:55.203959  tar: ./tc-testing/tc-tests/actions/bpf.json: time stamp 2024-10-28 11:31:42 is 23809186.655387685 s in the future
 2110 11:28:55.340510  tar: ./tc-testing/tc-tests/actions/simple.json: time stamp 2024-10-28 11:31:42 is 23809186.518616102 s in the future
 2111 11:28:55.478077  tar: ./tc-testing/tc-tests/actions/police.json: time stamp 2024-10-28 11:31:42 is 23809186.380500185 s in the future
 2112 11:28:55.616328  tar: ./tc-testing/tc-tests/actions/nat.json: time stamp 2024-10-28 11:31:42 is 23809186.243527518 s in the future
 2113 11:28:55.745409  tar: ./tc-testing/tc-tests/actions/csum.json: time stamp 2024-10-28 11:31:42 is 23809186.113488102 s in the future
 2114 11:28:55.887505  tar: ./tc-testing/tc-tests/actions/ctinfo.json: time stamp 2024-10-28 11:31:42 is 23809185.97192606 s in the future
 2115 11:28:56.030721  tar: ./tc-testing/tc-tests/actions/vlan.json: time stamp 2024-10-28 11:31:42 is 23809185.828591893 s in the future
 2116 11:28:56.175068  tar: ./tc-testing/tc-tests/actions/mirred.json: time stamp 2024-10-28 11:31:42 is 23809185.684700352 s in the future
 2117 11:28:56.307408  tar: ./tc-testing/tc-tests/actions/ct.json: time stamp 2024-10-28 11:31:42 is 23809185.550993393 s in the future
 2118 11:28:56.369236  tar: ./tc-testing/tc-tests/actions: time stamp 2024-10-28 11:31:42 is 23809185.489850518 s in the future
 2119 11:28:56.431993  tar: ./tc-testing/tc-tests: time stamp 2024-10-28 11:31:42 is 23809185.425864643 s in the future
 2120 11:28:56.654129  tar: ./tc-testing/config: time stamp 2024-10-28 11:31:42 is 23809185.204084893 s in the future
 2121 11:28:56.771924  tar: ./tc-testing/TdcPlugin.py: time stamp 2024-10-28 11:31:42 is 23809185.086513435 s in the future
 2122 11:28:56.888455  tar: ./tc-testing/tdc_helper.py: time stamp 2024-10-28 11:31:42 is 23809184.969719268 s in the future
 2123 11:28:57.015358  tar: ./tc-testing/tdc.sh: time stamp 2024-10-28 11:31:42 is 23809184.842136435 s in the future
 2124 11:28:57.156182  tar: ./tc-testing/tdc_config.py: time stamp 2024-10-28 11:31:42 is 23809184.702540018 s in the future
 2125 11:28:57.280075  tar: ./tc-testing/settings: time stamp 2024-10-28 11:31:42 is 23809184.577914476 s in the future
 2126 11:28:57.426229  tar: ./tc-testing/plugin-lib/scapyPlugin.py: time stamp 2024-10-28 11:31:42 is 23809184.433450393 s in the future
 2127 11:28:57.559849  tar: ./tc-testing/plugin-lib/README-PLUGINS: time stamp 2024-10-28 11:31:42 is 23809184.299874101 s in the future
 2128 11:28:57.690129  tar: ./tc-testing/plugin-lib/rootPlugin.py: time stamp 2024-10-28 11:31:42 is 23809184.16875256 s in the future
 2129 11:28:57.822733  tar: ./tc-testing/plugin-lib/nsPlugin.py: time stamp 2024-10-28 11:31:42 is 23809184.03569756 s in the future
 2130 11:28:57.957359  tar: ./tc-testing/plugin-lib/valgrindPlugin.py: time stamp 2024-10-28 11:31:42 is 23809183.90177131 s in the future
 2131 11:28:58.013262  tar: ./tc-testing/plugin-lib: time stamp 2024-10-28 11:31:42 is 23809183.844423351 s in the future
 2132 11:28:58.142037  tar: ./tc-testing/action-ebpf: time stamp 2024-10-28 11:31:42 is 23809183.71607781 s in the future
 2133 11:28:58.298929  tar: ./tc-testing/scripts/taprio_wait_for_admin.sh: time stamp 2024-10-28 11:31:42 is 23809183.561464643 s in the future
 2134 11:28:58.346729  tar: ./tc-testing/scripts: time stamp 2024-10-28 11:31:42 is 23809183.510462476 s in the future
 2135 11:28:58.465321  tar: ./tc-testing/tdc_config_local_template.py: time stamp 2024-10-28 11:31:42 is 23809183.393109601 s in the future
 2136 11:28:58.607189  tar: ./tc-testing/tdc_batch.py: time stamp 2024-10-28 11:31:42 is 23809183.251117101 s in the future
 2137 11:28:58.741569  tar: ./tc-testing/tdc_multibatch.py: time stamp 2024-10-28 11:31:42 is 23809183.117790143 s in the future
 2138 11:28:58.857449  tar: ./tc-testing/plugins/__init__.py: time stamp 2024-10-28 11:31:42 is 23809183.001018518 s in the future
 2139 11:28:58.906071  tar: ./tc-testing/plugins: time stamp 2024-10-28 11:31:42 is 23809182.952190726 s in the future
 2140 11:28:58.954938  tar: ./tc-testing: time stamp 2024-10-30 11:10:00 is 23980680.901717768 s in the future
 2141 11:28:59.107446  tar: ./kselftest/runner.sh: time stamp 2024-10-30 11:09:48 is 23980668.750873435 s in the future
 2142 11:28:59.224107  tar: ./kselftest/ktap_helpers.sh: time stamp 2024-10-28 11:31:42 is 23809182.634092435 s in the future
 2143 11:28:59.357486  tar: ./kselftest/module.sh: time stamp 2024-10-30 11:09:48 is 23980668.500541143 s in the future
 2144 11:28:59.475941  tar: ./kselftest/ksft.py: time stamp 2024-10-30 11:09:48 is 23980668.38114756 s in the future
 2145 11:28:59.606972  tar: ./kselftest/prefix.pl: time stamp 2024-10-30 11:09:48 is 23980668.25035706 s in the future
 2146 11:28:59.667691  tar: ./kselftest: time stamp 2024-10-28 11:31:42 is 23809182.189330851 s in the future
 2147 11:29:00.206415  tar: ./fchmodat2/fchmodat2_test: time stamp 2024-10-30 11:07:38 is 23980537.651438309 s in the future
 2148 11:29:00.256295  tar: ./fchmodat2: time stamp 2024-10-30 11:09:51 is 23980670.600268309 s in the future
 2149 11:29:00.398127  tar: ./tty/tty_tstamp_update: time stamp 2024-10-30 11:09:26 is 23980645.459888976 s in the future
 2150 11:29:00.451130  tar: ./tty: time stamp 2024-10-30 11:10:01 is 23980680.405448226 s in the future
 2151 11:29:00.508217  tar: .: time stamp 2024-10-30 11:10:04 is 23980683.346787893 s in the future
 2152 11:29:00.778431  skiplist:
 2153 11:29:00.778862  ========================================
 2154 11:29:00.783628  ========================================
 2155 11:29:01.116801  dt:test_unprobed_devices.sh
 2156 11:29:01.240052  ============== Tests to run ===============
 2157 11:29:01.255038  dt:test_unprobed_devices.sh
 2158 11:29:01.259311  ===========End Tests to run ===============
 2159 11:29:01.315738  shardfile-dt pass
 2160 11:29:01.647752  <12>[  221.035185] kselftest: Running tests in dt
 2161 11:29:01.678619  TAP version 13
 2162 11:29:01.702308  1..1
 2163 11:29:01.756160  # timeout set to 45
 2164 11:29:01.756540  # selftests: dt: test_unprobed_devices.sh
 2165 11:29:02.720328  # TAP version 13
 2166 11:29:28.121513  # 1..257
 2167 11:29:28.328923  # ok 1 / # SKIP
 2168 11:29:28.357125  # ok 2 /clk_mcasp0
 2169 11:29:28.424089  # ok 3 /clk_mcasp0_fixed # SKIP
 2170 11:29:28.496308  # ok 4 /cpus/cpu@0 # SKIP
 2171 11:29:28.573256  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 2172 11:29:28.598718  # ok 6 /fixedregulator0
 2173 11:29:28.617363  # ok 7 /leds
 2174 11:29:28.634576  # ok 8 /ocp
 2175 11:29:28.663034  # ok 9 /ocp/interconnect@44c00000
 2176 11:29:28.687480  # ok 10 /ocp/interconnect@44c00000/segment@0
 2177 11:29:28.711883  # ok 11 /ocp/interconnect@44c00000/segment@100000
 2178 11:29:28.736364  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 2179 11:29:28.808769  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 2180 11:29:28.827548  # ok 14 /ocp/interconnect@44c00000/segment@200000
 2181 11:29:28.852247  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 2182 11:29:28.960296  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 2183 11:29:29.034633  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 2184 11:29:29.109003  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 2185 11:29:29.186944  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 2186 11:29:29.257740  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 2187 11:29:29.334579  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 2188 11:29:29.404685  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 2189 11:29:29.479228  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 2190 11:29:29.553398  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 2191 11:29:29.627028  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 2192 11:29:29.699652  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 2193 11:29:29.774905  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 2194 11:29:29.850741  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 2195 11:29:29.922117  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 2196 11:29:29.995143  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 2197 11:29:30.074909  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 2198 11:29:30.142596  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 2199 11:29:30.215115  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 2200 11:29:30.293877  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 2201 11:29:30.367570  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 2202 11:29:30.436587  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 2203 11:29:30.512664  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 2204 11:29:30.589425  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 2205 11:29:30.663349  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 2206 11:29:30.734288  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 2207 11:29:30.807674  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 2208 11:29:30.881106  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 2209 11:29:30.956840  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 2210 11:29:31.035870  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 2211 11:29:31.104381  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 2212 11:29:31.179190  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 2213 11:29:31.253979  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 2214 11:29:31.327492  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 2215 11:29:31.402168  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 2216 11:29:31.474847  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 2217 11:29:31.554752  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 2218 11:29:31.624073  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 2219 11:29:31.699154  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 2220 11:29:31.778850  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 2221 11:29:31.849198  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 2222 11:29:31.926929  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 2223 11:29:31.999487  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 2224 11:29:32.072401  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 2225 11:29:32.144808  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 2226 11:29:32.217130  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 2227 11:29:32.291171  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 2228 11:29:32.365034  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 2229 11:29:32.440760  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 2230 11:29:32.514530  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 2231 11:29:32.586886  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 2232 11:29:32.665835  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 2233 11:29:32.737256  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 2234 11:29:32.812286  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 2235 11:29:32.881510  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 2236 11:29:32.954928  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 2237 11:29:33.029629  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 2238 11:29:33.106202  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 2239 11:29:33.179866  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 2240 11:29:33.254709  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 2241 11:29:33.324097  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 2242 11:29:33.396769  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 2243 11:29:33.472168  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 2244 11:29:33.614273  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 2245 11:29:33.629317  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 2246 11:29:33.707109  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 2247 11:29:33.779763  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 2248 11:29:33.853280  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 2249 11:29:33.920259  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 2250 11:29:33.995738  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 2251 11:29:34.070856  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 2252 11:29:34.143168  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 2253 11:29:34.216620  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 2254 11:29:34.290739  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 2255 11:29:34.366828  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 2256 11:29:34.441676  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 2257 11:29:34.517164  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 2258 11:29:34.591951  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 2259 11:29:34.665810  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 2260 11:29:34.749195  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 2261 11:29:34.767703  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 2262 11:29:34.788283  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 2263 11:29:34.813967  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 2264 11:29:34.837398  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 2265 11:29:34.861962  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 2266 11:29:34.886097  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 2267 11:29:34.915699  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 2268 11:29:34.936274  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 2269 11:29:35.042240  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 2270 11:29:35.073602  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 2271 11:29:35.097222  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 2272 11:29:35.120762  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 2273 11:29:35.234147  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 2274 11:29:35.310080  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 2275 11:29:35.383080  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 2276 11:29:35.455779  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 2277 11:29:35.529621  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 2278 11:29:35.604396  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 2279 11:29:35.676988  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 2280 11:29:35.752734  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 2281 11:29:35.826265  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 2282 11:29:35.902154  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 2283 11:29:35.975931  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 2284 11:29:36.054191  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 2285 11:29:36.128729  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 2286 11:29:36.202976  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 2287 11:29:36.277939  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 2288 11:29:36.356048  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 2289 11:29:36.375909  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 2290 11:29:36.447277  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 2291 11:29:36.523683  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 2292 11:29:36.597069  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 2293 11:29:36.621968  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 2294 11:29:36.690986  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 2295 11:29:36.713693  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 2296 11:29:36.792061  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 2297 11:29:36.814662  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 2298 11:29:36.836270  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 2299 11:29:36.863190  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 2300 11:29:36.886637  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 2301 11:29:36.907171  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 2302 11:29:36.936169  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 2303 11:29:36.965248  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
 2304 11:29:37.034304  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
 2305 11:29:37.063881  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 2306 11:29:37.082218  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 2307 11:29:37.156850  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 2308 11:29:37.229245  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 2309 11:29:37.250798  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 2310 11:29:37.354022  # not ok 144 /ocp/interconnect@47c00000
 2311 11:29:37.432190  # not ok 145 /ocp/interconnect@47c00000/segment@0
 2312 11:29:37.452031  # ok 146 /ocp/interconnect@48000000
 2313 11:29:37.477702  # ok 147 /ocp/interconnect@48000000/segment@0
 2314 11:29:37.504161  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 2315 11:29:37.525502  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 2316 11:29:37.547810  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 2317 11:29:37.570189  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 2318 11:29:37.595811  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 2319 11:29:37.619198  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 2320 11:29:37.642692  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 2321 11:29:37.714945  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 2322 11:29:37.794233  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 2323 11:29:37.815694  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 2324 11:29:37.842440  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 2325 11:29:37.865147  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 2326 11:29:37.886821  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 2327 11:29:37.912582  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 2328 11:29:37.937077  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 2329 11:29:37.956504  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 2330 11:29:37.981099  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 2331 11:29:38.004576  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 2332 11:29:38.028872  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 2333 11:29:38.055909  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 2334 11:29:38.080570  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 2335 11:29:38.104171  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 2336 11:29:38.126640  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 2337 11:29:38.149161  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 2338 11:29:38.176999  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 2339 11:29:38.196336  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 2340 11:29:38.220904  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 2341 11:29:38.243026  # ok 175 /ocp/interconnect@48000000/segment@100000
 2342 11:29:38.268470  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 2343 11:29:38.292183  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 2344 11:29:38.366646  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
 2345 11:29:38.442075  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
 2346 11:29:38.594202  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
 2347 11:29:38.603480  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
 2348 11:29:38.670969  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
 2349 11:29:38.740250  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
 2350 11:29:38.813752  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
 2351 11:29:38.889543  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
 2352 11:29:38.909929  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 2353 11:29:38.933349  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 2354 11:29:38.958946  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 2355 11:29:38.981494  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 2356 11:29:39.005137  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 2357 11:29:39.030762  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 2358 11:29:39.053165  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 2359 11:29:39.077938  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 2360 11:29:39.105812  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 2361 11:29:39.126314  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 2362 11:29:39.148648  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 2363 11:29:39.173185  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 2364 11:29:39.195732  # ok 198 /ocp/interconnect@48000000/segment@200000
 2365 11:29:39.220316  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 2366 11:29:39.296742  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 2367 11:29:39.316772  # ok 201 /ocp/interconnect@48000000/segment@300000
 2368 11:29:39.341199  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 2369 11:29:39.365221  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 2370 11:29:39.389428  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 2371 11:29:39.413157  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 2372 11:29:39.436388  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 2373 11:29:39.465181  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 2374 11:29:39.536208  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 2375 11:29:39.554940  # ok 209 /ocp/interconnect@4a000000
 2376 11:29:39.577060  # ok 210 /ocp/interconnect@4a000000/segment@0
 2377 11:29:39.605889  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 2378 11:29:39.628159  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 2379 11:29:39.653008  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 2380 11:29:39.679902  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 2381 11:29:39.748744  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 2382 11:29:39.858859  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 2383 11:29:39.938048  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 2384 11:29:40.045493  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 2385 11:29:40.117849  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 2386 11:29:40.192280  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 2387 11:29:40.293477  # not ok 221 /ocp/interconnect@4b140000
 2388 11:29:40.364149  # not ok 222 /ocp/interconnect@4b140000/segment@0
 2389 11:29:40.442314  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 2390 11:29:40.462374  # ok 224 /ocp/target-module@40300000
 2391 11:29:40.489894  # ok 225 /ocp/target-module@40300000/sram@0
 2392 11:29:40.558605  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 2393 11:29:40.634862  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 2394 11:29:40.659011  # ok 228 /ocp/target-module@47400000
 2395 11:29:40.679034  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 2396 11:29:40.704520  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 2397 11:29:40.728975  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 2398 11:29:40.752232  # ok 232 /ocp/target-module@47400000/usb@1400
 2399 11:29:40.773472  # ok 233 /ocp/target-module@47400000/usb@1800
 2400 11:29:40.798970  # ok 234 /ocp/target-module@47810000
 2401 11:29:40.821023  # ok 235 /ocp/target-module@49000000
 2402 11:29:40.843181  # ok 236 /ocp/target-module@49000000/dma@0
 2403 11:29:40.868475  # ok 237 /ocp/target-module@49800000
 2404 11:29:40.888630  # ok 238 /ocp/target-module@49800000/dma@0
 2405 11:29:40.913810  # ok 239 /ocp/target-module@49900000
 2406 11:29:40.938167  # ok 240 /ocp/target-module@49900000/dma@0
 2407 11:29:40.957847  # ok 241 /ocp/target-module@49a00000
 2408 11:29:40.983162  # ok 242 /ocp/target-module@49a00000/dma@0
 2409 11:29:41.003004  # ok 243 /ocp/target-module@4c000000
 2410 11:29:41.078041  # not ok 244 /ocp/target-module@4c000000/emif@0
 2411 11:29:41.102249  # ok 245 /ocp/target-module@50000000
 2412 11:29:41.127734  # ok 246 /ocp/target-module@53100000
 2413 11:29:41.200628  # not ok 247 /ocp/target-module@53100000/sham@0
 2414 11:29:41.218174  # ok 248 /ocp/target-module@53500000
 2415 11:29:41.293070  # not ok 249 /ocp/target-module@53500000/aes@0
 2416 11:29:41.314829  # ok 250 /ocp/target-module@56000000
 2417 11:29:41.424682  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 2418 11:29:41.497086  # ok 252 /opp-table # SKIP
 2419 11:29:41.570741  # ok 253 /soc # SKIP
 2420 11:29:41.586965  # ok 254 /sound
 2421 11:29:41.611824  # ok 255 /target-module@4b000000
 2422 11:29:41.641450  # ok 256 /target-module@4b000000/target-module@140000
 2423 11:29:41.658379  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 2424 11:29:41.665815  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 2425 11:29:41.673012  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 2426 11:29:44.066626  dt_test_unprobed_devices_sh_ skip
 2427 11:29:44.072600  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 2428 11:29:44.078727  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 2429 11:29:44.079108  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 2430 11:29:44.085961  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 2431 11:29:44.086340  dt_test_unprobed_devices_sh_fixedregulator0 pass
 2432 11:29:44.092109  dt_test_unprobed_devices_sh_leds pass
 2433 11:29:44.096966  dt_test_unprobed_devices_sh_ocp pass
 2434 11:29:44.101959  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 2435 11:29:44.105609  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 2436 11:29:44.111734  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 2437 11:29:44.122519  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 2438 11:29:44.127465  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 2439 11:29:44.138470  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 2440 11:29:44.143409  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 2441 11:29:44.154629  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 2442 11:29:44.164238  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 2443 11:29:44.175414  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 2444 11:29:44.180240  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 2445 11:29:44.190037  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 2446 11:29:44.201008  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 2447 11:29:44.210910  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 2448 11:29:44.221912  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 2449 11:29:44.231592  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 2450 11:29:44.242557  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 2451 11:29:44.252293  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 2452 11:29:44.263381  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 2453 11:29:44.273203  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 2454 11:29:44.284234  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 2455 11:29:44.294016  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 2456 11:29:44.300109  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 2457 11:29:44.309913  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 2458 11:29:44.321066  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 2459 11:29:44.330697  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 2460 11:29:44.341907  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 2461 11:29:44.351457  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 2462 11:29:44.362522  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 2463 11:29:44.372382  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 2464 11:29:44.383473  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 2465 11:29:44.393130  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 2466 11:29:44.404280  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 2467 11:29:44.413923  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 2468 11:29:44.425071  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 2469 11:29:44.434805  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 2470 11:29:44.445899  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 2471 11:29:44.460651  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 2472 11:29:44.471621  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 2473 11:29:44.481313  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 2474 11:29:44.492343  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 2475 11:29:44.502150  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 2476 11:29:44.513071  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 2477 11:29:44.529065  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 2478 11:29:44.538814  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 2479 11:29:44.549933  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 2480 11:29:44.559578  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 2481 11:29:44.570751  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 2482 11:29:44.585389  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 2483 11:29:44.591472  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 2484 11:29:44.606151  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 2485 11:29:44.617112  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 2486 11:29:44.626848  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 2487 11:29:44.637909  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 2488 11:29:44.647603  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 2489 11:29:44.658608  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 2490 11:29:44.668377  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 2491 11:29:44.679385  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 2492 11:29:44.689388  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 2493 11:29:44.700386  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 2494 11:29:44.710120  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 2495 11:29:44.721149  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 2496 11:29:44.730875  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 2497 11:29:44.741873  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 2498 11:29:44.757835  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 2499 11:29:44.767478  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 2500 11:29:44.778611  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 2501 11:29:44.788268  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 2502 11:29:44.799432  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 2503 11:29:44.809177  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 2504 11:29:44.820438  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 2505 11:29:44.830023  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 2506 11:29:44.841188  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 2507 11:29:44.855944  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 2508 11:29:44.866792  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 2509 11:29:44.876505  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 2510 11:29:44.882632  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 2511 11:29:44.893803  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 2512 11:29:44.903419  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 2513 11:29:44.914393  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 2514 11:29:44.925497  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 2515 11:29:44.940176  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 2516 11:29:44.946305  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 2517 11:29:44.960952  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 2518 11:29:44.971908  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 2519 11:29:44.981822  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 2520 11:29:44.992893  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 2521 11:29:45.002633  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 2522 11:29:45.013689  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 2523 11:29:45.023392  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 2524 11:29:45.029547  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 2525 11:29:45.039139  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 2526 11:29:45.050273  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 2527 11:29:45.055182  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 2528 11:29:45.064956  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 2529 11:29:45.075929  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 2530 11:29:45.085790  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 2531 11:29:45.096837  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 2532 11:29:45.107752  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 2533 11:29:45.118749  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 2534 11:29:45.129707  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 2535 11:29:45.140826  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 2536 11:29:45.150619  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 2537 11:29:45.161835  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 2538 11:29:45.177558  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 2539 11:29:45.187415  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 2540 11:29:45.197797  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 2541 11:29:45.213796  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 2542 11:29:45.224956  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 2543 11:29:45.234666  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 2544 11:29:45.245926  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 2545 11:29:45.260955  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 2546 11:29:45.276878  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 2547 11:29:45.287929  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 2548 11:29:45.297933  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 2549 11:29:45.309204  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 2550 11:29:45.315437  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 2551 11:29:45.326554  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 2552 11:29:45.332957  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 2553 11:29:45.344037  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 2554 11:29:45.353929  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 2555 11:29:45.360202  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 2556 11:29:45.371335  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 2557 11:29:45.376425  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 2558 11:29:45.388957  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 2559 11:29:45.393798  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 2560 11:29:45.403799  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 2561 11:29:45.409927  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 2562 11:29:45.421192  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
 2563 11:29:45.432330  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
 2564 11:29:45.444954  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 2565 11:29:45.448827  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 2566 11:29:45.461062  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 2567 11:29:45.472199  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 2568 11:29:45.477172  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 2569 11:29:45.483221  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 2570 11:29:45.488172  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 2571 11:29:45.494425  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 2572 11:29:45.499315  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 2573 11:29:45.511674  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 2574 11:29:45.516554  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 2575 11:29:45.526426  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 2576 11:29:45.532563  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 2577 11:29:45.542491  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 2578 11:29:45.553810  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 2579 11:29:45.558601  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 2580 11:29:45.568680  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 2581 11:29:45.574809  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 2582 11:29:45.584510  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 2583 11:29:45.589545  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 2584 11:29:45.600960  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 2585 11:29:45.605659  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 2586 11:29:45.616947  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 2587 11:29:45.621792  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 2588 11:29:45.631576  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 2589 11:29:45.641786  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 2590 11:29:45.647820  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 2591 11:29:45.658929  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 2592 11:29:45.663914  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 2593 11:29:45.673754  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 2594 11:29:45.679892  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 2595 11:29:45.689551  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 2596 11:29:45.700902  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 2597 11:29:45.705653  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 2598 11:29:45.715759  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 2599 11:29:45.721890  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 2600 11:29:45.726776  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 2601 11:29:45.736467  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 2602 11:29:45.747594  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 2603 11:29:45.757592  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
 2604 11:29:45.768660  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
 2605 11:29:45.778522  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
 2606 11:29:45.789752  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
 2607 11:29:45.799528  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
 2608 11:29:45.810772  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
 2609 11:29:45.820636  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
 2610 11:29:45.826782  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
 2611 11:29:45.836399  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 2612 11:29:45.847525  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 2613 11:29:45.852780  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 2614 11:29:45.862655  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 2615 11:29:45.867755  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 2616 11:29:45.879019  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 2617 11:29:45.883876  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 2618 11:29:45.896269  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 2619 11:29:45.906026  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 2620 11:29:45.911138  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 2621 11:29:45.922153  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 2622 11:29:45.932015  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 2623 11:29:45.938225  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 2624 11:29:45.943149  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 2625 11:29:45.953127  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 2626 11:29:45.959276  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 2627 11:29:45.969153  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 2628 11:29:45.974141  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 2629 11:29:45.985282  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 2630 11:29:45.995053  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 2631 11:29:46.001200  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 2632 11:29:46.011085  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 2633 11:29:46.016093  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 2634 11:29:46.022258  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 2635 11:29:46.027263  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 2636 11:29:46.037173  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 2637 11:29:46.048137  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 2638 11:29:46.058147  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 2639 11:29:46.064272  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 2640 11:29:46.073956  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 2641 11:29:46.079253  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 2642 11:29:46.090213  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 2643 11:29:46.100041  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 2644 11:29:46.111348  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 2645 11:29:46.121151  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 2646 11:29:46.127341  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 2647 11:29:46.132290  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 2648 11:29:46.137232  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 2649 11:29:46.142385  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 2650 11:29:46.148459  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 2651 11:29:46.158173  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 2652 11:29:46.163376  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 2653 11:29:46.169516  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 2654 11:29:46.180865  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 2655 11:29:46.184771  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 2656 11:29:46.190895  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 2657 11:29:46.196954  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 2658 11:29:46.201867  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 2659 11:29:46.208249  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 2660 11:29:46.213107  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 2661 11:29:46.219250  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 2662 11:29:46.225306  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 2663 11:29:46.230254  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 2664 11:29:46.235001  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 2665 11:29:46.240137  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 2666 11:29:46.246219  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 2667 11:29:46.251142  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 2668 11:29:46.256019  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 2669 11:29:46.267239  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 2670 11:29:46.267620  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 2671 11:29:46.272137  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 2672 11:29:46.281976  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 2673 11:29:46.288032  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 2674 11:29:46.293005  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 2675 11:29:46.297763  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 2676 11:29:46.301713  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 2677 11:29:46.307840  dt_test_unprobed_devices_sh_opp-table skip
 2678 11:29:46.308217  dt_test_unprobed_devices_sh_soc skip
 2679 11:29:46.312861  dt_test_unprobed_devices_sh_sound pass
 2680 11:29:46.317968  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 2681 11:29:46.324036  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 2682 11:29:46.335143  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 2683 11:29:46.335526  dt_test_unprobed_devices_sh fail
 2684 11:29:46.339817  + ../../utils/send-to-lava.sh ./output/result.txt
 2685 11:29:46.443186  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 2686 11:29:46.444418  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 2688 11:29:46.611106  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 2689 11:29:46.611722  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 2691 11:29:46.817038  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 2692 11:29:46.817656  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 2694 11:29:47.007266  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 2695 11:29:47.007884  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 2697 11:29:47.190071  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 2698 11:29:47.190687  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 2700 11:29:47.404851  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 2701 11:29:47.405467  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 2703 11:29:47.603386  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 2704 11:29:47.604001  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 2706 11:29:47.812105  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 2707 11:29:47.812721  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 2709 11:29:48.029402  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 2710 11:29:48.030019  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 2712 11:29:48.274763  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 2713 11:29:48.275379  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 2715 11:29:48.453635  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 2716 11:29:48.454252  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 2718 11:29:48.650797  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 2719 11:29:48.651419  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 2721 11:29:48.848993  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 2722 11:29:48.849610  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 2724 11:29:49.059558  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 2725 11:29:49.059895  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 2727 11:29:49.262986  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 2728 11:29:49.263605  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 2730 11:29:49.505546  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 2731 11:29:49.506159  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 2733 11:29:49.702949  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 2734 11:29:49.703565  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 2736 11:29:49.944366  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 2737 11:29:49.945007  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 2739 11:29:50.131336  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 2740 11:29:50.131951  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 2742 11:29:50.388911  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 2743 11:29:50.389530  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 2745 11:29:50.609507  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 2746 11:29:50.610127  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 2748 11:29:50.930360  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 2749 11:29:50.930983  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 2751 11:29:51.166778  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 2752 11:29:51.167400  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 2754 11:29:51.441002  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 2755 11:29:51.441621  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 2757 11:29:51.756520  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 2758 11:29:51.757166  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 2760 11:29:51.927698  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 2761 11:29:51.928317  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 2763 11:29:52.135353  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 2764 11:29:52.135976  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 2766 11:29:52.326994  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 2767 11:29:52.327617  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 2769 11:29:52.615528  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 2770 11:29:52.616145  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 2772 11:29:52.813967  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 2773 11:29:52.814585  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 2775 11:29:53.049206  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 2776 11:29:53.049827  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 2778 11:29:53.266905  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 2779 11:29:53.267526  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 2781 11:29:53.457001  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 2782 11:29:53.457622  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 2784 11:29:53.655375  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 2785 11:29:53.656008  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 2787 11:29:53.838138  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 2788 11:29:53.838762  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 2790 11:29:54.008033  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 2791 11:29:54.008651  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 2793 11:29:54.192028  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 2794 11:29:54.192646  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 2796 11:29:54.417020  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 2797 11:29:54.417641  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 2799 11:29:54.622750  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 2800 11:29:54.623370  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 2802 11:29:54.821719  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 2803 11:29:54.822336  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 2805 11:29:55.016711  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 2806 11:29:55.017352  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 2808 11:29:55.209841  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 2809 11:29:55.210462  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 2811 11:29:55.409534  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 2812 11:29:55.410158  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 2814 11:29:55.614808  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 2815 11:29:55.615430  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 2817 11:29:55.827052  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 2818 11:29:55.827670  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 2820 11:29:56.068872  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 2821 11:29:56.069496  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 2823 11:29:56.259943  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 2824 11:29:56.260558  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 2826 11:29:56.499726  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 2827 11:29:56.500346  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 2829 11:29:56.717243  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 2830 11:29:56.717860  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 2832 11:29:56.907441  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 2833 11:29:56.908060  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 2835 11:29:57.083933  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 2836 11:29:57.084554  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 2838 11:29:57.266692  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 2839 11:29:57.267311  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 2841 11:29:57.426167  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 2842 11:29:57.426784  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 2844 11:29:57.608002  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 2845 11:29:57.608624  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 2847 11:29:57.794898  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 2848 11:29:57.795520  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 2850 11:29:57.985873  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 2851 11:29:57.986494  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 2853 11:29:58.186738  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 2854 11:29:58.187359  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 2856 11:29:58.381578  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 2857 11:29:58.382198  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 2859 11:29:58.564721  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 2860 11:29:58.565368  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 2862 11:29:58.739247  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 2863 11:29:58.739872  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 2865 11:29:58.951638  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 2866 11:29:58.952260  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 2868 11:29:59.126854  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 2869 11:29:59.127474  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 2871 11:29:59.335899  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 2872 11:29:59.336518  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 2874 11:29:59.582703  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 2875 11:29:59.583321  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 2877 11:29:59.782454  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 2878 11:29:59.783069  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 2880 11:29:59.949780  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 2881 11:29:59.950400  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 2883 11:30:00.126067  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 2884 11:30:00.126688  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 2886 11:30:00.307957  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 2887 11:30:00.308579  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 2889 11:30:00.504686  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 2890 11:30:00.505330  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 2892 11:30:00.700921  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 2893 11:30:00.701539  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 2895 11:30:00.883800  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 2896 11:30:00.884418  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 2898 11:30:01.084319  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 2899 11:30:01.084939  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 2901 11:30:01.291006  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 2902 11:30:01.291624  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 2904 11:30:01.465393  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 2905 11:30:01.466008  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 2907 11:30:01.700575  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 2908 11:30:01.701233  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 2910 11:30:01.917272  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 2911 11:30:01.917904  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 2913 11:30:02.144761  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 2914 11:30:02.145422  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 2916 11:30:02.366244  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 2917 11:30:02.366864  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 2919 11:30:02.563517  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 2920 11:30:02.564141  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 2922 11:30:02.800873  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 2923 11:30:02.801492  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 2925 11:30:03.012291  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 2926 11:30:03.012896  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 2928 11:30:03.245755  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 2929 11:30:03.246375  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 2931 11:30:03.472970  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 2932 11:30:03.473585  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 2934 11:30:03.709511  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 2935 11:30:03.710134  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 2937 11:30:03.930870  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 2938 11:30:03.931490  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 2940 11:30:04.161590  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 2941 11:30:04.162207  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 2943 11:30:04.381367  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 2944 11:30:04.381990  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 2946 11:30:04.617871  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 2947 11:30:04.618495  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 2949 11:30:04.830052  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 2950 11:30:04.830669  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 2952 11:30:05.044721  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 2953 11:30:05.045378  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 2955 11:30:05.262547  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 2956 11:30:05.262951  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 2958 11:30:05.524621  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 2959 11:30:05.525308  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 2961 11:30:05.750607  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 2962 11:30:05.751231  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 2964 11:30:05.967234  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 2965 11:30:05.967857  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 2967 11:30:06.193495  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 2968 11:30:06.194132  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 2970 11:30:06.399611  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 2971 11:30:06.400237  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 2973 11:30:06.597968  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 2974 11:30:06.598591  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 2976 11:30:06.863100  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 2977 11:30:06.863722  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 2979 11:30:07.072904  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 2980 11:30:07.073526  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 2982 11:30:07.285793  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 2983 11:30:07.286423  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 2985 11:30:07.562638  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 2986 11:30:07.563259  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 2988 11:30:07.769321  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 2989 11:30:07.769938  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 2991 11:30:07.982606  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 2992 11:30:07.983228  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 2994 11:30:08.242076  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 2995 11:30:08.242701  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 2997 11:30:08.499908  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 2998 11:30:08.500527  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 3000 11:30:08.716569  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 3001 11:30:08.717249  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 3003 11:30:08.937171  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 3004 11:30:08.937796  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 3006 11:30:09.184351  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 3007 11:30:09.184971  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 3009 11:30:09.407590  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 3010 11:30:09.408213  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 3012 11:30:09.606224  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 3013 11:30:09.606840  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 3015 11:30:09.847241  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 3016 11:30:09.847863  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 3018 11:30:10.074839  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 3019 11:30:10.075465  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 3021 11:30:10.282134  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 3022 11:30:10.282761  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 3024 11:30:10.498948  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 3025 11:30:10.499568  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 3027 11:30:10.745982  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 3028 11:30:10.746605  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 3030 11:30:10.981856  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 3031 11:30:10.982476  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 3033 11:30:11.215553  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 3034 11:30:11.216174  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 3036 11:30:11.426135  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 3037 11:30:11.426758  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 3039 11:30:11.657636  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 3040 11:30:11.658258  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 3042 11:30:11.965843  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 3043 11:30:11.966466  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 3045 11:30:12.197538  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 3047 11:30:12.200552  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 3048 11:30:12.436656  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 3050 11:30:12.439817  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 3051 11:30:12.665147  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 3053 11:30:12.668134  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 3054 11:30:12.908807  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 3055 11:30:12.909445  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 3057 11:30:13.140938  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 3058 11:30:13.141562  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 3060 11:30:13.351967  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 3061 11:30:13.352593  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 3063 11:30:13.567979  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 3064 11:30:13.568599  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 3066 11:30:13.782086  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 3067 11:30:13.782703  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 3069 11:30:14.033034  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 3070 11:30:14.033660  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 3072 11:30:14.265091  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 3073 11:30:14.265712  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 3075 11:30:14.505579  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 3076 11:30:14.506197  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 3078 11:30:14.757757  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 3079 11:30:14.758372  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 3081 11:30:14.997361  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 3082 11:30:14.997977  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 3084 11:30:15.249414  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 3085 11:30:15.250026  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 3087 11:30:15.483534  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 3088 11:30:15.484153  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 3090 11:30:15.767102  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 3091 11:30:15.767719  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 3093 11:30:15.959063  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 3094 11:30:15.959687  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 3096 11:30:16.160810  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
 3097 11:30:16.161436  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
 3099 11:30:16.420772  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
 3100 11:30:16.421424  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
 3102 11:30:16.685802  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 3103 11:30:16.686424  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 3105 11:30:16.933937  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 3106 11:30:16.934564  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 3108 11:30:17.175524  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 3109 11:30:17.176140  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 3111 11:30:17.436258  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 3112 11:30:17.436885  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 3114 11:30:17.698923  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 3115 11:30:17.699540  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 3117 11:30:17.923174  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 3118 11:30:17.923802  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 3120 11:30:18.150745  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 3121 11:30:18.151362  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 3123 11:30:18.382126  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 3124 11:30:18.382746  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 3126 11:30:18.616183  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 3127 11:30:18.616836  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 3129 11:30:18.886205  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 3130 11:30:18.886822  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 3132 11:30:19.134117  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 3133 11:30:19.134735  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 3135 11:30:19.344917  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 3136 11:30:19.345620  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 3138 11:30:19.603160  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 3139 11:30:19.603815  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 3141 11:30:19.833187  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 3142 11:30:19.833808  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 3144 11:30:20.113710  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 3145 11:30:20.114323  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 3147 11:30:20.361520  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 3148 11:30:20.362134  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 3150 11:30:20.606397  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 3151 11:30:20.607011  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 3153 11:30:20.825319  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 3154 11:30:20.825937  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 3156 11:30:21.064889  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 3157 11:30:21.065509  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 3159 11:30:21.335712  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 3160 11:30:21.336327  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 3162 11:30:21.581660  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 3163 11:30:21.582275  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 3165 11:30:21.849860  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 3166 11:30:21.850482  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 3168 11:30:22.212652  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 3169 11:30:22.213306  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 3171 11:30:22.447894  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 3172 11:30:22.448540  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 3174 11:30:22.716674  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 3175 11:30:22.717335  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 3177 11:30:22.949742  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 3178 11:30:22.950360  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 3180 11:30:23.186997  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 3181 11:30:23.187614  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 3183 11:30:23.438218  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 3184 11:30:23.438831  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 3186 11:30:23.674594  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 3187 11:30:23.675211  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 3189 11:30:23.931786  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 3190 11:30:23.932402  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 3192 11:30:24.173005  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 3193 11:30:24.173622  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 3195 11:30:24.431744  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 3196 11:30:24.432361  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 3198 11:30:24.683699  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 3199 11:30:24.684314  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 3201 11:30:24.932936  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 3202 11:30:24.933552  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 3204 11:30:25.180748  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 3205 11:30:25.181398  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 3207 11:30:25.426407  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 3208 11:30:25.427021  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 3210 11:30:25.675029  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 3211 11:30:25.675648  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 3213 11:30:25.924946  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 3214 11:30:25.925566  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 3216 11:30:26.174670  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 3217 11:30:26.175286  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 3219 11:30:26.433356  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
 3220 11:30:26.433974  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
 3222 11:30:26.691064  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
 3223 11:30:26.691683  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
 3225 11:30:26.960307  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
 3226 11:30:26.960923  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
 3228 11:30:27.306698  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
 3229 11:30:27.307320  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
 3231 11:30:27.557977  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
 3232 11:30:27.558596  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
 3234 11:30:27.771075  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
 3235 11:30:27.771693  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
 3237 11:30:28.023368  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
 3238 11:30:28.023989  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
 3240 11:30:28.269612  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
 3241 11:30:28.270229  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
 3243 11:30:28.510110  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 3244 11:30:28.510732  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 3246 11:30:28.766692  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 3247 11:30:28.767307  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 3249 11:30:28.973535  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 3250 11:30:28.974151  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 3252 11:30:29.199114  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 3253 11:30:29.199733  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 3255 11:30:29.451261  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 3256 11:30:29.451877  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 3258 11:30:29.693707  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 3259 11:30:29.694390  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 3261 11:30:29.934172  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 3262 11:30:29.934828  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 3264 11:30:30.167653  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 3265 11:30:30.168268  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 3267 11:30:30.407949  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 3268 11:30:30.408568  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 3270 11:30:30.641530  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 3271 11:30:30.642146  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 3273 11:30:30.914716  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 3274 11:30:30.915334  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 3276 11:30:31.143645  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 3277 11:30:31.144266  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 3279 11:30:31.400772  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 3280 11:30:31.401426  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 3282 11:30:31.633866  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 3283 11:30:31.634488  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 3285 11:30:31.868849  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 3286 11:30:31.869470  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 3288 11:30:32.094261  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 3289 11:30:32.094879  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 3291 11:30:32.378087  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 3292 11:30:32.378703  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 3294 11:30:32.621701  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 3295 11:30:32.622318  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 3297 11:30:32.854767  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 3298 11:30:32.855384  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 3300 11:30:33.122503  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 3301 11:30:33.123120  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 3303 11:30:33.382243  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 3304 11:30:33.382858  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 3306 11:30:33.611995  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 3307 11:30:33.612611  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 3309 11:30:33.855727  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 3310 11:30:33.856347  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 3312 11:30:34.091403  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 3313 11:30:34.092024  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 3315 11:30:34.331362  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 3316 11:30:34.331977  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 3318 11:30:34.564428  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 3319 11:30:34.565152  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 3321 11:30:34.802770  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 3322 11:30:34.803389  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 3324 11:30:35.058332  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 3325 11:30:35.058951  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 3327 11:30:35.294548  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 3328 11:30:35.295165  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 3330 11:30:35.523544  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 3331 11:30:35.524161  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 3333 11:30:35.754823  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 3334 11:30:35.755441  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 3336 11:30:36.013620  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 3337 11:30:36.014250  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 3339 11:30:36.241543  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 3340 11:30:36.242159  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 3342 11:30:36.478893  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 3343 11:30:36.479511  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 3345 11:30:36.717594  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 3346 11:30:36.718213  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 3348 11:30:36.949148  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 3349 11:30:36.949770  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 3351 11:30:37.212124  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 3352 11:30:37.212772  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 3354 11:30:37.552126  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 3355 11:30:37.552748  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 3357 11:30:37.831414  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
 3358 11:30:37.832030  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
 3360 11:30:38.075663  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
 3361 11:30:38.076277  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
 3363 11:30:38.320451  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
 3364 11:30:38.321101  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
 3366 11:30:38.568554  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
 3368 11:30:38.571567  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
 3369 11:30:38.812409  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
 3370 11:30:38.813067  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
 3372 11:30:39.057961  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
 3373 11:30:39.058578  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
 3375 11:30:39.320435  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
 3376 11:30:39.321074  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
 3378 11:30:39.581995  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
 3379 11:30:39.582611  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
 3381 11:30:39.849634  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
 3382 11:30:39.850254  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
 3384 11:30:40.115221  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
 3385 11:30:40.115839  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
 3387 11:30:40.398620  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
 3388 11:30:40.399238  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
 3390 11:30:40.652452  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
 3391 11:30:40.653088  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
 3393 11:30:40.872522  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
 3394 11:30:40.873169  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
 3396 11:30:41.137147  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
 3397 11:30:41.137766  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
 3399 11:30:41.358321  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
 3400 11:30:41.358939  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
 3402 11:30:41.602344  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
 3403 11:30:41.602959  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
 3405 11:30:41.840489  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
 3406 11:30:41.841130  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
 3408 11:30:42.101902  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
 3409 11:30:42.102518  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
 3411 11:30:42.310402  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
 3412 11:30:42.311024  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
 3414 11:30:42.529300  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
 3415 11:30:42.529916  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
 3417 11:30:42.839388  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
 3418 11:30:42.840003  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
 3420 11:30:43.042470  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
 3421 11:30:43.043085  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
 3423 11:30:43.250059  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
 3424 11:30:43.250674  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
 3426 11:30:43.535528  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
 3427 11:30:43.536142  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
 3429 11:30:43.742921  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
 3430 11:30:43.743537  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
 3432 11:30:43.967468  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
 3433 11:30:43.968084  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
 3435 11:30:44.204230  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
 3436 11:30:44.204863  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
 3438 11:30:44.461313  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
 3439 11:30:44.461961  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
 3441 11:30:44.786777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
 3442 11:30:44.787402  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
 3444 11:30:44.999095  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
 3445 11:30:44.999710  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
 3447 11:30:45.227916  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
 3448 11:30:45.228531  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
 3450 11:30:45.494954  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
 3451 11:30:45.495572  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
 3453 11:30:45.702328  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
 3454 11:30:45.702948  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
 3456 11:30:45.916479  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
 3457 11:30:45.917133  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
 3459 11:30:46.142284  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
 3460 11:30:46.142667  + set +x
 3461 11:30:46.143211  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
 3463 11:30:46.146532  <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1213804_1.6.2.4.5>
 3464 11:30:46.147144  Received signal: <ENDRUN> 1_kselftest-dt 1213804_1.6.2.4.5
 3465 11:30:46.147488  Ending use of test pattern.
 3466 11:30:46.147790  Ending test lava.1_kselftest-dt (1213804_1.6.2.4.5), duration 270.43
 3468 11:30:46.219037  <LAVA_TEST_RUNNER EXIT>
 3469 11:30:46.219674  ok: lava_test_shell seems to have completed
 3470 11:30:46.227405  dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass

 3471 11:30:46.228862  end: 3.1 lava-test-shell (duration 00:04:32) [common]
 3472 11:30:46.229283  end: 3 lava-test-retry (duration 00:04:32) [common]
 3473 11:30:46.229701  start: 4 finalize (timeout 00:01:54) [common]
 3474 11:30:46.230117  start: 4.1 power-off (timeout 00:00:30) [common]
 3475 11:30:46.230607  Calling: 'drpm' 'lf-bbb' 'off'
 3476 11:30:46.614688  >> OFF

 3477 11:30:46.616035  Returned 0 in 0 seconds
 3478 11:30:46.716924  end: 4.1 power-off (duration 00:00:00) [common]
 3480 11:30:46.717987  start: 4.2 read-feedback (timeout 00:01:53) [common]
 3481 11:30:46.718842  Listened to connection for namespace 'common' for up to 1s
 3482 11:30:46.719525  Listened to connection for namespace 'common' for up to 1s
 3483 11:30:47.719010  Finalising connection for namespace 'common'
 3484 11:30:47.719498  Disconnecting from shell: Finalise
 3485 11:30:47.719879  / # 
 3486 11:30:47.820618  end: 4.2 read-feedback (duration 00:00:01) [common]
 3487 11:30:47.821144  end: 4 finalize (duration 00:00:02) [common]
 3488 11:30:47.821634  Cleaning after the job
 3489 11:30:47.822088  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/ramdisk
 3490 11:30:47.827851  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/kernel
 3491 11:30:47.832409  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/dtb
 3492 11:30:47.833142  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/nfsrootfs
 3493 11:30:47.945044  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1213804/tftp-deploy-qte23qrv/modules
 3494 11:30:47.950258  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1213804
 3495 11:30:49.216656  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1213804
 3496 11:30:49.217169  Job finished correctly