Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 11:33:55.162696 lava-dispatcher, installed at version: 2024.01
2 11:33:55.163475 start: 0 validate
3 11:33:55.163963 Start time: 2024-10-30 11:33:55.163934+00:00 (UTC)
4 11:33:55.164527 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 11:33:55.165048 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 11:33:55.209666 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 11:33:55.210216 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 11:33:55.243893 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 11:33:55.244584 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 11:33:55.276755 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 11:33:55.277234 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:33:55.308497 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 11:33:55.308971 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
14 11:33:55.353494 validate duration: 0.19
16 11:33:55.354935 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:33:55.355512 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:33:55.356118 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:33:55.357043 Not decompressing ramdisk as can be used compressed.
20 11:33:55.357761 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 11:33:55.358245 saving as /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/ramdisk/initrd.cpio.gz
22 11:33:55.358719 total size: 5628182 (5 MB)
23 11:33:55.400621 progress 0 % (0 MB)
24 11:33:55.409905 progress 5 % (0 MB)
25 11:33:55.419828 progress 10 % (0 MB)
26 11:33:55.428744 progress 15 % (0 MB)
27 11:33:55.435242 progress 20 % (1 MB)
28 11:33:55.439629 progress 25 % (1 MB)
29 11:33:55.444524 progress 30 % (1 MB)
30 11:33:55.449341 progress 35 % (1 MB)
31 11:33:55.453661 progress 40 % (2 MB)
32 11:33:55.458506 progress 45 % (2 MB)
33 11:33:55.462816 progress 50 % (2 MB)
34 11:33:55.467607 progress 55 % (2 MB)
35 11:33:55.472380 progress 60 % (3 MB)
36 11:33:55.476652 progress 65 % (3 MB)
37 11:33:55.481457 progress 70 % (3 MB)
38 11:33:55.485762 progress 75 % (4 MB)
39 11:33:55.490561 progress 80 % (4 MB)
40 11:33:55.494845 progress 85 % (4 MB)
41 11:33:55.499505 progress 90 % (4 MB)
42 11:33:55.503866 progress 95 % (5 MB)
43 11:33:55.507876 progress 100 % (5 MB)
44 11:33:55.508838 5 MB downloaded in 0.15 s (35.76 MB/s)
45 11:33:55.509518 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:33:55.510595 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:33:55.510947 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:33:55.511277 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:33:55.511842 downloading http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
51 11:33:55.512172 saving as /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/kernel/Image
52 11:33:55.512427 total size: 46256640 (44 MB)
53 11:33:55.512679 No compression specified
54 11:33:55.552203 progress 0 % (0 MB)
55 11:33:55.580858 progress 5 % (2 MB)
56 11:33:55.609813 progress 10 % (4 MB)
57 11:33:55.638203 progress 15 % (6 MB)
58 11:33:55.666907 progress 20 % (8 MB)
59 11:33:55.695259 progress 25 % (11 MB)
60 11:33:55.724061 progress 30 % (13 MB)
61 11:33:55.752905 progress 35 % (15 MB)
62 11:33:55.781707 progress 40 % (17 MB)
63 11:33:55.810424 progress 45 % (19 MB)
64 11:33:55.838802 progress 50 % (22 MB)
65 11:33:55.867700 progress 55 % (24 MB)
66 11:33:55.896292 progress 60 % (26 MB)
67 11:33:55.924774 progress 65 % (28 MB)
68 11:33:55.953570 progress 70 % (30 MB)
69 11:33:55.982142 progress 75 % (33 MB)
70 11:33:56.011203 progress 80 % (35 MB)
71 11:33:56.039658 progress 85 % (37 MB)
72 11:33:56.068525 progress 90 % (39 MB)
73 11:33:56.097386 progress 95 % (41 MB)
74 11:33:56.125182 progress 100 % (44 MB)
75 11:33:56.125875 44 MB downloaded in 0.61 s (71.91 MB/s)
76 11:33:56.126358 end: 1.2.1 http-download (duration 00:00:01) [common]
78 11:33:56.127175 end: 1.2 download-retry (duration 00:00:01) [common]
79 11:33:56.127450 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:33:56.127716 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:33:56.128206 downloading http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 11:33:56.128484 saving as /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/dtb/meson-g12b-a311d-libretech-cc.dtb
83 11:33:56.128693 total size: 54703 (0 MB)
84 11:33:56.128902 No compression specified
85 11:33:56.173331 progress 59 % (0 MB)
86 11:33:56.174794 progress 100 % (0 MB)
87 11:33:56.175391 0 MB downloaded in 0.05 s (1.12 MB/s)
88 11:33:56.175855 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:33:56.176715 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:33:56.176983 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:33:56.177247 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:33:56.177699 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 11:33:56.177942 saving as /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/nfsrootfs/full.rootfs.tar
95 11:33:56.178146 total size: 107552908 (102 MB)
96 11:33:56.178355 Using unxz to decompress xz
97 11:33:56.219059 progress 0 % (0 MB)
98 11:33:56.850929 progress 5 % (5 MB)
99 11:33:57.572760 progress 10 % (10 MB)
100 11:33:58.328704 progress 15 % (15 MB)
101 11:33:59.085000 progress 20 % (20 MB)
102 11:33:59.650262 progress 25 % (25 MB)
103 11:34:00.269291 progress 30 % (30 MB)
104 11:34:01.003408 progress 35 % (35 MB)
105 11:34:01.350791 progress 40 % (41 MB)
106 11:34:01.770086 progress 45 % (46 MB)
107 11:34:02.456628 progress 50 % (51 MB)
108 11:34:03.134218 progress 55 % (56 MB)
109 11:34:03.880925 progress 60 % (61 MB)
110 11:34:04.626330 progress 65 % (66 MB)
111 11:34:05.347005 progress 70 % (71 MB)
112 11:34:06.110174 progress 75 % (76 MB)
113 11:34:06.777687 progress 80 % (82 MB)
114 11:34:07.476009 progress 85 % (87 MB)
115 11:34:08.193196 progress 90 % (92 MB)
116 11:34:08.896611 progress 95 % (97 MB)
117 11:34:09.630230 progress 100 % (102 MB)
118 11:34:09.641889 102 MB downloaded in 13.46 s (7.62 MB/s)
119 11:34:09.642770 end: 1.4.1 http-download (duration 00:00:13) [common]
121 11:34:09.644449 end: 1.4 download-retry (duration 00:00:13) [common]
122 11:34:09.644984 start: 1.5 download-retry (timeout 00:09:46) [common]
123 11:34:09.645510 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 11:34:09.646317 downloading http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
125 11:34:09.646784 saving as /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/modules/modules.tar
126 11:34:09.647200 total size: 11596668 (11 MB)
127 11:34:09.647625 Using unxz to decompress xz
128 11:34:09.697432 progress 0 % (0 MB)
129 11:34:09.772231 progress 5 % (0 MB)
130 11:34:09.854148 progress 10 % (1 MB)
131 11:34:09.941648 progress 15 % (1 MB)
132 11:34:10.025028 progress 20 % (2 MB)
133 11:34:10.108221 progress 25 % (2 MB)
134 11:34:10.194720 progress 30 % (3 MB)
135 11:34:10.274064 progress 35 % (3 MB)
136 11:34:10.362384 progress 40 % (4 MB)
137 11:34:10.457192 progress 45 % (5 MB)
138 11:34:10.541427 progress 50 % (5 MB)
139 11:34:10.633119 progress 55 % (6 MB)
140 11:34:10.722009 progress 60 % (6 MB)
141 11:34:10.814389 progress 65 % (7 MB)
142 11:34:10.897382 progress 70 % (7 MB)
143 11:34:10.988151 progress 75 % (8 MB)
144 11:34:11.078302 progress 80 % (8 MB)
145 11:34:11.161032 progress 85 % (9 MB)
146 11:34:11.240604 progress 90 % (9 MB)
147 11:34:11.350412 progress 95 % (10 MB)
148 11:34:11.451429 progress 100 % (11 MB)
149 11:34:11.467236 11 MB downloaded in 1.82 s (6.08 MB/s)
150 11:34:11.468040 end: 1.5.1 http-download (duration 00:00:02) [common]
152 11:34:11.469957 end: 1.5 download-retry (duration 00:00:02) [common]
153 11:34:11.470615 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 11:34:11.471270 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 11:34:21.306189 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/913381/extract-nfsrootfs-5l6mg_f1
156 11:34:21.306784 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 11:34:21.307075 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 11:34:21.307711 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53
159 11:34:21.308248 makedir: /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin
160 11:34:21.308600 makedir: /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/tests
161 11:34:21.308991 makedir: /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/results
162 11:34:21.309388 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-add-keys
163 11:34:21.309991 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-add-sources
164 11:34:21.310580 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-background-process-start
165 11:34:21.311109 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-background-process-stop
166 11:34:21.311819 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-common-functions
167 11:34:21.312407 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-echo-ipv4
168 11:34:21.312915 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-install-packages
169 11:34:21.313435 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-installed-packages
170 11:34:21.313955 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-os-build
171 11:34:21.314506 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-probe-channel
172 11:34:21.315024 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-probe-ip
173 11:34:21.315588 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-target-ip
174 11:34:21.316176 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-target-mac
175 11:34:21.316738 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-target-storage
176 11:34:21.317271 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-test-case
177 11:34:21.317862 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-test-event
178 11:34:21.318363 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-test-feedback
179 11:34:21.318855 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-test-raise
180 11:34:21.319339 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-test-reference
181 11:34:21.319974 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-test-runner
182 11:34:21.320514 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-test-set
183 11:34:21.321025 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-test-shell
184 11:34:21.321543 Updating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-install-packages (oe)
185 11:34:21.322093 Updating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/bin/lava-installed-packages (oe)
186 11:34:21.322611 Creating /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/environment
187 11:34:21.322999 LAVA metadata
188 11:34:21.323316 - LAVA_JOB_ID=913381
189 11:34:21.323537 - LAVA_DISPATCHER_IP=192.168.6.2
190 11:34:21.323947 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 11:34:21.325034 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 11:34:21.325353 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 11:34:21.325597 skipped lava-vland-overlay
194 11:34:21.325849 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 11:34:21.326137 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 11:34:21.326364 skipped lava-multinode-overlay
197 11:34:21.326642 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 11:34:21.326905 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 11:34:21.327158 Loading test definitions
200 11:34:21.327480 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 11:34:21.327706 Using /lava-913381 at stage 0
202 11:34:21.329124 uuid=913381_1.6.2.4.1 testdef=None
203 11:34:21.329443 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 11:34:21.329762 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 11:34:21.331726 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 11:34:21.332587 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 11:34:21.335037 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 11:34:21.335954 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 11:34:21.338298 runner path: /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/0/tests/0_dmesg test_uuid 913381_1.6.2.4.1
212 11:34:21.338861 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 11:34:21.339722 Creating lava-test-runner.conf files
215 11:34:21.339931 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/913381/lava-overlay-jrschq53/lava-913381/0 for stage 0
216 11:34:21.340360 - 0_dmesg
217 11:34:21.340770 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 11:34:21.341065 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 11:34:21.364084 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 11:34:21.364488 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 11:34:21.364748 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 11:34:21.365019 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 11:34:21.365283 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 11:34:21.984630 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 11:34:21.985095 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 11:34:21.985341 extracting modules file /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/913381/extract-nfsrootfs-5l6mg_f1
227 11:34:23.354145 extracting modules file /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/913381/extract-overlay-ramdisk-7klo45m1/ramdisk
228 11:34:24.751412 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 11:34:24.751896 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
230 11:34:24.752226 [common] Applying overlay to NFS
231 11:34:24.752455 [common] Applying overlay /var/lib/lava/dispatcher/tmp/913381/compress-overlay-cha5mzg4/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/913381/extract-nfsrootfs-5l6mg_f1
232 11:34:24.781772 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 11:34:24.782196 start: 1.6.6 prepare-kernel (timeout 00:09:31) [common]
234 11:34:24.782491 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:31) [common]
235 11:34:24.782733 Converting downloaded kernel to a uImage
236 11:34:24.783055 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/kernel/Image /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/kernel/uImage
237 11:34:25.244856 output: Image Name:
238 11:34:25.245357 output: Created: Wed Oct 30 11:34:24 2024
239 11:34:25.245638 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 11:34:25.245899 output: Data Size: 46256640 Bytes = 45172.50 KiB = 44.11 MiB
241 11:34:25.246163 output: Load Address: 01080000
242 11:34:25.246419 output: Entry Point: 01080000
243 11:34:25.246669 output:
244 11:34:25.247081 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 11:34:25.247423 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 11:34:25.247769 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 11:34:25.248151 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 11:34:25.248491 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 11:34:25.248827 Building ramdisk /var/lib/lava/dispatcher/tmp/913381/extract-overlay-ramdisk-7klo45m1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/913381/extract-overlay-ramdisk-7klo45m1/ramdisk
250 11:34:27.410885 >> 167116 blocks
251 11:34:35.210409 Adding RAMdisk u-boot header.
252 11:34:35.211131 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/913381/extract-overlay-ramdisk-7klo45m1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/913381/extract-overlay-ramdisk-7klo45m1/ramdisk.cpio.gz.uboot
253 11:34:35.484547 output: Image Name:
254 11:34:35.484968 output: Created: Wed Oct 30 11:34:35 2024
255 11:34:35.485182 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 11:34:35.485389 output: Data Size: 23428593 Bytes = 22879.49 KiB = 22.34 MiB
257 11:34:35.485592 output: Load Address: 00000000
258 11:34:35.485793 output: Entry Point: 00000000
259 11:34:35.485991 output:
260 11:34:35.486723 rename /var/lib/lava/dispatcher/tmp/913381/extract-overlay-ramdisk-7klo45m1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/ramdisk/ramdisk.cpio.gz.uboot
261 11:34:35.487146 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 11:34:35.487431 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 11:34:35.487731 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 11:34:35.487974 No LXC device requested
265 11:34:35.488562 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 11:34:35.489131 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 11:34:35.489683 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 11:34:35.490140 Checking files for TFTP limit of 4294967296 bytes.
269 11:34:35.493118 end: 1 tftp-deploy (duration 00:00:40) [common]
270 11:34:35.493751 start: 2 uboot-action (timeout 00:05:00) [common]
271 11:34:35.494327 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 11:34:35.494876 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 11:34:35.495426 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 11:34:35.496036 Using kernel file from prepare-kernel: 913381/tftp-deploy-md15v7tt/kernel/uImage
275 11:34:35.496733 substitutions:
276 11:34:35.497182 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 11:34:35.497630 - {DTB_ADDR}: 0x01070000
278 11:34:35.498071 - {DTB}: 913381/tftp-deploy-md15v7tt/dtb/meson-g12b-a311d-libretech-cc.dtb
279 11:34:35.498512 - {INITRD}: 913381/tftp-deploy-md15v7tt/ramdisk/ramdisk.cpio.gz.uboot
280 11:34:35.498951 - {KERNEL_ADDR}: 0x01080000
281 11:34:35.499384 - {KERNEL}: 913381/tftp-deploy-md15v7tt/kernel/uImage
282 11:34:35.499821 - {LAVA_MAC}: None
283 11:34:35.500331 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/913381/extract-nfsrootfs-5l6mg_f1
284 11:34:35.500780 - {NFS_SERVER_IP}: 192.168.6.2
285 11:34:35.501213 - {PRESEED_CONFIG}: None
286 11:34:35.501644 - {PRESEED_LOCAL}: None
287 11:34:35.502074 - {RAMDISK_ADDR}: 0x08000000
288 11:34:35.502504 - {RAMDISK}: 913381/tftp-deploy-md15v7tt/ramdisk/ramdisk.cpio.gz.uboot
289 11:34:35.502935 - {ROOT_PART}: None
290 11:34:35.503363 - {ROOT}: None
291 11:34:35.503793 - {SERVER_IP}: 192.168.6.2
292 11:34:35.504251 - {TEE_ADDR}: 0x83000000
293 11:34:35.504678 - {TEE}: None
294 11:34:35.505108 Parsed boot commands:
295 11:34:35.505525 - setenv autoload no
296 11:34:35.505948 - setenv initrd_high 0xffffffff
297 11:34:35.506373 - setenv fdt_high 0xffffffff
298 11:34:35.506797 - dhcp
299 11:34:35.507219 - setenv serverip 192.168.6.2
300 11:34:35.507642 - tftpboot 0x01080000 913381/tftp-deploy-md15v7tt/kernel/uImage
301 11:34:35.508105 - tftpboot 0x08000000 913381/tftp-deploy-md15v7tt/ramdisk/ramdisk.cpio.gz.uboot
302 11:34:35.508537 - tftpboot 0x01070000 913381/tftp-deploy-md15v7tt/dtb/meson-g12b-a311d-libretech-cc.dtb
303 11:34:35.508965 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/913381/extract-nfsrootfs-5l6mg_f1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 11:34:35.509406 - bootm 0x01080000 0x08000000 0x01070000
305 11:34:35.509950 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 11:34:35.511578 start: 2.3 connect-device (timeout 00:05:00) [common]
308 11:34:35.512064 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 11:34:35.527705 Setting prompt string to ['lava-test: # ']
310 11:34:35.529316 end: 2.3 connect-device (duration 00:00:00) [common]
311 11:34:35.529961 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 11:34:35.530571 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 11:34:35.531140 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 11:34:35.532405 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 11:34:35.572512 >> OK - accepted request
316 11:34:35.574653 Returned 0 in 0 seconds
317 11:34:35.675797 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 11:34:35.677539 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 11:34:35.678138 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 11:34:35.678694 Setting prompt string to ['Hit any key to stop autoboot']
322 11:34:35.679197 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 11:34:35.680893 Trying 192.168.56.21...
324 11:34:35.681420 Connected to conserv1.
325 11:34:35.681892 Escape character is '^]'.
326 11:34:35.682361
327 11:34:35.682830 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 11:34:35.683307
329 11:34:47.186865 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 11:34:47.187543 bl2_stage_init 0x01
331 11:34:47.188037 bl2_stage_init 0x81
332 11:34:47.192601 hw id: 0x0000 - pwm id 0x01
333 11:34:47.193087 bl2_stage_init 0xc1
334 11:34:47.193539 bl2_stage_init 0x02
335 11:34:47.193973
336 11:34:47.198053 L0:00000000
337 11:34:47.198518 L1:20000703
338 11:34:47.198954 L2:00008067
339 11:34:47.199399 L3:14000000
340 11:34:47.200867 B2:00402000
341 11:34:47.201342 B1:e0f83180
342 11:34:47.201776
343 11:34:47.202210 TE: 58159
344 11:34:47.202643
345 11:34:47.212023 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 11:34:47.212503
347 11:34:47.212939 Board ID = 1
348 11:34:47.213369 Set A53 clk to 24M
349 11:34:47.213797 Set A73 clk to 24M
350 11:34:47.217681 Set clk81 to 24M
351 11:34:47.218141 A53 clk: 1200 MHz
352 11:34:47.218570 A73 clk: 1200 MHz
353 11:34:47.223208 CLK81: 166.6M
354 11:34:47.223671 smccc: 00012ab5
355 11:34:47.228790 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 11:34:47.229256 board id: 1
357 11:34:47.234436 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 11:34:47.248053 fw parse done
359 11:34:47.253972 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 11:34:47.296653 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 11:34:47.307528 PIEI prepare done
362 11:34:47.308017 fastboot data load
363 11:34:47.308460 fastboot data verify
364 11:34:47.313274 verify result: 266
365 11:34:47.318794 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 11:34:47.319253 LPDDR4 probe
367 11:34:47.319688 ddr clk to 1584MHz
368 11:34:47.326798 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 11:34:47.364123
370 11:34:47.364604 dmc_version 0001
371 11:34:47.370800 Check phy result
372 11:34:47.376600 INFO : End of CA training
373 11:34:47.377061 INFO : End of initialization
374 11:34:47.382254 INFO : Training has run successfully!
375 11:34:47.382711 Check phy result
376 11:34:47.387793 INFO : End of initialization
377 11:34:47.388285 INFO : End of read enable training
378 11:34:47.391126 INFO : End of fine write leveling
379 11:34:47.396641 INFO : End of Write leveling coarse delay
380 11:34:47.402257 INFO : Training has run successfully!
381 11:34:47.402718 Check phy result
382 11:34:47.403155 INFO : End of initialization
383 11:34:47.407839 INFO : End of read dq deskew training
384 11:34:47.411354 INFO : End of MPR read delay center optimization
385 11:34:47.416879 INFO : End of write delay center optimization
386 11:34:47.422480 INFO : End of read delay center optimization
387 11:34:47.422964 INFO : End of max read latency training
388 11:34:47.428080 INFO : Training has run successfully!
389 11:34:47.428555 1D training succeed
390 11:34:47.436254 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 11:34:47.483764 Check phy result
392 11:34:47.484265 INFO : End of initialization
393 11:34:47.505562 INFO : End of 2D read delay Voltage center optimization
394 11:34:47.524938 INFO : End of 2D read delay Voltage center optimization
395 11:34:47.577716 INFO : End of 2D write delay Voltage center optimization
396 11:34:47.627109 INFO : End of 2D write delay Voltage center optimization
397 11:34:47.632665 INFO : Training has run successfully!
398 11:34:47.633124
399 11:34:47.633566 channel==0
400 11:34:47.638257 RxClkDly_Margin_A0==88 ps 9
401 11:34:47.638727 TxDqDly_Margin_A0==98 ps 10
402 11:34:47.643845 RxClkDly_Margin_A1==88 ps 9
403 11:34:47.644351 TxDqDly_Margin_A1==88 ps 9
404 11:34:47.644796 TrainedVREFDQ_A0==74
405 11:34:47.649445 TrainedVREFDQ_A1==74
406 11:34:47.649909 VrefDac_Margin_A0==25
407 11:34:47.650343 DeviceVref_Margin_A0==40
408 11:34:47.655051 VrefDac_Margin_A1==25
409 11:34:47.655511 DeviceVref_Margin_A1==40
410 11:34:47.655944
411 11:34:47.656409
412 11:34:47.656845 channel==1
413 11:34:47.660693 RxClkDly_Margin_A0==98 ps 10
414 11:34:47.661217 TxDqDly_Margin_A0==98 ps 10
415 11:34:47.666244 RxClkDly_Margin_A1==98 ps 10
416 11:34:47.666725 TxDqDly_Margin_A1==88 ps 9
417 11:34:47.671821 TrainedVREFDQ_A0==77
418 11:34:47.672372 TrainedVREFDQ_A1==77
419 11:34:47.672825 VrefDac_Margin_A0==22
420 11:34:47.677462 DeviceVref_Margin_A0==37
421 11:34:47.677931 VrefDac_Margin_A1==22
422 11:34:47.683073 DeviceVref_Margin_A1==37
423 11:34:47.683538
424 11:34:47.684001 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 11:34:47.684448
426 11:34:47.716660 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 11:34:47.717224 2D training succeed
428 11:34:47.722272 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 11:34:47.727854 auto size-- 65535DDR cs0 size: 2048MB
430 11:34:47.728354 DDR cs1 size: 2048MB
431 11:34:47.733477 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 11:34:47.733959 cs0 DataBus test pass
433 11:34:47.739069 cs1 DataBus test pass
434 11:34:47.739554 cs0 AddrBus test pass
435 11:34:47.740025 cs1 AddrBus test pass
436 11:34:47.740468
437 11:34:47.744669 100bdlr_step_size ps== 420
438 11:34:47.745166 result report
439 11:34:47.750560 boot times 0Enable ddr reg access
440 11:34:47.763175 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 11:34:47.769259 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 11:34:48.342817 0.0;M3 CHK:0;cm4_sp_mode 0
443 11:34:48.343496 MVN_1=0x00000000
444 11:34:48.348261 MVN_2=0x00000000
445 11:34:48.353999 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 11:34:48.354485 OPS=0x10
447 11:34:48.354946 ring efuse init
448 11:34:48.355391 chipver efuse init
449 11:34:48.359637 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 11:34:48.365229 [0.018961 Inits done]
451 11:34:48.365714 secure task start!
452 11:34:48.366164 high task start!
453 11:34:48.369818 low task start!
454 11:34:48.370287 run into bl31
455 11:34:48.376475 NOTICE: BL31: v1.3(release):4fc40b1
456 11:34:48.384305 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 11:34:48.384786 NOTICE: BL31: G12A normal boot!
458 11:34:48.409635 NOTICE: BL31: BL33 decompress pass
459 11:34:48.415310 ERROR: Error initializing runtime service opteed_fast
460 11:34:49.648237
461 11:34:49.648829
462 11:34:49.656771 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 11:34:49.657258
464 11:34:49.657713 Model: Libre Computer AML-A311D-CC Alta
465 11:34:49.865071 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 11:34:49.888452 DRAM: 2 GiB (effective 3.8 GiB)
467 11:34:50.031417 Core: 408 devices, 31 uclasses, devicetree: separate
468 11:34:50.037302 WDT: Not starting watchdog@f0d0
469 11:34:50.069561 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 11:34:50.081994 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 11:34:50.087011 ** Bad device specification mmc 0 **
472 11:34:50.097318 Card did not respond to voltage select! : -110
473 11:34:50.104956 ** Bad device specification mmc 0 **
474 11:34:50.105426 Couldn't find partition mmc 0
475 11:34:50.113324 Card did not respond to voltage select! : -110
476 11:34:50.118846 ** Bad device specification mmc 0 **
477 11:34:50.119321 Couldn't find partition mmc 0
478 11:34:50.123884 Error: could not access storage.
479 11:34:51.387038 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 11:34:51.387663 bl2_stage_init 0x01
481 11:34:51.388207 bl2_stage_init 0x81
482 11:34:51.392543 hw id: 0x0000 - pwm id 0x01
483 11:34:51.393031 bl2_stage_init 0xc1
484 11:34:51.393487 bl2_stage_init 0x02
485 11:34:51.393933
486 11:34:51.398148 L0:00000000
487 11:34:51.398626 L1:20000703
488 11:34:51.399076 L2:00008067
489 11:34:51.399515 L3:14000000
490 11:34:51.403786 B2:00402000
491 11:34:51.404314 B1:e0f83180
492 11:34:51.404774
493 11:34:51.405221 TE: 58124
494 11:34:51.405662
495 11:34:51.409348 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 11:34:51.409833
497 11:34:51.410282 Board ID = 1
498 11:34:51.415013 Set A53 clk to 24M
499 11:34:51.415484 Set A73 clk to 24M
500 11:34:51.415931 Set clk81 to 24M
501 11:34:51.420552 A53 clk: 1200 MHz
502 11:34:51.421024 A73 clk: 1200 MHz
503 11:34:51.421470 CLK81: 166.6M
504 11:34:51.421914 smccc: 00012a92
505 11:34:51.426140 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 11:34:51.431728 board id: 1
507 11:34:51.437609 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 11:34:51.448313 fw parse done
509 11:34:51.454227 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 11:34:51.496978 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 11:34:51.507804 PIEI prepare done
512 11:34:51.508317 fastboot data load
513 11:34:51.508770 fastboot data verify
514 11:34:51.513441 verify result: 266
515 11:34:51.519030 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 11:34:51.519515 LPDDR4 probe
517 11:34:51.519965 ddr clk to 1584MHz
518 11:34:51.527065 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 11:34:51.564267
520 11:34:51.564745 dmc_version 0001
521 11:34:51.571069 Check phy result
522 11:34:51.576804 INFO : End of CA training
523 11:34:51.577272 INFO : End of initialization
524 11:34:51.582399 INFO : Training has run successfully!
525 11:34:51.582866 Check phy result
526 11:34:51.588051 INFO : End of initialization
527 11:34:51.588520 INFO : End of read enable training
528 11:34:51.593648 INFO : End of fine write leveling
529 11:34:51.599211 INFO : End of Write leveling coarse delay
530 11:34:51.599677 INFO : Training has run successfully!
531 11:34:51.600159 Check phy result
532 11:34:51.604790 INFO : End of initialization
533 11:34:51.605258 INFO : End of read dq deskew training
534 11:34:51.610415 INFO : End of MPR read delay center optimization
535 11:34:51.616075 INFO : End of write delay center optimization
536 11:34:51.621628 INFO : End of read delay center optimization
537 11:34:51.622110 INFO : End of max read latency training
538 11:34:51.627251 INFO : Training has run successfully!
539 11:34:51.627728 1D training succeed
540 11:34:51.636413 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 11:34:51.684281 Check phy result
542 11:34:51.684845 INFO : End of initialization
543 11:34:51.705764 INFO : End of 2D read delay Voltage center optimization
544 11:34:51.726143 INFO : End of 2D read delay Voltage center optimization
545 11:34:51.777217 INFO : End of 2D write delay Voltage center optimization
546 11:34:51.827468 INFO : End of 2D write delay Voltage center optimization
547 11:34:51.833060 INFO : Training has run successfully!
548 11:34:51.833590
549 11:34:51.834055 channel==0
550 11:34:51.838626 RxClkDly_Margin_A0==88 ps 9
551 11:34:51.839154 TxDqDly_Margin_A0==98 ps 10
552 11:34:51.844233 RxClkDly_Margin_A1==88 ps 9
553 11:34:51.844743 TxDqDly_Margin_A1==88 ps 9
554 11:34:51.845202 TrainedVREFDQ_A0==74
555 11:34:51.849807 TrainedVREFDQ_A1==74
556 11:34:51.850322 VrefDac_Margin_A0==25
557 11:34:51.850780 DeviceVref_Margin_A0==40
558 11:34:51.855399 VrefDac_Margin_A1==25
559 11:34:51.855898 DeviceVref_Margin_A1==40
560 11:34:51.856397
561 11:34:51.856845
562 11:34:51.857287 channel==1
563 11:34:51.861129 RxClkDly_Margin_A0==98 ps 10
564 11:34:51.861636 TxDqDly_Margin_A0==98 ps 10
565 11:34:51.866598 RxClkDly_Margin_A1==98 ps 10
566 11:34:51.867109 TxDqDly_Margin_A1==88 ps 9
567 11:34:51.872224 TrainedVREFDQ_A0==76
568 11:34:51.872731 TrainedVREFDQ_A1==77
569 11:34:51.873182 VrefDac_Margin_A0==22
570 11:34:51.877805 DeviceVref_Margin_A0==38
571 11:34:51.878281 VrefDac_Margin_A1==22
572 11:34:51.883408 DeviceVref_Margin_A1==37
573 11:34:51.883882
574 11:34:51.884366 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 11:34:51.884815
576 11:34:51.917070 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 11:34:51.917607 2D training succeed
578 11:34:51.922565 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 11:34:51.928201 auto size-- 65535DDR cs0 size: 2048MB
580 11:34:51.928683 DDR cs1 size: 2048MB
581 11:34:51.933784 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 11:34:51.934261 cs0 DataBus test pass
583 11:34:51.939451 cs1 DataBus test pass
584 11:34:51.939945 cs0 AddrBus test pass
585 11:34:51.940443 cs1 AddrBus test pass
586 11:34:51.940887
587 11:34:51.945083 100bdlr_step_size ps== 420
588 11:34:51.945592 result report
589 11:34:51.950566 boot times 0Enable ddr reg access
590 11:34:51.955625 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 11:34:51.969439 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 11:34:52.543172 0.0;M3 CHK:0;cm4_sp_mode 0
593 11:34:52.543824 MVN_1=0x00000000
594 11:34:52.548564 MVN_2=0x00000000
595 11:34:52.554319 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 11:34:52.554834 OPS=0x10
597 11:34:52.555310 ring efuse init
598 11:34:52.555795 chipver efuse init
599 11:34:52.562607 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 11:34:52.563135 [0.018961 Inits done]
601 11:34:52.570281 secure task start!
602 11:34:52.570750 high task start!
603 11:34:52.571181 low task start!
604 11:34:52.571610 run into bl31
605 11:34:52.576725 NOTICE: BL31: v1.3(release):4fc40b1
606 11:34:52.584597 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 11:34:52.585069 NOTICE: BL31: G12A normal boot!
608 11:34:52.609949 NOTICE: BL31: BL33 decompress pass
609 11:34:52.615648 ERROR: Error initializing runtime service opteed_fast
610 11:34:53.848643
611 11:34:53.849306
612 11:34:53.857080 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 11:34:53.857566
614 11:34:53.858042 Model: Libre Computer AML-A311D-CC Alta
615 11:34:54.064822 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 11:34:54.088868 DRAM: 2 GiB (effective 3.8 GiB)
617 11:34:54.231748 Core: 408 devices, 31 uclasses, devicetree: separate
618 11:34:54.237669 WDT: Not starting watchdog@f0d0
619 11:34:54.269865 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 11:34:54.282411 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 11:34:54.287467 ** Bad device specification mmc 0 **
622 11:34:54.297755 Card did not respond to voltage select! : -110
623 11:34:54.304876 ** Bad device specification mmc 0 **
624 11:34:54.305360 Couldn't find partition mmc 0
625 11:34:54.313686 Card did not respond to voltage select! : -110
626 11:34:54.319225 ** Bad device specification mmc 0 **
627 11:34:54.319698 Couldn't find partition mmc 0
628 11:34:54.324324 Error: could not access storage.
629 11:34:54.666212 Net: eth0: ethernet@ff3f0000
630 11:34:54.666794 starting USB...
631 11:34:54.918859 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 11:34:54.919497 Starting the controller
633 11:34:54.925748 USB XHCI 1.10
634 11:34:56.639014 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 11:34:56.639711 bl2_stage_init 0x01
636 11:34:56.640224 bl2_stage_init 0x81
637 11:34:56.644467 hw id: 0x0000 - pwm id 0x01
638 11:34:56.644965 bl2_stage_init 0xc1
639 11:34:56.645425 bl2_stage_init 0x02
640 11:34:56.645877
641 11:34:56.650044 L0:00000000
642 11:34:56.650529 L1:20000703
643 11:34:56.650979 L2:00008067
644 11:34:56.651427 L3:14000000
645 11:34:56.655682 B2:00402000
646 11:34:56.656202 B1:e0f83180
647 11:34:56.656651
648 11:34:56.657101 TE: 58124
649 11:34:56.657547
650 11:34:56.661278 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 11:34:56.661769
652 11:34:56.662224 Board ID = 1
653 11:34:56.667072 Set A53 clk to 24M
654 11:34:56.667555 Set A73 clk to 24M
655 11:34:56.668026 Set clk81 to 24M
656 11:34:56.672411 A53 clk: 1200 MHz
657 11:34:56.672889 A73 clk: 1200 MHz
658 11:34:56.673336 CLK81: 166.6M
659 11:34:56.673778 smccc: 00012a92
660 11:34:56.678086 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 11:34:56.685924 board id: 1
662 11:34:56.690033 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 11:34:56.700716 fw parse done
664 11:34:56.706309 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 11:34:56.748802 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 11:34:56.759748 PIEI prepare done
667 11:34:56.760299 fastboot data load
668 11:34:56.760765 fastboot data verify
669 11:34:56.765391 verify result: 266
670 11:34:56.771050 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 11:34:56.771544 LPDDR4 probe
672 11:34:56.772027 ddr clk to 1584MHz
673 11:34:56.779004 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 11:34:56.816204
675 11:34:56.816714 dmc_version 0001
676 11:34:56.822049 Check phy result
677 11:34:56.828658 INFO : End of CA training
678 11:34:56.829164 INFO : End of initialization
679 11:34:56.834308 INFO : Training has run successfully!
680 11:34:56.834788 Check phy result
681 11:34:56.839861 INFO : End of initialization
682 11:34:56.840379 INFO : End of read enable training
683 11:34:56.845492 INFO : End of fine write leveling
684 11:34:56.851092 INFO : End of Write leveling coarse delay
685 11:34:56.851581 INFO : Training has run successfully!
686 11:34:56.852061 Check phy result
687 11:34:56.856717 INFO : End of initialization
688 11:34:56.857200 INFO : End of read dq deskew training
689 11:34:56.862344 INFO : End of MPR read delay center optimization
690 11:34:56.867855 INFO : End of write delay center optimization
691 11:34:56.873558 INFO : End of read delay center optimization
692 11:34:56.874052 INFO : End of max read latency training
693 11:34:56.879155 INFO : Training has run successfully!
694 11:34:56.879642 1D training succeed
695 11:34:56.888295 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 11:34:56.935878 Check phy result
697 11:34:56.936418 INFO : End of initialization
698 11:34:56.957178 INFO : End of 2D read delay Voltage center optimization
699 11:34:56.977490 INFO : End of 2D read delay Voltage center optimization
700 11:34:57.029382 INFO : End of 2D write delay Voltage center optimization
701 11:34:57.078592 INFO : End of 2D write delay Voltage center optimization
702 11:34:57.084222 INFO : Training has run successfully!
703 11:34:57.084702
704 11:34:57.085157 channel==0
705 11:34:57.089791 RxClkDly_Margin_A0==88 ps 9
706 11:34:57.090292 TxDqDly_Margin_A0==98 ps 10
707 11:34:57.093153 RxClkDly_Margin_A1==88 ps 9
708 11:34:57.093633 TxDqDly_Margin_A1==98 ps 10
709 11:34:57.098625 TrainedVREFDQ_A0==74
710 11:34:57.099107 TrainedVREFDQ_A1==75
711 11:34:57.104258 VrefDac_Margin_A0==25
712 11:34:57.104755 DeviceVref_Margin_A0==40
713 11:34:57.105210 VrefDac_Margin_A1==24
714 11:34:57.109851 DeviceVref_Margin_A1==39
715 11:34:57.110336
716 11:34:57.110790
717 11:34:57.111233 channel==1
718 11:34:57.111672 RxClkDly_Margin_A0==98 ps 10
719 11:34:57.115443 TxDqDly_Margin_A0==88 ps 9
720 11:34:57.115933 RxClkDly_Margin_A1==88 ps 9
721 11:34:57.121054 TxDqDly_Margin_A1==88 ps 9
722 11:34:57.121541 TrainedVREFDQ_A0==76
723 11:34:57.121995 TrainedVREFDQ_A1==77
724 11:34:57.126672 VrefDac_Margin_A0==22
725 11:34:57.127152 DeviceVref_Margin_A0==38
726 11:34:57.132229 VrefDac_Margin_A1==24
727 11:34:57.132704 DeviceVref_Margin_A1==37
728 11:34:57.133148
729 11:34:57.137837 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 11:34:57.138318
731 11:34:57.165845 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 11:34:57.171445 2D training succeed
733 11:34:57.177061 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 11:34:57.177585 auto size-- 65535DDR cs0 size: 2048MB
735 11:34:57.182634 DDR cs1 size: 2048MB
736 11:34:57.183116 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 11:34:57.188234 cs0 DataBus test pass
738 11:34:57.188712 cs1 DataBus test pass
739 11:34:57.189158 cs0 AddrBus test pass
740 11:34:57.193863 cs1 AddrBus test pass
741 11:34:57.194346
742 11:34:57.194795 100bdlr_step_size ps== 420
743 11:34:57.195250 result report
744 11:34:57.199459 boot times 0Enable ddr reg access
745 11:34:57.207046 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 11:34:57.220530 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 11:34:57.792530 0.0;M3 CHK:0;cm4_sp_mode 0
748 11:34:57.793216 MVN_1=0x00000000
749 11:34:57.797997 MVN_2=0x00000000
750 11:34:57.803859 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 11:34:57.804470 OPS=0x10
752 11:34:57.804924 ring efuse init
753 11:34:57.805359 chipver efuse init
754 11:34:57.809316 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 11:34:57.814930 [0.018961 Inits done]
756 11:34:57.815408 secure task start!
757 11:34:57.815846 high task start!
758 11:34:57.819536 low task start!
759 11:34:57.820030 run into bl31
760 11:34:57.826123 NOTICE: BL31: v1.3(release):4fc40b1
761 11:34:57.833950 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 11:34:57.834432 NOTICE: BL31: G12A normal boot!
763 11:34:57.859652 NOTICE: BL31: BL33 decompress pass
764 11:34:57.864983 ERROR: Error initializing runtime service opteed_fast
765 11:34:59.097919
766 11:34:59.098590
767 11:34:59.106305 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 11:34:59.106804
769 11:34:59.107260 Model: Libre Computer AML-A311D-CC Alta
770 11:34:59.314741 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 11:34:59.338116 DRAM: 2 GiB (effective 3.8 GiB)
772 11:34:59.481145 Core: 408 devices, 31 uclasses, devicetree: separate
773 11:34:59.486966 WDT: Not starting watchdog@f0d0
774 11:34:59.519218 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 11:34:59.531677 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 11:34:59.536642 ** Bad device specification mmc 0 **
777 11:34:59.547066 Card did not respond to voltage select! : -110
778 11:34:59.554617 ** Bad device specification mmc 0 **
779 11:34:59.555128 Couldn't find partition mmc 0
780 11:34:59.563078 Card did not respond to voltage select! : -110
781 11:34:59.568455 ** Bad device specification mmc 0 **
782 11:34:59.568932 Couldn't find partition mmc 0
783 11:34:59.573516 Error: could not access storage.
784 11:34:59.917399 Net: eth0: ethernet@ff3f0000
785 11:34:59.918000 starting USB...
786 11:35:00.169282 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 11:35:00.169940 Starting the controller
788 11:35:00.176250 USB XHCI 1.10
789 11:35:02.337524 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 11:35:02.338221 bl2_stage_init 0x01
791 11:35:02.338736 bl2_stage_init 0x81
792 11:35:02.343075 hw id: 0x0000 - pwm id 0x01
793 11:35:02.343628 bl2_stage_init 0xc1
794 11:35:02.344156 bl2_stage_init 0x02
795 11:35:02.344645
796 11:35:02.348715 L0:00000000
797 11:35:02.349248 L1:20000703
798 11:35:02.349733 L2:00008067
799 11:35:02.350215 L3:14000000
800 11:35:02.351743 B2:00402000
801 11:35:02.352306 B1:e0f83180
802 11:35:02.352796
803 11:35:02.353285 TE: 58167
804 11:35:02.353771
805 11:35:02.363069 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 11:35:02.363627
807 11:35:02.364156 Board ID = 1
808 11:35:02.364643 Set A53 clk to 24M
809 11:35:02.365120 Set A73 clk to 24M
810 11:35:02.368678 Set clk81 to 24M
811 11:35:02.369215 A53 clk: 1200 MHz
812 11:35:02.369707 A73 clk: 1200 MHz
813 11:35:02.372225 CLK81: 166.6M
814 11:35:02.372749 smccc: 00012abe
815 11:35:02.377910 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 11:35:02.378496 board id: 1
817 11:35:02.388303 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 11:35:02.398680 fw parse done
819 11:35:02.404657 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 11:35:02.447327 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 11:35:02.458335 PIEI prepare done
822 11:35:02.458904 fastboot data load
823 11:35:02.459376 fastboot data verify
824 11:35:02.463921 verify result: 266
825 11:35:02.469524 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 11:35:02.470081 LPDDR4 probe
827 11:35:02.470547 ddr clk to 1584MHz
828 11:35:02.477462 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 11:35:02.514780
830 11:35:02.515388 dmc_version 0001
831 11:35:02.521403 Check phy result
832 11:35:02.527295 INFO : End of CA training
833 11:35:02.527849 INFO : End of initialization
834 11:35:02.532891 INFO : Training has run successfully!
835 11:35:02.533447 Check phy result
836 11:35:02.538485 INFO : End of initialization
837 11:35:02.539036 INFO : End of read enable training
838 11:35:02.544159 INFO : End of fine write leveling
839 11:35:02.549710 INFO : End of Write leveling coarse delay
840 11:35:02.550274 INFO : Training has run successfully!
841 11:35:02.550745 Check phy result
842 11:35:02.555314 INFO : End of initialization
843 11:35:02.555865 INFO : End of read dq deskew training
844 11:35:02.560870 INFO : End of MPR read delay center optimization
845 11:35:02.566464 INFO : End of write delay center optimization
846 11:35:02.572110 INFO : End of read delay center optimization
847 11:35:02.572666 INFO : End of max read latency training
848 11:35:02.577717 INFO : Training has run successfully!
849 11:35:02.578262 1D training succeed
850 11:35:02.586818 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 11:35:02.634541 Check phy result
852 11:35:02.635116 INFO : End of initialization
853 11:35:02.656080 INFO : End of 2D read delay Voltage center optimization
854 11:35:02.676238 INFO : End of 2D read delay Voltage center optimization
855 11:35:02.728120 INFO : End of 2D write delay Voltage center optimization
856 11:35:02.777354 INFO : End of 2D write delay Voltage center optimization
857 11:35:02.782888 INFO : Training has run successfully!
858 11:35:02.783439
859 11:35:02.783908 channel==0
860 11:35:02.788493 RxClkDly_Margin_A0==88 ps 9
861 11:35:02.789048 TxDqDly_Margin_A0==98 ps 10
862 11:35:02.794071 RxClkDly_Margin_A1==88 ps 9
863 11:35:02.794636 TxDqDly_Margin_A1==88 ps 9
864 11:35:02.795131 TrainedVREFDQ_A0==74
865 11:35:02.799737 TrainedVREFDQ_A1==74
866 11:35:02.800354 VrefDac_Margin_A0==25
867 11:35:02.800833 DeviceVref_Margin_A0==40
868 11:35:02.805273 VrefDac_Margin_A1==24
869 11:35:02.805841 DeviceVref_Margin_A1==40
870 11:35:02.806277
871 11:35:02.806711
872 11:35:02.807145 channel==1
873 11:35:02.810878 RxClkDly_Margin_A0==98 ps 10
874 11:35:02.811426 TxDqDly_Margin_A0==88 ps 9
875 11:35:02.816467 RxClkDly_Margin_A1==88 ps 9
876 11:35:02.816996 TxDqDly_Margin_A1==88 ps 9
877 11:35:02.822072 TrainedVREFDQ_A0==76
878 11:35:02.822606 TrainedVREFDQ_A1==77
879 11:35:02.823045 VrefDac_Margin_A0==22
880 11:35:02.827693 DeviceVref_Margin_A0==38
881 11:35:02.828271 VrefDac_Margin_A1==24
882 11:35:02.833252 DeviceVref_Margin_A1==37
883 11:35:02.833779
884 11:35:02.834220 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 11:35:02.834653
886 11:35:02.866830 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 11:35:02.867443 2D training succeed
888 11:35:02.872516 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 11:35:02.878077 auto size-- 65535DDR cs0 size: 2048MB
890 11:35:02.878621 DDR cs1 size: 2048MB
891 11:35:02.883708 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 11:35:02.884277 cs0 DataBus test pass
893 11:35:02.889306 cs1 DataBus test pass
894 11:35:02.889838 cs0 AddrBus test pass
895 11:35:02.890277 cs1 AddrBus test pass
896 11:35:02.890709
897 11:35:02.894873 100bdlr_step_size ps== 420
898 11:35:02.895424 result report
899 11:35:02.900498 boot times 0Enable ddr reg access
900 11:35:02.905773 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 11:35:02.919075 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 11:35:03.491054 0.0;M3 CHK:0;cm4_sp_mode 0
903 11:35:03.491687 MVN_1=0x00000000
904 11:35:03.496643 MVN_2=0x00000000
905 11:35:03.502382 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 11:35:03.502944 OPS=0x10
907 11:35:03.503416 ring efuse init
908 11:35:03.504080 chipver efuse init
909 11:35:03.507871 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 11:35:03.513529 [0.018960 Inits done]
911 11:35:03.514078 secure task start!
912 11:35:03.514540 high task start!
913 11:35:03.518115 low task start!
914 11:35:03.518654 run into bl31
915 11:35:03.524744 NOTICE: BL31: v1.3(release):4fc40b1
916 11:35:03.532548 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 11:35:03.533100 NOTICE: BL31: G12A normal boot!
918 11:35:03.557892 NOTICE: BL31: BL33 decompress pass
919 11:35:03.563604 ERROR: Error initializing runtime service opteed_fast
920 11:35:04.796321
921 11:35:04.796979
922 11:35:04.804971 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 11:35:04.805521
924 11:35:04.806005 Model: Libre Computer AML-A311D-CC Alta
925 11:35:05.013234 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 11:35:05.036650 DRAM: 2 GiB (effective 3.8 GiB)
927 11:35:05.179556 Core: 408 devices, 31 uclasses, devicetree: separate
928 11:35:05.185506 WDT: Not starting watchdog@f0d0
929 11:35:05.217766 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 11:35:05.230155 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 11:35:05.235326 ** Bad device specification mmc 0 **
932 11:35:05.245639 Card did not respond to voltage select! : -110
933 11:35:05.253262 ** Bad device specification mmc 0 **
934 11:35:05.253814 Couldn't find partition mmc 0
935 11:35:05.261628 Card did not respond to voltage select! : -110
936 11:35:05.267129 ** Bad device specification mmc 0 **
937 11:35:05.267677 Couldn't find partition mmc 0
938 11:35:05.272212 Error: could not access storage.
939 11:35:05.614616 Net: eth0: ethernet@ff3f0000
940 11:35:05.615250 starting USB...
941 11:35:05.866412 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 11:35:05.867015 Starting the controller
943 11:35:05.873449 USB XHCI 1.10
944 11:35:07.617385 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 11:35:07.618041 bl2_stage_init 0x01
946 11:35:07.618524 bl2_stage_init 0x81
947 11:35:07.622879 hw id: 0x0000 - pwm id 0x01
948 11:35:07.623421 bl2_stage_init 0xc1
949 11:35:07.623895 bl2_stage_init 0x02
950 11:35:07.624628
951 11:35:07.628478 L0:00000000
952 11:35:07.628997 L1:20000703
953 11:35:07.629466 L2:00008067
954 11:35:07.629921 L3:14000000
955 11:35:07.634022 B2:00402000
956 11:35:07.634535 B1:e0f83180
957 11:35:07.634999
958 11:35:07.635452 TE: 58159
959 11:35:07.635905
960 11:35:07.639532 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 11:35:07.640066
962 11:35:07.640541 Board ID = 1
963 11:35:07.645236 Set A53 clk to 24M
964 11:35:07.645735 Set A73 clk to 24M
965 11:35:07.646190 Set clk81 to 24M
966 11:35:07.650786 A53 clk: 1200 MHz
967 11:35:07.651324 A73 clk: 1200 MHz
968 11:35:07.651787 CLK81: 166.6M
969 11:35:07.652281 smccc: 00012ab5
970 11:35:07.656319 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 11:35:07.662022 board id: 1
972 11:35:07.667824 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 11:35:07.678478 fw parse done
974 11:35:07.684485 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 11:35:07.727097 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 11:35:07.738011 PIEI prepare done
977 11:35:07.738542 fastboot data load
978 11:35:07.739013 fastboot data verify
979 11:35:07.743633 verify result: 266
980 11:35:07.749318 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 11:35:07.749823 LPDDR4 probe
982 11:35:07.750282 ddr clk to 1584MHz
983 11:35:07.757211 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 11:35:07.793651
985 11:35:07.794240 dmc_version 0001
986 11:35:07.800294 Check phy result
987 11:35:07.807291 INFO : End of CA training
988 11:35:07.807870 INFO : End of initialization
989 11:35:07.812686 INFO : Training has run successfully!
990 11:35:07.813204 Check phy result
991 11:35:07.818383 INFO : End of initialization
992 11:35:07.818896 INFO : End of read enable training
993 11:35:07.821610 INFO : End of fine write leveling
994 11:35:07.826994 INFO : End of Write leveling coarse delay
995 11:35:07.832685 INFO : Training has run successfully!
996 11:35:07.833233 Check phy result
997 11:35:07.833671 INFO : End of initialization
998 11:35:07.838279 INFO : End of read dq deskew training
999 11:35:07.841963 INFO : End of MPR read delay center optimization
1000 11:35:07.847395 INFO : End of write delay center optimization
1001 11:35:07.853209 INFO : End of read delay center optimization
1002 11:35:07.853694 INFO : End of max read latency training
1003 11:35:07.858723 INFO : Training has run successfully!
1004 11:35:07.859242 1D training succeed
1005 11:35:07.865663 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 11:35:07.914244 Check phy result
1007 11:35:07.914814 INFO : End of initialization
1008 11:35:07.936656 INFO : End of 2D read delay Voltage center optimization
1009 11:35:07.956743 INFO : End of 2D read delay Voltage center optimization
1010 11:35:08.008695 INFO : End of 2D write delay Voltage center optimization
1011 11:35:08.057880 INFO : End of 2D write delay Voltage center optimization
1012 11:35:08.063452 INFO : Training has run successfully!
1013 11:35:08.063975
1014 11:35:08.064495 channel==0
1015 11:35:08.069074 RxClkDly_Margin_A0==88 ps 9
1016 11:35:08.069589 TxDqDly_Margin_A0==98 ps 10
1017 11:35:08.072386 RxClkDly_Margin_A1==88 ps 9
1018 11:35:08.072988 TxDqDly_Margin_A1==98 ps 10
1019 11:35:08.077992 TrainedVREFDQ_A0==74
1020 11:35:08.078578 TrainedVREFDQ_A1==74
1021 11:35:08.083573 VrefDac_Margin_A0==25
1022 11:35:08.084192 DeviceVref_Margin_A0==40
1023 11:35:08.084678 VrefDac_Margin_A1==25
1024 11:35:08.089182 DeviceVref_Margin_A1==40
1025 11:35:08.089747
1026 11:35:08.090226
1027 11:35:08.090688 channel==1
1028 11:35:08.091138 RxClkDly_Margin_A0==98 ps 10
1029 11:35:08.094788 TxDqDly_Margin_A0==98 ps 10
1030 11:35:08.095365 RxClkDly_Margin_A1==88 ps 9
1031 11:35:08.100483 TxDqDly_Margin_A1==88 ps 9
1032 11:35:08.101051 TrainedVREFDQ_A0==77
1033 11:35:08.101520 TrainedVREFDQ_A1==77
1034 11:35:08.106004 VrefDac_Margin_A0==22
1035 11:35:08.106587 DeviceVref_Margin_A0==37
1036 11:35:08.111581 VrefDac_Margin_A1==24
1037 11:35:08.112176 DeviceVref_Margin_A1==37
1038 11:35:08.112650
1039 11:35:08.117153 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 11:35:08.117717
1041 11:35:08.145224 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1042 11:35:08.150792 2D training succeed
1043 11:35:08.156454 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 11:35:08.157030 auto size-- 65535DDR cs0 size: 2048MB
1045 11:35:08.161974 DDR cs1 size: 2048MB
1046 11:35:08.162534 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 11:35:08.167571 cs0 DataBus test pass
1048 11:35:08.168197 cs1 DataBus test pass
1049 11:35:08.168712 cs0 AddrBus test pass
1050 11:35:08.173199 cs1 AddrBus test pass
1051 11:35:08.173765
1052 11:35:08.174240 100bdlr_step_size ps== 420
1053 11:35:08.174707 result report
1054 11:35:08.178776 boot times 0Enable ddr reg access
1055 11:35:08.186584 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 11:35:08.199918 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 11:35:08.771865 0.0;M3 CHK:0;cm4_sp_mode 0
1058 11:35:08.772482 MVN_1=0x00000000
1059 11:35:08.777527 MVN_2=0x00000000
1060 11:35:08.783252 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 11:35:08.783813 OPS=0x10
1062 11:35:08.784336 ring efuse init
1063 11:35:08.784803 chipver efuse init
1064 11:35:08.788835 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 11:35:08.794513 [0.018961 Inits done]
1066 11:35:08.795068 secure task start!
1067 11:35:08.795535 high task start!
1068 11:35:08.798983 low task start!
1069 11:35:08.799547 run into bl31
1070 11:35:08.805671 NOTICE: BL31: v1.3(release):4fc40b1
1071 11:35:08.813589 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 11:35:08.814153 NOTICE: BL31: G12A normal boot!
1073 11:35:08.838805 NOTICE: BL31: BL33 decompress pass
1074 11:35:08.844584 ERROR: Error initializing runtime service opteed_fast
1075 11:35:10.077273
1076 11:35:10.077882
1077 11:35:10.084920 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 11:35:10.085509
1079 11:35:10.086020 Model: Libre Computer AML-A311D-CC Alta
1080 11:35:10.293188 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 11:35:10.316661 DRAM: 2 GiB (effective 3.8 GiB)
1082 11:35:10.460534 Core: 408 devices, 31 uclasses, devicetree: separate
1083 11:35:10.466436 WDT: Not starting watchdog@f0d0
1084 11:35:10.498752 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 11:35:10.511103 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 11:35:10.516119 ** Bad device specification mmc 0 **
1087 11:35:10.526480 Card did not respond to voltage select! : -110
1088 11:35:10.533240 ** Bad device specification mmc 0 **
1089 11:35:10.533812 Couldn't find partition mmc 0
1090 11:35:10.542494 Card did not respond to voltage select! : -110
1091 11:35:10.548018 ** Bad device specification mmc 0 **
1092 11:35:10.548580 Couldn't find partition mmc 0
1093 11:35:10.553040 Error: could not access storage.
1094 11:35:10.895561 Net: eth0: ethernet@ff3f0000
1095 11:35:10.896238 starting USB...
1096 11:35:11.147290 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 11:35:11.147881 Starting the controller
1098 11:35:11.153974 USB XHCI 1.10
1099 11:35:12.708269 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 11:35:12.716624 scanning usb for storage devices... 0 Storage Device(s) found
1102 11:35:12.768335 Hit any key to stop autoboot: 1
1103 11:35:12.769457 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 11:35:12.770162 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 11:35:12.770709 Setting prompt string to ['=>']
1106 11:35:12.771252 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 11:35:12.784203 0
1108 11:35:12.785206 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 11:35:12.785772 Sending with 10 millisecond of delay
1111 11:35:13.920665 => setenv autoload no
1112 11:35:13.931484 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 11:35:13.937024 setenv autoload no
1114 11:35:13.937830 Sending with 10 millisecond of delay
1116 11:35:15.735244 => setenv initrd_high 0xffffffff
1117 11:35:15.746127 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 11:35:15.747187 setenv initrd_high 0xffffffff
1119 11:35:15.748025 Sending with 10 millisecond of delay
1121 11:35:17.364678 => setenv fdt_high 0xffffffff
1122 11:35:17.375537 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 11:35:17.376515 setenv fdt_high 0xffffffff
1124 11:35:17.377297 Sending with 10 millisecond of delay
1126 11:35:17.669268 => dhcp
1127 11:35:17.680096 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 11:35:17.681015 dhcp
1129 11:35:17.681499 Speed: 1000, full duplex
1130 11:35:17.681958 BOOTP broadcast 1
1131 11:35:17.689296 DHCP client bound to address 192.168.6.27 (9 ms)
1132 11:35:17.690099 Sending with 10 millisecond of delay
1134 11:35:19.367031 => setenv serverip 192.168.6.2
1135 11:35:19.377761 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 11:35:19.378439 setenv serverip 192.168.6.2
1137 11:35:19.379043 Sending with 10 millisecond of delay
1139 11:35:23.103037 => tftpboot 0x01080000 913381/tftp-deploy-md15v7tt/kernel/uImage
1140 11:35:23.113844 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 11:35:23.114700 tftpboot 0x01080000 913381/tftp-deploy-md15v7tt/kernel/uImage
1142 11:35:23.115163 Speed: 1000, full duplex
1143 11:35:23.115587 Using ethernet@ff3f0000 device
1144 11:35:23.116684 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 11:35:23.122138 Filename '913381/tftp-deploy-md15v7tt/kernel/uImage'.
1146 11:35:23.125901 Load address: 0x1080000
1147 11:35:26.078244 Loading: *################################################## 44.1 MiB
1148 11:35:26.078914 14.9 MiB/s
1149 11:35:26.079364 done
1150 11:35:26.082888 Bytes transferred = 46256704 (2c1d240 hex)
1151 11:35:26.083688 Sending with 10 millisecond of delay
1153 11:35:30.778885 => tftpboot 0x08000000 913381/tftp-deploy-md15v7tt/ramdisk/ramdisk.cpio.gz.uboot
1154 11:35:30.790065 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 11:35:30.791369 tftpboot 0x08000000 913381/tftp-deploy-md15v7tt/ramdisk/ramdisk.cpio.gz.uboot
1156 11:35:30.792155 Speed: 1000, full duplex
1157 11:35:30.792869 Using ethernet@ff3f0000 device
1158 11:35:30.793688 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 11:35:30.804475 Filename '913381/tftp-deploy-md15v7tt/ramdisk/ramdisk.cpio.gz.uboot'.
1160 11:35:30.805252 Load address: 0x8000000
1161 11:35:37.747710 Loading: *###############T ################################## UDP wrong checksum 00000005 0000120f
1162 11:35:42.748260 T UDP wrong checksum 00000005 0000120f
1163 11:35:52.751346 T T UDP wrong checksum 00000005 0000120f
1164 11:35:57.772219 T UDP wrong checksum 000000ff 00005f6b
1165 11:35:57.782559 UDP wrong checksum 000000ff 0000f65d
1166 11:36:12.755406 T T T UDP wrong checksum 00000005 0000120f
1167 11:36:27.759496 T T
1168 11:36:27.760254 Retry count exceeded; starting again
1170 11:36:27.761777 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1173 11:36:27.763723 end: 2.4 uboot-commands (duration 00:01:52) [common]
1175 11:36:27.765249 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1177 11:36:27.766561 end: 2 uboot-action (duration 00:01:52) [common]
1179 11:36:27.768258 Cleaning after the job
1180 11:36:27.768887 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/ramdisk
1181 11:36:27.770398 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/kernel
1182 11:36:27.820138 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/dtb
1183 11:36:27.821050 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/nfsrootfs
1184 11:36:27.980295 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913381/tftp-deploy-md15v7tt/modules
1185 11:36:28.001822 start: 4.1 power-off (timeout 00:00:30) [common]
1186 11:36:28.002562 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1187 11:36:28.038174 >> OK - accepted request
1188 11:36:28.040504 Returned 0 in 0 seconds
1189 11:36:28.141731 end: 4.1 power-off (duration 00:00:00) [common]
1191 11:36:28.142833 start: 4.2 read-feedback (timeout 00:10:00) [common]
1192 11:36:28.143589 Listened to connection for namespace 'common' for up to 1s
1193 11:36:29.144481 Finalising connection for namespace 'common'
1194 11:36:29.144975 Disconnecting from shell: Finalise
1195 11:36:29.145260 =>
1196 11:36:29.245977 end: 4.2 read-feedback (duration 00:00:01) [common]
1197 11:36:29.246551 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/913381
1198 11:36:30.934991 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/913381
1199 11:36:30.935617 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.