Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 11:31:35.562755 lava-dispatcher, installed at version: 2024.01
2 11:31:35.563557 start: 0 validate
3 11:31:35.564029 Start time: 2024-10-30 11:31:35.563997+00:00 (UTC)
4 11:31:35.564596 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 11:31:35.565125 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 11:31:35.602578 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 11:31:35.603177 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 11:31:35.632890 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 11:31:35.633500 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 11:31:36.679680 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 11:31:36.680284 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 11:31:36.723739 validate duration: 1.16
14 11:31:36.724688 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:31:36.725038 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:31:36.725371 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:31:36.725994 Not decompressing ramdisk as can be used compressed.
18 11:31:36.726444 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 11:31:36.726728 saving as /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/ramdisk/rootfs.cpio.gz
20 11:31:36.727017 total size: 8181887 (7 MB)
21 11:31:36.761232 progress 0 % (0 MB)
22 11:31:36.767084 progress 5 % (0 MB)
23 11:31:36.772607 progress 10 % (0 MB)
24 11:31:36.778443 progress 15 % (1 MB)
25 11:31:36.783738 progress 20 % (1 MB)
26 11:31:36.789304 progress 25 % (1 MB)
27 11:31:36.794492 progress 30 % (2 MB)
28 11:31:36.800020 progress 35 % (2 MB)
29 11:31:36.805147 progress 40 % (3 MB)
30 11:31:36.810658 progress 45 % (3 MB)
31 11:31:36.815778 progress 50 % (3 MB)
32 11:31:36.821310 progress 55 % (4 MB)
33 11:31:36.826390 progress 60 % (4 MB)
34 11:31:36.831872 progress 65 % (5 MB)
35 11:31:36.837052 progress 70 % (5 MB)
36 11:31:36.842528 progress 75 % (5 MB)
37 11:31:36.847613 progress 80 % (6 MB)
38 11:31:36.853117 progress 85 % (6 MB)
39 11:31:36.858282 progress 90 % (7 MB)
40 11:31:36.863849 progress 95 % (7 MB)
41 11:31:36.868713 progress 100 % (7 MB)
42 11:31:36.869377 7 MB downloaded in 0.14 s (54.82 MB/s)
43 11:31:36.869925 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:31:36.870805 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:31:36.871095 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:31:36.871363 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:31:36.871839 downloading http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
49 11:31:36.872105 saving as /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/kernel/Image
50 11:31:36.872313 total size: 46256640 (44 MB)
51 11:31:36.872520 No compression specified
52 11:31:36.904631 progress 0 % (0 MB)
53 11:31:36.932646 progress 5 % (2 MB)
54 11:31:36.960985 progress 10 % (4 MB)
55 11:31:36.989076 progress 15 % (6 MB)
56 11:31:37.017237 progress 20 % (8 MB)
57 11:31:37.044841 progress 25 % (11 MB)
58 11:31:37.072985 progress 30 % (13 MB)
59 11:31:37.101210 progress 35 % (15 MB)
60 11:31:37.129258 progress 40 % (17 MB)
61 11:31:37.157559 progress 45 % (19 MB)
62 11:31:37.185343 progress 50 % (22 MB)
63 11:31:37.213627 progress 55 % (24 MB)
64 11:31:37.241456 progress 60 % (26 MB)
65 11:31:37.270555 progress 65 % (28 MB)
66 11:31:37.299324 progress 70 % (30 MB)
67 11:31:37.328076 progress 75 % (33 MB)
68 11:31:37.356540 progress 80 % (35 MB)
69 11:31:37.384354 progress 85 % (37 MB)
70 11:31:37.412540 progress 90 % (39 MB)
71 11:31:37.440735 progress 95 % (41 MB)
72 11:31:37.468491 progress 100 % (44 MB)
73 11:31:37.469164 44 MB downloaded in 0.60 s (73.91 MB/s)
74 11:31:37.469649 end: 1.2.1 http-download (duration 00:00:01) [common]
76 11:31:37.470455 end: 1.2 download-retry (duration 00:00:01) [common]
77 11:31:37.470726 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:31:37.470986 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:31:37.471462 downloading http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 11:31:37.471739 saving as /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 11:31:37.471949 total size: 53209 (0 MB)
82 11:31:37.472188 No compression specified
83 11:31:37.508093 progress 61 % (0 MB)
84 11:31:37.508958 progress 100 % (0 MB)
85 11:31:37.509509 0 MB downloaded in 0.04 s (1.35 MB/s)
86 11:31:37.509995 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:31:37.510872 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:31:37.511155 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:31:37.511434 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:31:37.511913 downloading http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
92 11:31:37.512197 saving as /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/modules/modules.tar
93 11:31:37.512412 total size: 11596668 (11 MB)
94 11:31:37.512630 Using unxz to decompress xz
95 11:31:37.548160 progress 0 % (0 MB)
96 11:31:37.621032 progress 5 % (0 MB)
97 11:31:37.698319 progress 10 % (1 MB)
98 11:31:37.782056 progress 15 % (1 MB)
99 11:31:37.859700 progress 20 % (2 MB)
100 11:31:37.938634 progress 25 % (2 MB)
101 11:31:38.019509 progress 30 % (3 MB)
102 11:31:38.094302 progress 35 % (3 MB)
103 11:31:38.176754 progress 40 % (4 MB)
104 11:31:38.264289 progress 45 % (5 MB)
105 11:31:38.342703 progress 50 % (5 MB)
106 11:31:38.427625 progress 55 % (6 MB)
107 11:31:38.508992 progress 60 % (6 MB)
108 11:31:38.593740 progress 65 % (7 MB)
109 11:31:38.669151 progress 70 % (7 MB)
110 11:31:38.752908 progress 75 % (8 MB)
111 11:31:38.836004 progress 80 % (8 MB)
112 11:31:38.911816 progress 85 % (9 MB)
113 11:31:38.984917 progress 90 % (9 MB)
114 11:31:39.086213 progress 95 % (10 MB)
115 11:31:39.179467 progress 100 % (11 MB)
116 11:31:39.194924 11 MB downloaded in 1.68 s (6.57 MB/s)
117 11:31:39.195898 end: 1.4.1 http-download (duration 00:00:02) [common]
119 11:31:39.197724 end: 1.4 download-retry (duration 00:00:02) [common]
120 11:31:39.198298 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 11:31:39.198867 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 11:31:39.199409 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:31:39.199959 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 11:31:39.201125 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd
125 11:31:39.202017 makedir: /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin
126 11:31:39.202708 makedir: /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/tests
127 11:31:39.203376 makedir: /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/results
128 11:31:39.204073 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-add-keys
129 11:31:39.205104 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-add-sources
130 11:31:39.206121 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-background-process-start
131 11:31:39.207146 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-background-process-stop
132 11:31:39.208248 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-common-functions
133 11:31:39.209417 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-echo-ipv4
134 11:31:39.210413 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-install-packages
135 11:31:39.211418 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-installed-packages
136 11:31:39.212435 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-os-build
137 11:31:39.213420 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-probe-channel
138 11:31:39.214392 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-probe-ip
139 11:31:39.215368 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-target-ip
140 11:31:39.216379 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-target-mac
141 11:31:39.217371 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-target-storage
142 11:31:39.218353 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-test-case
143 11:31:39.219329 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-test-event
144 11:31:39.220330 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-test-feedback
145 11:31:39.221313 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-test-raise
146 11:31:39.222276 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-test-reference
147 11:31:39.223250 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-test-runner
148 11:31:39.224248 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-test-set
149 11:31:39.225220 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-test-shell
150 11:31:39.226222 Updating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-install-packages (oe)
151 11:31:39.227261 Updating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/bin/lava-installed-packages (oe)
152 11:31:39.228180 Creating /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/environment
153 11:31:39.228954 LAVA metadata
154 11:31:39.229474 - LAVA_JOB_ID=913397
155 11:31:39.229944 - LAVA_DISPATCHER_IP=192.168.6.2
156 11:31:39.230674 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 11:31:39.232685 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 11:31:39.233286 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 11:31:39.233693 skipped lava-vland-overlay
160 11:31:39.234175 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 11:31:39.234674 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 11:31:39.235101 skipped lava-multinode-overlay
163 11:31:39.235574 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 11:31:39.236099 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 11:31:39.236576 Loading test definitions
166 11:31:39.237114 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 11:31:39.237546 Using /lava-913397 at stage 0
168 11:31:39.239450 uuid=913397_1.5.2.4.1 testdef=None
169 11:31:39.239781 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 11:31:39.240146 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 11:31:39.243850 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 11:31:39.245588 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 11:31:39.250331 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 11:31:39.252127 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 11:31:39.256743 runner path: /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/0/tests/0_dmesg test_uuid 913397_1.5.2.4.1
178 11:31:39.257765 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 11:31:39.259237 Creating lava-test-runner.conf files
181 11:31:39.259635 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/913397/lava-overlay-saj8waxd/lava-913397/0 for stage 0
182 11:31:39.260313 - 0_dmesg
183 11:31:39.260973 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 11:31:39.261500 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 11:31:39.286196 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 11:31:39.286630 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 11:31:39.286897 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 11:31:39.287167 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 11:31:39.287433 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 11:31:40.224809 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 11:31:40.225384 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 11:31:40.225688 extracting modules file /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/913397/extract-overlay-ramdisk-cw6_z2c0/ramdisk
193 11:31:41.634075 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 11:31:41.634628 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 11:31:41.634966 [common] Applying overlay /var/lib/lava/dispatcher/tmp/913397/compress-overlay-einp90ce/overlay-1.5.2.5.tar.gz to ramdisk
196 11:31:41.635225 [common] Applying overlay /var/lib/lava/dispatcher/tmp/913397/compress-overlay-einp90ce/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/913397/extract-overlay-ramdisk-cw6_z2c0/ramdisk
197 11:31:41.672708 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 11:31:41.673228 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 11:31:41.673560 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 11:31:41.673831 Converting downloaded kernel to a uImage
201 11:31:41.674209 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/kernel/Image /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/kernel/uImage
202 11:31:42.141396 output: Image Name:
203 11:31:42.141803 output: Created: Wed Oct 30 11:31:41 2024
204 11:31:42.142012 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 11:31:42.142218 output: Data Size: 46256640 Bytes = 45172.50 KiB = 44.11 MiB
206 11:31:42.142418 output: Load Address: 01080000
207 11:31:42.142615 output: Entry Point: 01080000
208 11:31:42.142809 output:
209 11:31:42.143138 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 11:31:42.143403 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 11:31:42.143675 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 11:31:42.143927 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 11:31:42.144227 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 11:31:42.144486 Building ramdisk /var/lib/lava/dispatcher/tmp/913397/extract-overlay-ramdisk-cw6_z2c0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/913397/extract-overlay-ramdisk-cw6_z2c0/ramdisk
215 11:31:44.762897 >> 181899 blocks
216 11:31:53.241827 Adding RAMdisk u-boot header.
217 11:31:53.242258 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/913397/extract-overlay-ramdisk-cw6_z2c0/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/913397/extract-overlay-ramdisk-cw6_z2c0/ramdisk.cpio.gz.uboot
218 11:31:53.521051 output: Image Name:
219 11:31:53.521467 output: Created: Wed Oct 30 11:31:53 2024
220 11:31:53.521676 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 11:31:53.521878 output: Data Size: 26053193 Bytes = 25442.57 KiB = 24.85 MiB
222 11:31:53.522076 output: Load Address: 00000000
223 11:31:53.522273 output: Entry Point: 00000000
224 11:31:53.522465 output:
225 11:31:53.523102 rename /var/lib/lava/dispatcher/tmp/913397/extract-overlay-ramdisk-cw6_z2c0/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/ramdisk/ramdisk.cpio.gz.uboot
226 11:31:53.523514 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 11:31:53.523797 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 11:31:53.524193 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 11:31:53.524653 No LXC device requested
230 11:31:53.525150 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 11:31:53.525649 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 11:31:53.526130 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 11:31:53.526543 Checking files for TFTP limit of 4294967296 bytes.
234 11:31:53.529205 end: 1 tftp-deploy (duration 00:00:17) [common]
235 11:31:53.529774 start: 2 uboot-action (timeout 00:05:00) [common]
236 11:31:53.530284 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 11:31:53.530771 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 11:31:53.531260 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 11:31:53.531781 Using kernel file from prepare-kernel: 913397/tftp-deploy-hvtvztz6/kernel/uImage
240 11:31:53.532413 substitutions:
241 11:31:53.532816 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 11:31:53.533213 - {DTB_ADDR}: 0x01070000
243 11:31:53.533603 - {DTB}: 913397/tftp-deploy-hvtvztz6/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 11:31:53.533997 - {INITRD}: 913397/tftp-deploy-hvtvztz6/ramdisk/ramdisk.cpio.gz.uboot
245 11:31:53.534386 - {KERNEL_ADDR}: 0x01080000
246 11:31:53.534773 - {KERNEL}: 913397/tftp-deploy-hvtvztz6/kernel/uImage
247 11:31:53.535159 - {LAVA_MAC}: None
248 11:31:53.535581 - {PRESEED_CONFIG}: None
249 11:31:53.535969 - {PRESEED_LOCAL}: None
250 11:31:53.536392 - {RAMDISK_ADDR}: 0x08000000
251 11:31:53.536774 - {RAMDISK}: 913397/tftp-deploy-hvtvztz6/ramdisk/ramdisk.cpio.gz.uboot
252 11:31:53.537162 - {ROOT_PART}: None
253 11:31:53.537547 - {ROOT}: None
254 11:31:53.537930 - {SERVER_IP}: 192.168.6.2
255 11:31:53.538315 - {TEE_ADDR}: 0x83000000
256 11:31:53.538699 - {TEE}: None
257 11:31:53.539081 Parsed boot commands:
258 11:31:53.539453 - setenv autoload no
259 11:31:53.539832 - setenv initrd_high 0xffffffff
260 11:31:53.540233 - setenv fdt_high 0xffffffff
261 11:31:53.540615 - dhcp
262 11:31:53.540995 - setenv serverip 192.168.6.2
263 11:31:53.541375 - tftpboot 0x01080000 913397/tftp-deploy-hvtvztz6/kernel/uImage
264 11:31:53.541759 - tftpboot 0x08000000 913397/tftp-deploy-hvtvztz6/ramdisk/ramdisk.cpio.gz.uboot
265 11:31:53.542372 - tftpboot 0x01070000 913397/tftp-deploy-hvtvztz6/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 11:31:53.542767 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 11:31:53.543157 - bootm 0x01080000 0x08000000 0x01070000
268 11:31:53.543653 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 11:31:53.545197 start: 2.3 connect-device (timeout 00:05:00) [common]
271 11:31:53.545644 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 11:31:53.559928 Setting prompt string to ['lava-test: # ']
273 11:31:53.561437 end: 2.3 connect-device (duration 00:00:00) [common]
274 11:31:53.562006 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 11:31:53.562546 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 11:31:53.563289 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 11:31:53.564451 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 11:31:53.597929 >> OK - accepted request
279 11:31:53.599964 Returned 0 in 0 seconds
280 11:31:53.701144 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 11:31:53.702834 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 11:31:53.703397 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 11:31:53.703899 Setting prompt string to ['Hit any key to stop autoboot']
285 11:31:53.704415 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 11:31:53.706011 Trying 192.168.56.21...
287 11:31:53.706500 Connected to conserv1.
288 11:31:53.706922 Escape character is '^]'.
289 11:31:53.707340
290 11:31:53.707752 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 11:31:53.708215
292 11:32:01.125081 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 11:32:01.125677 bl2_stage_init 0x01
294 11:32:01.126094 bl2_stage_init 0x81
295 11:32:01.130739 hw id: 0x0000 - pwm id 0x01
296 11:32:01.131185 bl2_stage_init 0xc1
297 11:32:01.131587 bl2_stage_init 0x02
298 11:32:01.132016
299 11:32:01.136205 L0:00000000
300 11:32:01.136631 L1:00000703
301 11:32:01.137022 L2:00008067
302 11:32:01.137405 L3:15000000
303 11:32:01.137793 S1:00000000
304 11:32:01.141819 B2:20282000
305 11:32:01.142237 B1:a0f83180
306 11:32:01.142629
307 11:32:01.143019 TE: 72532
308 11:32:01.143408
309 11:32:01.147398 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 11:32:01.147818
311 11:32:01.153040 Board ID = 1
312 11:32:01.153473 Set cpu clk to 24M
313 11:32:01.153860 Set clk81 to 24M
314 11:32:01.158691 Use GP1_pll as DSU clk.
315 11:32:01.159108 DSU clk: 1200 Mhz
316 11:32:01.159501 CPU clk: 1200 MHz
317 11:32:01.159887 Set clk81 to 166.6M
318 11:32:01.169810 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 11:32:01.170243 board id: 1
320 11:32:01.176213 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 11:32:01.186890 fw parse done
322 11:32:01.192871 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 11:32:01.235585 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 11:32:01.246455 PIEI prepare done
325 11:32:01.246902 fastboot data load
326 11:32:01.247298 fastboot data verify
327 11:32:01.252069 verify result: 266
328 11:32:01.257789 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 11:32:01.258208 LPDDR4 probe
330 11:32:01.258599 ddr clk to 1584MHz
331 11:32:01.265665 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 11:32:01.302917
333 11:32:01.303392 dmc_version 0001
334 11:32:01.309565 Check phy result
335 11:32:01.315442 INFO : End of CA training
336 11:32:01.315869 INFO : End of initialization
337 11:32:01.321145 INFO : Training has run successfully!
338 11:32:01.321570 Check phy result
339 11:32:01.326801 INFO : End of initialization
340 11:32:01.327215 INFO : End of read enable training
341 11:32:01.332279 INFO : End of fine write leveling
342 11:32:01.337892 INFO : End of Write leveling coarse delay
343 11:32:01.338309 INFO : Training has run successfully!
344 11:32:01.338698 Check phy result
345 11:32:01.343388 INFO : End of initialization
346 11:32:01.343800 INFO : End of read dq deskew training
347 11:32:01.349058 INFO : End of MPR read delay center optimization
348 11:32:01.354795 INFO : End of write delay center optimization
349 11:32:01.360272 INFO : End of read delay center optimization
350 11:32:01.360690 INFO : End of max read latency training
351 11:32:01.365859 INFO : Training has run successfully!
352 11:32:01.366272 1D training succeed
353 11:32:01.375046 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 11:32:01.422652 Check phy result
355 11:32:01.423086 INFO : End of initialization
356 11:32:01.444070 INFO : End of 2D read delay Voltage center optimization
357 11:32:01.464195 INFO : End of 2D read delay Voltage center optimization
358 11:32:01.516190 INFO : End of 2D write delay Voltage center optimization
359 11:32:01.565318 INFO : End of 2D write delay Voltage center optimization
360 11:32:01.570923 INFO : Training has run successfully!
361 11:32:01.571344
362 11:32:01.571737 channel==0
363 11:32:01.576426 RxClkDly_Margin_A0==88 ps 9
364 11:32:01.576851 TxDqDly_Margin_A0==98 ps 10
365 11:32:01.582095 RxClkDly_Margin_A1==88 ps 9
366 11:32:01.582522 TxDqDly_Margin_A1==98 ps 10
367 11:32:01.582915 TrainedVREFDQ_A0==74
368 11:32:01.587647 TrainedVREFDQ_A1==75
369 11:32:01.588094 VrefDac_Margin_A0==24
370 11:32:01.588484 DeviceVref_Margin_A0==40
371 11:32:01.593219 VrefDac_Margin_A1==23
372 11:32:01.593635 DeviceVref_Margin_A1==39
373 11:32:01.594025
374 11:32:01.594409
375 11:32:01.598926 channel==1
376 11:32:01.599343 RxClkDly_Margin_A0==78 ps 8
377 11:32:01.599734 TxDqDly_Margin_A0==98 ps 10
378 11:32:01.604549 RxClkDly_Margin_A1==78 ps 8
379 11:32:01.605005 TxDqDly_Margin_A1==88 ps 9
380 11:32:01.610693 TrainedVREFDQ_A0==78
381 11:32:01.611127 TrainedVREFDQ_A1==75
382 11:32:01.611517 VrefDac_Margin_A0==22
383 11:32:01.615826 DeviceVref_Margin_A0==36
384 11:32:01.616576 VrefDac_Margin_A1==22
385 11:32:01.621273 DeviceVref_Margin_A1==39
386 11:32:01.621785
387 11:32:01.622205 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 11:32:01.622610
389 11:32:01.655154 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
390 11:32:01.655855 2D training succeed
391 11:32:01.660430 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 11:32:01.666036 auto size-- 65535DDR cs0 size: 2048MB
393 11:32:01.666489 DDR cs1 size: 2048MB
394 11:32:01.671589 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 11:32:01.672076 cs0 DataBus test pass
396 11:32:01.677199 cs1 DataBus test pass
397 11:32:01.677666 cs0 AddrBus test pass
398 11:32:01.678060 cs1 AddrBus test pass
399 11:32:01.678448
400 11:32:01.682925 100bdlr_step_size ps== 464
401 11:32:01.683380 result report
402 11:32:01.688499 boot times 0Enable ddr reg access
403 11:32:01.693752 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 11:32:01.707495 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 11:32:02.361946 bl2z: ptr: 05129330, size: 00001e40
406 11:32:02.369411 0.0;M3 CHK:0;cm4_sp_mode 0
407 11:32:02.369939 MVN_1=0x00000000
408 11:32:02.370348 MVN_2=0x00000000
409 11:32:02.380946 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 11:32:02.381570 OPS=0x04
411 11:32:02.382008 ring efuse init
412 11:32:02.386461 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 11:32:02.387013 [0.017319 Inits done]
414 11:32:02.387448 secure task start!
415 11:32:02.393656 high task start!
416 11:32:02.394228 low task start!
417 11:32:02.394700 run into bl31
418 11:32:02.402234 NOTICE: BL31: v1.3(release):4fc40b1
419 11:32:02.410042 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 11:32:02.410571 NOTICE: BL31: G12A normal boot!
421 11:32:02.425688 NOTICE: BL31: BL33 decompress pass
422 11:32:02.431334 ERROR: Error initializing runtime service opteed_fast
423 11:32:05.171469 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 11:32:05.172167 bl2_stage_init 0x01
425 11:32:05.172654 bl2_stage_init 0x81
426 11:32:05.177021 hw id: 0x0000 - pwm id 0x01
427 11:32:05.177541 bl2_stage_init 0xc1
428 11:32:05.182622 bl2_stage_init 0x02
429 11:32:05.183166
430 11:32:05.183612 L0:00000000
431 11:32:05.184120 L1:00000703
432 11:32:05.184555 L2:00008067
433 11:32:05.184980 L3:15000000
434 11:32:05.188332 S1:00000000
435 11:32:05.188811 B2:20282000
436 11:32:05.189246 B1:a0f83180
437 11:32:05.189670
438 11:32:05.190096 TE: 68424
439 11:32:05.190518
440 11:32:05.193823 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 11:32:05.194298
442 11:32:05.199385 Board ID = 1
443 11:32:05.199858 Set cpu clk to 24M
444 11:32:05.200324 Set clk81 to 24M
445 11:32:05.205043 Use GP1_pll as DSU clk.
446 11:32:05.205517 DSU clk: 1200 Mhz
447 11:32:05.205947 CPU clk: 1200 MHz
448 11:32:05.210581 Set clk81 to 166.6M
449 11:32:05.216296 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 11:32:05.216833 board id: 1
451 11:32:05.222482 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 11:32:05.234055 fw parse done
453 11:32:05.239144 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 11:32:05.281738 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 11:32:05.293704 PIEI prepare done
456 11:32:05.294257 fastboot data load
457 11:32:05.294704 fastboot data verify
458 11:32:05.299412 verify result: 266
459 11:32:05.304904 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 11:32:05.305404 LPDDR4 probe
461 11:32:05.305838 ddr clk to 1584MHz
462 11:32:05.312828 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 11:32:05.349177
464 11:32:05.349721 dmc_version 0001
465 11:32:05.356048 Check phy result
466 11:32:05.362706 INFO : End of CA training
467 11:32:05.363215 INFO : End of initialization
468 11:32:05.368298 INFO : Training has run successfully!
469 11:32:05.368799 Check phy result
470 11:32:05.373889 INFO : End of initialization
471 11:32:05.374389 INFO : End of read enable training
472 11:32:05.379493 INFO : End of fine write leveling
473 11:32:05.385087 INFO : End of Write leveling coarse delay
474 11:32:05.385592 INFO : Training has run successfully!
475 11:32:05.386032 Check phy result
476 11:32:05.390689 INFO : End of initialization
477 11:32:05.391182 INFO : End of read dq deskew training
478 11:32:05.396393 INFO : End of MPR read delay center optimization
479 11:32:05.401886 INFO : End of write delay center optimization
480 11:32:05.407448 INFO : End of read delay center optimization
481 11:32:05.407936 INFO : End of max read latency training
482 11:32:05.413045 INFO : Training has run successfully!
483 11:32:05.413537 1D training succeed
484 11:32:05.421295 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 11:32:05.469887 Check phy result
486 11:32:05.470484 INFO : End of initialization
487 11:32:05.491366 INFO : End of 2D read delay Voltage center optimization
488 11:32:05.510526 INFO : End of 2D read delay Voltage center optimization
489 11:32:05.562517 INFO : End of 2D write delay Voltage center optimization
490 11:32:05.612544 INFO : End of 2D write delay Voltage center optimization
491 11:32:05.617994 INFO : Training has run successfully!
492 11:32:05.618527
493 11:32:05.619001 channel==0
494 11:32:05.623653 RxClkDly_Margin_A0==88 ps 9
495 11:32:05.624209 TxDqDly_Margin_A0==98 ps 10
496 11:32:05.626945 RxClkDly_Margin_A1==69 ps 7
497 11:32:05.627430 TxDqDly_Margin_A1==98 ps 10
498 11:32:05.632563 TrainedVREFDQ_A0==74
499 11:32:05.633090 TrainedVREFDQ_A1==75
500 11:32:05.633532 VrefDac_Margin_A0==25
501 11:32:05.638133 DeviceVref_Margin_A0==40
502 11:32:05.638637 VrefDac_Margin_A1==23
503 11:32:05.643835 DeviceVref_Margin_A1==39
504 11:32:05.644370
505 11:32:05.644811
506 11:32:05.645243 channel==1
507 11:32:05.645674 RxClkDly_Margin_A0==88 ps 9
508 11:32:05.649314 TxDqDly_Margin_A0==98 ps 10
509 11:32:05.649812 RxClkDly_Margin_A1==78 ps 8
510 11:32:05.654969 TxDqDly_Margin_A1==88 ps 9
511 11:32:05.655472 TrainedVREFDQ_A0==77
512 11:32:05.655947 TrainedVREFDQ_A1==75
513 11:32:05.660605 VrefDac_Margin_A0==22
514 11:32:05.661129 DeviceVref_Margin_A0==37
515 11:32:05.666187 VrefDac_Margin_A1==22
516 11:32:05.666694 DeviceVref_Margin_A1==39
517 11:32:05.667146
518 11:32:05.671911 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 11:32:05.672518
520 11:32:05.699815 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 11:32:05.705595 2D training succeed
522 11:32:05.711263 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 11:32:05.711881 auto size-- 65535DDR cs0 size: 2048MB
524 11:32:05.716596 DDR cs1 size: 2048MB
525 11:32:05.717193 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 11:32:05.722296 cs0 DataBus test pass
527 11:32:05.722935 cs1 DataBus test pass
528 11:32:05.723389 cs0 AddrBus test pass
529 11:32:05.727791 cs1 AddrBus test pass
530 11:32:05.728396
531 11:32:05.728843 100bdlr_step_size ps== 478
532 11:32:05.729289 result report
533 11:32:05.733428 boot times 0Enable ddr reg access
534 11:32:05.741142 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 11:32:05.754703 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 11:32:06.409642 bl2z: ptr: 05129330, size: 00001e40
537 11:32:06.415133 0.0;M3 CHK:0;cm4_sp_mode 0
538 11:32:06.415570 MVN_1=0x00000000
539 11:32:06.415826 MVN_2=0x00000000
540 11:32:06.420803 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 11:32:06.421222 OPS=0x04
542 11:32:06.426683 ring efuse init
543 11:32:06.432424 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 11:32:06.433021 [0.017319 Inits done]
545 11:32:06.433288 secure task start!
546 11:32:06.438976 high task start!
547 11:32:06.439647 low task start!
548 11:32:06.439912 run into bl31
549 11:32:06.447540 NOTICE: BL31: v1.3(release):4fc40b1
550 11:32:06.455313 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 11:32:06.456054 NOTICE: BL31: G12A normal boot!
552 11:32:06.473089 NOTICE: BL31: BL33 decompress pass
553 11:32:06.476373 ERROR: Error initializing runtime service opteed_fast
554 11:32:07.875471 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 11:32:07.876200 bl2_stage_init 0x01
556 11:32:07.876709 bl2_stage_init 0x81
557 11:32:07.881136 hw id: 0x0000 - pwm id 0x01
558 11:32:07.881649 bl2_stage_init 0xc1
559 11:32:07.886543 bl2_stage_init 0x02
560 11:32:07.887061
561 11:32:07.887540 L0:00000000
562 11:32:07.888020 L1:00000703
563 11:32:07.888468 L2:00008067
564 11:32:07.888912 L3:15000000
565 11:32:07.892088 S1:00000000
566 11:32:07.892576 B2:20282000
567 11:32:07.893021 B1:a0f83180
568 11:32:07.893458
569 11:32:07.893906 TE: 73373
570 11:32:07.894344
571 11:32:07.897702 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 11:32:07.898193
573 11:32:07.903276 Board ID = 1
574 11:32:07.903790 Set cpu clk to 24M
575 11:32:07.904277 Set clk81 to 24M
576 11:32:07.908784 Use GP1_pll as DSU clk.
577 11:32:07.909273 DSU clk: 1200 Mhz
578 11:32:07.909722 CPU clk: 1200 MHz
579 11:32:07.914609 Set clk81 to 166.6M
580 11:32:07.920041 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 11:32:07.920525 board id: 1
582 11:32:07.926310 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 11:32:07.937854 fw parse done
584 11:32:07.942911 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 11:32:07.986432 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 11:32:07.997553 PIEI prepare done
587 11:32:07.998069 fastboot data load
588 11:32:07.998531 fastboot data verify
589 11:32:08.003082 verify result: 266
590 11:32:08.008638 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 11:32:08.009141 LPDDR4 probe
592 11:32:08.009589 ddr clk to 1584MHz
593 11:32:08.016701 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 11:32:08.053966
595 11:32:08.054529 dmc_version 0001
596 11:32:08.060600 Check phy result
597 11:32:08.066473 INFO : End of CA training
598 11:32:08.066988 INFO : End of initialization
599 11:32:08.072098 INFO : Training has run successfully!
600 11:32:08.072604 Check phy result
601 11:32:08.077602 INFO : End of initialization
602 11:32:08.078098 INFO : End of read enable training
603 11:32:08.080942 INFO : End of fine write leveling
604 11:32:08.086612 INFO : End of Write leveling coarse delay
605 11:32:08.092263 INFO : Training has run successfully!
606 11:32:08.092771 Check phy result
607 11:32:08.093224 INFO : End of initialization
608 11:32:08.097854 INFO : End of read dq deskew training
609 11:32:08.103361 INFO : End of MPR read delay center optimization
610 11:32:08.103862 INFO : End of write delay center optimization
611 11:32:08.108978 INFO : End of read delay center optimization
612 11:32:08.114594 INFO : End of max read latency training
613 11:32:08.115092 INFO : Training has run successfully!
614 11:32:08.120220 1D training succeed
615 11:32:08.126095 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 11:32:08.173726 Check phy result
617 11:32:08.174301 INFO : End of initialization
618 11:32:08.196140 INFO : End of 2D read delay Voltage center optimization
619 11:32:08.215146 INFO : End of 2D read delay Voltage center optimization
620 11:32:08.266133 INFO : End of 2D write delay Voltage center optimization
621 11:32:08.316347 INFO : End of 2D write delay Voltage center optimization
622 11:32:08.321990 INFO : Training has run successfully!
623 11:32:08.322512
624 11:32:08.322967 channel==0
625 11:32:08.327429 RxClkDly_Margin_A0==78 ps 8
626 11:32:08.327935 TxDqDly_Margin_A0==98 ps 10
627 11:32:08.330835 RxClkDly_Margin_A1==88 ps 9
628 11:32:08.331336 TxDqDly_Margin_A1==98 ps 10
629 11:32:08.336365 TrainedVREFDQ_A0==74
630 11:32:08.336869 TrainedVREFDQ_A1==74
631 11:32:08.337324 VrefDac_Margin_A0==22
632 11:32:08.342042 DeviceVref_Margin_A0==40
633 11:32:08.342541 VrefDac_Margin_A1==23
634 11:32:08.347642 DeviceVref_Margin_A1==40
635 11:32:08.348171
636 11:32:08.348624
637 11:32:08.349067 channel==1
638 11:32:08.349500 RxClkDly_Margin_A0==88 ps 9
639 11:32:08.353271 TxDqDly_Margin_A0==98 ps 10
640 11:32:08.353778 RxClkDly_Margin_A1==88 ps 9
641 11:32:08.358757 TxDqDly_Margin_A1==88 ps 9
642 11:32:08.359263 TrainedVREFDQ_A0==78
643 11:32:08.359715 TrainedVREFDQ_A1==75
644 11:32:08.364367 VrefDac_Margin_A0==23
645 11:32:08.364877 DeviceVref_Margin_A0==36
646 11:32:08.369834 VrefDac_Margin_A1==22
647 11:32:08.370341 DeviceVref_Margin_A1==39
648 11:32:08.370788
649 11:32:08.375436 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 11:32:08.375935
651 11:32:08.403430 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 11:32:08.409073 2D training succeed
653 11:32:08.414654 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 11:32:08.415160 auto size-- 65535DDR cs0 size: 2048MB
655 11:32:08.420292 DDR cs1 size: 2048MB
656 11:32:08.420794 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 11:32:08.425818 cs0 DataBus test pass
658 11:32:08.426315 cs1 DataBus test pass
659 11:32:08.426759 cs0 AddrBus test pass
660 11:32:08.431470 cs1 AddrBus test pass
661 11:32:08.432022
662 11:32:08.432490 100bdlr_step_size ps== 478
663 11:32:08.432948 result report
664 11:32:08.437047 boot times 0Enable ddr reg access
665 11:32:08.444542 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 11:32:08.458402 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 11:32:09.113627 bl2z: ptr: 05129330, size: 00001e40
668 11:32:09.121045 0.0;M3 CHK:0;cm4_sp_mode 0
669 11:32:09.121588 MVN_1=0x00000000
670 11:32:09.122047 MVN_2=0x00000000
671 11:32:09.132475 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 11:32:09.133000 OPS=0x04
673 11:32:09.133507 ring efuse init
674 11:32:09.138112 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 11:32:09.138642 [0.017319 Inits done]
676 11:32:09.139099 secure task start!
677 11:32:09.145649 high task start!
678 11:32:09.146210 low task start!
679 11:32:09.146835 run into bl31
680 11:32:09.154201 NOTICE: BL31: v1.3(release):4fc40b1
681 11:32:09.161932 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 11:32:09.162471 NOTICE: BL31: G12A normal boot!
683 11:32:09.177405 NOTICE: BL31: BL33 decompress pass
684 11:32:09.183109 ERROR: Error initializing runtime service opteed_fast
685 11:32:09.978463
686 11:32:09.979126
687 11:32:09.983910 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 11:32:09.984476
689 11:32:09.987290 Model: Libre Computer AML-S905D3-CC Solitude
690 11:32:10.134375 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 11:32:10.149696 DRAM: 2 GiB (effective 3.8 GiB)
692 11:32:10.250675 Core: 406 devices, 33 uclasses, devicetree: separate
693 11:32:10.256561 WDT: Not starting watchdog@f0d0
694 11:32:10.281666 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 11:32:10.293909 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 11:32:10.298779 ** Bad device specification mmc 0 **
697 11:32:10.308940 Card did not respond to voltage select! : -110
698 11:32:10.316474 ** Bad device specification mmc 0 **
699 11:32:10.316937 Couldn't find partition mmc 0
700 11:32:10.324907 Card did not respond to voltage select! : -110
701 11:32:10.330401 ** Bad device specification mmc 0 **
702 11:32:10.330861 Couldn't find partition mmc 0
703 11:32:10.335388 Error: could not access storage.
704 11:32:10.631960 Net: eth0: ethernet@ff3f0000
705 11:32:10.632617 starting USB...
706 11:32:10.877742 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 11:32:10.878133 Starting the controller
708 11:32:10.883675 USB XHCI 1.10
709 11:32:12.438742 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 11:32:12.447004 scanning usb for storage devices... 0 Storage Device(s) found
712 11:32:12.498119 Hit any key to stop autoboot: 1
713 11:32:12.498724 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 11:32:12.499070 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 11:32:12.499336 Setting prompt string to ['=>']
716 11:32:12.499603 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 11:32:12.513052 0
718 11:32:12.513653 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 11:32:12.614456 => setenv autoload no
721 11:32:12.614978 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 11:32:12.619330 setenv autoload no
724 11:32:12.720336 => setenv initrd_high 0xffffffff
725 11:32:12.720813 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 11:32:12.724938 setenv initrd_high 0xffffffff
728 11:32:12.825943 => setenv fdt_high 0xffffffff
729 11:32:12.826521 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 11:32:12.830324 setenv fdt_high 0xffffffff
732 11:32:12.931443 => dhcp
733 11:32:12.932023 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 11:32:12.936098 dhcp
735 11:32:13.490577 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 11:32:13.490972 Speed: 1000, full duplex
737 11:32:13.491192 BOOTP broadcast 1
738 11:32:13.504828 DHCP client bound to address 192.168.6.21 (13 ms)
740 11:32:13.606511 => setenv serverip 192.168.6.2
741 11:32:13.607246 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
742 11:32:13.610972 setenv serverip 192.168.6.2
744 11:32:13.712569 => tftpboot 0x01080000 913397/tftp-deploy-hvtvztz6/kernel/uImage
745 11:32:13.713346 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 11:32:13.720082 tftpboot 0x01080000 913397/tftp-deploy-hvtvztz6/kernel/uImage
747 11:32:13.720638 Speed: 1000, full duplex
748 11:32:13.721082 Using ethernet@ff3f0000 device
749 11:32:13.725618 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 11:32:13.731122 Filename '913397/tftp-deploy-hvtvztz6/kernel/uImage'.
751 11:32:13.734443 Load address: 0x1080000
752 11:32:16.665767 Loading: *################################################## 44.1 MiB
753 11:32:16.666405 15 MiB/s
754 11:32:16.666883 done
755 11:32:16.669196 Bytes transferred = 46256704 (2c1d240 hex)
757 11:32:16.771282 => tftpboot 0x08000000 913397/tftp-deploy-hvtvztz6/ramdisk/ramdisk.cpio.gz.uboot
758 11:32:16.772496 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
759 11:32:16.779167 tftpboot 0x08000000 913397/tftp-deploy-hvtvztz6/ramdisk/ramdisk.cpio.gz.uboot
760 11:32:16.779906 Speed: 1000, full duplex
761 11:32:16.780669 Using ethernet@ff3f0000 device
762 11:32:16.784626 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 11:32:16.794293 Filename '913397/tftp-deploy-hvtvztz6/ramdisk/ramdisk.cpio.gz.uboot'.
764 11:32:16.794752 Load address: 0x8000000
765 11:32:18.443240 Loading: *################################################# UDP wrong checksum 00000005 0000fb1d
766 11:32:23.445379 T UDP wrong checksum 00000005 0000fb1d
767 11:32:33.447559 T T UDP wrong checksum 00000005 0000fb1d
768 11:32:53.451480 T T T T UDP wrong checksum 00000005 0000fb1d
769 11:33:10.342840 T T T UDP wrong checksum 000000ff 00003403
770 11:33:10.390883 UDP wrong checksum 000000ff 0000bff5
771 11:33:13.456255
772 11:33:13.456855 Retry count exceeded; starting again
774 11:33:13.458333 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
777 11:33:13.460392 end: 2.4 uboot-commands (duration 00:01:20) [common]
779 11:33:13.461891 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
781 11:33:13.463044 end: 2 uboot-action (duration 00:01:20) [common]
783 11:33:13.464770 Cleaning after the job
784 11:33:13.465388 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/ramdisk
785 11:33:13.467051 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/kernel
786 11:33:13.515269 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/dtb
787 11:33:13.516117 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913397/tftp-deploy-hvtvztz6/modules
788 11:33:13.535435 start: 4.1 power-off (timeout 00:00:30) [common]
789 11:33:13.536097 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
790 11:33:13.587862 >> OK - accepted request
791 11:33:13.590537 Returned 0 in 0 seconds
792 11:33:13.691374 end: 4.1 power-off (duration 00:00:00) [common]
794 11:33:13.692986 start: 4.2 read-feedback (timeout 00:10:00) [common]
795 11:33:13.694086 Listened to connection for namespace 'common' for up to 1s
796 11:33:14.694919 Finalising connection for namespace 'common'
797 11:33:14.695695 Disconnecting from shell: Finalise
798 11:33:14.696312 =>
799 11:33:14.797352 end: 4.2 read-feedback (duration 00:00:01) [common]
800 11:33:14.798067 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/913397
801 11:33:15.088375 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/913397
802 11:33:15.088970 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.