Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 5
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 10:52:53.424295 lava-dispatcher, installed at version: 2024.01
2 10:52:53.425044 start: 0 validate
3 10:52:53.425510 Start time: 2024-10-30 10:52:53.425480+00:00 (UTC)
4 10:52:53.426032 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:52:53.426571 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 10:52:53.468254 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:52:53.468756 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 10:52:53.497180 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:52:53.497784 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 10:52:53.526700 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:52:53.527397 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 10:52:53.558957 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 10:52:53.559414 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241030%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 10:52:53.597510 validate duration: 0.17
16 10:52:53.598433 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:52:53.598775 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:52:53.599119 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:52:53.599729 Not decompressing ramdisk as can be used compressed.
20 10:52:53.600727 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 10:52:53.601283 saving as /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/ramdisk/initrd.cpio.gz
22 10:52:53.601834 total size: 5628169 (5 MB)
23 10:52:53.638215 progress 0 % (0 MB)
24 10:52:53.643332 progress 5 % (0 MB)
25 10:52:53.648631 progress 10 % (0 MB)
26 10:52:53.653231 progress 15 % (0 MB)
27 10:52:53.658393 progress 20 % (1 MB)
28 10:52:53.662965 progress 25 % (1 MB)
29 10:52:53.667999 progress 30 % (1 MB)
30 10:52:53.673985 progress 35 % (1 MB)
31 10:52:53.678602 progress 40 % (2 MB)
32 10:52:53.682512 progress 45 % (2 MB)
33 10:52:53.686037 progress 50 % (2 MB)
34 10:52:53.689994 progress 55 % (2 MB)
35 10:52:53.693897 progress 60 % (3 MB)
36 10:52:53.697414 progress 65 % (3 MB)
37 10:52:53.701342 progress 70 % (3 MB)
38 10:52:53.704929 progress 75 % (4 MB)
39 10:52:53.708838 progress 80 % (4 MB)
40 10:52:53.712371 progress 85 % (4 MB)
41 10:52:53.716300 progress 90 % (4 MB)
42 10:52:53.720209 progress 95 % (5 MB)
43 10:52:53.723485 progress 100 % (5 MB)
44 10:52:53.724188 5 MB downloaded in 0.12 s (43.87 MB/s)
45 10:52:53.724745 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:52:53.725640 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:52:53.725938 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:52:53.726213 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:52:53.726692 downloading http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig/gcc-12/kernel/Image
51 10:52:53.726950 saving as /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/kernel/Image
52 10:52:53.727159 total size: 45906432 (43 MB)
53 10:52:53.727370 No compression specified
54 10:52:53.761861 progress 0 % (0 MB)
55 10:52:53.791576 progress 5 % (2 MB)
56 10:52:53.820901 progress 10 % (4 MB)
57 10:52:53.849915 progress 15 % (6 MB)
58 10:52:53.879021 progress 20 % (8 MB)
59 10:52:53.911387 progress 25 % (10 MB)
60 10:52:53.940144 progress 30 % (13 MB)
61 10:52:53.969759 progress 35 % (15 MB)
62 10:52:53.998859 progress 40 % (17 MB)
63 10:52:54.028358 progress 45 % (19 MB)
64 10:52:54.057354 progress 50 % (21 MB)
65 10:52:54.085863 progress 55 % (24 MB)
66 10:52:54.115270 progress 60 % (26 MB)
67 10:52:54.143976 progress 65 % (28 MB)
68 10:52:54.172960 progress 70 % (30 MB)
69 10:52:54.201968 progress 75 % (32 MB)
70 10:52:54.230162 progress 80 % (35 MB)
71 10:52:54.258848 progress 85 % (37 MB)
72 10:52:54.287053 progress 90 % (39 MB)
73 10:52:54.315681 progress 95 % (41 MB)
74 10:52:54.343843 progress 100 % (43 MB)
75 10:52:54.344700 43 MB downloaded in 0.62 s (70.90 MB/s)
76 10:52:54.345231 end: 1.2.1 http-download (duration 00:00:01) [common]
78 10:52:54.346076 end: 1.2 download-retry (duration 00:00:01) [common]
79 10:52:54.346355 start: 1.3 download-retry (timeout 00:09:59) [common]
80 10:52:54.346623 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 10:52:54.347077 downloading http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 10:52:54.347332 saving as /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/dtb/meson-g12b-a311d-libretech-cc.dtb
83 10:52:54.347539 total size: 54703 (0 MB)
84 10:52:54.347749 No compression specified
85 10:52:54.387393 progress 59 % (0 MB)
86 10:52:54.388368 progress 100 % (0 MB)
87 10:52:54.388957 0 MB downloaded in 0.04 s (1.26 MB/s)
88 10:52:54.389448 end: 1.3.1 http-download (duration 00:00:00) [common]
90 10:52:54.390274 end: 1.3 download-retry (duration 00:00:00) [common]
91 10:52:54.390539 start: 1.4 download-retry (timeout 00:09:59) [common]
92 10:52:54.390803 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 10:52:54.391254 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 10:52:54.391506 saving as /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/nfsrootfs/full.rootfs.tar
95 10:52:54.391712 total size: 120894716 (115 MB)
96 10:52:54.391922 Using unxz to decompress xz
97 10:52:54.426082 progress 0 % (0 MB)
98 10:52:55.225133 progress 5 % (5 MB)
99 10:52:56.064478 progress 10 % (11 MB)
100 10:52:56.898513 progress 15 % (17 MB)
101 10:52:57.627938 progress 20 % (23 MB)
102 10:52:58.217023 progress 25 % (28 MB)
103 10:52:59.047795 progress 30 % (34 MB)
104 10:52:59.845853 progress 35 % (40 MB)
105 10:53:00.208746 progress 40 % (46 MB)
106 10:53:00.587653 progress 45 % (51 MB)
107 10:53:01.341075 progress 50 % (57 MB)
108 10:53:02.248025 progress 55 % (63 MB)
109 10:53:03.035144 progress 60 % (69 MB)
110 10:53:03.789791 progress 65 % (74 MB)
111 10:53:04.565712 progress 70 % (80 MB)
112 10:53:05.392258 progress 75 % (86 MB)
113 10:53:06.179845 progress 80 % (92 MB)
114 10:53:06.941083 progress 85 % (98 MB)
115 10:53:07.796284 progress 90 % (103 MB)
116 10:53:08.574456 progress 95 % (109 MB)
117 10:53:09.416342 progress 100 % (115 MB)
118 10:53:09.429779 115 MB downloaded in 15.04 s (7.67 MB/s)
119 10:53:09.430502 end: 1.4.1 http-download (duration 00:00:15) [common]
121 10:53:09.432336 end: 1.4 download-retry (duration 00:00:15) [common]
122 10:53:09.432919 start: 1.5 download-retry (timeout 00:09:44) [common]
123 10:53:09.433492 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 10:53:09.434685 downloading http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig/gcc-12/modules.tar.xz
125 10:53:09.435206 saving as /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/modules/modules.tar
126 10:53:09.435663 total size: 11588888 (11 MB)
127 10:53:09.436168 Using unxz to decompress xz
128 10:53:09.476939 progress 0 % (0 MB)
129 10:53:09.546676 progress 5 % (0 MB)
130 10:53:09.621765 progress 10 % (1 MB)
131 10:53:09.703287 progress 15 % (1 MB)
132 10:53:09.778711 progress 20 % (2 MB)
133 10:53:09.853610 progress 25 % (2 MB)
134 10:53:09.931383 progress 30 % (3 MB)
135 10:53:10.002771 progress 35 % (3 MB)
136 10:53:10.080977 progress 40 % (4 MB)
137 10:53:10.165665 progress 45 % (5 MB)
138 10:53:10.243350 progress 50 % (5 MB)
139 10:53:10.325149 progress 55 % (6 MB)
140 10:53:10.404683 progress 60 % (6 MB)
141 10:53:10.483632 progress 65 % (7 MB)
142 10:53:10.561323 progress 70 % (7 MB)
143 10:53:10.643161 progress 75 % (8 MB)
144 10:53:10.719410 progress 80 % (8 MB)
145 10:53:10.797954 progress 85 % (9 MB)
146 10:53:10.869526 progress 90 % (9 MB)
147 10:53:10.969783 progress 95 % (10 MB)
148 10:53:11.066288 progress 100 % (11 MB)
149 10:53:11.080071 11 MB downloaded in 1.64 s (6.72 MB/s)
150 10:53:11.080987 end: 1.5.1 http-download (duration 00:00:02) [common]
152 10:53:11.082725 end: 1.5 download-retry (duration 00:00:02) [common]
153 10:53:11.083291 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 10:53:11.083852 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 10:53:27.671783 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/913099/extract-nfsrootfs-davzblro
156 10:53:27.672437 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 10:53:27.672776 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 10:53:27.673426 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm
159 10:53:27.673990 makedir: /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin
160 10:53:27.674455 makedir: /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/tests
161 10:53:27.674887 makedir: /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/results
162 10:53:27.675325 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-add-keys
163 10:53:27.675976 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-add-sources
164 10:53:27.676608 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-background-process-start
165 10:53:27.677119 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-background-process-stop
166 10:53:27.677648 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-common-functions
167 10:53:27.678145 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-echo-ipv4
168 10:53:27.678629 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-install-packages
169 10:53:27.679161 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-installed-packages
170 10:53:27.679684 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-os-build
171 10:53:27.680237 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-probe-channel
172 10:53:27.680747 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-probe-ip
173 10:53:27.681260 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-target-ip
174 10:53:27.681777 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-target-mac
175 10:53:27.682282 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-target-storage
176 10:53:27.682801 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-test-case
177 10:53:27.683324 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-test-event
178 10:53:27.683899 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-test-feedback
179 10:53:27.684505 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-test-raise
180 10:53:27.685021 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-test-reference
181 10:53:27.685537 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-test-runner
182 10:53:27.686072 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-test-set
183 10:53:27.686594 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-test-shell
184 10:53:27.687126 Updating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-add-keys (debian)
185 10:53:27.687719 Updating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-add-sources (debian)
186 10:53:27.688327 Updating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-install-packages (debian)
187 10:53:27.688900 Updating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-installed-packages (debian)
188 10:53:27.689449 Updating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/bin/lava-os-build (debian)
189 10:53:27.689923 Creating /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/environment
190 10:53:27.690363 LAVA metadata
191 10:53:27.690646 - LAVA_JOB_ID=913099
192 10:53:27.690866 - LAVA_DISPATCHER_IP=192.168.6.2
193 10:53:27.691274 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 10:53:27.692448 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 10:53:27.692821 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 10:53:27.693029 skipped lava-vland-overlay
197 10:53:27.693271 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 10:53:27.693528 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 10:53:27.693752 skipped lava-multinode-overlay
200 10:53:27.693994 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 10:53:27.694244 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 10:53:27.694504 Loading test definitions
203 10:53:27.694790 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 10:53:27.695015 Using /lava-913099 at stage 0
205 10:53:27.696287 uuid=913099_1.6.2.4.1 testdef=None
206 10:53:27.696645 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 10:53:27.696920 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 10:53:27.699832 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 10:53:27.700754 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 10:53:27.702997 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 10:53:27.703911 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 10:53:27.706090 runner path: /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/0/tests/0_timesync-off test_uuid 913099_1.6.2.4.1
215 10:53:27.706763 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 10:53:27.707627 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 10:53:27.707868 Using /lava-913099 at stage 0
219 10:53:27.708342 Fetching tests from https://github.com/kernelci/test-definitions.git
220 10:53:27.708705 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/0/tests/1_kselftest-alsa'
221 10:53:31.826430 Running '/usr/bin/git checkout kernelci.org
222 10:53:32.278149 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 10:53:32.279598 uuid=913099_1.6.2.4.5 testdef=None
224 10:53:32.279949 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
226 10:53:32.280742 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 10:53:32.283572 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 10:53:32.284420 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 10:53:32.288207 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 10:53:32.289070 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 10:53:32.292636 runner path: /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/0/tests/1_kselftest-alsa test_uuid 913099_1.6.2.4.5
234 10:53:32.292921 BOARD='meson-g12b-a311d-libretech-cc'
235 10:53:32.293134 BRANCH='next'
236 10:53:32.293336 SKIPFILE='/dev/null'
237 10:53:32.293537 SKIP_INSTALL='True'
238 10:53:32.293735 TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 10:53:32.293937 TST_CASENAME=''
240 10:53:32.294134 TST_CMDFILES='alsa'
241 10:53:32.294693 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 10:53:32.295484 Creating lava-test-runner.conf files
244 10:53:32.295693 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/913099/lava-overlay-wm3cclsm/lava-913099/0 for stage 0
245 10:53:32.296084 - 0_timesync-off
246 10:53:32.296338 - 1_kselftest-alsa
247 10:53:32.296683 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
248 10:53:32.296970 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 10:53:55.499678 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 10:53:55.500134 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 10:53:55.500435 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 10:53:55.500746 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 10:53:55.501035 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 10:53:56.121576 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 10:53:56.122028 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 10:53:56.122277 extracting modules file /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/modules/modules.tar to /var/lib/lava/dispatcher/tmp/913099/extract-nfsrootfs-davzblro
257 10:53:57.455810 extracting modules file /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/modules/modules.tar to /var/lib/lava/dispatcher/tmp/913099/extract-overlay-ramdisk-oyxpjaa6/ramdisk
258 10:53:58.829229 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 10:53:58.829688 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 10:53:58.829962 [common] Applying overlay to NFS
261 10:53:58.830176 [common] Applying overlay /var/lib/lava/dispatcher/tmp/913099/compress-overlay-f4_ra06h/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/913099/extract-nfsrootfs-davzblro
262 10:54:01.545869 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 10:54:01.546315 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 10:54:01.546587 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 10:54:01.546814 Converting downloaded kernel to a uImage
266 10:54:01.547119 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/kernel/Image /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/kernel/uImage
267 10:54:02.004216 output: Image Name:
268 10:54:02.004641 output: Created: Wed Oct 30 10:54:01 2024
269 10:54:02.004849 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 10:54:02.005052 output: Data Size: 45906432 Bytes = 44830.50 KiB = 43.78 MiB
271 10:54:02.005252 output: Load Address: 01080000
272 10:54:02.005452 output: Entry Point: 01080000
273 10:54:02.005647 output:
274 10:54:02.005979 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 10:54:02.006243 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 10:54:02.006506 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 10:54:02.006761 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 10:54:02.007015 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 10:54:02.007271 Building ramdisk /var/lib/lava/dispatcher/tmp/913099/extract-overlay-ramdisk-oyxpjaa6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/913099/extract-overlay-ramdisk-oyxpjaa6/ramdisk
280 10:54:04.188355 >> 167174 blocks
281 10:54:11.980832 Adding RAMdisk u-boot header.
282 10:54:11.981531 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/913099/extract-overlay-ramdisk-oyxpjaa6/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/913099/extract-overlay-ramdisk-oyxpjaa6/ramdisk.cpio.gz.uboot
283 10:54:12.219320 output: Image Name:
284 10:54:12.219751 output: Created: Wed Oct 30 10:54:11 2024
285 10:54:12.220085 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 10:54:12.220536 output: Data Size: 23445128 Bytes = 22895.63 KiB = 22.36 MiB
287 10:54:12.220960 output: Load Address: 00000000
288 10:54:12.221384 output: Entry Point: 00000000
289 10:54:12.221779 output:
290 10:54:12.222868 rename /var/lib/lava/dispatcher/tmp/913099/extract-overlay-ramdisk-oyxpjaa6/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/ramdisk/ramdisk.cpio.gz.uboot
291 10:54:12.223573 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 10:54:12.224144 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 10:54:12.224669 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 10:54:12.225117 No LXC device requested
295 10:54:12.225605 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 10:54:12.226103 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 10:54:12.226587 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 10:54:12.226990 Checking files for TFTP limit of 4294967296 bytes.
299 10:54:12.229648 end: 1 tftp-deploy (duration 00:01:19) [common]
300 10:54:12.230214 start: 2 uboot-action (timeout 00:05:00) [common]
301 10:54:12.230729 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 10:54:12.231218 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 10:54:12.231712 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 10:54:12.232262 Using kernel file from prepare-kernel: 913099/tftp-deploy-ij06ok07/kernel/uImage
305 10:54:12.232883 substitutions:
306 10:54:12.233287 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 10:54:12.233688 - {DTB_ADDR}: 0x01070000
308 10:54:12.234085 - {DTB}: 913099/tftp-deploy-ij06ok07/dtb/meson-g12b-a311d-libretech-cc.dtb
309 10:54:12.234482 - {INITRD}: 913099/tftp-deploy-ij06ok07/ramdisk/ramdisk.cpio.gz.uboot
310 10:54:12.234875 - {KERNEL_ADDR}: 0x01080000
311 10:54:12.235264 - {KERNEL}: 913099/tftp-deploy-ij06ok07/kernel/uImage
312 10:54:12.235654 - {LAVA_MAC}: None
313 10:54:12.236149 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/913099/extract-nfsrootfs-davzblro
314 10:54:12.236556 - {NFS_SERVER_IP}: 192.168.6.2
315 10:54:12.236942 - {PRESEED_CONFIG}: None
316 10:54:12.237328 - {PRESEED_LOCAL}: None
317 10:54:12.237714 - {RAMDISK_ADDR}: 0x08000000
318 10:54:12.238096 - {RAMDISK}: 913099/tftp-deploy-ij06ok07/ramdisk/ramdisk.cpio.gz.uboot
319 10:54:12.238482 - {ROOT_PART}: None
320 10:54:12.238865 - {ROOT}: None
321 10:54:12.239247 - {SERVER_IP}: 192.168.6.2
322 10:54:12.239626 - {TEE_ADDR}: 0x83000000
323 10:54:12.240054 - {TEE}: None
324 10:54:12.240445 Parsed boot commands:
325 10:54:12.240818 - setenv autoload no
326 10:54:12.241201 - setenv initrd_high 0xffffffff
327 10:54:12.241582 - setenv fdt_high 0xffffffff
328 10:54:12.241960 - dhcp
329 10:54:12.242336 - setenv serverip 192.168.6.2
330 10:54:12.242717 - tftpboot 0x01080000 913099/tftp-deploy-ij06ok07/kernel/uImage
331 10:54:12.243102 - tftpboot 0x08000000 913099/tftp-deploy-ij06ok07/ramdisk/ramdisk.cpio.gz.uboot
332 10:54:12.243486 - tftpboot 0x01070000 913099/tftp-deploy-ij06ok07/dtb/meson-g12b-a311d-libretech-cc.dtb
333 10:54:12.243871 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/913099/extract-nfsrootfs-davzblro,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 10:54:12.244301 - bootm 0x01080000 0x08000000 0x01070000
335 10:54:12.244790 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 10:54:12.246253 start: 2.3 connect-device (timeout 00:05:00) [common]
338 10:54:12.246665 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 10:54:12.261504 Setting prompt string to ['lava-test: # ']
340 10:54:12.263021 end: 2.3 connect-device (duration 00:00:00) [common]
341 10:54:12.263670 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 10:54:12.264325 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 10:54:12.264968 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 10:54:12.266170 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 10:54:12.302803 >> OK - accepted request
346 10:54:12.304909 Returned 0 in 0 seconds
347 10:54:12.406010 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 10:54:12.407597 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 10:54:12.408191 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 10:54:12.408699 Setting prompt string to ['Hit any key to stop autoboot']
352 10:54:12.409137 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 10:54:12.410660 Trying 192.168.56.21...
354 10:54:12.411127 Connected to conserv1.
355 10:54:12.411546 Escape character is '^]'.
356 10:54:12.411956
357 10:54:12.412403 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 10:54:12.412831
359 10:54:24.440866 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 10:54:24.441459 bl2_stage_init 0x01
361 10:54:24.441877 bl2_stage_init 0x81
362 10:54:24.446422 hw id: 0x0000 - pwm id 0x01
363 10:54:24.446913 bl2_stage_init 0xc1
364 10:54:24.447331 bl2_stage_init 0x02
365 10:54:24.447738
366 10:54:24.452042 L0:00000000
367 10:54:24.452537 L1:20000703
368 10:54:24.452949 L2:00008067
369 10:54:24.453353 L3:14000000
370 10:54:24.454928 B2:00402000
371 10:54:24.455381 B1:e0f83180
372 10:54:24.455798
373 10:54:24.456250 TE: 58167
374 10:54:24.456652
375 10:54:24.466023 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 10:54:24.466505
377 10:54:24.466911 Board ID = 1
378 10:54:24.467319 Set A53 clk to 24M
379 10:54:24.467716 Set A73 clk to 24M
380 10:54:24.471563 Set clk81 to 24M
381 10:54:24.472043 A53 clk: 1200 MHz
382 10:54:24.472464 A73 clk: 1200 MHz
383 10:54:24.475036 CLK81: 166.6M
384 10:54:24.475453 smccc: 00012abe
385 10:54:24.480561 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 10:54:24.486146 board id: 1
387 10:54:24.490464 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 10:54:24.502107 fw parse done
389 10:54:24.507100 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 10:54:24.549856 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 10:54:24.561816 PIEI prepare done
392 10:54:24.562268 fastboot data load
393 10:54:24.562663 fastboot data verify
394 10:54:24.567461 verify result: 266
395 10:54:24.572883 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 10:54:24.573354 LPDDR4 probe
397 10:54:24.573768 ddr clk to 1584MHz
398 10:54:24.579866 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 10:54:24.617231
400 10:54:24.617737 dmc_version 0001
401 10:54:24.623932 Check phy result
402 10:54:24.630615 INFO : End of CA training
403 10:54:24.631106 INFO : End of initialization
404 10:54:24.636251 INFO : Training has run successfully!
405 10:54:24.636725 Check phy result
406 10:54:24.641894 INFO : End of initialization
407 10:54:24.642351 INFO : End of read enable training
408 10:54:24.645134 INFO : End of fine write leveling
409 10:54:24.650778 INFO : End of Write leveling coarse delay
410 10:54:24.656249 INFO : Training has run successfully!
411 10:54:24.656691 Check phy result
412 10:54:24.657115 INFO : End of initialization
413 10:54:24.661880 INFO : End of read dq deskew training
414 10:54:24.665259 INFO : End of MPR read delay center optimization
415 10:54:24.670851 INFO : End of write delay center optimization
416 10:54:24.676384 INFO : End of read delay center optimization
417 10:54:24.677051 INFO : End of max read latency training
418 10:54:24.681997 INFO : Training has run successfully!
419 10:54:24.682472 1D training succeed
420 10:54:24.689262 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 10:54:24.737009 Check phy result
422 10:54:24.737531 INFO : End of initialization
423 10:54:24.758658 INFO : End of 2D read delay Voltage center optimization
424 10:54:24.778968 INFO : End of 2D read delay Voltage center optimization
425 10:54:24.831066 INFO : End of 2D write delay Voltage center optimization
426 10:54:24.881252 INFO : End of 2D write delay Voltage center optimization
427 10:54:24.886822 INFO : Training has run successfully!
428 10:54:24.887273
429 10:54:24.887685 channel==0
430 10:54:24.892437 RxClkDly_Margin_A0==88 ps 9
431 10:54:24.892982 TxDqDly_Margin_A0==98 ps 10
432 10:54:24.895694 RxClkDly_Margin_A1==88 ps 9
433 10:54:24.896253 TxDqDly_Margin_A1==98 ps 10
434 10:54:24.901237 TrainedVREFDQ_A0==74
435 10:54:24.901719 TrainedVREFDQ_A1==74
436 10:54:24.906780 VrefDac_Margin_A0==25
437 10:54:24.907254 DeviceVref_Margin_A0==40
438 10:54:24.907699 VrefDac_Margin_A1==25
439 10:54:24.912411 DeviceVref_Margin_A1==40
440 10:54:24.912886
441 10:54:24.913328
442 10:54:24.913768 channel==1
443 10:54:24.914202 RxClkDly_Margin_A0==98 ps 10
444 10:54:24.918147 TxDqDly_Margin_A0==98 ps 10
445 10:54:24.918623 RxClkDly_Margin_A1==98 ps 10
446 10:54:24.923658 TxDqDly_Margin_A1==88 ps 9
447 10:54:24.924163 TrainedVREFDQ_A0==77
448 10:54:24.924609 TrainedVREFDQ_A1==77
449 10:54:24.929249 VrefDac_Margin_A0==22
450 10:54:24.929721 DeviceVref_Margin_A0==37
451 10:54:24.934837 VrefDac_Margin_A1==22
452 10:54:24.935310 DeviceVref_Margin_A1==37
453 10:54:24.935749
454 10:54:24.940448 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 10:54:24.940925
456 10:54:24.968405 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 10:54:24.974052 2D training succeed
458 10:54:24.979717 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 10:54:24.980256 auto size-- 65535DDR cs0 size: 2048MB
460 10:54:24.985243 DDR cs1 size: 2048MB
461 10:54:24.985720 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 10:54:24.990867 cs0 DataBus test pass
463 10:54:24.991344 cs1 DataBus test pass
464 10:54:24.991784 cs0 AddrBus test pass
465 10:54:24.996418 cs1 AddrBus test pass
466 10:54:24.996892
467 10:54:24.997333 100bdlr_step_size ps== 420
468 10:54:24.997777 result report
469 10:54:25.002052 boot times 0Enable ddr reg access
470 10:54:25.008956 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 10:54:25.022366 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 10:54:25.597029 0.0;M3 CHK:0;cm4_sp_mode 0
473 10:54:25.597586 MVN_1=0x00000000
474 10:54:25.602384 MVN_2=0x00000000
475 10:54:25.608172 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 10:54:25.608675 OPS=0x10
477 10:54:25.609136 ring efuse init
478 10:54:25.609591 chipver efuse init
479 10:54:25.616457 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 10:54:25.616967 [0.018961 Inits done]
481 10:54:25.617422 secure task start!
482 10:54:25.623074 high task start!
483 10:54:25.623567 low task start!
484 10:54:25.624076 run into bl31
485 10:54:25.630685 NOTICE: BL31: v1.3(release):4fc40b1
486 10:54:25.637405 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 10:54:25.637905 NOTICE: BL31: G12A normal boot!
488 10:54:25.663694 NOTICE: BL31: BL33 decompress pass
489 10:54:25.668441 ERROR: Error initializing runtime service opteed_fast
490 10:54:26.902341
491 10:54:26.902949
492 10:54:26.909862 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 10:54:26.910360
494 10:54:26.910815 Model: Libre Computer AML-A311D-CC Alta
495 10:54:27.118333 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 10:54:27.141617 DRAM: 2 GiB (effective 3.8 GiB)
497 10:54:27.285535 Core: 408 devices, 31 uclasses, devicetree: separate
498 10:54:27.290415 WDT: Not starting watchdog@f0d0
499 10:54:27.323625 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 10:54:27.336107 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 10:54:27.340241 ** Bad device specification mmc 0 **
502 10:54:27.351389 Card did not respond to voltage select! : -110
503 10:54:27.358185 ** Bad device specification mmc 0 **
504 10:54:27.358673 Couldn't find partition mmc 0
505 10:54:27.367395 Card did not respond to voltage select! : -110
506 10:54:27.372926 ** Bad device specification mmc 0 **
507 10:54:27.373419 Couldn't find partition mmc 0
508 10:54:27.377047 Error: could not access storage.
509 10:54:28.641385 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 10:54:28.642048 bl2_stage_init 0x01
511 10:54:28.642539 bl2_stage_init 0x81
512 10:54:28.646876 hw id: 0x0000 - pwm id 0x01
513 10:54:28.647414 bl2_stage_init 0xc1
514 10:54:28.647884 bl2_stage_init 0x02
515 10:54:28.648570
516 10:54:28.652457 L0:00000000
517 10:54:28.652913 L1:20000703
518 10:54:28.653335 L2:00008067
519 10:54:28.653745 L3:14000000
520 10:54:28.655371 B2:00402000
521 10:54:28.655814 B1:e0f83180
522 10:54:28.656257
523 10:54:28.656671 TE: 58159
524 10:54:28.657081
525 10:54:28.666497 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 10:54:28.666956
527 10:54:28.667371 Board ID = 1
528 10:54:28.667776 Set A53 clk to 24M
529 10:54:28.668220 Set A73 clk to 24M
530 10:54:28.672174 Set clk81 to 24M
531 10:54:28.672614 A53 clk: 1200 MHz
532 10:54:28.673028 A73 clk: 1200 MHz
533 10:54:28.675484 CLK81: 166.6M
534 10:54:28.675924 smccc: 00012ab5
535 10:54:28.680948 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 10:54:28.686537 board id: 1
537 10:54:28.690892 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 10:54:28.702484 fw parse done
539 10:54:28.707464 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 10:54:28.750113 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 10:54:28.761995 PIEI prepare done
542 10:54:28.762452 fastboot data load
543 10:54:28.762871 fastboot data verify
544 10:54:28.767603 verify result: 266
545 10:54:28.773183 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 10:54:28.773655 LPDDR4 probe
547 10:54:28.774076 ddr clk to 1584MHz
548 10:54:28.780203 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 10:54:28.817531
550 10:54:28.817991 dmc_version 0001
551 10:54:28.824100 Check phy result
552 10:54:28.830925 INFO : End of CA training
553 10:54:28.831376 INFO : End of initialization
554 10:54:28.836626 INFO : Training has run successfully!
555 10:54:28.837081 Check phy result
556 10:54:28.842170 INFO : End of initialization
557 10:54:28.842627 INFO : End of read enable training
558 10:54:28.845437 INFO : End of fine write leveling
559 10:54:28.851000 INFO : End of Write leveling coarse delay
560 10:54:28.856558 INFO : Training has run successfully!
561 10:54:28.857032 Check phy result
562 10:54:28.857450 INFO : End of initialization
563 10:54:28.862175 INFO : End of read dq deskew training
564 10:54:28.865551 INFO : End of MPR read delay center optimization
565 10:54:28.871247 INFO : End of write delay center optimization
566 10:54:28.876793 INFO : End of read delay center optimization
567 10:54:28.877256 INFO : End of max read latency training
568 10:54:28.882388 INFO : Training has run successfully!
569 10:54:28.882840 1D training succeed
570 10:54:28.890194 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 10:54:28.937223 Check phy result
572 10:54:28.937724 INFO : End of initialization
573 10:54:28.959664 INFO : End of 2D read delay Voltage center optimization
574 10:54:28.979764 INFO : End of 2D read delay Voltage center optimization
575 10:54:29.031609 INFO : End of 2D write delay Voltage center optimization
576 10:54:29.081884 INFO : End of 2D write delay Voltage center optimization
577 10:54:29.087445 INFO : Training has run successfully!
578 10:54:29.087901
579 10:54:29.088375 channel==0
580 10:54:29.092972 RxClkDly_Margin_A0==88 ps 9
581 10:54:29.093425 TxDqDly_Margin_A0==108 ps 11
582 10:54:29.096441 RxClkDly_Margin_A1==78 ps 8
583 10:54:29.096891 TxDqDly_Margin_A1==98 ps 10
584 10:54:29.101982 TrainedVREFDQ_A0==74
585 10:54:29.102434 TrainedVREFDQ_A1==75
586 10:54:29.102856 VrefDac_Margin_A0==25
587 10:54:29.107611 DeviceVref_Margin_A0==40
588 10:54:29.108087 VrefDac_Margin_A1==25
589 10:54:29.113263 DeviceVref_Margin_A1==39
590 10:54:29.113715
591 10:54:29.114134
592 10:54:29.114547 channel==1
593 10:54:29.114953 RxClkDly_Margin_A0==98 ps 10
594 10:54:29.116592 TxDqDly_Margin_A0==98 ps 10
595 10:54:29.122140 RxClkDly_Margin_A1==88 ps 9
596 10:54:29.122593 TxDqDly_Margin_A1==88 ps 9
597 10:54:29.123014 TrainedVREFDQ_A0==77
598 10:54:29.127714 TrainedVREFDQ_A1==77
599 10:54:29.128193 VrefDac_Margin_A0==22
600 10:54:29.133374 DeviceVref_Margin_A0==37
601 10:54:29.133822 VrefDac_Margin_A1==24
602 10:54:29.134234 DeviceVref_Margin_A1==37
603 10:54:29.134641
604 10:54:29.139011 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 10:54:29.139471
606 10:54:29.172535 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 10:54:29.173040 2D training succeed
608 10:54:29.178147 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 10:54:29.183696 auto size-- 65535DDR cs0 size: 2048MB
610 10:54:29.184187 DDR cs1 size: 2048MB
611 10:54:29.189393 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 10:54:29.189858 cs0 DataBus test pass
613 10:54:29.190276 cs1 DataBus test pass
614 10:54:29.194909 cs0 AddrBus test pass
615 10:54:29.195374 cs1 AddrBus test pass
616 10:54:29.195793
617 10:54:29.200520 100bdlr_step_size ps== 420
618 10:54:29.200986 result report
619 10:54:29.201407 boot times 0Enable ddr reg access
620 10:54:29.209523 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 10:54:29.222954 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 10:54:29.795864 0.0;M3 CHK:0;cm4_sp_mode 0
623 10:54:29.796501 MVN_1=0x00000000
624 10:54:29.801427 MVN_2=0x00000000
625 10:54:29.807092 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 10:54:29.807625 OPS=0x10
627 10:54:29.808161 ring efuse init
628 10:54:29.808644 chipver efuse init
629 10:54:29.813008 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 10:54:29.818391 [0.018961 Inits done]
631 10:54:29.818830 secure task start!
632 10:54:29.819221 high task start!
633 10:54:29.822049 low task start!
634 10:54:29.822480 run into bl31
635 10:54:29.829618 NOTICE: BL31: v1.3(release):4fc40b1
636 10:54:29.836367 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 10:54:29.836809 NOTICE: BL31: G12A normal boot!
638 10:54:29.862684 NOTICE: BL31: BL33 decompress pass
639 10:54:29.867571 ERROR: Error initializing runtime service opteed_fast
640 10:54:31.101487
641 10:54:31.102099
642 10:54:31.109127 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 10:54:31.109588
644 10:54:31.110010 Model: Libre Computer AML-A311D-CC Alta
645 10:54:31.317318 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 10:54:31.340614 DRAM: 2 GiB (effective 3.8 GiB)
647 10:54:31.484601 Core: 408 devices, 31 uclasses, devicetree: separate
648 10:54:31.489495 WDT: Not starting watchdog@f0d0
649 10:54:31.522659 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 10:54:31.535226 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 10:54:31.539155 ** Bad device specification mmc 0 **
652 10:54:31.550544 Card did not respond to voltage select! : -110
653 10:54:31.557192 ** Bad device specification mmc 0 **
654 10:54:31.557629 Couldn't find partition mmc 0
655 10:54:31.566499 Card did not respond to voltage select! : -110
656 10:54:31.571949 ** Bad device specification mmc 0 **
657 10:54:31.572410 Couldn't find partition mmc 0
658 10:54:31.576076 Error: could not access storage.
659 10:54:31.918537 Net: eth0: ethernet@ff3f0000
660 10:54:31.918998 starting USB...
661 10:54:32.171282 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 10:54:32.171751 Starting the controller
663 10:54:32.177264 USB XHCI 1.10
664 10:54:33.891276 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 10:54:33.891788 bl2_stage_init 0x01
666 10:54:33.892277 bl2_stage_init 0x81
667 10:54:33.896853 hw id: 0x0000 - pwm id 0x01
668 10:54:33.897294 bl2_stage_init 0xc1
669 10:54:33.897702 bl2_stage_init 0x02
670 10:54:33.898106
671 10:54:33.902458 L0:00000000
672 10:54:33.902886 L1:20000703
673 10:54:33.903291 L2:00008067
674 10:54:33.903687 L3:14000000
675 10:54:33.908033 B2:00402000
676 10:54:33.908471 B1:e0f83180
677 10:54:33.908879
678 10:54:33.909284 TE: 58167
679 10:54:33.909689
680 10:54:33.913688 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 10:54:33.914167
682 10:54:33.914582 Board ID = 1
683 10:54:33.919243 Set A53 clk to 24M
684 10:54:33.919678 Set A73 clk to 24M
685 10:54:33.920115 Set clk81 to 24M
686 10:54:33.924839 A53 clk: 1200 MHz
687 10:54:33.925275 A73 clk: 1200 MHz
688 10:54:33.925679 CLK81: 166.6M
689 10:54:33.926079 smccc: 00012abd
690 10:54:33.930439 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 10:54:33.936035 board id: 1
692 10:54:33.941025 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 10:54:33.952571 fw parse done
694 10:54:33.957604 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 10:54:34.000207 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 10:54:34.012133 PIEI prepare done
697 10:54:34.012562 fastboot data load
698 10:54:34.012974 fastboot data verify
699 10:54:34.017735 verify result: 266
700 10:54:34.023357 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 10:54:34.023792 LPDDR4 probe
702 10:54:34.024236 ddr clk to 1584MHz
703 10:54:34.030337 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 10:54:34.067726
705 10:54:34.068217 dmc_version 0001
706 10:54:34.074317 Check phy result
707 10:54:34.081126 INFO : End of CA training
708 10:54:34.081597 INFO : End of initialization
709 10:54:34.086734 INFO : Training has run successfully!
710 10:54:34.087182 Check phy result
711 10:54:34.092377 INFO : End of initialization
712 10:54:34.092810 INFO : End of read enable training
713 10:54:34.098021 INFO : End of fine write leveling
714 10:54:34.103542 INFO : End of Write leveling coarse delay
715 10:54:34.104021 INFO : Training has run successfully!
716 10:54:34.104439 Check phy result
717 10:54:34.109216 INFO : End of initialization
718 10:54:34.109665 INFO : End of read dq deskew training
719 10:54:34.114737 INFO : End of MPR read delay center optimization
720 10:54:34.120355 INFO : End of write delay center optimization
721 10:54:34.125919 INFO : End of read delay center optimization
722 10:54:34.126391 INFO : End of max read latency training
723 10:54:34.131509 INFO : Training has run successfully!
724 10:54:34.131800 1D training succeed
725 10:54:34.139655 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 10:54:34.187435 Check phy result
727 10:54:34.187914 INFO : End of initialization
728 10:54:34.209069 INFO : End of 2D read delay Voltage center optimization
729 10:54:34.229364 INFO : End of 2D read delay Voltage center optimization
730 10:54:34.281410 INFO : End of 2D write delay Voltage center optimization
731 10:54:34.331685 INFO : End of 2D write delay Voltage center optimization
732 10:54:34.337232 INFO : Training has run successfully!
733 10:54:34.337713
734 10:54:34.338127 channel==0
735 10:54:34.342959 RxClkDly_Margin_A0==88 ps 9
736 10:54:34.343401 TxDqDly_Margin_A0==98 ps 10
737 10:54:34.346141 RxClkDly_Margin_A1==88 ps 9
738 10:54:34.346573 TxDqDly_Margin_A1==98 ps 10
739 10:54:34.351661 TrainedVREFDQ_A0==74
740 10:54:34.352121 TrainedVREFDQ_A1==74
741 10:54:34.357232 VrefDac_Margin_A0==25
742 10:54:34.357670 DeviceVref_Margin_A0==40
743 10:54:34.358071 VrefDac_Margin_A1==25
744 10:54:34.362884 DeviceVref_Margin_A1==40
745 10:54:34.363314
746 10:54:34.363720
747 10:54:34.364150 channel==1
748 10:54:34.364549 RxClkDly_Margin_A0==98 ps 10
749 10:54:34.366299 TxDqDly_Margin_A0==88 ps 9
750 10:54:34.371780 RxClkDly_Margin_A1==98 ps 10
751 10:54:34.372239 TxDqDly_Margin_A1==88 ps 9
752 10:54:34.372647 TrainedVREFDQ_A0==76
753 10:54:34.377389 TrainedVREFDQ_A1==77
754 10:54:34.377826 VrefDac_Margin_A0==22
755 10:54:34.382985 DeviceVref_Margin_A0==38
756 10:54:34.383410 VrefDac_Margin_A1==22
757 10:54:34.383817 DeviceVref_Margin_A1==37
758 10:54:34.384254
759 10:54:34.391892 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 10:54:34.392359
761 10:54:34.417620 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 10:54:34.423213 2D training succeed
763 10:54:34.426594 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 10:54:34.432218 auto size-- 65535DDR cs0 size: 2048MB
765 10:54:34.432645 DDR cs1 size: 2048MB
766 10:54:34.437780 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 10:54:34.438210 cs0 DataBus test pass
768 10:54:34.443334 cs1 DataBus test pass
769 10:54:34.443759 cs0 AddrBus test pass
770 10:54:34.444211 cs1 AddrBus test pass
771 10:54:34.444612
772 10:54:34.446695 100bdlr_step_size ps== 420
773 10:54:34.447131 result report
774 10:54:34.452257 boot times 0Enable ddr reg access
775 10:54:34.459308 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 10:54:34.472689 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 10:54:35.047334 0.0;M3 CHK:0;cm4_sp_mode 0
778 10:54:35.047843 MVN_1=0x00000000
779 10:54:35.052838 MVN_2=0x00000000
780 10:54:35.058597 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 10:54:35.059095 OPS=0x10
782 10:54:35.059493 ring efuse init
783 10:54:35.059879 chipver efuse init
784 10:54:35.066792 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 10:54:35.067232 [0.018961 Inits done]
786 10:54:35.073422 secure task start!
787 10:54:35.073846 high task start!
788 10:54:35.074235 low task start!
789 10:54:35.074621 run into bl31
790 10:54:35.081153 NOTICE: BL31: v1.3(release):4fc40b1
791 10:54:35.087832 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 10:54:35.088287 NOTICE: BL31: G12A normal boot!
793 10:54:35.114295 NOTICE: BL31: BL33 decompress pass
794 10:54:35.118903 ERROR: Error initializing runtime service opteed_fast
795 10:54:36.352803
796 10:54:36.353388
797 10:54:36.360255 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 10:54:36.360697
799 10:54:36.361107 Model: Libre Computer AML-A311D-CC Alta
800 10:54:36.568835 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 10:54:36.592133 DRAM: 2 GiB (effective 3.8 GiB)
802 10:54:36.736128 Core: 408 devices, 31 uclasses, devicetree: separate
803 10:54:36.741001 WDT: Not starting watchdog@f0d0
804 10:54:36.774170 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 10:54:36.786585 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 10:54:36.790689 ** Bad device specification mmc 0 **
807 10:54:36.801898 Card did not respond to voltage select! : -110
808 10:54:36.808556 ** Bad device specification mmc 0 **
809 10:54:36.808876 Couldn't find partition mmc 0
810 10:54:36.817877 Card did not respond to voltage select! : -110
811 10:54:36.823490 ** Bad device specification mmc 0 **
812 10:54:36.823962 Couldn't find partition mmc 0
813 10:54:36.827464 Error: could not access storage.
814 10:54:37.170051 Net: eth0: ethernet@ff3f0000
815 10:54:37.170742 starting USB...
816 10:54:37.422873 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 10:54:37.423542 Starting the controller
818 10:54:37.428815 USB XHCI 1.10
819 10:54:39.591729 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 10:54:39.592440 bl2_stage_init 0x01
821 10:54:39.592911 bl2_stage_init 0x81
822 10:54:39.597174 hw id: 0x0000 - pwm id 0x01
823 10:54:39.597711 bl2_stage_init 0xc1
824 10:54:39.598174 bl2_stage_init 0x02
825 10:54:39.598627
826 10:54:39.602889 L0:00000000
827 10:54:39.603420 L1:20000703
828 10:54:39.603876 L2:00008067
829 10:54:39.604373 L3:14000000
830 10:54:39.608402 B2:00402000
831 10:54:39.608925 B1:e0f83180
832 10:54:39.609381
833 10:54:39.609832 TE: 58124
834 10:54:39.610287
835 10:54:39.613963 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 10:54:39.614494
837 10:54:39.614953 Board ID = 1
838 10:54:39.619625 Set A53 clk to 24M
839 10:54:39.620179 Set A73 clk to 24M
840 10:54:39.620640 Set clk81 to 24M
841 10:54:39.625224 A53 clk: 1200 MHz
842 10:54:39.625765 A73 clk: 1200 MHz
843 10:54:39.626227 CLK81: 166.6M
844 10:54:39.626681 smccc: 00012a92
845 10:54:39.630899 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 10:54:39.636368 board id: 1
847 10:54:39.641280 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 10:54:39.652934 fw parse done
849 10:54:39.658022 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 10:54:39.700468 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 10:54:39.712395 PIEI prepare done
852 10:54:39.712951 fastboot data load
853 10:54:39.713411 fastboot data verify
854 10:54:39.718134 verify result: 266
855 10:54:39.723796 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 10:54:39.724398 LPDDR4 probe
857 10:54:39.724863 ddr clk to 1584MHz
858 10:54:39.730674 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 10:54:39.767954
860 10:54:39.768543 dmc_version 0001
861 10:54:39.774588 Check phy result
862 10:54:39.781440 INFO : End of CA training
863 10:54:39.781967 INFO : End of initialization
864 10:54:39.787098 INFO : Training has run successfully!
865 10:54:39.787647 Check phy result
866 10:54:39.792662 INFO : End of initialization
867 10:54:39.793188 INFO : End of read enable training
868 10:54:39.798272 INFO : End of fine write leveling
869 10:54:39.804027 INFO : End of Write leveling coarse delay
870 10:54:39.804559 INFO : Training has run successfully!
871 10:54:39.805024 Check phy result
872 10:54:39.809462 INFO : End of initialization
873 10:54:39.809994 INFO : End of read dq deskew training
874 10:54:39.815107 INFO : End of MPR read delay center optimization
875 10:54:39.820644 INFO : End of write delay center optimization
876 10:54:39.826258 INFO : End of read delay center optimization
877 10:54:39.826787 INFO : End of max read latency training
878 10:54:39.831850 INFO : Training has run successfully!
879 10:54:39.832426 1D training succeed
880 10:54:39.840039 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 10:54:39.887720 Check phy result
882 10:54:39.888347 INFO : End of initialization
883 10:54:39.909305 INFO : End of 2D read delay Voltage center optimization
884 10:54:39.929407 INFO : End of 2D read delay Voltage center optimization
885 10:54:39.981316 INFO : End of 2D write delay Voltage center optimization
886 10:54:40.031546 INFO : End of 2D write delay Voltage center optimization
887 10:54:40.037112 INFO : Training has run successfully!
888 10:54:40.037628
889 10:54:40.038086 channel==0
890 10:54:40.042662 RxClkDly_Margin_A0==78 ps 8
891 10:54:40.043183 TxDqDly_Margin_A0==98 ps 10
892 10:54:40.046033 RxClkDly_Margin_A1==88 ps 9
893 10:54:40.046543 TxDqDly_Margin_A1==98 ps 10
894 10:54:40.051556 TrainedVREFDQ_A0==74
895 10:54:40.052102 TrainedVREFDQ_A1==74
896 10:54:40.052577 VrefDac_Margin_A0==25
897 10:54:40.057191 DeviceVref_Margin_A0==40
898 10:54:40.057726 VrefDac_Margin_A1==25
899 10:54:40.062818 DeviceVref_Margin_A1==40
900 10:54:40.063381
901 10:54:40.063821
902 10:54:40.064302 channel==1
903 10:54:40.064731 RxClkDly_Margin_A0==98 ps 10
904 10:54:40.068441 TxDqDly_Margin_A0==98 ps 10
905 10:54:40.068963 RxClkDly_Margin_A1==98 ps 10
906 10:54:40.074058 TxDqDly_Margin_A1==88 ps 9
907 10:54:40.074574 TrainedVREFDQ_A0==77
908 10:54:40.075012 TrainedVREFDQ_A1==77
909 10:54:40.079562 VrefDac_Margin_A0==22
910 10:54:40.080099 DeviceVref_Margin_A0==37
911 10:54:40.085225 VrefDac_Margin_A1==24
912 10:54:40.085746 DeviceVref_Margin_A1==37
913 10:54:40.086179
914 10:54:40.090782 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 10:54:40.091287
916 10:54:40.118740 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
917 10:54:40.124394 2D training succeed
918 10:54:40.130017 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 10:54:40.130516 auto size-- 65535DDR cs0 size: 2048MB
920 10:54:40.135568 DDR cs1 size: 2048MB
921 10:54:40.136122 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 10:54:40.141162 cs0 DataBus test pass
923 10:54:40.141658 cs1 DataBus test pass
924 10:54:40.142091 cs0 AddrBus test pass
925 10:54:40.146782 cs1 AddrBus test pass
926 10:54:40.147274
927 10:54:40.147710 100bdlr_step_size ps== 420
928 10:54:40.148192 result report
929 10:54:40.152387 boot times 0Enable ddr reg access
930 10:54:40.159115 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 10:54:40.172553 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 10:54:40.745509 0.0;M3 CHK:0;cm4_sp_mode 0
933 10:54:40.746161 MVN_1=0x00000000
934 10:54:40.751020 MVN_2=0x00000000
935 10:54:40.756792 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 10:54:40.757307 OPS=0x10
937 10:54:40.757778 ring efuse init
938 10:54:40.758232 chipver efuse init
939 10:54:40.762362 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 10:54:40.768038 [0.018961 Inits done]
941 10:54:40.768552 secure task start!
942 10:54:40.769007 high task start!
943 10:54:40.771578 low task start!
944 10:54:40.772110 run into bl31
945 10:54:40.779132 NOTICE: BL31: v1.3(release):4fc40b1
946 10:54:40.785956 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 10:54:40.786470 NOTICE: BL31: G12A normal boot!
948 10:54:40.812308 NOTICE: BL31: BL33 decompress pass
949 10:54:40.817185 ERROR: Error initializing runtime service opteed_fast
950 10:54:42.050854
951 10:54:42.051502
952 10:54:42.058382 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 10:54:42.058920
954 10:54:42.059383 Model: Libre Computer AML-A311D-CC Alta
955 10:54:42.266695 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 10:54:42.290092 DRAM: 2 GiB (effective 3.8 GiB)
957 10:54:42.434134 Core: 408 devices, 31 uclasses, devicetree: separate
958 10:54:42.439011 WDT: Not starting watchdog@f0d0
959 10:54:42.472304 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 10:54:42.484634 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 10:54:42.488730 ** Bad device specification mmc 0 **
962 10:54:42.500149 Card did not respond to voltage select! : -110
963 10:54:42.506736 ** Bad device specification mmc 0 **
964 10:54:42.507312 Couldn't find partition mmc 0
965 10:54:42.516085 Card did not respond to voltage select! : -110
966 10:54:42.521545 ** Bad device specification mmc 0 **
967 10:54:42.522118 Couldn't find partition mmc 0
968 10:54:42.525597 Error: could not access storage.
969 10:54:42.869102 Net: eth0: ethernet@ff3f0000
970 10:54:42.869739 starting USB...
971 10:54:43.121865 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 10:54:43.122466 Starting the controller
973 10:54:43.127904 USB XHCI 1.10
974 10:54:44.991173 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 10:54:44.991835 bl2_stage_init 0x01
976 10:54:44.992373 bl2_stage_init 0x81
977 10:54:44.996838 hw id: 0x0000 - pwm id 0x01
978 10:54:44.997413 bl2_stage_init 0xc1
979 10:54:44.997881 bl2_stage_init 0x02
980 10:54:44.998334
981 10:54:45.002407 L0:00000000
982 10:54:45.002943 L1:20000703
983 10:54:45.003403 L2:00008067
984 10:54:45.003849 L3:14000000
985 10:54:45.007976 B2:00402000
986 10:54:45.008560 B1:e0f83180
987 10:54:45.009030
988 10:54:45.009482 TE: 58159
989 10:54:45.009936
990 10:54:45.013669 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 10:54:45.014211
992 10:54:45.014670 Board ID = 1
993 10:54:45.019190 Set A53 clk to 24M
994 10:54:45.019739 Set A73 clk to 24M
995 10:54:45.020239 Set clk81 to 24M
996 10:54:45.024811 A53 clk: 1200 MHz
997 10:54:45.025344 A73 clk: 1200 MHz
998 10:54:45.025803 CLK81: 166.6M
999 10:54:45.026248 smccc: 00012ab5
1000 10:54:45.030407 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 10:54:45.035947 board id: 1
1002 10:54:45.040869 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 10:54:45.052603 fw parse done
1004 10:54:45.057571 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 10:54:45.100199 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 10:54:45.112090 PIEI prepare done
1007 10:54:45.112569 fastboot data load
1008 10:54:45.112973 fastboot data verify
1009 10:54:45.117603 verify result: 266
1010 10:54:45.123183 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 10:54:45.123647 LPDDR4 probe
1012 10:54:45.124075 ddr clk to 1584MHz
1013 10:54:45.130233 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 10:54:45.167552
1015 10:54:45.168148 dmc_version 0001
1016 10:54:45.174097 Check phy result
1017 10:54:45.180965 INFO : End of CA training
1018 10:54:45.181456 INFO : End of initialization
1019 10:54:45.186599 INFO : Training has run successfully!
1020 10:54:45.187083 Check phy result
1021 10:54:45.192191 INFO : End of initialization
1022 10:54:45.192658 INFO : End of read enable training
1023 10:54:45.195526 INFO : End of fine write leveling
1024 10:54:45.201138 INFO : End of Write leveling coarse delay
1025 10:54:45.206618 INFO : Training has run successfully!
1026 10:54:45.207103 Check phy result
1027 10:54:45.207530 INFO : End of initialization
1028 10:54:45.212413 INFO : End of read dq deskew training
1029 10:54:45.215666 INFO : End of MPR read delay center optimization
1030 10:54:45.221232 INFO : End of write delay center optimization
1031 10:54:45.226808 INFO : End of read delay center optimization
1032 10:54:45.227344 INFO : End of max read latency training
1033 10:54:45.232441 INFO : Training has run successfully!
1034 10:54:45.233204 1D training succeed
1035 10:54:45.239622 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 10:54:45.287226 Check phy result
1037 10:54:45.287791 INFO : End of initialization
1038 10:54:45.308973 INFO : End of 2D read delay Voltage center optimization
1039 10:54:45.329272 INFO : End of 2D read delay Voltage center optimization
1040 10:54:45.381177 INFO : End of 2D write delay Voltage center optimization
1041 10:54:45.431575 INFO : End of 2D write delay Voltage center optimization
1042 10:54:45.437053 INFO : Training has run successfully!
1043 10:54:45.437562
1044 10:54:45.437992 channel==0
1045 10:54:45.442679 RxClkDly_Margin_A0==88 ps 9
1046 10:54:45.443156 TxDqDly_Margin_A0==98 ps 10
1047 10:54:45.445951 RxClkDly_Margin_A1==88 ps 9
1048 10:54:45.446440 TxDqDly_Margin_A1==98 ps 10
1049 10:54:45.451478 TrainedVREFDQ_A0==74
1050 10:54:45.451964 TrainedVREFDQ_A1==74
1051 10:54:45.457106 VrefDac_Margin_A0==25
1052 10:54:45.457592 DeviceVref_Margin_A0==40
1053 10:54:45.458015 VrefDac_Margin_A1==25
1054 10:54:45.462709 DeviceVref_Margin_A1==40
1055 10:54:45.463194
1056 10:54:45.463612
1057 10:54:45.464054 channel==1
1058 10:54:45.464468 RxClkDly_Margin_A0==98 ps 10
1059 10:54:45.466054 TxDqDly_Margin_A0==88 ps 9
1060 10:54:45.471642 RxClkDly_Margin_A1==98 ps 10
1061 10:54:45.472170 TxDqDly_Margin_A1==88 ps 9
1062 10:54:45.472608 TrainedVREFDQ_A0==77
1063 10:54:45.477335 TrainedVREFDQ_A1==77
1064 10:54:45.477785 VrefDac_Margin_A0==22
1065 10:54:45.482957 DeviceVref_Margin_A0==37
1066 10:54:45.483412 VrefDac_Margin_A1==24
1067 10:54:45.483825 DeviceVref_Margin_A1==37
1068 10:54:45.484265
1069 10:54:45.488616 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 10:54:45.489062
1071 10:54:45.522119 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 10:54:45.522609 2D training succeed
1073 10:54:45.527731 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 10:54:45.533393 auto size-- 65535DDR cs0 size: 2048MB
1075 10:54:45.533844 DDR cs1 size: 2048MB
1076 10:54:45.538990 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 10:54:45.539438 cs0 DataBus test pass
1078 10:54:45.539847 cs1 DataBus test pass
1079 10:54:45.544586 cs0 AddrBus test pass
1080 10:54:45.545030 cs1 AddrBus test pass
1081 10:54:45.545442
1082 10:54:45.550139 100bdlr_step_size ps== 420
1083 10:54:45.550645 result report
1084 10:54:45.551061 boot times 0Enable ddr reg access
1085 10:54:45.559041 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 10:54:45.572586 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 10:54:46.147368 0.0;M3 CHK:0;cm4_sp_mode 0
1088 10:54:46.148027 MVN_1=0x00000000
1089 10:54:46.152800 MVN_2=0x00000000
1090 10:54:46.158586 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 10:54:46.159140 OPS=0x10
1092 10:54:46.159547 ring efuse init
1093 10:54:46.159939 chipver efuse init
1094 10:54:46.164126 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 10:54:46.169812 [0.018961 Inits done]
1096 10:54:46.170408 secure task start!
1097 10:54:46.170809 high task start!
1098 10:54:46.173349 low task start!
1099 10:54:46.173907 run into bl31
1100 10:54:46.180932 NOTICE: BL31: v1.3(release):4fc40b1
1101 10:54:46.187926 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 10:54:46.188517 NOTICE: BL31: G12A normal boot!
1103 10:54:46.214163 NOTICE: BL31: BL33 decompress pass
1104 10:54:46.218960 ERROR: Error initializing runtime service opteed_fast
1105 10:54:47.452705
1106 10:54:47.453348
1107 10:54:47.460127 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 10:54:47.460653
1109 10:54:47.461124 Model: Libre Computer AML-A311D-CC Alta
1110 10:54:47.668523 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 10:54:47.691944 DRAM: 2 GiB (effective 3.8 GiB)
1112 10:54:47.835908 Core: 408 devices, 31 uclasses, devicetree: separate
1113 10:54:47.840823 WDT: Not starting watchdog@f0d0
1114 10:54:47.873978 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 10:54:47.886445 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 10:54:47.890366 ** Bad device specification mmc 0 **
1117 10:54:47.901875 Card did not respond to voltage select! : -110
1118 10:54:47.908482 ** Bad device specification mmc 0 **
1119 10:54:47.909008 Couldn't find partition mmc 0
1120 10:54:47.917842 Card did not respond to voltage select! : -110
1121 10:54:47.923315 ** Bad device specification mmc 0 **
1122 10:54:47.923859 Couldn't find partition mmc 0
1123 10:54:47.927393 Error: could not access storage.
1124 10:54:48.269927 Net: eth0: ethernet@ff3f0000
1125 10:54:48.270559 starting USB...
1126 10:54:48.522641 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 10:54:48.523246 Starting the controller
1128 10:54:48.528651 USB XHCI 1.10
1129 10:54:50.083619 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 10:54:50.091015 scanning usb for storage devices... 0 Storage Device(s) found
1132 10:54:50.142908 Hit any key to stop autoboot: 1
1133 10:54:50.143952 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1134 10:54:50.144829 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1135 10:54:50.145353 Setting prompt string to ['=>']
1136 10:54:50.145892 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1137 10:54:50.158459 0
1138 10:54:50.159474 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 10:54:50.160029 Sending with 10 millisecond of delay
1141 10:54:51.295391 => setenv autoload no
1142 10:54:51.306262 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 10:54:51.311672 setenv autoload no
1144 10:54:51.312491 Sending with 10 millisecond of delay
1146 10:54:53.110062 => setenv initrd_high 0xffffffff
1147 10:54:53.120888 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1148 10:54:53.121825 setenv initrd_high 0xffffffff
1149 10:54:53.122592 Sending with 10 millisecond of delay
1151 10:54:54.739564 => setenv fdt_high 0xffffffff
1152 10:54:54.750445 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1153 10:54:54.751365 setenv fdt_high 0xffffffff
1154 10:54:54.752149 Sending with 10 millisecond of delay
1156 10:54:55.044182 => dhcp
1157 10:54:55.055003 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1158 10:54:55.055949 dhcp
1159 10:54:55.056492 Speed: 1000, full duplex
1160 10:54:55.056956 BOOTP broadcast 1
1161 10:54:55.065022 DHCP client bound to address 192.168.6.27 (11 ms)
1162 10:54:55.065864 Sending with 10 millisecond of delay
1164 10:54:56.742724 => setenv serverip 192.168.6.2
1165 10:54:56.753555 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1166 10:54:56.754524 setenv serverip 192.168.6.2
1167 10:54:56.755266 Sending with 10 millisecond of delay
1169 10:55:00.479799 => tftpboot 0x01080000 913099/tftp-deploy-ij06ok07/kernel/uImage
1170 10:55:00.490702 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 10:55:00.491670 tftpboot 0x01080000 913099/tftp-deploy-ij06ok07/kernel/uImage
1172 10:55:00.492218 Speed: 1000, full duplex
1173 10:55:00.492689 Using ethernet@ff3f0000 device
1174 10:55:00.493556 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 10:55:00.498912 Filename '913099/tftp-deploy-ij06ok07/kernel/uImage'.
1176 10:55:00.501982 Load address: 0x1080000
1177 10:55:03.343700 Loading: *################################################## 43.8 MiB
1178 10:55:03.344434 15.4 MiB/s
1179 10:55:03.344924 done
1180 10:55:03.348188 Bytes transferred = 45906496 (2bc7a40 hex)
1181 10:55:03.348993 Sending with 10 millisecond of delay
1183 10:55:08.034588 => tftpboot 0x08000000 913099/tftp-deploy-ij06ok07/ramdisk/ramdisk.cpio.gz.uboot
1184 10:55:08.045148 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 10:55:08.045651 tftpboot 0x08000000 913099/tftp-deploy-ij06ok07/ramdisk/ramdisk.cpio.gz.uboot
1186 10:55:08.045900 Speed: 1000, full duplex
1187 10:55:08.046121 Using ethernet@ff3f0000 device
1188 10:55:08.048060 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 10:55:08.056525 Filename '913099/tftp-deploy-ij06ok07/ramdisk/ramdisk.cpio.gz.uboot'.
1190 10:55:08.056830 Load address: 0x8000000
1191 10:55:14.867619 Loading: *#######################T ########################### 22.4 MiB
1192 10:55:14.868499 3.3 MiB/s
1193 10:55:14.869062 done
1194 10:55:14.871928 Bytes transferred = 23445192 (165bec8 hex)
1195 10:55:14.872855 Sending with 10 millisecond of delay
1197 10:55:20.045600 => tftpboot 0x01070000 913099/tftp-deploy-ij06ok07/dtb/meson-g12b-a311d-libretech-cc.dtb
1198 10:55:20.056448 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:52)
1199 10:55:20.057331 tftpboot 0x01070000 913099/tftp-deploy-ij06ok07/dtb/meson-g12b-a311d-libretech-cc.dtb
1200 10:55:20.057847 Speed: 1000, full duplex
1201 10:55:20.058314 Using ethernet@ff3f0000 device
1202 10:55:20.061840 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1203 10:55:20.069058 Filename '913099/tftp-deploy-ij06ok07/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1204 10:55:20.079971 Load address: 0x1070000
1205 10:55:20.091776 Loading: *################################################## 53.4 KiB
1206 10:55:20.092328 3.1 MiB/s
1207 10:55:20.092797 done
1208 10:55:20.096102 Bytes transferred = 54703 (d5af hex)
1209 10:55:20.096885 Sending with 10 millisecond of delay
1211 10:55:33.392174 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/913099/extract-nfsrootfs-davzblro,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1212 10:55:33.403089 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:39)
1213 10:55:33.403713 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/913099/extract-nfsrootfs-davzblro,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1214 10:55:33.404253 Sending with 10 millisecond of delay
1216 10:55:35.743809 => bootm 0x01080000 0x08000000 0x01070000
1217 10:55:35.754730 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1218 10:55:35.755373 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:36)
1219 10:55:35.756508 bootm 0x01080000 0x08000000 0x01070000
1220 10:55:35.757006 ## Booting kernel from Legacy Image at 01080000 ...
1221 10:55:35.759913 Image Name:
1222 10:55:35.765300 Image Type: AArch64 Linux Kernel Image (uncompressed)
1223 10:55:35.765826 Data Size: 45906432 Bytes = 43.8 MiB
1224 10:55:35.770842 Load Address: 01080000
1225 10:55:35.771353 Entry Point: 01080000
1226 10:55:35.966769 Verifying Checksum ... OK
1227 10:55:35.967364 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1228 10:55:35.972330 Image Name:
1229 10:55:35.977780 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1230 10:55:35.978298 Data Size: 23445128 Bytes = 22.4 MiB
1231 10:55:35.983331 Load Address: 00000000
1232 10:55:35.983848 Entry Point: 00000000
1233 10:55:36.085714 Verifying Checksum ... OK
1234 10:55:36.086349 ## Flattened Device Tree blob at 01070000
1235 10:55:36.091147 Booting using the fdt blob at 0x1070000
1236 10:55:36.091667 Working FDT set to 1070000
1237 10:55:36.095560 Loading Kernel Image
1238 10:55:36.140234 Loading Ramdisk to 7e9a4000, end 7ffffe88 ... OK
1239 10:55:36.148695 Loading Device Tree to 000000007e993000, end 000000007e9a35ae ... OK
1240 10:55:36.149224 Working FDT set to 7e993000
1241 10:55:36.149681
1242 10:55:36.150640 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1243 10:55:36.151277 start: 2.4.4 auto-login-action (timeout 00:03:36) [common]
1244 10:55:36.151808 Setting prompt string to ['Linux version [0-9]']
1245 10:55:36.152386 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1246 10:55:36.152911 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1247 10:55:36.154016 Starting kernel ...
1248 10:55:36.154512
1249 10:55:36.188884 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1250 10:55:36.189939 start: 2.4.4.1 login-action (timeout 00:03:36) [common]
1251 10:55:36.190509 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1252 10:55:36.191022 Setting prompt string to []
1253 10:55:36.191557 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1254 10:55:36.192115 Using line separator: #'\n'#
1255 10:55:36.192579 No login prompt set.
1256 10:55:36.193054 Parsing kernel messages
1257 10:55:36.193502 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1258 10:55:36.194406 [login-action] Waiting for messages, (timeout 00:03:36)
1259 10:55:36.194943 Waiting using forced prompt support (timeout 00:01:48)
1260 10:55:36.209062 [ 0.000000] Linux version 6.12.0-rc5-next-20241030 (KernelCI@build-j357129-arm64-gcc-12-defconfig-z772r) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Wed Oct 30 10:38:14 UTC 2024
1261 10:55:36.214706 [ 0.000000] KASLR disabled due to lack of seed
1262 10:55:36.220086 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1263 10:55:36.220611 [ 0.000000] efi: UEFI not found.
1264 10:55:36.231116 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1265 10:55:36.236652 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1266 10:55:36.242243 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1267 10:55:36.253206 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1268 10:55:36.258803 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1269 10:55:36.264304 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1270 10:55:36.275297 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1271 10:55:36.286223 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1272 10:55:36.291789 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1273 10:55:36.297325 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a00-0xe466903f]
1274 10:55:36.302822 [ 0.000000] Zone ranges:
1275 10:55:36.308336 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1276 10:55:36.313832 [ 0.000000] DMA32 empty
1277 10:55:36.314356 [ 0.000000] Normal empty
1278 10:55:36.319462 [ 0.000000] Movable zone start for each node
1279 10:55:36.319971 [ 0.000000] Early memory node ranges
1280 10:55:36.330411 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1281 10:55:36.335969 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1282 10:55:36.341458 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1283 10:55:36.347752 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1284 10:55:36.372000 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1285 10:55:36.377593 [ 0.000000] psci: probing for conduit method from DT.
1286 10:55:36.378105 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1287 10:55:36.386555 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1288 10:55:36.387078 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1289 10:55:36.392135 [ 0.000000] psci: SMC Calling Convention v1.1
1290 10:55:36.403084 [ 0.000000] RME: RMM doesn't support RSI version 1.0. Supported range: 1.0-0.0
1291 10:55:36.408671 [ 0.000000] percpu: Embedded 25 pages/cpu s61784 r8192 d32424 u102400
1292 10:55:36.409186 [ 0.000000] Detected VIPT I-cache on CPU0
1293 10:55:36.414181 [ 0.000000] CPU features: detected: ARM erratum 845719
1294 10:55:36.419708 [ 0.000000] alternatives: applying boot alternatives
1295 10:55:36.441744 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/913099/extract-nfsrootfs-davzblro,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1296 10:55:36.447334 <6>[ 0.000000] printk: log buffer data + meta data: 131072 + 458752 = 589824 bytes
1297 10:55:36.458367 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1298 10:55:36.463874 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1299 10:55:36.469389 <6>[ 0.000000] Fallback order for Node 0: 0
1300 10:55:36.474919 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1301 10:55:36.480458 <6>[ 0.000000] Policy zone: DMA
1302 10:55:36.485923 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1303 10:55:36.491487 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1304 10:55:36.497010 <6>[ 0.000000] software IO TLB: area num 8.
1305 10:55:36.506043 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1306 10:55:36.552724 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1307 10:55:36.558289 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1308 10:55:36.563799 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1309 10:55:36.569362 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1310 10:55:36.574868 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1311 10:55:36.580390 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1312 10:55:36.585896 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1313 10:55:36.591422 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1314 10:55:36.602456 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1315 10:55:36.613491 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1316 10:55:36.619019 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1317 10:55:36.624612 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1318 10:55:36.625122 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1319 10:55:36.634352 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1320 10:55:36.647190 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1321 10:55:36.658241 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1322 10:55:36.663810 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1323 10:55:36.669319 <6>[ 0.008798] Console: colour dummy device 80x25
1324 10:55:36.680339 <6>[ 0.012941] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1325 10:55:36.685886 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1326 10:55:36.691406 <6>[ 0.028191] LSM: initializing lsm=capability
1327 10:55:36.696925 <6>[ 0.032733] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1328 10:55:36.702422 <6>[ 0.040213] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1329 10:55:36.707959 <6>[ 0.052302] rcu: Hierarchical SRCU implementation.
1330 10:55:36.713511 <6>[ 0.053216] rcu: Max phase no-delay instances is 1000.
1331 10:55:36.724462 <6>[ 0.058887] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1332 10:55:36.732969 <6>[ 0.071588] EFI services will not be available.
1333 10:55:36.733507 <6>[ 0.075240] smp: Bringing up secondary CPUs ...
1334 10:55:36.753249 <6>[ 0.077142] Detected VIPT I-cache on CPU1
1335 10:55:36.758730 <6>[ 0.077260] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1336 10:55:36.764294 <6>[ 0.078608] CPU features: detected: Spectre-v2
1337 10:55:36.769774 <6>[ 0.078623] CPU features: detected: Spectre-v4
1338 10:55:36.775265 <6>[ 0.078628] CPU features: detected: Spectre-BHB
1339 10:55:36.780844 <6>[ 0.078634] CPU features: detected: ARM erratum 858921
1340 10:55:36.786348 <6>[ 0.078641] Detected VIPT I-cache on CPU2
1341 10:55:36.791776 <6>[ 0.078713] arch_timer: Enabling local workaround for ARM erratum 858921
1342 10:55:36.797311 <6>[ 0.078731] arch_timer: CPU2: Trapping CNTVCT access
1343 10:55:36.802831 <6>[ 0.078741] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1344 10:55:36.808346 <6>[ 0.083672] Detected VIPT I-cache on CPU3
1345 10:55:36.813851 <6>[ 0.083718] arch_timer: Enabling local workaround for ARM erratum 858921
1346 10:55:36.819440 <6>[ 0.083728] arch_timer: CPU3: Trapping CNTVCT access
1347 10:55:36.824892 <6>[ 0.083735] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1348 10:55:36.830443 <6>[ 0.095563] Detected VIPT I-cache on CPU4
1349 10:55:36.835929 <6>[ 0.095610] arch_timer: Enabling local workaround for ARM erratum 858921
1350 10:55:36.841445 <6>[ 0.095619] arch_timer: CPU4: Trapping CNTVCT access
1351 10:55:36.852563 <6>[ 0.095626] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1352 10:55:36.853045 <6>[ 0.099645] Detected VIPT I-cache on CPU5
1353 10:55:36.863597 <6>[ 0.099693] arch_timer: Enabling local workaround for ARM erratum 858921
1354 10:55:36.864125 <6>[ 0.099703] arch_timer: CPU5: Trapping CNTVCT access
1355 10:55:36.874557 <6>[ 0.099710] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1356 10:55:36.875040 <6>[ 0.099824] smp: Brought up 1 node, 6 CPUs
1357 10:55:36.880090 <6>[ 0.221059] SMP: Total of 6 processors activated.
1358 10:55:36.885628 <6>[ 0.225959] CPU: All CPU(s) started at EL2
1359 10:55:36.891108 <6>[ 0.230304] CPU features: detected: 32-bit EL0 Support
1360 10:55:36.896629 <6>[ 0.235617] CPU features: detected: 32-bit EL1 Support
1361 10:55:36.902144 <6>[ 0.240980] CPU features: detected: CRC32 instructions
1362 10:55:36.907715 <6>[ 0.246374] alternatives: applying system-wide alternatives
1363 10:55:36.925658 <6>[ 0.253580] Memory: 3557136K/4012396K available (17344K kernel code, 4894K rwdata, 11940K rodata, 10496K init, 744K bss, 188000K reserved, 262144K cma-reserved)
1364 10:55:36.926168 <6>[ 0.267911] devtmpfs: initialized
1365 10:55:36.936712 <6>[ 0.277095] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1366 10:55:36.942218 <6>[ 0.281451] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1367 10:55:36.947708 <6>[ 0.292248] 21344 pages in range for non-PLT usage
1368 10:55:36.953253 <6>[ 0.292257] 512864 pages in range for PLT usage
1369 10:55:36.958771 <6>[ 0.293823] pinctrl core: initialized pinctrl subsystem
1370 10:55:36.964303 <6>[ 0.305886] DMI not present or invalid.
1371 10:55:36.969828 <6>[ 0.310214] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1372 10:55:36.975342 <6>[ 0.314995] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1373 10:55:36.986386 <6>[ 0.321794] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1374 10:55:36.991899 <6>[ 0.329921] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1375 10:55:36.997479 <6>[ 0.337283] audit: initializing netlink subsys (disabled)
1376 10:55:37.008466 <5>[ 0.343039] audit: type=2000 audit(0.264:1): state=initialized audit_enabled=0 res=1
1377 10:55:37.013971 <6>[ 0.344451] thermal_sys: Registered thermal governor 'step_wise'
1378 10:55:37.019596 <6>[ 0.350788] thermal_sys: Registered thermal governor 'power_allocator'
1379 10:55:37.024998 <6>[ 0.357049] cpuidle: using governor menu
1380 10:55:37.030601 <6>[ 0.368016] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1381 10:55:37.036054 <6>[ 0.374954] ASID allocator initialised with 65536 entries
1382 10:55:37.044478 <6>[ 0.382405] Serial: AMBA PL011 UART driver
1383 10:55:37.052299 <6>[ 0.393230] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1384 10:55:37.067599 <6>[ 0.408770] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1385 10:55:37.078656 <6>[ 0.411439] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1386 10:55:37.084210 <6>[ 0.424599] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1387 10:55:37.089682 <6>[ 0.427816] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1388 10:55:37.100736 <6>[ 0.436244] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1389 10:55:37.106202 <6>[ 0.443861] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1390 10:55:37.117295 <6>[ 0.457437] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1391 10:55:37.122805 <6>[ 0.459684] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1392 10:55:37.128327 <6>[ 0.466166] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1393 10:55:37.133862 <6>[ 0.473143] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1394 10:55:37.144882 <6>[ 0.479612] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1395 10:55:37.150410 <6>[ 0.486597] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1396 10:55:37.155923 <6>[ 0.493073] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1397 10:55:37.161489 <6>[ 0.500052] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1398 10:55:37.166935 <6>[ 0.508208] ACPI: Interpreter disabled.
1399 10:55:37.172469 <6>[ 0.513468] iommu: Default domain type: Translated
1400 10:55:37.178000 <6>[ 0.515586] iommu: DMA domain TLB invalidation policy: strict mode
1401 10:55:37.183623 <5>[ 0.522295] SCSI subsystem initialized
1402 10:55:37.189036 <6>[ 0.526224] usbcore: registered new interface driver usbfs
1403 10:55:37.194638 <6>[ 0.531646] usbcore: registered new interface driver hub
1404 10:55:37.200076 <6>[ 0.537161] usbcore: registered new device driver usb
1405 10:55:37.205621 <6>[ 0.543430] pps_core: LinuxPPS API ver. 1 registered
1406 10:55:37.211122 <6>[ 0.547579] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1407 10:55:37.216660 <6>[ 0.556898] PTP clock support registered
1408 10:55:37.222114 <6>[ 0.561143] EDAC MC: Ver: 3.0.0
1409 10:55:37.227661 <6>[ 0.564806] scmi_core: SCMI protocol bus registered
1410 10:55:37.228203 <6>[ 0.570527] FPGA manager framework
1411 10:55:37.233197 <6>[ 0.573163] Advanced Linux Sound Architecture Driver Initialized.
1412 10:55:37.238724 <6>[ 0.580102] vgaarb: loaded
1413 10:55:37.244250 <6>[ 0.582665] clocksource: Switched to clocksource arch_sys_counter
1414 10:55:37.249749 <5>[ 0.588815] VFS: Disk quotas dquot_6.6.0
1415 10:55:37.255275 <6>[ 0.592791] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1416 10:55:37.260773 <6>[ 0.600006] pnp: PnP ACPI: disabled
1417 10:55:37.266311 <6>[ 0.608514] NET: Registered PF_INET protocol family
1418 10:55:37.271829 <6>[ 0.608830] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1419 10:55:37.282886 <6>[ 0.619000] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1420 10:55:37.288390 <6>[ 0.624994] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1421 10:55:37.299425 <6>[ 0.632892] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1422 10:55:37.304959 <6>[ 0.641127] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1423 10:55:37.310503 <6>[ 0.648925] TCP: Hash tables configured (established 32768 bind 32768)
1424 10:55:37.316037 <6>[ 0.655400] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1425 10:55:37.327037 <6>[ 0.662248] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1426 10:55:37.332638 <6>[ 0.669673] NET: Registered PF_UNIX/PF_LOCAL protocol family
1427 10:55:37.338067 <6>[ 0.675774] RPC: Registered named UNIX socket transport module.
1428 10:55:37.343635 <6>[ 0.681537] RPC: Registered udp transport module.
1429 10:55:37.349125 <6>[ 0.686442] RPC: Registered tcp transport module.
1430 10:55:37.354614 <6>[ 0.691356] RPC: Registered tcp-with-tls transport module.
1431 10:55:37.360150 <6>[ 0.697050] RPC: Registered tcp NFSv4.1 backchannel transport module.
1432 10:55:37.365691 <6>[ 0.703697] PCI: CLS 0 bytes, default 64
1433 10:55:37.366177 <6>[ 0.708027] Unpacking initramfs...
1434 10:55:37.371194 <6>[ 0.714214] kvm [1]: nv: 554 coarse grained trap handlers
1435 10:55:37.376712 <6>[ 0.717364] kvm [1]: IPA Size Limit: 40 bits
1436 10:55:37.382225 <6>[ 0.723003] kvm [1]: vgic interrupt IRQ9
1437 10:55:37.387764 <6>[ 0.725708] kvm [1]: Hyp nVHE mode initialized successfully
1438 10:55:37.393271 <5>[ 0.733125] Initialise system trusted keyrings
1439 10:55:37.398773 <6>[ 0.736354] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1440 10:55:37.404323 <6>[ 0.742999] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1441 10:55:37.409843 <5>[ 0.749108] NFS: Registering the id_resolver key type
1442 10:55:37.415366 <5>[ 0.754085] Key type id_resolver registered
1443 10:55:37.420883 <5>[ 0.758462] Key type id_legacy registered
1444 10:55:37.426401 <6>[ 0.762698] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1445 10:55:37.431913 <6>[ 0.769588] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1446 10:55:37.439308 <6>[ 0.777403] 9p: Installing v9fs 9p2000 file system support
1447 10:55:37.476864 <5>[ 0.823521] Key type asymmetric registered
1448 10:55:37.482353 <5>[ 0.823558] Asymmetric key parser 'x509' registered
1449 10:55:37.493383 <6>[ 0.827429] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1450 10:55:37.493878 <6>[ 0.834952] io scheduler mq-deadline registered
1451 10:55:37.498907 <6>[ 0.839695] io scheduler kyber registered
1452 10:55:37.504407 <6>[ 0.843959] io scheduler bfq registered
1453 10:55:37.510850 <6>[ 0.852479] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1454 10:55:37.527269 <6>[ 0.870197] ledtrig-cpu: registered to indicate activity on CPUs
1455 10:55:37.559622 <6>[ 0.901312] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1456 10:55:37.579424 <6>[ 0.914859] Serial: 8250/16550 driver, 4 ports<6>[ 0.919484] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1457 10:55:37.584951 <6>[ 0.929109] printk: legacy console [ttyAML0] enabled
1458 10:55:37.590545 <6>[ 0.929109] printk: legacy console [ttyAML0] enabled
1459 10:55:37.596066 <6>[ 0.933906] printk: legacy bootconsole [meson0] disabled
1460 10:55:37.601652 <6>[ 0.933906] printk: legacy bootconsole [meson0] disabled
1461 10:55:37.607090 <6>[ 0.947495] msm_serial: driver initialized
1462 10:55:37.612695 <6>[ 0.949844] SuperH (H)SCI(F) driver initialized
1463 10:55:37.613188 <6>[ 0.954377] STM32 USART driver initialized
1464 10:55:37.620829 <5>[ 0.960721] random: crng init done
1465 10:55:37.627921 <6>[ 0.970263] loop: module loaded
1466 10:55:37.628439 <6>[ 0.971575] megasas: 07.727.03.00-rc1
1467 10:55:37.633460 <6>[ 0.979095] tun: Universal TUN/TAP device driver, 1.6
1468 10:55:37.639059 <6>[ 0.980286] thunder_xcv, ver 1.0
1469 10:55:37.644556 <6>[ 0.982250] thunder_bgx, ver 1.0
1470 10:55:37.645040 <6>[ 0.985739] nicpf, ver 1.0
1471 10:55:37.650093 <6>[ 0.990252] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1472 10:55:37.655668 <6>[ 0.996110] hns3: Copyright (c) 2017 Huawei Corporation.
1473 10:55:37.661197 <6>[ 1.001700] hclge is initializing
1474 10:55:37.666735 <6>[ 1.005240] e1000: Intel(R) PRO/1000 Network Driver
1475 10:55:37.672293 <6>[ 1.010320] e1000: Copyright (c) 1999-2006 Intel Corporation.
1476 10:55:37.677830 <6>[ 1.016344] e1000e: Intel(R) PRO/1000 Network Driver
1477 10:55:37.683381 <6>[ 1.021500] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1478 10:55:37.688907 <6>[ 1.027681] igb: Intel(R) Gigabit Ethernet Network Driver
1479 10:55:37.694471 <6>[ 1.033286] igb: Copyright (c) 2007-2014 Intel Corporation.
1480 10:55:37.700032 <6>[ 1.039118] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1481 10:55:37.705558 <6>[ 1.045591] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1482 10:55:37.711101 <6>[ 1.052342] sky2: driver version 1.30
1483 10:55:37.716689 <6>[ 1.057470] VFIO - User Level meta-driver version: 0.3
1484 10:55:37.722201 <6>[ 1.064908] usbcore: registered new interface driver usb-storage
1485 10:55:37.728228 <6>[ 1.071047] i2c_dev: i2c /dev entries driver
1486 10:55:37.741036 <6>[ 1.082160] sdhci: Secure Digital Host Controller Interface driver
1487 10:55:37.741522 <6>[ 1.082986] sdhci: Copyright(c) Pierre Ossman
1488 10:55:37.752149 <6>[ 1.088703] Synopsys Designware Multimedia Card Interface Driver
1489 10:55:37.757693 <6>[ 1.095236] sdhci-pltfm: SDHCI platform and OF driver helper
1490 10:55:37.758171 <6>[ 1.102878] meson-sm: secure-monitor enabled
1491 10:55:37.770541 <6>[ 1.105365] usbcore: registered new interface driver usbhid
1492 10:55:37.771029 <6>[ 1.110020] usbhid: USB HID core driver
1493 10:55:37.778199 <6>[ 1.124858] NET: Registered PF_PACKET protocol family
1494 10:55:37.783746 <6>[ 1.124946] 9pnet: Installing 9P2000 support
1495 10:55:37.790726 <5>[ 1.129107] Key type dns_resolver registered
1496 10:55:37.798186 <6>[ 1.140608] registered taskstats version 1
1497 10:55:37.798673 <5>[ 1.140775] Loading compiled-in X.509 certificates
1498 10:55:37.805420 <6>[ 1.149572] Demotion targets for Node 0: null
1499 10:55:37.846598 <6>[ 1.193176] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1500 10:55:37.852091 <6>[ 1.193219] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1501 10:55:37.863151 <4>[ 1.203470] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1502 10:55:37.868710 <4>[ 1.205959] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1503 10:55:37.874233 <6>[ 1.213560] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1504 10:55:37.879787 <6>[ 1.222884] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1505 10:55:37.890854 <6>[ 1.226237] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1506 10:55:37.901944 <6>[ 1.234252] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1507 10:55:37.907572 <6>[ 1.243780] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1508 10:55:37.913084 <6>[ 1.249992] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1509 10:55:37.918716 <6>[ 1.255624] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1510 10:55:37.924209 <6>[ 1.263508] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1511 10:55:37.929714 <6>[ 1.270810] hub 1-0:1.0: USB hub found
1512 10:55:37.935262 <6>[ 1.274259] hub 1-0:1.0: 2 ports detected
1513 10:55:37.940806 <6>[ 1.280399] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1514 10:55:37.946353 <6>[ 1.287258] hub 2-0:1.0: USB hub found
1515 10:55:37.951417 <6>[ 1.290833] hub 2-0:1.0: 1 port detected
1516 10:55:37.977856 <6>[ 1.321960] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1517 10:55:37.988972 <6>[ 1.332303] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1518 10:55:38.022685 <6>[ 1.365608] Trying to probe devices needed for running init ...
1519 10:55:38.180329 <6>[ 1.522695] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1520 10:55:38.334422 <6>[ 1.681046] Freeing initrd memory: 22892K
1521 10:55:38.339933 <6>[ 1.681966] mmc0: new UHS-I speed SDR104 SDXC card at address e624
1522 10:55:38.345475 <6>[ 1.686692] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1523 10:55:38.349939 <6>[ 1.692291] mmcblk0: p1
1524 10:55:38.371936 <6>[ 1.718620] hub 1-1:1.0: USB hub found
1525 10:55:38.377725 <6>[ 1.718925] hub 1-1:1.0: 4 ports detected
1526 10:55:38.440458 <6>[ 1.782824] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1527 10:55:38.484654 <6>[ 1.831273] hub 2-1:1.0: USB hub found
1528 10:55:38.490333 <6>[ 1.832101] hub 2-1:1.0: 4 ports detected
1529 10:55:50.304364 <6>[ 13.650731] clk: Disabling unused clocks
1530 10:55:50.309768 <6>[ 13.650900] PM: genpd: Disabling unused power domains
1531 10:55:50.318192 <6>[ 13.654588] ALSA device list:
1532 10:55:50.318702 <6>[ 13.657786] No soundcards found.
1533 10:55:50.324246 <6>[ 13.669990] Freeing unused kernel memory: 10496K
1534 10:55:50.329623 <6>[ 13.670091] Run /init as init process
1535 10:55:50.336857 Loading, please wait...
1536 10:55:50.374867 Starting systemd-udevd version 252.22-1~deb12u1
1537 10:55:50.810141 <6>[ 14.154886] mc: Linux media interface: v0.10
1538 10:55:50.817868 <6>[ 14.161121] videodev: Linux video capture interface: v2.00
1539 10:55:50.840246 <4>[ 14.179317] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1540 10:55:50.867808 <6>[ 14.214368] meson-vrtc ff8000a8.rtc: registered as rtc0
1541 10:55:50.879104 <6>[ 14.214425] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1542 10:55:50.906230 <4>[ 14.246332] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1543 10:55:50.911711 <6>[ 14.255845] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1544 10:55:50.917245 <6>[ 14.257092] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1545 10:55:50.928464 <6>[ 14.263560] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1546 10:55:50.933887 <6>[ 14.269872] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1547 10:55:50.939613 <6>[ 14.277005] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1548 10:55:50.944986 <3>[ 14.277290] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1549 10:55:50.950642 <6>[ 14.283310] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1550 10:55:50.961732 <6>[ 14.283324] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1551 10:55:50.967288 <6>[ 14.304356] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1552 10:55:50.972820 <6>[ 14.312074] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1553 10:55:50.978424 <6>[ 14.317532] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1554 10:55:50.989563 <6>[ 14.318877] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1555 10:55:50.995025 <6>[ 14.324802] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1556 10:55:51.000576 <6>[ 14.337738] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1557 10:55:51.006073 <6>[ 14.337850] usbcore: registered new device driver onboard-usb-dev
1558 10:55:51.011639 <6>[ 14.343463] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1559 10:55:51.017113 <6>[ 14.345582] Registered IR keymap rc-empty
1560 10:55:51.022671 <6>[ 14.345670] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1561 10:55:51.033764 <6>[ 14.345763] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1562 10:55:51.034152 <6>[ 14.350117] rc rc0: sw decoder init
1563 10:55:51.044828 <6>[ 14.355825] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1564 10:55:51.050518 <6>[ 14.360219] meson-ir ff808000.ir: receiver initialized
1565 10:55:51.061473 <6>[ 14.363394] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1566 10:55:51.067055 <6>[ 14.365493] panfrost ffe40000.gpu: clock rate = 24000000
1567 10:55:51.072648 <3>[ 14.365637] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1568 10:55:51.083677 <6>[ 14.370644] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1569 10:55:51.094746 <6>[ 14.372414] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 kHz, changing to: 1000000 kHz
1570 10:55:51.100377 <6>[ 14.377855] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1571 10:55:51.111516 <6>[ 14.394486] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1572 10:55:51.117019 <6>[ 14.404611] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1573 10:55:51.128088 <6>[ 14.404972] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1574 10:55:51.139146 <6>[ 14.409635] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1575 10:55:51.144696 <6>[ 14.409643] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1576 10:55:51.150249 <3>[ 14.418724] meson-drm ff900000.vpu: DSI transceiver device is disabled
1577 10:55:51.155787 <6>[ 14.432800] [drm] Initialized panfrost 1.3.0 for ffe40000.gpu on minor 1
1578 10:55:51.165077 <6>[ 14.437785] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 0
1579 10:55:51.344574 <6>[ 14.667424] Console: switching to colour frame buffer device 128x48
1580 10:55:51.350530 <6>[ 14.686636] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1581 10:55:51.588098 <6>[ 14.934760] hub 1-1:1.0: USB hub found
1582 10:55:51.593558 <6>[ 14.935097] hub 1-1:1.0: 4 ports detected
1583 10:55:51.599999 <6>[ 14.940530] onboard-usb-dev 1-1: USB disconnect, device number 2
1584 10:55:51.936145 <4>[ 15.282687] rc rc0: two consecutive events of type space
1585 10:55:51.945974 <6>[ 15.286593] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1586 10:55:52.080280 <6>[ 15.422700] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1587 10:55:52.260165 <6>[ 15.606749] hub 1-1:1.0: USB hub found
1588 10:55:52.265851 <6>[ 15.607107] hub 1-1:1.0: 4 ports detected
1589 10:55:52.278340 Begin: Loading essential drivers ... done.
1590 10:55:52.283867 Begin: Running /scripts/init-premount ... done.
1591 10:55:52.289428 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1592 10:55:52.303323 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1593 10:55:52.303890 Device /sys/class/net/end0 found
1594 10:55:52.304404 done.
1595 10:55:52.313239 Begin: Waiting up to 180 secs for any network device to become available ... done.
1596 10:55:52.371454 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.707873] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1597 10:55:52.372088
1598 10:55:52.460356 <6>[ 15.798780] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1599 10:55:52.474428 <6>[ 15.815531] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1600 10:55:52.480076 <6>[ 15.817716] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1601 10:55:52.489279 <6>[ 15.825063] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1602 10:55:54.369726 IP-Config: no response after 2 secs - giving up
1603 10:55:54.407177 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1604 10:55:55.461572 <6>[ 18.802054] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1605 10:55:56.618718 IP-Config: end0 guessed broadcast address 192.168.6.255
1606 10:55:56.623874 IP-Config: end0 complete (dhcp from 192.168.6.1):
1607 10:55:56.629384 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1608 10:55:56.638657 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1609 10:55:56.643962 rootserver: 192.168.6.1 rootpath:
1610 10:55:56.644509 filename :
1611 10:55:56.746865 done.
1612 10:55:56.757711 Begin: Running /scripts/nfs-bottom ... done.
1613 10:55:56.769705 Begin: Running /scripts/init-bottom ... done.
1614 10:55:57.097658 <30>[ 20.439571] systemd[1]: System time before build time, advancing clock.
1615 10:55:57.145371 <6>[ 20.491850] NET: Registered PF_INET6 protocol family
1616 10:55:57.150857 <6>[ 20.494419] Segment Routing with IPv6
1617 10:55:57.156115 <6>[ 20.495376] In-situ OAM (IOAM) with IPv6
1618 10:55:57.236414 <30>[ 20.555373] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1619 10:55:57.241946 <30>[ 20.582811] systemd[1]: Detected architecture arm64.
1620 10:55:57.242234
1621 10:55:57.249310 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1622 10:55:57.249692
1623 10:55:57.257396 <30>[ 20.600300] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1624 10:55:58.030713 <30>[ 21.372309] systemd[1]: Queued start job for default target graphical.target.
1625 10:55:58.054465 <30>[ 21.395433] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1626 10:55:58.061868 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1627 10:55:58.079546 <30>[ 21.420670] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1628 10:55:58.088035 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1629 10:55:58.099671 <30>[ 21.440734] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1630 10:55:58.108579 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1631 10:55:58.119551 <30>[ 21.459729] systemd[1]: Created slice user.slice - User and Session Slice.
1632 10:55:58.125783 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1633 10:55:58.136752 <30>[ 21.474963] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1634 10:55:58.142671 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1635 10:55:58.153677 <30>[ 21.494877] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1636 10:55:58.165797 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1637 10:55:58.182503 <30>[ 21.514850] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1638 10:55:58.193552 <30>[ 21.528922] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1639 10:55:58.201185 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1640 10:55:58.206725 <30>[ 21.550768] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1641 10:55:58.217668 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1642 10:55:58.233520 <30>[ 21.574784] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1643 10:55:58.247288 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1644 10:55:58.252789 <30>[ 21.594816] systemd[1]: Reached target paths.target - Path Units.
1645 10:55:58.261184 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1646 10:55:58.266792 <30>[ 21.610772] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1647 10:55:58.278477 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1648 10:55:58.284045 <30>[ 21.626765] systemd[1]: Reached target slices.target - Slice Units.
1649 10:55:58.292171 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1650 10:55:58.297699 <30>[ 21.642776] systemd[1]: Reached target swap.target - Swaps.
1651 10:55:58.305543 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1652 10:55:58.317528 <30>[ 21.658805] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1653 10:55:58.326503 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1654 10:55:58.341699 <30>[ 21.682967] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1655 10:55:58.350936 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1656 10:55:58.363568 <30>[ 21.704839] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1657 10:55:58.376763 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1658 10:55:58.382304 <30>[ 21.723729] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1659 10:55:58.395458 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1660 10:55:58.400884 <30>[ 21.743109] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1661 10:55:58.407766 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1662 10:55:58.418876 <30>[ 21.759763] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1663 10:55:58.427652 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1664 10:55:58.439533 <30>[ 21.780765] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1665 10:55:58.445071 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1666 10:55:58.459613 <30>[ 21.799007] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1667 10:55:58.466304 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1668 10:55:58.497644 <30>[ 21.838881] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1669 10:55:58.504408 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1670 10:55:58.516069 <30>[ 21.857284] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1671 10:55:58.523544 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1672 10:55:58.535892 <30>[ 21.877134] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1673 10:55:58.543871 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1674 10:55:58.560515 <30>[ 21.895024] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1675 10:55:58.571634 <30>[ 21.908138] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1676 10:55:58.577543 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1677 10:55:58.625725 <30>[ 21.966992] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1678 10:55:58.633712 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1679 10:55:58.652461 <30>[ 21.993682] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1680 10:55:58.660060 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1681 10:55:58.672224 <30>[ 22.013432] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1682 10:55:58.677739 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1683 10:55:58.688176 <6>[ 22.025610] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1684 10:55:58.704472 <30>[ 22.045620] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1685 10:55:58.712698 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1686 10:55:58.728515 <30>[ 22.069630] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1687 10:55:58.735702 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1688 10:55:58.745211 <6>[ 22.091994] fuse: init (API version 7.41)
1689 10:55:58.756355 <30>[ 22.093609] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1690 10:55:58.760220 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1691 10:55:58.782348 <30>[ 22.123593] systemd[1]: Starting systemd-journald.service - Journal Service...
1692 10:55:58.788712 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1693 10:55:58.807768 <30>[ 22.148969] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1694 10:55:58.815234 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1695 10:55:58.828184 <30>[ 22.169439] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1696 10:55:58.837581 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1697 10:55:58.851690 <30>[ 22.192920] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1698 10:55:58.860551 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1699 10:55:58.875890 <30>[ 22.217149] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1700 10:55:58.883892 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1701 10:55:58.896658 <30>[ 22.237922] systemd[1]: Started systemd-journald.service - Journal Service.
1702 10:55:58.903608 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1703 10:55:58.918371 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1704 10:55:58.925235 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1705 10:55:58.942238 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1706 10:55:58.958431 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1707 10:55:58.974734 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1708 10:55:58.990800 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1709 10:55:59.006451 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1710 10:55:59.022741 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1711 10:55:59.038630 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1712 10:55:59.050582 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1713 10:55:59.066580 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1714 10:55:59.082472 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1715 10:55:59.098588 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1716 10:55:59.114805 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1717 10:55:59.157293 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1718 10:55:59.168155 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1719 10:55:59.185065 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1720 10:55:59.196050 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1721 10:55:59.213863 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1722 10:55:59.225124 <46>[ 22.566289] systemd-journald[234]: Received client request to flush runtime journal.
1723 10:55:59.244259 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1724 10:55:59.269408 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1725 10:55:59.286971 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1726 10:55:59.294447 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1727 10:55:59.307702 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1728 10:55:59.319642 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1729 10:55:59.387192 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1730 10:55:59.441971 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1731 10:55:59.513807 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1732 10:55:59.557711 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1733 10:55:59.566184 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1734 10:55:59.577198 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1735 10:55:59.621283 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1736 10:55:59.631914 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1737 10:55:59.859848 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1738 10:55:59.897730 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1739 10:55:59.934956 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1740 10:55:59.955722 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1741 10:56:00.021325 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1742 10:56:00.032133 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1743 10:56:00.063867 <5>[ 23.405217] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1744 10:56:00.101796 <5>[ 23.443107] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1745 10:56:00.107436 <5>[ 23.443799] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1746 10:56:00.118599 [[<4>[ 23.451851] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1747 10:56:00.119131 <6>[ 23.460283] cfg80211: failed to load regulatory.db
1748 10:56:00.129281 0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1749 10:56:00.196548 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1750 10:56:00.210919 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1751 10:56:00.223489 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1752 10:56:00.239379 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1753 10:56:00.250373 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1754 10:56:00.262441 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1755 10:56:00.277300 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1756 10:56:00.306502 <46>[ 23.636665] systemd-journald[234]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1757 10:56:00.317725 <46>[ 23.649100] systemd-journald[234]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1758 10:56:00.328320 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1759 10:56:00.341770 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1760 10:56:00.350236 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1761 10:56:00.440320 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1762 10:56:00.453934 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1763 10:56:00.462329 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1764 10:56:00.472034 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1765 10:56:00.487383 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1766 10:56:00.493255 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1767 10:56:00.540790 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1768 10:56:00.577187 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1769 10:56:00.595142 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1770 10:56:00.608064 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1771 10:56:00.646048 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1772 10:56:00.654555 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1773 10:56:00.700837 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1774 10:56:00.706918 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1775 10:56:00.725659 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1776 10:56:00.732796 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1777 10:56:00.741625 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1778 10:56:00.766029 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1779 10:56:00.782992 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1780 10:56:00.792910 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1781 10:56:00.806018 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1782 10:56:00.818952 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1783 10:56:00.829952 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1784 10:56:00.889906 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1785 10:56:00.941279 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1786 10:56:00.982983
1787 10:56:00.983347 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1788 10:56:00.983567
1789 10:56:00.990142 debian-bookworm-arm64 login: root (automatic login)
1790 10:56:00.990446
1791 10:56:01.141912 Linux debian-bookworm-arm64 6.12.0-rc5-next-20241030 #1 SMP PREEMPT Wed Oct 30 10:38:14 UTC 2024 aarch64
1792 10:56:01.142323
1793 10:56:01.147340 The programs included with the Debian GNU/Linux system are free software;
1794 10:56:01.156369 the exact distribution terms for each program are described in the
1795 10:56:01.161869 individual files in /usr/share/doc/*/copyright.
1796 10:56:01.162164
1797 10:56:01.168323 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1798 10:56:01.168618 permitted by applicable law.
1799 10:56:01.750319 Matched prompt #10: / #
1801 10:56:01.751263 Setting prompt string to ['/ #']
1802 10:56:01.751596 end: 2.4.4.1 login-action (duration 00:00:26) [common]
1804 10:56:01.752979 end: 2.4.4 auto-login-action (duration 00:00:26) [common]
1805 10:56:01.753585 start: 2.4.5 expect-shell-connection (timeout 00:03:10) [common]
1806 10:56:01.754049 Setting prompt string to ['/ #']
1807 10:56:01.754477 Forcing a shell prompt, looking for ['/ #']
1809 10:56:01.805449 / #
1810 10:56:01.806046 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1811 10:56:01.806520 Waiting using forced prompt support (timeout 00:02:30)
1812 10:56:01.811476
1813 10:56:01.812286 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1814 10:56:01.812866 start: 2.4.6 export-device-env (timeout 00:03:10) [common]
1815 10:56:01.813350 Sending with 10 millisecond of delay
1817 10:56:06.799918 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/913099/extract-nfsrootfs-davzblro'
1818 10:56:06.810918 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/913099/extract-nfsrootfs-davzblro'
1819 10:56:06.811735 Sending with 10 millisecond of delay
1821 10:56:08.908973 / # export NFS_SERVER_IP='192.168.6.2'
1822 10:56:08.919841 export NFS_SERVER_IP='192.168.6.2'
1823 10:56:08.920767 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1824 10:56:08.921375 end: 2.4 uboot-commands (duration 00:01:57) [common]
1825 10:56:08.921965 end: 2 uboot-action (duration 00:01:57) [common]
1826 10:56:08.922542 start: 3 lava-test-retry (timeout 00:06:45) [common]
1827 10:56:08.923123 start: 3.1 lava-test-shell (timeout 00:06:45) [common]
1828 10:56:08.923598 Using namespace: common
1830 10:56:09.024812 / # #
1831 10:56:09.025474 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1832 10:56:09.030395 #
1833 10:56:09.031156 Using /lava-913099
1835 10:56:09.132296 / # export SHELL=/bin/bash
1836 10:56:09.137912 export SHELL=/bin/bash
1838 10:56:09.239293 / # . /lava-913099/environment
1839 10:56:09.244342 . /lava-913099/environment
1841 10:56:09.349005 / # /lava-913099/bin/lava-test-runner /lava-913099/0
1842 10:56:09.349683 Test shell timeout: 10s (minimum of the action and connection timeout)
1843 10:56:09.353904 /lava-913099/bin/lava-test-runner /lava-913099/0
1844 10:56:09.537379 + export TESTRUN_ID=0_timesync-off
1845 10:56:09.543260 + TESTRUN_ID=0_timesync-off
1846 10:56:09.543785 + cd /lava-913099/0/tests/0_timesync-off
1847 10:56:09.544283 ++ cat uuid
1848 10:56:09.548788 + UUID=913099_1.6.2.4.1
1849 10:56:09.549397 + set +x
1850 10:56:09.556649 <LAVA_SIGNAL_STARTRUN 0_timesync-off 913099_1.6.2.4.1>
1851 10:56:09.557153 + systemctl stop systemd-timesyncd
1852 10:56:09.557885 Received signal: <STARTRUN> 0_timesync-off 913099_1.6.2.4.1
1853 10:56:09.558336 Starting test lava.0_timesync-off (913099_1.6.2.4.1)
1854 10:56:09.558874 Skipping test definition patterns.
1855 10:56:09.614015 + set +x
1856 10:56:09.614531 <LAVA_SIGNAL_ENDRUN 0_timesync-off 913099_1.6.2.4.1>
1857 10:56:09.615214 Received signal: <ENDRUN> 0_timesync-off 913099_1.6.2.4.1
1858 10:56:09.615710 Ending use of test pattern.
1859 10:56:09.616170 Ending test lava.0_timesync-off (913099_1.6.2.4.1), duration 0.06
1861 10:56:09.686137 + export TESTRUN_ID=1_kselftest-alsa
1862 10:56:09.694435 + TESTRUN_ID=1_kselftest-alsa
1863 10:56:09.694920 + cd /lava-913099/0/tests/1_kselftest-alsa
1864 10:56:09.695164 ++ cat uuid
1865 10:56:09.700735 + UUID=913099_1.6.2.4.5
1866 10:56:09.701372 + set +x
1867 10:56:09.706316 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 913099_1.6.2.4.5>
1868 10:56:09.706960 + cd ./automated/linux/kselftest/
1869 10:56:09.707691 Received signal: <STARTRUN> 1_kselftest-alsa 913099_1.6.2.4.5
1870 10:56:09.708196 Starting test lava.1_kselftest-alsa (913099_1.6.2.4.5)
1871 10:56:09.708721 Skipping test definition patterns.
1872 10:56:09.732937 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1873 10:56:09.773209 INFO: install_deps skipped
1874 10:56:09.883705 --2024-10-30 10:56:09-- http://storage.kernelci.org/next/master/next-20241030/arm64/defconfig/gcc-12/kselftest.tar.xz
1875 10:56:09.910339 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1876 10:56:10.056468 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1877 10:56:10.198949 HTTP request sent, awaiting response... 200 OK
1878 10:56:10.199515 Length: 7306664 (7.0M) [application/octet-stream]
1879 10:56:10.204331 Saving to: 'kselftest_armhf.tar.gz'
1880 10:56:10.204813
1881 10:56:11.389368
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 175KB/s
kselftest_armhf.tar 3%[ ] 218.67K 383KB/s
kselftest_armhf.tar 12%[=> ] 893.67K 1.01MB/s
kselftest_armhf.tar 50%[=========> ] 3.51M 3.06MB/s
kselftest_armhf.tar 100%[===================>] 6.97M 5.88MB/s in 1.2s
1882 10:56:11.389825
1883 10:56:11.484928 2024-10-30 10:56:11 (5.88 MB/s) - 'kselftest_armhf.tar.gz' saved [7306664/7306664]
1884 10:56:11.485571
1885 10:56:21.396756 skiplist:
1886 10:56:21.397384 ========================================
1887 10:56:21.402330 ========================================
1888 10:56:21.440882 alsa:mixer-test
1889 10:56:21.441482 alsa:pcm-test
1890 10:56:21.441940 alsa:test-pcmtest-driver
1891 10:56:21.444997 alsa:utimer-test
1892 10:56:21.457007 ============== Tests to run ===============
1893 10:56:21.457519 alsa:mixer-test
1894 10:56:21.462593 alsa:pcm-test
1895 10:56:21.463107 alsa:test-pcmtest-driver
1896 10:56:21.463526 alsa:utimer-test
1897 10:56:21.470860 ===========End Tests to run ===============
1898 10:56:21.471345 shardfile-alsa pass
1899 10:56:21.574607 <12>[ 44.919075] kselftest: Running tests in alsa
1900 10:56:21.586371 TAP version 13
1901 10:56:21.593975 1..4
1902 10:56:21.620949 # timeout set to 45
1903 10:56:21.621507 # selftests: alsa: mixer-test
1904 10:56:21.767398 # TAP version 13
1905 10:56:21.768049 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1906 10:56:21.772850 # 1..427
1907 10:56:21.773301 # ok 1 get_value.LCALTA.60
1908 10:56:21.773712 # # LCALTA.60 TDMOUT_A SRC SEL
1909 10:56:21.778370 # ok 2 name.LCALTA.60
1910 10:56:21.778813 # ok 3 write_default.LCALTA.60
1911 10:56:21.781922 # ok 4 write_valid.LCALTA.60
1912 10:56:21.787429 # ok 5 write_invalid.LCALTA.60
1913 10:56:21.787866 # ok 6 event_missing.LCALTA.60
1914 10:56:21.792974 # ok 7 event_spurious.LCALTA.60
1915 10:56:21.793436 # ok 8 get_value.LCALTA.59
1916 10:56:21.798471 # # LCALTA.59 TDMOUT_B SRC SEL
1917 10:56:21.798944 # ok 9 name.LCALTA.59
1918 10:56:21.804063 # ok 10 write_default.LCALTA.59
1919 10:56:21.804549 # ok 11 write_valid.LCALTA.59
1920 10:56:21.809539 # ok 12 write_invalid.LCALTA.59
1921 10:56:21.810039 # ok 13 event_missing.LCALTA.59
1922 10:56:21.815130 # ok 14 event_spurious.LCALTA.59
1923 10:56:21.815567 # ok 15 get_value.LCALTA.58
1924 10:56:21.820776 # # LCALTA.58 TDMOUT_C SRC SEL
1925 10:56:21.821206 # ok 16 name.LCALTA.58
1926 10:56:21.821617 # ok 17 write_default.LCALTA.58
1927 10:56:21.826248 # ok 18 write_valid.LCALTA.58
1928 10:56:21.826677 # ok 19 write_invalid.LCALTA.58
1929 10:56:21.831849 # ok 20 event_missing.LCALTA.58
1930 10:56:21.832306 # ok 21 event_spurious.LCALTA.58
1931 10:56:21.837235 # ok 22 get_value.LCALTA.57
1932 10:56:21.837663 # # LCALTA.57 TDMIN_A SRC SEL
1933 10:56:21.842840 # ok 23 name.LCALTA.57
1934 10:56:21.843265 # ok 24 write_default.LCALTA.57
1935 10:56:21.848345 # ok 25 write_valid.LCALTA.57
1936 10:56:21.848791 # ok 26 write_invalid.LCALTA.57
1937 10:56:21.853911 # ok 27 event_missing.LCALTA.57
1938 10:56:21.854354 # ok 28 event_spurious.LCALTA.57
1939 10:56:21.870490 # ok 29 get_value.LCALTA.5<3>[ 45.203752] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1940 10:56:21.871034 6
1941 10:56:21.871456 # # LCALTA.56 TDMIN_B SRC SEL
1942 10:56:21.876042 # ok 30 name.LCALTA.56
1943 10:56:21.876517 # ok 31 write_default.LCALTA.56
1944 10:56:21.881621 # ok 32 write_valid.LCALTA.56
1945 10:56:21.882098 # ok 33 write_invalid.LCALTA.56
1946 10:56:21.887098 # ok 34 event_missing.LCALTA.56
1947 10:56:21.887559 # ok 35 event_spurious.LCALTA.56
1948 10:56:21.892725 # ok 36 get_value.LCALTA.55
1949 10:56:21.893174 # # LCALTA.55 TDMIN_C SRC SEL
1950 10:56:21.898187 # ok 37 name.LCALTA.55
1951 10:56:21.898636 # ok 38 write_default.LCALTA.55
1952 10:56:21.903749 # ok 39 write_valid.LCALTA.55
1953 10:56:21.904221 # ok 40 write_invalid.LCALTA.55
1954 10:56:21.909300 # ok 41 event_missing.LCALTA.55
1955 10:56:21.909736 # ok 42 event_spurious.LCALTA.55
1956 10:56:21.914847 # ok 43 get_value.LCALTA.54
1957 10:56:21.915281 # # LCALTA.54 ACODEC Left DAC Sel
1958 10:56:21.920390 # ok 44 name.LCALTA.54
1959 10:56:21.920826 # ok 45 write_default.LCALTA.54
1960 10:56:21.925915 # ok 46 write_valid.LCALTA.54
1961 10:56:21.926349 # ok 47 write_invalid.LCALTA.54
1962 10:56:21.931464 # ok 48 event_missing.LCALTA.54
1963 10:56:21.931896 # ok 49 event_spurious.LCALTA.54
1964 10:56:21.937034 # ok 50 get_value.LCALTA.53
1965 10:56:21.937473 # # LCALTA.53 ACODEC Right DAC Sel
1966 10:56:21.942611 # ok 51 name.LCALTA.53
1967 10:56:21.943047 # ok 52 write_default.LCALTA.53
1968 10:56:21.948174 # ok 53 write_valid.LCALTA.53
1969 10:56:21.948605 # ok 54 write_invalid.LCALTA.53
1970 10:56:21.953729 # ok 55 event_missing.LCALTA.53
1971 10:56:21.954154 # ok 56 event_spurious.LCALTA.53
1972 10:56:21.959219 # ok 57 get_value.LCALTA.52
1973 10:56:21.959645 # # LCALTA.52 TOACODEC OUT EN Switch
1974 10:56:21.964801 # ok 58 name.LCALTA.52
1975 10:56:21.965285 # ok 59 write_default.LCALTA.52
1976 10:56:21.970353 # ok 60 write_valid.LCALTA.52
1977 10:56:21.970835 # ok 61 write_invalid.LCALTA.52
1978 10:56:21.975883 # ok 62 event_missing.LCALTA.52
1979 10:56:21.976357 # ok 63 event_spurious.LCALTA.52
1980 10:56:21.981412 # ok 64 get_value.LCALTA.51
1981 10:56:21.981847 # # LCALTA.51 TOACODEC SRC
1982 10:56:21.982255 # ok 65 name.LCALTA.51
1983 10:56:21.986925 # ok 66 write_default.LCALTA.51
1984 10:56:21.987359 # ok 67 write_valid.LCALTA.51
1985 10:56:21.992490 # ok 68 write_invalid.LCALTA.51
1986 10:56:21.992919 # ok 69 event_missing.LCALTA.51
1987 10:56:21.998033 # ok 70 event_spurious.LCALTA.51
1988 10:56:21.998468 # ok 71 get_value.LCALTA.50
1989 10:56:22.003610 # # LCALTA.50 TOHDMITX SPDIF SRC
1990 10:56:22.004062 # ok 72 name.LCALTA.50
1991 10:56:22.009158 # ok 73 write_default.LCALTA.50
1992 10:56:22.009601 # ok 74 write_valid.LCALTA.50
1993 10:56:22.014777 # ok 75 write_invalid.LCALTA.50
1994 10:56:22.015213 # ok 76 event_missing.LCALTA.50
1995 10:56:22.020237 # ok 77 event_spurious.LCALTA.50
1996 10:56:22.020668 # ok 78 get_value.LCALTA.49
1997 10:56:22.025806 # # LCALTA.49 TOHDMITX Switch
1998 10:56:22.026236 # ok 79 name.LCALTA.49
1999 10:56:22.031316 # ok 80 write_default.LCALTA.49
2000 10:56:22.031745 # ok 81 write_valid.LCALTA.49
2001 10:56:22.036914 # ok 82 write_invalid.LCALTA.49
2002 10:56:22.037344 # ok 83 event_missing.LCALTA.49
2003 10:56:22.042452 # ok 84 event_spurious.LCALTA.49
2004 10:56:22.042889 # ok 85 get_value.LCALTA.48
2005 10:56:22.048001 # # LCALTA.48 TOHDMITX I2S SRC
2006 10:56:22.048438 # ok 86 name.LCALTA.48
2007 10:56:22.053515 # ok 87 write_default.LCALTA.48
2008 10:56:22.053944 # ok 88 write_valid.LCALTA.48
2009 10:56:22.059057 # ok 89 write_invalid.LCALTA.48
2010 10:56:22.059489 # ok 90 event_missing.LCALTA.48
2011 10:56:22.064642 # ok 91 event_spurious.LCALTA.48
2012 10:56:22.065124 # ok 92 get_value.LCALTA.47
2013 10:56:22.070141 # # LCALTA.47 TODDR_C SRC SEL
2014 10:56:22.070573 # ok 93 name.LCALTA.47
2015 10:56:22.070978 # ok 94 write_default.LCALTA.47
2016 10:56:22.075769 # ok 95 write_valid.LCALTA.47
2017 10:56:22.076276 # ok 96 write_invalid.LCALTA.47
2018 10:56:22.081253 # ok 97 event_missing.LCALTA.47
2019 10:56:22.086809 # ok 98 event_spurious.LCALTA.47
2020 10:56:22.087261 # ok 99 get_value.LCALTA.46
2021 10:56:22.087680 # # LCALTA.46 TODDR_B SRC SEL
2022 10:56:22.092342 # ok 100 name.LCALTA.46
2023 10:56:22.092785 # ok 101 write_default.LCALTA.46
2024 10:56:22.097899 # ok 102 write_valid.LCALTA.46
2025 10:56:22.098340 # ok 103 write_invalid.LCALTA.46
2026 10:56:22.103440 # ok 104 event_missing.LCALTA.46
2027 10:56:22.108982 # ok 105 event_spurious.LCALTA.46
2028 10:56:22.109425 # ok 106 get_value.LCALTA.45
2029 10:56:22.109836 # # LCALTA.45 TODDR_A SRC SEL
2030 10:56:22.114539 # ok 107 name.LCALTA.45
2031 10:56:22.114984 # ok 108 write_default.LCALTA.45
2032 10:56:22.120075 # ok 109 write_valid.LCALTA.45
2033 10:56:22.120513 # ok 110 write_invalid.LCALTA.45
2034 10:56:22.125644 # ok 111 event_missing.LCALTA.45
2035 10:56:22.126078 # ok 112 event_spurious.LCALTA.45
2036 10:56:22.131166 # ok 113 get_value.LCALTA.44
2037 10:56:22.131603 # # LCALTA.44 FRDDR_C SINK 3 SEL
2038 10:56:22.136777 # ok 114 name.LCALTA.44
2039 10:56:22.137213 # ok 115 write_default.LCALTA.44
2040 10:56:22.142261 # ok 116 write_valid.LCALTA.44
2041 10:56:22.142698 # ok 117 write_invalid.LCALTA.44
2042 10:56:22.147811 # ok 118 event_missing.LCALTA.44
2043 10:56:22.153338 # ok 119 event_spurious.LCALTA.44
2044 10:56:22.153779 # ok 120 get_value.LCALTA.43
2045 10:56:22.158880 # # LCALTA.43 FRDDR_C SINK 2 SEL
2046 10:56:22.159313 # ok 121 name.LCALTA.43
2047 10:56:22.159719 # ok 122 write_default.LCALTA.43
2048 10:56:22.164466 # ok 123 write_valid.LCALTA.43
2049 10:56:22.164986 # ok 124 write_invalid.LCALTA.43
2050 10:56:22.170008 # ok 125 event_missing.LCALTA.43
2051 10:56:22.175576 # ok 126 event_spurious.LCALTA.43
2052 10:56:22.176063 # ok 127 get_value.LCALTA.42
2053 10:56:22.181090 # # LCALTA.42 FRDDR_C SINK 1 SEL
2054 10:56:22.181524 # ok 128 name.LCALTA.42
2055 10:56:22.181936 # ok 129 write_default.LCALTA.42
2056 10:56:22.186654 # ok 130 write_valid.LCALTA.42
2057 10:56:22.192227 # ok 131 write_invalid.LCALTA.42
2058 10:56:22.192704 # ok 132 event_missing.LCALTA.42
2059 10:56:22.197789 # ok 133 event_spurious.LCALTA.42
2060 10:56:22.198226 # ok 134 get_value.LCALTA.41
2061 10:56:22.203280 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
2062 10:56:22.203720 # ok 135 name.LCALTA.41
2063 10:56:22.208840 # ok 136 write_default.LCALTA.41
2064 10:56:22.209281 # ok 137 write_valid.LCALTA.41
2065 10:56:22.214372 # ok 138 write_invalid.LCALTA.41
2066 10:56:22.214811 # ok 139 event_missing.LCALTA.41
2067 10:56:22.219893 # ok 140 event_spurious.LCALTA.41
2068 10:56:22.220365 # ok 141 get_value.LCALTA.40
2069 10:56:22.225467 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
2070 10:56:22.225903 # ok 142 name.LCALTA.40
2071 10:56:22.231019 # ok 143 write_default.LCALTA.40
2072 10:56:22.231484 # ok 144 write_valid.LCALTA.40
2073 10:56:22.236547 # ok 145 write_invalid.LCALTA.40
2074 10:56:22.236992 # ok 146 event_missing.LCALTA.40
2075 10:56:22.242111 # ok 147 event_spurious.LCALTA.40
2076 10:56:22.242553 # ok 148 get_value.LCALTA.39
2077 10:56:22.247661 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
2078 10:56:22.248135 # ok 149 name.LCALTA.39
2079 10:56:22.253208 # ok 150 write_default.LCALTA.39
2080 10:56:22.253647 # ok 151 write_valid.LCALTA.39
2081 10:56:22.258815 # ok 152 write_invalid.LCALTA.39
2082 10:56:22.259246 # ok 153 event_missing.LCALTA.39
2083 10:56:22.264306 # ok 154 event_spurious.LCALTA.39
2084 10:56:22.264798 # ok 155 get_value.LCALTA.38
2085 10:56:22.269840 # # LCALTA.38 FRDDR_B SINK 3 SEL
2086 10:56:22.270279 # ok 156 name.LCALTA.38
2087 10:56:22.275376 # ok 157 write_default.LCALTA.38
2088 10:56:22.275808 # ok 158 write_valid.LCALTA.38
2089 10:56:22.280938 # ok 159 write_invalid.LCALTA.38
2090 10:56:22.281380 # ok 160 event_missing.LCALTA.38
2091 10:56:22.286503 # ok 161 event_spurious.LCALTA.38
2092 10:56:22.286994 # ok 162 get_value.LCALTA.37
2093 10:56:22.292071 # # LCALTA.37 FRDDR_B SINK 2 SEL
2094 10:56:22.292524 # ok 163 name.LCALTA.37
2095 10:56:22.297569 # ok 164 write_default.LCALTA.37
2096 10:56:22.298009 # ok 165 write_valid.LCALTA.37
2097 10:56:22.303124 # ok 166 write_invalid.LCALTA.37
2098 10:56:22.303567 # ok 167 event_missing.LCALTA.37
2099 10:56:22.308668 # ok 168 event_spurious.LCALTA.37
2100 10:56:22.309111 # ok 169 get_value.LCALTA.36
2101 10:56:22.314225 # # LCALTA.36 FRDDR_B SINK 1 SEL
2102 10:56:22.314664 # ok 170 name.LCALTA.36
2103 10:56:22.319832 # ok 171 write_default.LCALTA.36
2104 10:56:22.320305 # ok 172 write_valid.LCALTA.36
2105 10:56:22.325291 # ok 173 write_invalid.LCALTA.36
2106 10:56:22.325740 # ok 174 event_missing.LCALTA.36
2107 10:56:22.330854 # ok 175 event_spurious.LCALTA.36
2108 10:56:22.331301 # ok 176 get_value.LCALTA.35
2109 10:56:22.336403 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
2110 10:56:22.336859 # ok 177 name.LCALTA.35
2111 10:56:22.341958 # ok 178 write_default.LCALTA.35
2112 10:56:22.347477 # ok 179 write_valid.LCALTA.35
2113 10:56:22.347923 # ok 180 write_invalid.LCALTA.35
2114 10:56:22.353086 # ok 181 event_missing.LCALTA.35
2115 10:56:22.353537 # ok 182 event_spurious.LCALTA.35
2116 10:56:22.358581 # ok 183 get_value.LCALTA.34
2117 10:56:22.359026 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
2118 10:56:22.364192 # ok 184 name.LCALTA.34
2119 10:56:22.364686 # ok 185 write_default.LCALTA.34
2120 10:56:22.369674 # ok 186 write_valid.LCALTA.34
2121 10:56:22.370120 # ok 187 write_invalid.LCALTA.34
2122 10:56:22.375235 # ok 188 event_missing.LCALTA.34
2123 10:56:22.375725 # ok 189 event_spurious.LCALTA.34
2124 10:56:22.380795 # ok 190 get_value.LCALTA.33
2125 10:56:22.381240 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
2126 10:56:22.386306 # ok 191 name.LCALTA.33
2127 10:56:22.386754 # ok 192 write_default.LCALTA.33
2128 10:56:22.391856 # ok 193 write_valid.LCALTA.33
2129 10:56:22.392333 # ok 194 write_invalid.LCALTA.33
2130 10:56:22.397418 # ok 195 event_missing.LCALTA.33
2131 10:56:22.397860 # ok 196 event_spurious.LCALTA.33
2132 10:56:22.402959 # ok 197 get_value.LCALTA.32
2133 10:56:22.403399 # # LCALTA.32 FRDDR_A SINK 3 SEL
2134 10:56:22.408508 # ok 198 name.LCALTA.32
2135 10:56:22.408947 # ok 199 write_default.LCALTA.32
2136 10:56:22.414071 # ok 200 write_valid.LCALTA.32
2137 10:56:22.414508 # ok 201 write_invalid.LCALTA.32
2138 10:56:22.419598 # ok 202 event_missing.LCALTA.32
2139 10:56:22.420061 # ok 203 event_spurious.LCALTA.32
2140 10:56:22.425144 # ok 204 get_value.LCALTA.31
2141 10:56:22.425583 # # LCALTA.31 FRDDR_A SINK 2 SEL
2142 10:56:22.430673 # ok 205 name.LCALTA.31
2143 10:56:22.431119 # ok 206 write_default.LCALTA.31
2144 10:56:22.436235 # ok 207 write_valid.LCALTA.31
2145 10:56:22.436676 # ok 208 write_invalid.LCALTA.31
2146 10:56:22.441803 # ok 209 event_missing.LCALTA.31
2147 10:56:22.442247 # ok 210 event_spurious.LCALTA.31
2148 10:56:22.447315 # ok 211 get_value.LCALTA.30
2149 10:56:22.447751 # # LCALTA.30 FRDDR_A SINK 1 SEL
2150 10:56:22.452874 # ok 212 name.LCALTA.30
2151 10:56:22.453326 # ok 213 write_default.LCALTA.30
2152 10:56:22.458437 # ok 214 write_valid.LCALTA.30
2153 10:56:22.458893 # ok 215 write_invalid.LCALTA.30
2154 10:56:22.463958 # ok 216 event_missing.LCALTA.30
2155 10:56:22.464461 # ok 217 event_spurious.LCALTA.30
2156 10:56:22.469514 # ok 218 get_value.LCALTA.29
2157 10:56:22.475078 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2158 10:56:22.475517 # ok 219 name.LCALTA.29
2159 10:56:22.475923 # ok 220 write_default.LCALTA.29
2160 10:56:22.480611 # ok 221 write_valid.LCALTA.29
2161 10:56:22.481080 # ok 222 write_invalid.LCALTA.29
2162 10:56:22.486117 # ok 223 event_missing.LCALTA.29
2163 10:56:22.491809 # ok 224 event_spurious.LCALTA.29
2164 10:56:22.492288 # ok 225 get_value.LCALTA.28
2165 10:56:22.497219 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2166 10:56:22.497658 # ok 226 name.LCALTA.28
2167 10:56:22.502816 # ok 227 write_default.LCALTA.28
2168 10:56:22.503251 # ok 228 write_valid.LCALTA.28
2169 10:56:22.508360 # ok 229 write_invalid.LCALTA.28
2170 10:56:22.508814 # ok 230 event_missing.LCALTA.28
2171 10:56:22.513880 # ok 231 event_spurious.LCALTA.28
2172 10:56:22.514325 # ok 232 get_value.LCALTA.27
2173 10:56:22.519457 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2174 10:56:22.519902 # ok 233 name.LCALTA.27
2175 10:56:22.524974 # ok 234 write_default.LCALTA.27
2176 10:56:22.525413 # ok 235 write_valid.LCALTA.27
2177 10:56:22.530541 # ok 236 write_invalid.LCALTA.27
2178 10:56:22.530982 # ok 237 event_missing.LCALTA.27
2179 10:56:22.536101 # ok 238 event_spurious.LCALTA.27
2180 10:56:22.536543 # ok 239 get_value.LCALTA.26
2181 10:56:22.541622 # # LCALTA.26 ELD
2182 10:56:22.542051 # ok 240 name.LCALTA.26
2183 10:56:22.542453 # # ELD is not writeable
2184 10:56:22.547179 # ok 241 # SKIP write_default.LCALTA.26
2185 10:56:22.547619 # # ELD is not writeable
2186 10:56:22.552822 # ok 242 # SKIP write_valid.LCALTA.26
2187 10:56:22.553260 # # ELD is not writeable
2188 10:56:22.558265 # ok 243 # SKIP write_invalid.LCALTA.26
2189 10:56:22.563852 # ok 244 event_missing.LCALTA.26
2190 10:56:22.564375 # ok 245 event_spurious.LCALTA.26
2191 10:56:22.569355 # ok 246 get_value.LCALTA.25
2192 10:56:22.569801 # # LCALTA.25 IEC958 Playback Default
2193 10:56:22.574906 # ok 247 name.LCALTA.25
2194 10:56:22.575344 # ok 248 write_default.LCALTA.25
2195 10:56:22.580478 # ok 249 # SKIP write_valid.LCALTA.25
2196 10:56:22.580974 # ok 250 # SKIP write_invalid.LCALTA.25
2197 10:56:22.585999 # ok 251 event_missing.LCALTA.25
2198 10:56:22.586438 # ok 252 event_spurious.LCALTA.25
2199 10:56:22.591525 # ok 253 get_value.LCALTA.24
2200 10:56:22.591962 # # LCALTA.24 IEC958 Playback Mask
2201 10:56:22.597071 # ok 254 name.LCALTA.24
2202 10:56:22.602694 # # IEC958 Playback Mask is not writeable
2203 10:56:22.603139 # ok 255 # SKIP write_default.LCALTA.24
2204 10:56:22.608216 # # IEC958 Playback Mask is not writeable
2205 10:56:22.608665 # ok 256 # SKIP write_valid.LCALTA.24
2206 10:56:22.613837 # # IEC958 Playback Mask is not writeable
2207 10:56:22.619249 # ok 257 # SKIP write_invalid.LCALTA.24
2208 10:56:22.619685 # ok 258 event_missing.LCALTA.24
2209 10:56:22.624820 # ok 259 event_spurious.LCALTA.24
2210 10:56:22.625262 # ok 260 get_value.LCALTA.23
2211 10:56:22.630341 # # LCALTA.23 Playback Channel Map
2212 10:56:22.630778 # ok 261 name.LCALTA.23
2213 10:56:22.635890 # # Playback Channel Map is not writeable
2214 10:56:22.641478 # ok 262 # SKIP write_default.LCALTA.23
2215 10:56:22.641921 # # Playback Channel Map is not writeable
2216 10:56:22.647015 # ok 263 # SKIP write_valid.LCALTA.23
2217 10:56:22.652558 # # Playback Channel Map is not writeable
2218 10:56:22.653001 # ok 264 # SKIP write_invalid.LCALTA.23
2219 10:56:22.658089 # ok 265 event_missing.LCALTA.23
2220 10:56:22.658526 # ok 266 event_spurious.LCALTA.23
2221 10:56:22.663698 # ok 267 get_value.LCALTA.22
2222 10:56:22.664229 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2223 10:56:22.669194 # ok 268 name.LCALTA.22
2224 10:56:22.669644 # ok 269 write_default.LCALTA.22
2225 10:56:22.674863 # ok 270 write_valid.LCALTA.22
2226 10:56:22.675300 # ok 271 write_invalid.LCALTA.22
2227 10:56:22.680353 # ok 272 event_missing.LCALTA.22
2228 10:56:22.680794 # ok 273 event_spurious.LCALTA.22
2229 10:56:22.685861 # ok 274 get_value.LCALTA.21
2230 10:56:22.686304 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2231 10:56:22.691374 # ok 275 name.LCALTA.21
2232 10:56:22.691821 # ok 276 write_default.LCALTA.21
2233 10:56:22.696940 # ok 277 write_valid.LCALTA.21
2234 10:56:22.697375 # ok 278 write_invalid.LCALTA.21
2235 10:56:22.702493 # ok 279 event_missing.LCALTA.21
2236 10:56:22.708053 # ok 280 event_spurious.LCALTA.21
2237 10:56:22.708494 # ok 281 get_value.LCALTA.20
2238 10:56:22.713590 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2239 10:56:22.714037 # ok 282 name.LCALTA.20
2240 10:56:22.714440 # ok 283 write_default.LCALTA.20
2241 10:56:22.719112 # ok 284 write_valid.LCALTA.20
2242 10:56:22.724723 # ok 285 write_invalid.LCALTA.20
2243 10:56:22.725162 # ok 286 event_missing.LCALTA.20
2244 10:56:22.730233 # ok 287 event_spurious.LCALTA.20
2245 10:56:22.730674 # ok 288 get_value.LCALTA.19
2246 10:56:22.735860 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2247 10:56:22.736345 # ok 289 name.LCALTA.19
2248 10:56:22.741314 # ok 290 write_default.LCALTA.19
2249 10:56:22.741765 # ok 291 write_valid.LCALTA.19
2250 10:56:22.746857 # ok 292 write_invalid.LCALTA.19
2251 10:56:22.747305 # ok 293 event_missing.LCALTA.19
2252 10:56:22.752409 # ok 294 event_spurious.LCALTA.19
2253 10:56:22.752854 # ok 295 get_value.LCALTA.18
2254 10:56:22.757915 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2255 10:56:22.758359 # ok 296 name.LCALTA.18
2256 10:56:22.763509 # ok 297 write_default.LCALTA.18
2257 10:56:22.764033 # ok 298 write_valid.LCALTA.18
2258 10:56:22.769077 # ok 299 write_invalid.LCALTA.18
2259 10:56:22.769569 # ok 300 event_missing.LCALTA.18
2260 10:56:22.774608 # ok 301 event_spurious.LCALTA.18
2261 10:56:22.775108 # ok 302 get_value.LCALTA.17
2262 10:56:22.780270 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2263 10:56:22.780805 # ok 303 name.LCALTA.17
2264 10:56:22.785814 # ok 304 write_default.LCALTA.17
2265 10:56:22.786262 # ok 305 write_valid.LCALTA.17
2266 10:56:22.791301 # ok 306 write_invalid.LCALTA.17
2267 10:56:22.791746 # ok 307 event_missing.LCALTA.17
2268 10:56:22.796948 # ok 308 event_spurious.LCALTA.17
2269 10:56:22.797392 # ok 309 get_value.LCALTA.16
2270 10:56:22.802403 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2271 10:56:22.802841 # ok 310 name.LCALTA.16
2272 10:56:22.807892 # ok 311 write_default.LCALTA.16
2273 10:56:22.808387 # ok 312 write_valid.LCALTA.16
2274 10:56:22.813509 # ok 313 write_invalid.LCALTA.16
2275 10:56:22.818968 # ok 314 event_missing.LCALTA.16
2276 10:56:22.819414 # ok 315 event_spurious.LCALTA.16
2277 10:56:22.824514 # ok 316 get_value.LCALTA.15
2278 10:56:22.824957 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2279 10:56:22.830062 # ok 317 name.LCALTA.15
2280 10:56:22.830506 # ok 318 write_default.LCALTA.15
2281 10:56:22.835627 # ok 319 write_valid.LCALTA.15
2282 10:56:22.836095 # ok 320 write_invalid.LCALTA.15
2283 10:56:22.841156 # ok 321 event_missing.LCALTA.15
2284 10:56:22.841589 # ok 322 event_spurious.LCALTA.15
2285 10:56:22.846782 # ok 323 get_value.LCALTA.14
2286 10:56:22.847232 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2287 10:56:22.852339 # ok 324 name.LCALTA.14
2288 10:56:22.852782 # ok 325 write_default.LCALTA.14
2289 10:56:22.857901 # ok 326 write_valid.LCALTA.14
2290 10:56:22.858338 # ok 327 write_invalid.LCALTA.14
2291 10:56:22.863349 # ok 328 event_missing.LCALTA.14
2292 10:56:22.863786 # ok 329 event_spurious.LCALTA.14
2293 10:56:22.868991 # ok 330 get_value.LCALTA.13
2294 10:56:22.869474 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2295 10:56:22.874491 # ok 331 name.LCALTA.13
2296 10:56:22.874934 # ok 332 write_default.LCALTA.13
2297 10:56:22.880068 # ok 333 write_valid.LCALTA.13
2298 10:56:22.880517 # ok 334 write_invalid.LCALTA.13
2299 10:56:22.885531 # ok 335 event_missing.LCALTA.13
2300 10:56:22.885967 # ok 336 event_spurious.LCALTA.13
2301 10:56:22.891073 # ok 337 get_value.LCALTA.12
2302 10:56:22.891517 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2303 10:56:22.896646 # ok 338 name.LCALTA.12
2304 10:56:22.897092 # ok 339 write_default.LCALTA.12
2305 10:56:22.902203 # ok 340 write_valid.LCALTA.12
2306 10:56:22.902646 # ok 341 write_invalid.LCALTA.12
2307 10:56:22.907836 # ok 342 event_missing.LCALTA.12
2308 10:56:22.913336 # ok 343 event_spurious.LCALTA.12
2309 10:56:22.913864 # ok 344 get_value.LCALTA.11
2310 10:56:22.918917 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2311 10:56:22.919376 # ok 345 name.LCALTA.11
2312 10:56:22.919793 # ok 346 write_default.LCALTA.11
2313 10:56:22.924376 # ok 347 write_valid.LCALTA.11
2314 10:56:22.929970 # ok 348 write_invalid.LCALTA.11
2315 10:56:22.930417 # ok 349 event_missing.LCALTA.11
2316 10:56:22.935541 # ok 350 event_spurious.LCALTA.11
2317 10:56:22.936009 # ok 351 get_value.LCALTA.10
2318 10:56:22.940986 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2319 10:56:22.941436 # ok 352 name.LCALTA.10
2320 10:56:22.946645 # ok 353 write_default.LCALTA.10
2321 10:56:22.947092 # ok 354 write_valid.LCALTA.10
2322 10:56:22.952105 # ok 355 write_invalid.LCALTA.10
2323 10:56:22.952553 # ok 356 event_missing.LCALTA.10
2324 10:56:22.957771 # ok 357 event_spurious.LCALTA.10
2325 10:56:22.958268 # ok 358 get_value.LCALTA.9
2326 10:56:22.963178 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2327 10:56:22.963631 # ok 359 name.LCALTA.9
2328 10:56:22.968812 # ok 360 write_default.LCALTA.9
2329 10:56:22.969319 # ok 361 write_valid.LCALTA.9
2330 10:56:22.974282 # ok 362 write_invalid.LCALTA.9
2331 10:56:22.974731 # ok 363 event_missing.LCALTA.9
2332 10:56:22.979908 # ok 364 event_spurious.LCALTA.9
2333 10:56:22.980385 # ok 365 get_value.LCALTA.8
2334 10:56:22.985366 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2335 10:56:22.985811 # ok 366 name.LCALTA.8
2336 10:56:22.990984 # ok 367 write_default.LCALTA.8
2337 10:56:22.991433 # ok 368 write_valid.LCALTA.8
2338 10:56:22.996462 # ok 369 write_invalid.LCALTA.8
2339 10:56:22.996912 # ok 370 event_missing.LCALTA.8
2340 10:56:23.002018 # ok 371 event_spurious.LCALTA.8
2341 10:56:23.002461 # ok 372 get_value.LCALTA.7
2342 10:56:23.007557 # # LCALTA.7 ACODEC Unmute Ramp Switch
2343 10:56:23.008036 # ok 373 name.LCALTA.7
2344 10:56:23.013110 # ok 374 write_default.LCALTA.7
2345 10:56:23.013548 # ok 375 write_valid.LCALTA.7
2346 10:56:23.018659 # ok 376 write_invalid.LCALTA.7
2347 10:56:23.019101 # ok 377 event_missing.LCALTA.7
2348 10:56:23.024212 # ok 378 event_spurious.LCALTA.7
2349 10:56:23.024681 # ok 379 get_value.LCALTA.6
2350 10:56:23.029768 # # LCALTA.6 ACODEC Mute Ramp Switch
2351 10:56:23.030229 # ok 380 name.LCALTA.6
2352 10:56:23.035289 # ok 381 write_default.LCALTA.6
2353 10:56:23.035732 # ok 382 write_valid.LCALTA.6
2354 10:56:23.040926 # ok 383 write_invalid.LCALTA.6
2355 10:56:23.041362 # ok 384 event_missing.LCALTA.6
2356 10:56:23.046380 # ok 385 event_spurious.LCALTA.6
2357 10:56:23.046822 # ok 386 get_value.LCALTA.5
2358 10:56:23.051941 # # LCALTA.5 ACODEC Volume Ramp Switch
2359 10:56:23.052409 # ok 387 name.LCALTA.5
2360 10:56:23.057479 # ok 388 write_default.LCALTA.5
2361 10:56:23.057933 # ok 389 write_valid.LCALTA.5
2362 10:56:23.062995 # ok 390 write_invalid.LCALTA.5
2363 10:56:23.063439 # ok 391 event_missing.LCALTA.5
2364 10:56:23.068578 # ok 392 event_spurious.LCALTA.5
2365 10:56:23.069073 # ok 393 get_value.LCALTA.4
2366 10:56:23.074119 # # LCALTA.4 ACODEC Ramp Rate
2367 10:56:23.074562 # ok 394 name.LCALTA.4
2368 10:56:23.074972 # ok 395 write_default.LCALTA.4
2369 10:56:23.079668 # ok 396 write_valid.LCALTA.4
2370 10:56:23.080144 # ok 397 write_invalid.LCALTA.4
2371 10:56:23.085197 # ok 398 event_missing.LCALTA.4
2372 10:56:23.090788 # ok 399 event_spurious.LCALTA.4
2373 10:56:23.091231 # ok 400 get_value.LCALTA.3
2374 10:56:23.096311 # # LCALTA.3 ACODEC Playback Volume
2375 10:56:23.096756 # ok 401 name.LCALTA.3
2376 10:56:23.097167 # ok 402 write_default.LCALTA.3
2377 10:56:23.101937 # ok 403 write_valid.LCALTA.3
2378 10:56:23.102373 # ok 404 write_invalid.LCALTA.3
2379 10:56:23.107379 # ok 405 event_missing.LCALTA.3
2380 10:56:23.107820 # ok 406 event_spurious.LCALTA.3
2381 10:56:23.112978 # ok 407 get_value.LCALTA.2
2382 10:56:23.118450 # # LCALTA.2 ACODEC Playback Switch
2383 10:56:23.118896 # ok 408 name.LCALTA.2
2384 10:56:23.119301 # ok 409 write_default.LCALTA.2
2385 10:56:23.124040 # ok 410 write_valid.LCALTA.2
2386 10:56:23.124487 # ok 411 write_invalid.LCALTA.2
2387 10:56:23.129556 # ok 412 event_missing.LCALTA.2
2388 10:56:23.129992 # ok 413 event_spurious.LCALTA.2
2389 10:56:23.135129 # ok 414 get_value.LCALTA.1
2390 10:56:23.140674 # # LCALTA.1 ACODEC Playback Channel Mode
2391 10:56:23.141138 # ok 415 name.LCALTA.1
2392 10:56:23.141551 # ok 416 write_default.LCALTA.1
2393 10:56:23.146193 # ok 417 write_valid.LCALTA.1
2394 10:56:23.146642 # ok 418 write_invalid.LCALTA.1
2395 10:56:23.151763 # ok 419 event_missing.LCALTA.1
2396 10:56:23.157247 # ok 420 event_spurious.LCALTA.1
2397 10:56:23.157686 # ok 421 get_value.LCALTA.0
2398 10:56:23.162876 # # LCALTA.0 TOACODEC Lane Select
2399 10:56:23.163310 # ok 422 name.LCALTA.0
2400 10:56:23.163715 # ok 423 write_default.LCALTA.0
2401 10:56:23.168442 # ok 424 write_valid.LCALTA.0
2402 10:56:23.169008 # ok 425 write_invalid.LCALTA.0
2403 10:56:23.174003 # ok 426 event_missing.LCALTA.0
2404 10:56:23.174477 # ok 427 event_spurious.LCALTA.0
2405 10:56:23.179501 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2406 10:56:23.185047 ok 1 selftests: alsa: mixer-test
2407 10:56:23.185506 # timeout set to 45
2408 10:56:23.190602 # selftests: alsa: pcm-test
2409 10:56:23.191044 # TAP version 13
2410 10:56:23.196188 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2411 10:56:23.196685 # # LCALTA.0 - fe.dai-link-0 (*)
2412 10:56:23.201679 # # LCALTA.0 - fe.dai-link-1 (*)
2413 10:56:23.202184 # # LCALTA.0 - fe.dai-link-2 (*)
2414 10:56:23.207242 # # LCALTA.0 - fe.dai-link-3 (*)
2415 10:56:23.207705 # # LCALTA.0 - fe.dai-link-4 (*)
2416 10:56:23.212801 # # LCALTA.0 - fe.dai-link-5 (*)
2417 10:56:23.213267 # 1..42
2418 10:56:23.218304 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2419 10:56:23.223937 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2420 10:56:23.224418 # # snd_pcm_hw_params: Invalid argument
2421 10:56:23.229430 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2422 10:56:23.234988 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2423 10:56:23.240511 # # snd_pcm_hw_params: Invalid argument
2424 10:56:23.246030 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2425 10:56:23.251575 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2426 10:56:23.252055 # # snd_pcm_hw_params: Invalid argument
2427 10:56:23.257211 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2428 10:56:23.262750 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2429 10:56:23.268320 # # snd_pcm_hw_params: Invalid argument
2430 10:56:23.273847 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2431 10:56:23.274315 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2432 10:56:23.279485 # # snd_pcm_hw_params: Invalid argument
2433 10:56:23.284951 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2434 10:56:23.290443 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2435 10:56:23.296085 # # snd_pcm_hw_params: Invalid argument
2436 10:56:23.301574 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2437 10:56:23.302030 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2438 10:56:23.307201 # # snd_pcm_hw_params: Invalid argument
2439 10:56:23.312692 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2440 10:56:23.318225 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2441 10:56:23.318663 # # snd_pcm_hw_params: Invalid argument
2442 10:56:23.323727 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2443 10:56:23.329224 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2444 10:56:23.334769 # # snd_pcm_hw_params: Invalid argument
2445 10:56:23.340348 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2446 10:56:23.345997 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2447 10:56:23.346444 # # snd_pcm_hw_params: Invalid argument
2448 10:56:23.351529 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2449 10:56:23.357020 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2450 10:56:23.362617 # # snd_pcm_hw_params: Invalid argument
2451 10:56:23.368230 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2452 10:56:23.373639 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2453 10:56:23.374097 # # snd_pcm_hw_params: Invalid argument
2454 10:56:23.379265 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2455 10:56:23.384756 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2456 10:56:23.390365 # # snd_pcm_hw_params: Invalid argument
2457 10:56:23.395859 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2458 10:56:23.401403 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2459 10:56:23.401844 # # snd_pcm_hw_params: Invalid argument
2460 10:56:23.406996 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2461 10:56:23.412523 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2462 10:56:23.418077 # # snd_pcm_hw_params: Invalid argument
2463 10:56:23.423571 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2464 10:56:23.424043 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2465 10:56:23.429064 # # snd_pcm_hw_params: Invalid argument
2466 10:56:23.434637 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2467 10:56:23.440284 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2468 10:56:23.445772 # # snd_pcm_hw_params: Invalid argument
2469 10:56:23.451373 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2470 10:56:23.451813 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2471 10:56:23.456869 # # snd_pcm_hw_params: Invalid argument
2472 10:56:23.462348 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2473 10:56:23.467943 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2474 10:56:23.468407 # # snd_pcm_hw_params: Invalid argument
2475 10:56:23.479141 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2476 10:56:23.479616 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2477 10:56:23.484658 # # snd_pcm_hw_params: Invalid argument
2478 10:56:23.490152 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2479 10:56:23.495707 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2480 10:56:23.496181 # # snd_pcm_hw_params: Invalid argument
2481 10:56:23.501294 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2482 10:56:23.506736 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2483 10:56:23.512412 # # snd_pcm_hw_params: Invalid argument
2484 10:56:23.517815 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2485 10:56:23.523394 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2486 10:56:23.523832 # # snd_pcm_hw_params: Invalid argument
2487 10:56:23.528930 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2488 10:56:23.534476 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2489 10:56:23.540016 # # snd_pcm_hw_params: Invalid argument
2490 10:56:23.545587 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2491 10:56:23.551125 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2492 10:56:23.551569 # # snd_pcm_hw_params: Invalid argument
2493 10:56:23.556681 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2494 10:56:23.562206 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2495 10:56:23.567786 # # snd_pcm_hw_params: Invalid argument
2496 10:56:23.573328 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2497 10:56:23.578864 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2498 10:56:23.579315 # # snd_pcm_hw_params: Invalid argument
2499 10:56:23.584403 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2500 10:56:23.589987 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2501 10:56:23.595504 # # snd_pcm_hw_params: Invalid argument
2502 10:56:23.601029 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2503 10:56:23.606611 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2504 10:56:23.607046 # # snd_pcm_hw_params: Invalid argument
2505 10:56:23.612193 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2506 10:56:23.617679 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2507 10:56:23.623397 # # snd_pcm_hw_params: Invalid argument
2508 10:56:23.628908 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2509 10:56:23.634385 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2510 10:56:23.634827 # # snd_pcm_hw_params: Invalid argument
2511 10:56:23.639947 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2512 10:56:23.645412 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2513 10:56:23.651160 # # snd_pcm_hw_params: Invalid argument
2514 10:56:23.656537 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2515 10:56:23.662156 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2516 10:56:23.662600 # # snd_pcm_hw_params: Invalid argument
2517 10:56:23.667671 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2518 10:56:23.673238 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2519 10:56:23.678686 # # snd_pcm_hw_params: Invalid argument
2520 10:56:23.684259 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2521 10:56:23.689800 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2522 10:56:23.690292 # # snd_pcm_hw_params: Invalid argument
2523 10:56:23.695320 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2524 10:56:23.700985 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2525 10:56:23.706452 # # snd_pcm_hw_params: Invalid argument
2526 10:56:23.712026 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2527 10:56:23.712477 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2528 10:56:23.717562 # # snd_pcm_hw_params: Invalid argument
2529 10:56:23.723080 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2530 10:56:23.728616 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2531 10:56:23.734158 # # snd_pcm_hw_params: Invalid argument
2532 10:56:23.739704 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2533 10:56:23.740179 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2534 10:56:23.745264 # # snd_pcm_hw_params: Invalid argument
2535 10:56:23.750794 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2536 10:56:23.756351 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2537 10:56:23.761969 # # snd_pcm_hw_params: Invalid argument
2538 10:56:23.767417 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2539 10:56:23.767855 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2540 10:56:23.773017 # # snd_pcm_hw_params: Invalid argument
2541 10:56:23.778534 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2542 10:56:23.784070 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2543 10:56:23.789631 # # snd_pcm_hw_params: Invalid argument
2544 10:56:23.795168 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2545 10:56:23.795602 ok 2 selftests: alsa: pcm-test
2546 10:56:23.796041 # timeout set to 45
2547 10:56:23.800691 # selftests: alsa: test-pcmtest-driver
2548 10:56:23.801132 # TAP version 13
2549 10:56:23.801546 # 1..5
2550 10:56:23.806266 # # Starting 5 tests from 1 test cases.
2551 10:56:23.811876 # # RUN pcmtest.playback ...
2552 10:56:23.817368 # # SKIP Can't read patterns. Probably, module isn't loaded
2553 10:56:23.817804 # # OK pcmtest.playback
2554 10:56:23.828457 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2555 10:56:23.828929 # # RUN pcmtest.capture ...
2556 10:56:23.834019 # # SKIP Can't read patterns. Probably, module isn't loaded
2557 10:56:23.839587 # # OK pcmtest.capture
2558 10:56:23.845149 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2559 10:56:23.850686 # # RUN pcmtest.ni_capture ...
2560 10:56:23.856232 # # SKIP Can't read patterns. Probably, module isn't loaded
2561 10:56:23.861863 # # OK pcmtest.ni_capture
2562 10:56:23.867441 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2563 10:56:23.872924 # # RUN pcmtest.ni_playback ...
2564 10:56:23.878418 # # SKIP Can't read patterns. Probably, module isn't loaded
2565 10:56:23.878948 # # OK pcmtest.ni_playback
2566 10:56:23.889525 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2567 10:56:23.890182 # # RUN pcmtest.reset_ioctl ...
2568 10:56:23.895107 # # SKIP Can't read patterns. Probably, module isn't loaded
2569 10:56:23.900617 # # OK pcmtest.reset_ioctl
2570 10:56:23.906141 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2571 10:56:23.911704 # # PASSED: 5 / 5 tests passed.
2572 10:56:23.917208 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2573 10:56:23.922815 ok 3 selftests: alsa: test-pcmtest-driver
2574 10:56:23.923315 # timeout set to 45
2575 10:56:23.923735 # selftests: alsa: utimer-test
2576 10:56:23.928371 # TAP version 13
2577 10:56:23.928885 # 1..2
2578 10:56:23.929306 # # Starting 2 tests from 2 test cases.
2579 10:56:23.933901 # # RUN global.wrong_timers_test ...
2580 10:56:23.939392 # # OK global.wrong_timers_test
2581 10:56:23.939836 # ok 1 global.wrong_timers_test
2582 10:56:23.945069 # # RUN timer_f.utimer ...
2583 10:56:23.955969 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2584 10:56:23.961520 # # utimer: Test terminated by assertion
2585 10:56:23.961959 # # FAIL timer_f.utimer
2586 10:56:23.962367 # not ok 2 timer_f.utimer
2587 10:56:23.967130 # # FAILED: 1 / 2 tests passed.
2588 10:56:23.972852 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2589 10:56:23.976734 not ok 4 selftests: alsa: utimer-test # exit=1
2590 10:56:24.472421 alsa_mixer-test_get_value_LCALTA_60 pass
2591 10:56:24.477796 alsa_mixer-test_name_LCALTA_60 pass
2592 10:56:24.478294 alsa_mixer-test_write_default_LCALTA_60 pass
2593 10:56:24.483278 alsa_mixer-test_write_valid_LCALTA_60 pass
2594 10:56:24.488895 alsa_mixer-test_write_invalid_LCALTA_60 pass
2595 10:56:24.494417 alsa_mixer-test_event_missing_LCALTA_60 pass
2596 10:56:24.494874 alsa_mixer-test_event_spurious_LCALTA_60 pass
2597 10:56:24.500037 alsa_mixer-test_get_value_LCALTA_59 pass
2598 10:56:24.505458 alsa_mixer-test_name_LCALTA_59 pass
2599 10:56:24.505915 alsa_mixer-test_write_default_LCALTA_59 pass
2600 10:56:24.511058 alsa_mixer-test_write_valid_LCALTA_59 pass
2601 10:56:24.516525 alsa_mixer-test_write_invalid_LCALTA_59 pass
2602 10:56:24.516971 alsa_mixer-test_event_missing_LCALTA_59 pass
2603 10:56:24.522064 alsa_mixer-test_event_spurious_LCALTA_59 pass
2604 10:56:24.527613 alsa_mixer-test_get_value_LCALTA_58 pass
2605 10:56:24.528115 alsa_mixer-test_name_LCALTA_58 pass
2606 10:56:24.533174 alsa_mixer-test_write_default_LCALTA_58 pass
2607 10:56:24.538731 alsa_mixer-test_write_valid_LCALTA_58 pass
2608 10:56:24.539173 alsa_mixer-test_write_invalid_LCALTA_58 pass
2609 10:56:24.544273 alsa_mixer-test_event_missing_LCALTA_58 pass
2610 10:56:24.549823 alsa_mixer-test_event_spurious_LCALTA_58 pass
2611 10:56:24.555342 alsa_mixer-test_get_value_LCALTA_57 pass
2612 10:56:24.555782 alsa_mixer-test_name_LCALTA_57 pass
2613 10:56:24.560989 alsa_mixer-test_write_default_LCALTA_57 pass
2614 10:56:24.566486 alsa_mixer-test_write_valid_LCALTA_57 pass
2615 10:56:24.566926 alsa_mixer-test_write_invalid_LCALTA_57 pass
2616 10:56:24.572105 alsa_mixer-test_event_missing_LCALTA_57 pass
2617 10:56:24.577598 alsa_mixer-test_event_spurious_LCALTA_57 pass
2618 10:56:24.578088 alsa_mixer-test_get_value_LCALTA_56 pass
2619 10:56:24.583109 alsa_mixer-test_name_LCALTA_56 pass
2620 10:56:24.588670 alsa_mixer-test_write_default_LCALTA_56 pass
2621 10:56:24.589116 alsa_mixer-test_write_valid_LCALTA_56 pass
2622 10:56:24.594226 alsa_mixer-test_write_invalid_LCALTA_56 pass
2623 10:56:24.599761 alsa_mixer-test_event_missing_LCALTA_56 pass
2624 10:56:24.605308 alsa_mixer-test_event_spurious_LCALTA_56 pass
2625 10:56:24.605762 alsa_mixer-test_get_value_LCALTA_55 pass
2626 10:56:24.610912 alsa_mixer-test_name_LCALTA_55 pass
2627 10:56:24.616397 alsa_mixer-test_write_default_LCALTA_55 pass
2628 10:56:24.616856 alsa_mixer-test_write_valid_LCALTA_55 pass
2629 10:56:24.621993 alsa_mixer-test_write_invalid_LCALTA_55 pass
2630 10:56:24.627497 alsa_mixer-test_event_missing_LCALTA_55 pass
2631 10:56:24.627947 alsa_mixer-test_event_spurious_LCALTA_55 pass
2632 10:56:24.633117 alsa_mixer-test_get_value_LCALTA_54 pass
2633 10:56:24.638574 alsa_mixer-test_name_LCALTA_54 pass
2634 10:56:24.639018 alsa_mixer-test_write_default_LCALTA_54 pass
2635 10:56:24.644211 alsa_mixer-test_write_valid_LCALTA_54 pass
2636 10:56:24.649676 alsa_mixer-test_write_invalid_LCALTA_54 pass
2637 10:56:24.650120 alsa_mixer-test_event_missing_LCALTA_54 pass
2638 10:56:24.655233 alsa_mixer-test_event_spurious_LCALTA_54 pass
2639 10:56:24.660772 alsa_mixer-test_get_value_LCALTA_53 pass
2640 10:56:24.661215 alsa_mixer-test_name_LCALTA_53 pass
2641 10:56:24.666310 alsa_mixer-test_write_default_LCALTA_53 pass
2642 10:56:24.671866 alsa_mixer-test_write_valid_LCALTA_53 pass
2643 10:56:24.677462 alsa_mixer-test_write_invalid_LCALTA_53 pass
2644 10:56:24.677957 alsa_mixer-test_event_missing_LCALTA_53 pass
2645 10:56:24.683000 alsa_mixer-test_event_spurious_LCALTA_53 pass
2646 10:56:24.688505 alsa_mixer-test_get_value_LCALTA_52 pass
2647 10:56:24.688946 alsa_mixer-test_name_LCALTA_52 pass
2648 10:56:24.694146 alsa_mixer-test_write_default_LCALTA_52 pass
2649 10:56:24.699609 alsa_mixer-test_write_valid_LCALTA_52 pass
2650 10:56:24.700088 alsa_mixer-test_write_invalid_LCALTA_52 pass
2651 10:56:24.705179 alsa_mixer-test_event_missing_LCALTA_52 pass
2652 10:56:24.710677 alsa_mixer-test_event_spurious_LCALTA_52 pass
2653 10:56:24.711132 alsa_mixer-test_get_value_LCALTA_51 pass
2654 10:56:24.716240 alsa_mixer-test_name_LCALTA_51 pass
2655 10:56:24.721766 alsa_mixer-test_write_default_LCALTA_51 pass
2656 10:56:24.722210 alsa_mixer-test_write_valid_LCALTA_51 pass
2657 10:56:24.727324 alsa_mixer-test_write_invalid_LCALTA_51 pass
2658 10:56:24.732890 alsa_mixer-test_event_missing_LCALTA_51 pass
2659 10:56:24.738422 alsa_mixer-test_event_spurious_LCALTA_51 pass
2660 10:56:24.738866 alsa_mixer-test_get_value_LCALTA_50 pass
2661 10:56:24.744026 alsa_mixer-test_name_LCALTA_50 pass
2662 10:56:24.749513 alsa_mixer-test_write_default_LCALTA_50 pass
2663 10:56:24.749959 alsa_mixer-test_write_valid_LCALTA_50 pass
2664 10:56:24.755146 alsa_mixer-test_write_invalid_LCALTA_50 pass
2665 10:56:24.760626 alsa_mixer-test_event_missing_LCALTA_50 pass
2666 10:56:24.761083 alsa_mixer-test_event_spurious_LCALTA_50 pass
2667 10:56:24.766159 alsa_mixer-test_get_value_LCALTA_49 pass
2668 10:56:24.771658 alsa_mixer-test_name_LCALTA_49 pass
2669 10:56:24.772125 alsa_mixer-test_write_default_LCALTA_49 pass
2670 10:56:24.777284 alsa_mixer-test_write_valid_LCALTA_49 pass
2671 10:56:24.782794 alsa_mixer-test_write_invalid_LCALTA_49 pass
2672 10:56:24.788344 alsa_mixer-test_event_missing_LCALTA_49 pass
2673 10:56:24.788789 alsa_mixer-test_event_spurious_LCALTA_49 pass
2674 10:56:24.793928 alsa_mixer-test_get_value_LCALTA_48 pass
2675 10:56:24.794424 alsa_mixer-test_name_LCALTA_48 pass
2676 10:56:24.799432 alsa_mixer-test_write_default_LCALTA_48 pass
2677 10:56:24.805014 alsa_mixer-test_write_valid_LCALTA_48 pass
2678 10:56:24.810525 alsa_mixer-test_write_invalid_LCALTA_48 pass
2679 10:56:24.810967 alsa_mixer-test_event_missing_LCALTA_48 pass
2680 10:56:24.816189 alsa_mixer-test_event_spurious_LCALTA_48 pass
2681 10:56:24.821618 alsa_mixer-test_get_value_LCALTA_47 pass
2682 10:56:24.822056 alsa_mixer-test_name_LCALTA_47 pass
2683 10:56:24.827210 alsa_mixer-test_write_default_LCALTA_47 pass
2684 10:56:24.832716 alsa_mixer-test_write_valid_LCALTA_47 pass
2685 10:56:24.833166 alsa_mixer-test_write_invalid_LCALTA_47 pass
2686 10:56:24.838271 alsa_mixer-test_event_missing_LCALTA_47 pass
2687 10:56:24.843809 alsa_mixer-test_event_spurious_LCALTA_47 pass
2688 10:56:24.849360 alsa_mixer-test_get_value_LCALTA_46 pass
2689 10:56:24.849803 alsa_mixer-test_name_LCALTA_46 pass
2690 10:56:24.854881 alsa_mixer-test_write_default_LCALTA_46 pass
2691 10:56:24.860452 alsa_mixer-test_write_valid_LCALTA_46 pass
2692 10:56:24.860889 alsa_mixer-test_write_invalid_LCALTA_46 pass
2693 10:56:24.866019 alsa_mixer-test_event_missing_LCALTA_46 pass
2694 10:56:24.871539 alsa_mixer-test_event_spurious_LCALTA_46 pass
2695 10:56:24.871976 alsa_mixer-test_get_value_LCALTA_45 pass
2696 10:56:24.877197 alsa_mixer-test_name_LCALTA_45 pass
2697 10:56:24.882644 alsa_mixer-test_write_default_LCALTA_45 pass
2698 10:56:24.883119 alsa_mixer-test_write_valid_LCALTA_45 pass
2699 10:56:24.888214 alsa_mixer-test_write_invalid_LCALTA_45 pass
2700 10:56:24.893729 alsa_mixer-test_event_missing_LCALTA_45 pass
2701 10:56:24.894171 alsa_mixer-test_event_spurious_LCALTA_45 pass
2702 10:56:24.899268 alsa_mixer-test_get_value_LCALTA_44 pass
2703 10:56:24.904804 alsa_mixer-test_name_LCALTA_44 pass
2704 10:56:24.905242 alsa_mixer-test_write_default_LCALTA_44 pass
2705 10:56:24.910344 alsa_mixer-test_write_valid_LCALTA_44 pass
2706 10:56:24.915957 alsa_mixer-test_write_invalid_LCALTA_44 pass
2707 10:56:24.921489 alsa_mixer-test_event_missing_LCALTA_44 pass
2708 10:56:24.921984 alsa_mixer-test_event_spurious_LCALTA_44 pass
2709 10:56:24.927038 alsa_mixer-test_get_value_LCALTA_43 pass
2710 10:56:24.932559 alsa_mixer-test_name_LCALTA_43 pass
2711 10:56:24.933010 alsa_mixer-test_write_default_LCALTA_43 pass
2712 10:56:24.938176 alsa_mixer-test_write_valid_LCALTA_43 pass
2713 10:56:24.943642 alsa_mixer-test_write_invalid_LCALTA_43 pass
2714 10:56:24.944116 alsa_mixer-test_event_missing_LCALTA_43 pass
2715 10:56:24.949206 alsa_mixer-test_event_spurious_LCALTA_43 pass
2716 10:56:24.954787 alsa_mixer-test_get_value_LCALTA_42 pass
2717 10:56:24.955325 alsa_mixer-test_name_LCALTA_42 pass
2718 10:56:24.960279 alsa_mixer-test_write_default_LCALTA_42 pass
2719 10:56:24.965828 alsa_mixer-test_write_valid_LCALTA_42 pass
2720 10:56:24.966265 alsa_mixer-test_write_invalid_LCALTA_42 pass
2721 10:56:24.971390 alsa_mixer-test_event_missing_LCALTA_42 pass
2722 10:56:24.976951 alsa_mixer-test_event_spurious_LCALTA_42 pass
2723 10:56:24.982503 alsa_mixer-test_get_value_LCALTA_41 pass
2724 10:56:24.983008 alsa_mixer-test_name_LCALTA_41 pass
2725 10:56:24.988063 alsa_mixer-test_write_default_LCALTA_41 pass
2726 10:56:24.993571 alsa_mixer-test_write_valid_LCALTA_41 pass
2727 10:56:24.994014 alsa_mixer-test_write_invalid_LCALTA_41 pass
2728 10:56:24.999157 alsa_mixer-test_event_missing_LCALTA_41 pass
2729 10:56:25.004667 alsa_mixer-test_event_spurious_LCALTA_41 pass
2730 10:56:25.005126 alsa_mixer-test_get_value_LCALTA_40 pass
2731 10:56:25.010226 alsa_mixer-test_name_LCALTA_40 pass
2732 10:56:25.015761 alsa_mixer-test_write_default_LCALTA_40 pass
2733 10:56:25.016249 alsa_mixer-test_write_valid_LCALTA_40 pass
2734 10:56:25.021297 alsa_mixer-test_write_invalid_LCALTA_40 pass
2735 10:56:25.026854 alsa_mixer-test_event_missing_LCALTA_40 pass
2736 10:56:25.032405 alsa_mixer-test_event_spurious_LCALTA_40 pass
2737 10:56:25.032844 alsa_mixer-test_get_value_LCALTA_39 pass
2738 10:56:25.037938 alsa_mixer-test_name_LCALTA_39 pass
2739 10:56:25.043478 alsa_mixer-test_write_default_LCALTA_39 pass
2740 10:56:25.043913 alsa_mixer-test_write_valid_LCALTA_39 pass
2741 10:56:25.049021 alsa_mixer-test_write_invalid_LCALTA_39 pass
2742 10:56:25.054565 alsa_mixer-test_event_missing_LCALTA_39 pass
2743 10:56:25.055003 alsa_mixer-test_event_spurious_LCALTA_39 pass
2744 10:56:25.060192 alsa_mixer-test_get_value_LCALTA_38 pass
2745 10:56:25.065657 alsa_mixer-test_name_LCALTA_38 pass
2746 10:56:25.066093 alsa_mixer-test_write_default_LCALTA_38 pass
2747 10:56:25.071213 alsa_mixer-test_write_valid_LCALTA_38 pass
2748 10:56:25.076799 alsa_mixer-test_write_invalid_LCALTA_38 pass
2749 10:56:25.077314 alsa_mixer-test_event_missing_LCALTA_38 pass
2750 10:56:25.082312 alsa_mixer-test_event_spurious_LCALTA_38 pass
2751 10:56:25.087840 alsa_mixer-test_get_value_LCALTA_37 pass
2752 10:56:25.088335 alsa_mixer-test_name_LCALTA_37 pass
2753 10:56:25.093411 alsa_mixer-test_write_default_LCALTA_37 pass
2754 10:56:25.098921 alsa_mixer-test_write_valid_LCALTA_37 pass
2755 10:56:25.104475 alsa_mixer-test_write_invalid_LCALTA_37 pass
2756 10:56:25.104924 alsa_mixer-test_event_missing_LCALTA_37 pass
2757 10:56:25.110043 alsa_mixer-test_event_spurious_LCALTA_37 pass
2758 10:56:25.115589 alsa_mixer-test_get_value_LCALTA_36 pass
2759 10:56:25.116067 alsa_mixer-test_name_LCALTA_36 pass
2760 10:56:25.121169 alsa_mixer-test_write_default_LCALTA_36 pass
2761 10:56:25.126682 alsa_mixer-test_write_valid_LCALTA_36 pass
2762 10:56:25.127140 alsa_mixer-test_write_invalid_LCALTA_36 pass
2763 10:56:25.132229 alsa_mixer-test_event_missing_LCALTA_36 pass
2764 10:56:25.137776 alsa_mixer-test_event_spurious_LCALTA_36 pass
2765 10:56:25.138217 alsa_mixer-test_get_value_LCALTA_35 pass
2766 10:56:25.143322 alsa_mixer-test_name_LCALTA_35 pass
2767 10:56:25.148857 alsa_mixer-test_write_default_LCALTA_35 pass
2768 10:56:25.149314 alsa_mixer-test_write_valid_LCALTA_35 pass
2769 10:56:25.154431 alsa_mixer-test_write_invalid_LCALTA_35 pass
2770 10:56:25.159967 alsa_mixer-test_event_missing_LCALTA_35 pass
2771 10:56:25.165559 alsa_mixer-test_event_spurious_LCALTA_35 pass
2772 10:56:25.166090 alsa_mixer-test_get_value_LCALTA_34 pass
2773 10:56:25.171048 alsa_mixer-test_name_LCALTA_34 pass
2774 10:56:25.176630 alsa_mixer-test_write_default_LCALTA_34 pass
2775 10:56:25.177132 alsa_mixer-test_write_valid_LCALTA_34 pass
2776 10:56:25.182219 alsa_mixer-test_write_invalid_LCALTA_34 pass
2777 10:56:25.187697 alsa_mixer-test_event_missing_LCALTA_34 pass
2778 10:56:25.188192 alsa_mixer-test_event_spurious_LCALTA_34 pass
2779 10:56:25.193246 alsa_mixer-test_get_value_LCALTA_33 pass
2780 10:56:25.198798 alsa_mixer-test_name_LCALTA_33 pass
2781 10:56:25.199260 alsa_mixer-test_write_default_LCALTA_33 pass
2782 10:56:25.204304 alsa_mixer-test_write_valid_LCALTA_33 pass
2783 10:56:25.209889 alsa_mixer-test_write_invalid_LCALTA_33 pass
2784 10:56:25.215422 alsa_mixer-test_event_missing_LCALTA_33 pass
2785 10:56:25.215879 alsa_mixer-test_event_spurious_LCALTA_33 pass
2786 10:56:25.221011 alsa_mixer-test_get_value_LCALTA_32 pass
2787 10:56:25.221536 alsa_mixer-test_name_LCALTA_32 pass
2788 10:56:25.226516 alsa_mixer-test_write_default_LCALTA_32 pass
2789 10:56:25.232071 alsa_mixer-test_write_valid_LCALTA_32 pass
2790 10:56:25.237700 alsa_mixer-test_write_invalid_LCALTA_32 pass
2791 10:56:25.238136 alsa_mixer-test_event_missing_LCALTA_32 pass
2792 10:56:25.243231 alsa_mixer-test_event_spurious_LCALTA_32 pass
2793 10:56:25.248778 alsa_mixer-test_get_value_LCALTA_31 pass
2794 10:56:25.249235 alsa_mixer-test_name_LCALTA_31 pass
2795 10:56:25.254310 alsa_mixer-test_write_default_LCALTA_31 pass
2796 10:56:25.259840 alsa_mixer-test_write_valid_LCALTA_31 pass
2797 10:56:25.260314 alsa_mixer-test_write_invalid_LCALTA_31 pass
2798 10:56:25.265402 alsa_mixer-test_event_missing_LCALTA_31 pass
2799 10:56:25.270939 alsa_mixer-test_event_spurious_LCALTA_31 pass
2800 10:56:25.276500 alsa_mixer-test_get_value_LCALTA_30 pass
2801 10:56:25.276943 alsa_mixer-test_name_LCALTA_30 pass
2802 10:56:25.282057 alsa_mixer-test_write_default_LCALTA_30 pass
2803 10:56:25.287583 alsa_mixer-test_write_valid_LCALTA_30 pass
2804 10:56:25.288088 alsa_mixer-test_write_invalid_LCALTA_30 pass
2805 10:56:25.293099 alsa_mixer-test_event_missing_LCALTA_30 pass
2806 10:56:25.298689 alsa_mixer-test_event_spurious_LCALTA_30 pass
2807 10:56:25.299134 alsa_mixer-test_get_value_LCALTA_29 pass
2808 10:56:25.304255 alsa_mixer-test_name_LCALTA_29 pass
2809 10:56:25.309787 alsa_mixer-test_write_default_LCALTA_29 pass
2810 10:56:25.310233 alsa_mixer-test_write_valid_LCALTA_29 pass
2811 10:56:25.315382 alsa_mixer-test_write_invalid_LCALTA_29 pass
2812 10:56:25.320869 alsa_mixer-test_event_missing_LCALTA_29 pass
2813 10:56:25.321325 alsa_mixer-test_event_spurious_LCALTA_29 pass
2814 10:56:25.326387 alsa_mixer-test_get_value_LCALTA_28 pass
2815 10:56:25.331927 alsa_mixer-test_name_LCALTA_28 pass
2816 10:56:25.332396 alsa_mixer-test_write_default_LCALTA_28 pass
2817 10:56:25.337510 alsa_mixer-test_write_valid_LCALTA_28 pass
2818 10:56:25.343045 alsa_mixer-test_write_invalid_LCALTA_28 pass
2819 10:56:25.348633 alsa_mixer-test_event_missing_LCALTA_28 pass
2820 10:56:25.349123 alsa_mixer-test_event_spurious_LCALTA_28 pass
2821 10:56:25.354262 alsa_mixer-test_get_value_LCALTA_27 pass
2822 10:56:25.359653 alsa_mixer-test_name_LCALTA_27 pass
2823 10:56:25.360140 alsa_mixer-test_write_default_LCALTA_27 pass
2824 10:56:25.365218 alsa_mixer-test_write_valid_LCALTA_27 pass
2825 10:56:25.370774 alsa_mixer-test_write_invalid_LCALTA_27 pass
2826 10:56:25.371248 alsa_mixer-test_event_missing_LCALTA_27 pass
2827 10:56:25.376284 alsa_mixer-test_event_spurious_LCALTA_27 pass
2828 10:56:25.381845 alsa_mixer-test_get_value_LCALTA_26 pass
2829 10:56:25.382285 alsa_mixer-test_name_LCALTA_26 pass
2830 10:56:25.387387 alsa_mixer-test_write_default_LCALTA_26 skip
2831 10:56:25.392959 alsa_mixer-test_write_valid_LCALTA_26 skip
2832 10:56:25.393453 alsa_mixer-test_write_invalid_LCALTA_26 skip
2833 10:56:25.398479 alsa_mixer-test_event_missing_LCALTA_26 pass
2834 10:56:25.404090 alsa_mixer-test_event_spurious_LCALTA_26 pass
2835 10:56:25.409588 alsa_mixer-test_get_value_LCALTA_25 pass
2836 10:56:25.410033 alsa_mixer-test_name_LCALTA_25 pass
2837 10:56:25.415217 alsa_mixer-test_write_default_LCALTA_25 pass
2838 10:56:25.420634 alsa_mixer-test_write_valid_LCALTA_25 skip
2839 10:56:25.421075 alsa_mixer-test_write_invalid_LCALTA_25 skip
2840 10:56:25.426226 alsa_mixer-test_event_missing_LCALTA_25 pass
2841 10:56:25.431755 alsa_mixer-test_event_spurious_LCALTA_25 pass
2842 10:56:25.432220 alsa_mixer-test_get_value_LCALTA_24 pass
2843 10:56:25.437293 alsa_mixer-test_name_LCALTA_24 pass
2844 10:56:25.442850 alsa_mixer-test_write_default_LCALTA_24 skip
2845 10:56:25.443284 alsa_mixer-test_write_valid_LCALTA_24 skip
2846 10:56:25.448413 alsa_mixer-test_write_invalid_LCALTA_24 skip
2847 10:56:25.453933 alsa_mixer-test_event_missing_LCALTA_24 pass
2848 10:56:25.459493 alsa_mixer-test_event_spurious_LCALTA_24 pass
2849 10:56:25.459933 alsa_mixer-test_get_value_LCALTA_23 pass
2850 10:56:25.465096 alsa_mixer-test_name_LCALTA_23 pass
2851 10:56:25.470612 alsa_mixer-test_write_default_LCALTA_23 skip
2852 10:56:25.471044 alsa_mixer-test_write_valid_LCALTA_23 skip
2853 10:56:25.476246 alsa_mixer-test_write_invalid_LCALTA_23 skip
2854 10:56:25.481697 alsa_mixer-test_event_missing_LCALTA_23 pass
2855 10:56:25.482145 alsa_mixer-test_event_spurious_LCALTA_23 pass
2856 10:56:25.487247 alsa_mixer-test_get_value_LCALTA_22 pass
2857 10:56:25.492794 alsa_mixer-test_name_LCALTA_22 pass
2858 10:56:25.493257 alsa_mixer-test_write_default_LCALTA_22 pass
2859 10:56:25.498311 alsa_mixer-test_write_valid_LCALTA_22 pass
2860 10:56:25.503882 alsa_mixer-test_write_invalid_LCALTA_22 pass
2861 10:56:25.504357 alsa_mixer-test_event_missing_LCALTA_22 pass
2862 10:56:25.509408 alsa_mixer-test_event_spurious_LCALTA_22 pass
2863 10:56:25.514964 alsa_mixer-test_get_value_LCALTA_21 pass
2864 10:56:25.515424 alsa_mixer-test_name_LCALTA_21 pass
2865 10:56:25.520495 alsa_mixer-test_write_default_LCALTA_21 pass
2866 10:56:25.526120 alsa_mixer-test_write_valid_LCALTA_21 pass
2867 10:56:25.531610 alsa_mixer-test_write_invalid_LCALTA_21 pass
2868 10:56:25.532085 alsa_mixer-test_event_missing_LCALTA_21 pass
2869 10:56:25.537252 alsa_mixer-test_event_spurious_LCALTA_21 pass
2870 10:56:25.542698 alsa_mixer-test_get_value_LCALTA_20 pass
2871 10:56:25.543146 alsa_mixer-test_name_LCALTA_20 pass
2872 10:56:25.548245 alsa_mixer-test_write_default_LCALTA_20 pass
2873 10:56:25.553847 alsa_mixer-test_write_valid_LCALTA_20 pass
2874 10:56:25.554296 alsa_mixer-test_write_invalid_LCALTA_20 pass
2875 10:56:25.559347 alsa_mixer-test_event_missing_LCALTA_20 pass
2876 10:56:25.564878 alsa_mixer-test_event_spurious_LCALTA_20 pass
2877 10:56:25.565337 alsa_mixer-test_get_value_LCALTA_19 pass
2878 10:56:25.570453 alsa_mixer-test_name_LCALTA_19 pass
2879 10:56:25.575972 alsa_mixer-test_write_default_LCALTA_19 pass
2880 10:56:25.576470 alsa_mixer-test_write_valid_LCALTA_19 pass
2881 10:56:25.581519 alsa_mixer-test_write_invalid_LCALTA_19 pass
2882 10:56:25.587132 alsa_mixer-test_event_missing_LCALTA_19 pass
2883 10:56:25.592619 alsa_mixer-test_event_spurious_LCALTA_19 pass
2884 10:56:25.593099 alsa_mixer-test_get_value_LCALTA_18 pass
2885 10:56:25.598264 alsa_mixer-test_name_LCALTA_18 pass
2886 10:56:25.603705 alsa_mixer-test_write_default_LCALTA_18 pass
2887 10:56:25.604188 alsa_mixer-test_write_valid_LCALTA_18 pass
2888 10:56:25.609246 alsa_mixer-test_write_invalid_LCALTA_18 pass
2889 10:56:25.614820 alsa_mixer-test_event_missing_LCALTA_18 pass
2890 10:56:25.615300 alsa_mixer-test_event_spurious_LCALTA_18 pass
2891 10:56:25.620344 alsa_mixer-test_get_value_LCALTA_17 pass
2892 10:56:25.625887 alsa_mixer-test_name_LCALTA_17 pass
2893 10:56:25.626331 alsa_mixer-test_write_default_LCALTA_17 pass
2894 10:56:25.631443 alsa_mixer-test_write_valid_LCALTA_17 pass
2895 10:56:25.636998 alsa_mixer-test_write_invalid_LCALTA_17 pass
2896 10:56:25.642532 alsa_mixer-test_event_missing_LCALTA_17 pass
2897 10:56:25.642976 alsa_mixer-test_event_spurious_LCALTA_17 pass
2898 10:56:25.648167 alsa_mixer-test_get_value_LCALTA_16 pass
2899 10:56:25.648611 alsa_mixer-test_name_LCALTA_16 pass
2900 10:56:25.653659 alsa_mixer-test_write_default_LCALTA_16 pass
2901 10:56:25.659250 alsa_mixer-test_write_valid_LCALTA_16 pass
2902 10:56:25.664740 alsa_mixer-test_write_invalid_LCALTA_16 pass
2903 10:56:25.665222 alsa_mixer-test_event_missing_LCALTA_16 pass
2904 10:56:25.670272 alsa_mixer-test_event_spurious_LCALTA_16 pass
2905 10:56:25.675839 alsa_mixer-test_get_value_LCALTA_15 pass
2906 10:56:25.676333 alsa_mixer-test_name_LCALTA_15 pass
2907 10:56:25.681414 alsa_mixer-test_write_default_LCALTA_15 pass
2908 10:56:25.686941 alsa_mixer-test_write_valid_LCALTA_15 pass
2909 10:56:25.687432 alsa_mixer-test_write_invalid_LCALTA_15 pass
2910 10:56:25.692450 alsa_mixer-test_event_missing_LCALTA_15 pass
2911 10:56:25.698025 alsa_mixer-test_event_spurious_LCALTA_15 pass
2912 10:56:25.703550 alsa_mixer-test_get_value_LCALTA_14 pass
2913 10:56:25.703976 alsa_mixer-test_name_LCALTA_14 pass
2914 10:56:25.709137 alsa_mixer-test_write_default_LCALTA_14 pass
2915 10:56:25.714617 alsa_mixer-test_write_valid_LCALTA_14 pass
2916 10:56:25.715045 alsa_mixer-test_write_invalid_LCALTA_14 pass
2917 10:56:25.720265 alsa_mixer-test_event_missing_LCALTA_14 pass
2918 10:56:25.725728 alsa_mixer-test_event_spurious_LCALTA_14 pass
2919 10:56:25.726145 alsa_mixer-test_get_value_LCALTA_13 pass
2920 10:56:25.731263 alsa_mixer-test_name_LCALTA_13 pass
2921 10:56:25.736830 alsa_mixer-test_write_default_LCALTA_13 pass
2922 10:56:25.737250 alsa_mixer-test_write_valid_LCALTA_13 pass
2923 10:56:25.742389 alsa_mixer-test_write_invalid_LCALTA_13 pass
2924 10:56:25.747917 alsa_mixer-test_event_missing_LCALTA_13 pass
2925 10:56:25.748383 alsa_mixer-test_event_spurious_LCALTA_13 pass
2926 10:56:25.753456 alsa_mixer-test_get_value_LCALTA_12 pass
2927 10:56:25.759025 alsa_mixer-test_name_LCALTA_12 pass
2928 10:56:25.759460 alsa_mixer-test_write_default_LCALTA_12 pass
2929 10:56:25.764550 alsa_mixer-test_write_valid_LCALTA_12 pass
2930 10:56:25.770119 alsa_mixer-test_write_invalid_LCALTA_12 pass
2931 10:56:25.775630 alsa_mixer-test_event_missing_LCALTA_12 pass
2932 10:56:25.776272 alsa_mixer-test_event_spurious_LCALTA_12 pass
2933 10:56:25.781331 alsa_mixer-test_get_value_LCALTA_11 pass
2934 10:56:25.786795 alsa_mixer-test_name_LCALTA_11 pass
2935 10:56:25.787327 alsa_mixer-test_write_default_LCALTA_11 pass
2936 10:56:25.792327 alsa_mixer-test_write_valid_LCALTA_11 pass
2937 10:56:25.797851 alsa_mixer-test_write_invalid_LCALTA_11 pass
2938 10:56:25.798311 alsa_mixer-test_event_missing_LCALTA_11 pass
2939 10:56:25.803396 alsa_mixer-test_event_spurious_LCALTA_11 pass
2940 10:56:25.808952 alsa_mixer-test_get_value_LCALTA_10 pass
2941 10:56:25.809445 alsa_mixer-test_name_LCALTA_10 pass
2942 10:56:25.814466 alsa_mixer-test_write_default_LCALTA_10 pass
2943 10:56:25.820084 alsa_mixer-test_write_valid_LCALTA_10 pass
2944 10:56:25.820579 alsa_mixer-test_write_invalid_LCALTA_10 pass
2945 10:56:25.825621 alsa_mixer-test_event_missing_LCALTA_10 pass
2946 10:56:25.831190 alsa_mixer-test_event_spurious_LCALTA_10 pass
2947 10:56:25.836678 alsa_mixer-test_get_value_LCALTA_9 pass
2948 10:56:25.837145 alsa_mixer-test_name_LCALTA_9 pass
2949 10:56:25.842315 alsa_mixer-test_write_default_LCALTA_9 pass
2950 10:56:25.847781 alsa_mixer-test_write_valid_LCALTA_9 pass
2951 10:56:25.848272 alsa_mixer-test_write_invalid_LCALTA_9 pass
2952 10:56:25.853447 alsa_mixer-test_event_missing_LCALTA_9 pass
2953 10:56:25.858863 alsa_mixer-test_event_spurious_LCALTA_9 pass
2954 10:56:25.859322 alsa_mixer-test_get_value_LCALTA_8 pass
2955 10:56:25.864401 alsa_mixer-test_name_LCALTA_8 pass
2956 10:56:25.869946 alsa_mixer-test_write_default_LCALTA_8 pass
2957 10:56:25.870389 alsa_mixer-test_write_valid_LCALTA_8 pass
2958 10:56:25.875495 alsa_mixer-test_write_invalid_LCALTA_8 pass
2959 10:56:25.881045 alsa_mixer-test_event_missing_LCALTA_8 pass
2960 10:56:25.881522 alsa_mixer-test_event_spurious_LCALTA_8 pass
2961 10:56:25.886607 alsa_mixer-test_get_value_LCALTA_7 pass
2962 10:56:25.892217 alsa_mixer-test_name_LCALTA_7 pass
2963 10:56:25.892673 alsa_mixer-test_write_default_LCALTA_7 pass
2964 10:56:25.897698 alsa_mixer-test_write_valid_LCALTA_7 pass
2965 10:56:25.903328 alsa_mixer-test_write_invalid_LCALTA_7 pass
2966 10:56:25.903780 alsa_mixer-test_event_missing_LCALTA_7 pass
2967 10:56:25.908790 alsa_mixer-test_event_spurious_LCALTA_7 pass
2968 10:56:25.914334 alsa_mixer-test_get_value_LCALTA_6 pass
2969 10:56:25.914778 alsa_mixer-test_name_LCALTA_6 pass
2970 10:56:25.919867 alsa_mixer-test_write_default_LCALTA_6 pass
2971 10:56:25.925427 alsa_mixer-test_write_valid_LCALTA_6 pass
2972 10:56:25.925882 alsa_mixer-test_write_invalid_LCALTA_6 pass
2973 10:56:25.930962 alsa_mixer-test_event_missing_LCALTA_6 pass
2974 10:56:25.936511 alsa_mixer-test_event_spurious_LCALTA_6 pass
2975 10:56:25.936965 alsa_mixer-test_get_value_LCALTA_5 pass
2976 10:56:25.942126 alsa_mixer-test_name_LCALTA_5 pass
2977 10:56:25.947693 alsa_mixer-test_write_default_LCALTA_5 pass
2978 10:56:25.948315 alsa_mixer-test_write_valid_LCALTA_5 pass
2979 10:56:25.953331 alsa_mixer-test_write_invalid_LCALTA_5 pass
2980 10:56:25.958921 alsa_mixer-test_event_missing_LCALTA_5 pass
2981 10:56:25.959572 alsa_mixer-test_event_spurious_LCALTA_5 pass
2982 10:56:25.964498 alsa_mixer-test_get_value_LCALTA_4 pass
2983 10:56:25.969962 alsa_mixer-test_name_LCALTA_4 pass
2984 10:56:25.970575 alsa_mixer-test_write_default_LCALTA_4 pass
2985 10:56:25.975555 alsa_mixer-test_write_valid_LCALTA_4 pass
2986 10:56:25.980932 alsa_mixer-test_write_invalid_LCALTA_4 pass
2987 10:56:25.981466 alsa_mixer-test_event_missing_LCALTA_4 pass
2988 10:56:25.986473 alsa_mixer-test_event_spurious_LCALTA_4 pass
2989 10:56:25.992210 alsa_mixer-test_get_value_LCALTA_3 pass
2990 10:56:25.992869 alsa_mixer-test_name_LCALTA_3 pass
2991 10:56:25.997775 alsa_mixer-test_write_default_LCALTA_3 pass
2992 10:56:26.003270 alsa_mixer-test_write_valid_LCALTA_3 pass
2993 10:56:26.003717 alsa_mixer-test_write_invalid_LCALTA_3 pass
2994 10:56:26.008770 alsa_mixer-test_event_missing_LCALTA_3 pass
2995 10:56:26.014212 alsa_mixer-test_event_spurious_LCALTA_3 pass
2996 10:56:26.014804 alsa_mixer-test_get_value_LCALTA_2 pass
2997 10:56:26.019788 alsa_mixer-test_name_LCALTA_2 pass
2998 10:56:26.025539 alsa_mixer-test_write_default_LCALTA_2 pass
2999 10:56:26.026180 alsa_mixer-test_write_valid_LCALTA_2 pass
3000 10:56:26.030936 alsa_mixer-test_write_invalid_LCALTA_2 pass
3001 10:56:26.036385 alsa_mixer-test_event_missing_LCALTA_2 pass
3002 10:56:26.042002 alsa_mixer-test_event_spurious_LCALTA_2 pass
3003 10:56:26.042421 alsa_mixer-test_get_value_LCALTA_1 pass
3004 10:56:26.047444 alsa_mixer-test_name_LCALTA_1 pass
3005 10:56:26.048041 alsa_mixer-test_write_default_LCALTA_1 pass
3006 10:56:26.053006 alsa_mixer-test_write_valid_LCALTA_1 pass
3007 10:56:26.058517 alsa_mixer-test_write_invalid_LCALTA_1 pass
3008 10:56:26.064146 alsa_mixer-test_event_missing_LCALTA_1 pass
3009 10:56:26.064731 alsa_mixer-test_event_spurious_LCALTA_1 pass
3010 10:56:26.069738 alsa_mixer-test_get_value_LCALTA_0 pass
3011 10:56:26.070346 alsa_mixer-test_name_LCALTA_0 pass
3012 10:56:26.075293 alsa_mixer-test_write_default_LCALTA_0 pass
3013 10:56:26.080808 alsa_mixer-test_write_valid_LCALTA_0 pass
3014 10:56:26.086566 alsa_mixer-test_write_invalid_LCALTA_0 pass
3015 10:56:26.087227 alsa_mixer-test_event_missing_LCALTA_0 pass
3016 10:56:26.092034 alsa_mixer-test_event_spurious_LCALTA_0 pass
3017 10:56:26.092462 alsa_mixer-test pass
3018 10:56:26.097715 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
3019 10:56:26.103030 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
3020 10:56:26.108521 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
3021 10:56:26.114130 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
3022 10:56:26.114589 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
3023 10:56:26.119632 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
3024 10:56:26.125165 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
3025 10:56:26.130793 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
3026 10:56:26.136370 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
3027 10:56:26.141817 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
3028 10:56:26.142404 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
3029 10:56:26.147447 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
3030 10:56:26.153127 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
3031 10:56:26.158518 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
3032 10:56:26.164014 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
3033 10:56:26.169607 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
3034 10:56:26.170184 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
3035 10:56:26.175228 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
3036 10:56:26.180722 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
3037 10:56:26.186275 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
3038 10:56:26.191829 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
3039 10:56:26.197299 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
3040 10:56:26.197856 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
3041 10:56:26.202835 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
3042 10:56:26.208566 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
3043 10:56:26.214206 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
3044 10:56:26.219570 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
3045 10:56:26.225084 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
3046 10:56:26.225740 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
3047 10:56:26.230727 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
3048 10:56:26.236095 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
3049 10:56:26.241635 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
3050 10:56:26.247235 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
3051 10:56:26.252837 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
3052 10:56:26.258375 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
3053 10:56:26.258941 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
3054 10:56:26.263875 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
3055 10:56:26.269563 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
3056 10:56:26.275014 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
3057 10:56:26.280494 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
3058 10:56:26.286103 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
3059 10:56:26.286705 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
3060 10:56:26.291552 alsa_pcm-test pass
3061 10:56:26.297101 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3062 10:56:26.308325 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3063 10:56:26.313785 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3064 10:56:26.324854 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3065 10:56:26.330599 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
3066 10:56:26.336040 alsa_test-pcmtest-driver pass
3067 10:56:26.341539 alsa_utimer-test_global_wrong_timers_test pass
3068 10:56:26.342120 alsa_utimer-test_timer_f_utimer fail
3069 10:56:26.347144 alsa_utimer-test fail
3070 10:56:26.347799 + ../../utils/send-to-lava.sh ./output/result.txt
3071 10:56:26.352664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
3072 10:56:26.353842 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
3074 10:56:26.363976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
3075 10:56:26.365338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
3077 10:56:26.369609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
3078 10:56:26.370488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
3080 10:56:26.412826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
3081 10:56:26.413746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
3083 10:56:26.468260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
3084 10:56:26.469135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
3086 10:56:26.528738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
3087 10:56:26.529638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
3089 10:56:26.582727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
3090 10:56:26.583615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
3092 10:56:26.634348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
3093 10:56:26.635238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
3095 10:56:26.690791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
3096 10:56:26.691877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
3098 10:56:26.748938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
3099 10:56:26.749807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
3101 10:56:26.811812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
3102 10:56:26.812744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
3104 10:56:26.875707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
3105 10:56:26.876914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
3107 10:56:26.947500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
3108 10:56:26.948479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
3110 10:56:27.021986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
3111 10:56:27.022672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
3113 10:56:27.083674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
3114 10:56:27.084417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
3116 10:56:27.154596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
3117 10:56:27.155230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
3119 10:56:27.202080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
3120 10:56:27.203073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
3122 10:56:27.275559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
3123 10:56:27.277043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
3125 10:56:27.361668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
3126 10:56:27.362585 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
3128 10:56:27.415636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
3129 10:56:27.416658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
3131 10:56:27.504608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
3132 10:56:27.505738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
3134 10:56:27.567185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
3135 10:56:27.568109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
3137 10:56:27.626234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
3138 10:56:27.627127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
3140 10:56:27.681649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
3141 10:56:27.682547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
3143 10:56:27.727059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
3144 10:56:27.727876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
3146 10:56:27.777574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
3147 10:56:27.778427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
3149 10:56:27.820961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3150 10:56:27.821780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3152 10:56:27.879425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3153 10:56:27.880300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3155 10:56:27.925500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3156 10:56:27.926369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3158 10:56:27.982728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3159 10:56:27.983576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3161 10:56:28.035940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3162 10:56:28.036820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3164 10:56:28.092573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3165 10:56:28.093434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3167 10:56:28.142873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3168 10:56:28.143722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3170 10:56:28.191090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3171 10:56:28.192116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3173 10:56:28.245540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3174 10:56:28.246395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3176 10:56:28.297411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3177 10:56:28.298275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3179 10:56:28.350196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3180 10:56:28.351034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3182 10:56:28.407847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3183 10:56:28.408782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3185 10:56:28.458753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3186 10:56:28.459602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3188 10:56:28.504009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3189 10:56:28.504873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3191 10:56:28.553662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3192 10:56:28.554296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3194 10:56:28.607020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3195 10:56:28.607616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3197 10:56:28.665408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3198 10:56:28.666058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3200 10:56:28.720338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3201 10:56:28.720986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3203 10:56:28.772899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3204 10:56:28.773496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3206 10:56:28.825667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3207 10:56:28.826247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3209 10:56:28.880339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3210 10:56:28.880922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3212 10:56:28.931933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3213 10:56:28.932560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3215 10:56:28.977143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3216 10:56:28.977724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3218 10:56:29.032503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3219 10:56:29.033065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3221 10:56:29.090742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3222 10:56:29.091323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3224 10:56:29.141939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3225 10:56:29.142523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3227 10:56:29.185958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3228 10:56:29.186523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3230 10:56:29.240343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3231 10:56:29.240929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3233 10:56:29.297977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3234 10:56:29.298562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3236 10:56:29.350754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3237 10:56:29.351348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3239 10:56:29.404603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3240 10:56:29.405434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3242 10:56:29.456948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3243 10:56:29.457527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3245 10:56:29.510322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3246 10:56:29.510904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3248 10:56:29.571224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3249 10:56:29.571800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3251 10:56:29.618007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3252 10:56:29.618604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3254 10:56:29.680468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3255 10:56:29.681054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3257 10:56:29.726047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3258 10:56:29.726636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3260 10:56:29.776288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3261 10:56:29.776878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3263 10:56:29.823598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3264 10:56:29.824210 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3266 10:56:29.872069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3267 10:56:29.872652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3269 10:56:29.925083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3270 10:56:29.925665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3272 10:56:29.978439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3273 10:56:29.979010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3275 10:56:30.029555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3276 10:56:30.030160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3278 10:56:30.084207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3279 10:56:30.085220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3281 10:56:30.136707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3282 10:56:30.137547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3284 10:56:30.192773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3285 10:56:30.193649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3287 10:56:30.249420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3288 10:56:30.250215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3290 10:56:30.296922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3291 10:56:30.297701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3293 10:56:30.351019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3294 10:56:30.351809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3296 10:56:30.407948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3297 10:56:30.408957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3299 10:56:30.468482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3300 10:56:30.469356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3302 10:56:30.516468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3303 10:56:30.517294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3305 10:56:30.575252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3306 10:56:30.576083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3308 10:56:30.632280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3309 10:56:30.633097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3311 10:56:30.691044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3312 10:56:30.691813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3314 10:56:30.751072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3315 10:56:30.751863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3317 10:56:30.805658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3318 10:56:30.806518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3320 10:56:30.856955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3321 10:56:30.857817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3323 10:56:30.912321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3324 10:56:30.913156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3326 10:56:30.968084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3327 10:56:30.968876 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3329 10:56:31.019949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3330 10:56:31.020808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3332 10:56:31.077538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3333 10:56:31.078399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3335 10:56:31.130044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3336 10:56:31.130917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3338 10:56:31.181768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3339 10:56:31.182533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3341 10:56:31.232335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3342 10:56:31.233121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3344 10:56:31.277655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3345 10:56:31.278431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3347 10:56:31.334568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3348 10:56:31.335353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3350 10:56:31.386953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3351 10:56:31.387771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3353 10:56:31.443945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3354 10:56:31.444795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3356 10:56:31.493676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3357 10:56:31.494500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3359 10:56:31.546803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3360 10:56:31.547554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3362 10:56:31.601406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3363 10:56:31.602209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3365 10:56:31.653553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3366 10:56:31.654344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3368 10:56:31.707708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3369 10:56:31.708574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3371 10:56:31.764372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3372 10:56:31.765149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3374 10:56:31.817937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3375 10:56:31.818735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3377 10:56:31.871531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3378 10:56:31.872351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3380 10:56:31.927785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3381 10:56:31.928624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3383 10:56:31.986320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3384 10:56:31.987136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3386 10:56:32.033492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3387 10:56:32.034277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3389 10:56:32.084356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3390 10:56:32.085144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3392 10:56:32.135656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3393 10:56:32.136257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3395 10:56:32.192585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3396 10:56:32.193392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3398 10:56:32.243433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3399 10:56:32.244203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3401 10:56:32.292174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3402 10:56:32.292971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3404 10:56:32.338458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3405 10:56:32.339327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3407 10:56:32.394259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3408 10:56:32.395063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3410 10:56:32.447877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3411 10:56:32.448701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3413 10:56:32.503059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3414 10:56:32.503847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3416 10:56:32.553974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3417 10:56:32.554802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3419 10:56:32.603092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3420 10:56:32.603951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3422 10:56:32.656510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3423 10:56:32.657357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3425 10:56:32.704559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3426 10:56:32.705407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3428 10:56:32.762633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3429 10:56:32.763416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3431 10:56:32.807654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3432 10:56:32.808481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3434 10:56:32.857645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3435 10:56:32.858461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3437 10:56:32.913650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3438 10:56:32.914470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3440 10:56:32.971654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3441 10:56:32.972477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3443 10:56:33.023477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3444 10:56:33.024287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3446 10:56:33.074145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3447 10:56:33.074910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3449 10:56:33.130163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3450 10:56:33.130950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3452 10:56:33.182457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3453 10:56:33.183252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3455 10:56:33.240080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3456 10:56:33.240865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3458 10:56:33.298099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3459 10:56:33.298861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3461 10:56:33.350943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3462 10:56:33.351702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3464 10:56:33.396713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3465 10:56:33.397469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3467 10:56:33.448229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3468 10:56:33.448983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3470 10:56:33.500787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3471 10:56:33.501549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3473 10:56:33.546277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3474 10:56:33.547044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3476 10:56:33.593575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3477 10:56:33.594452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3479 10:56:33.646335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3480 10:56:33.647144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3482 10:56:33.695243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3483 10:56:33.695841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3485 10:56:33.739771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3486 10:56:33.740354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3488 10:56:33.785991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3489 10:56:33.786597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3491 10:56:33.839025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3492 10:56:33.839923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3494 10:56:33.885817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3495 10:56:33.886648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3497 10:56:33.938476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3498 10:56:33.939263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3500 10:56:33.989519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3501 10:56:33.990285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3503 10:56:34.045828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3504 10:56:34.046629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3506 10:56:34.098578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3507 10:56:34.099348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3509 10:56:34.151663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3510 10:56:34.152473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3512 10:56:34.205654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3513 10:56:34.206418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3515 10:56:34.253224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3516 10:56:34.253987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3518 10:56:34.306709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3519 10:56:34.307452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3521 10:56:34.353586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3522 10:56:34.354410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3524 10:56:34.412841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3525 10:56:34.413654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3527 10:56:34.470970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3528 10:56:34.471771 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3530 10:56:34.529211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3531 10:56:34.529989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3533 10:56:34.582116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3534 10:56:34.582857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3536 10:56:34.640584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3537 10:56:34.641326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3539 10:56:34.690429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3540 10:56:34.691170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3542 10:56:34.744146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3543 10:56:34.744885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3545 10:56:34.789777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3546 10:56:34.790515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3548 10:56:34.846740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3549 10:56:34.847538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3551 10:56:34.893488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3552 10:56:34.894230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3554 10:56:34.946745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3555 10:56:34.947502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3557 10:56:35.005433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3558 10:56:35.006219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3560 10:56:35.062019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3561 10:56:35.062767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3563 10:56:35.118343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3564 10:56:35.119090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3566 10:56:35.168088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3567 10:56:35.168832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3569 10:56:35.222111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3570 10:56:35.222847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3572 10:56:35.266789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3573 10:56:35.267565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3575 10:56:35.318450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3576 10:56:35.319209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3578 10:56:35.376070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3579 10:56:35.376816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3581 10:56:35.428725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3582 10:56:35.429463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3584 10:56:35.484887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3585 10:56:35.485650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3587 10:56:35.534904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3588 10:56:35.535646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3590 10:56:35.600178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3591 10:56:35.600939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3593 10:56:35.658264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3594 10:56:35.658996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3596 10:56:35.708275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3597 10:56:35.709015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3599 10:56:35.760867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3600 10:56:35.761666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3602 10:56:35.811873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3603 10:56:35.812675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3605 10:56:35.867466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3606 10:56:35.868318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3608 10:56:35.935682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3609 10:56:35.936503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3611 10:56:35.984227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3612 10:56:35.984987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3614 10:56:36.038588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3615 10:56:36.039380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3617 10:56:36.096768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3618 10:56:36.097514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3620 10:56:36.147313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3621 10:56:36.148084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3623 10:56:36.191406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3624 10:56:36.192142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3626 10:56:36.248284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3627 10:56:36.249020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3629 10:56:36.301989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3630 10:56:36.302732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3632 10:56:36.355291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3633 10:56:36.356059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3635 10:56:36.398228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3636 10:56:36.398966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3638 10:56:36.451965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3639 10:56:36.452750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3641 10:56:36.507482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3642 10:56:36.508339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3644 10:56:36.553214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3645 10:56:36.553998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3647 10:56:36.602648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3648 10:56:36.603382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3650 10:56:36.646756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3651 10:56:36.647545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3653 10:56:36.704799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3654 10:56:36.705541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3656 10:56:36.757798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3657 10:56:36.758531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3659 10:56:36.806562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3660 10:56:36.807361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3662 10:56:36.849621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3663 10:56:36.850444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3665 10:56:36.902077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3666 10:56:36.902853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3668 10:56:36.960316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3669 10:56:36.961067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3671 10:56:37.008085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3672 10:56:37.008875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3674 10:56:37.053708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3675 10:56:37.054458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3677 10:56:37.108305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3678 10:56:37.109044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3680 10:56:37.164337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3681 10:56:37.165091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3683 10:56:37.216415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3684 10:56:37.217157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3686 10:56:37.274718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3687 10:56:37.275458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3689 10:56:37.332711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3690 10:56:37.333469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3692 10:56:37.381563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3693 10:56:37.382323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3695 10:56:37.432381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3696 10:56:37.433135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3698 10:56:37.494683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3699 10:56:37.495479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3701 10:56:37.545552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3702 10:56:37.546325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3704 10:56:37.599103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3705 10:56:37.599881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3707 10:56:37.642950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3708 10:56:37.643766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3710 10:56:37.695877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3711 10:56:37.696693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3713 10:56:37.748826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3714 10:56:37.749635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3716 10:56:37.794207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3717 10:56:37.794975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3719 10:56:37.851023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3720 10:56:37.851973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3722 10:56:37.900335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3723 10:56:37.901117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3725 10:56:37.945182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3726 10:56:37.945951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3728 10:56:37.995369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3729 10:56:37.996135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3731 10:56:38.046816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3732 10:56:38.047609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3734 10:56:38.091605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3735 10:56:38.092414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3737 10:56:38.140403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3738 10:56:38.141167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3740 10:56:38.196772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3741 10:56:38.197541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3743 10:56:38.250650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3744 10:56:38.251422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3746 10:56:38.301404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3747 10:56:38.302155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3749 10:56:38.351142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3750 10:56:38.351912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3752 10:56:38.402584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3753 10:56:38.403340 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3755 10:56:38.451791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3756 10:56:38.452590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3758 10:56:38.508013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3759 10:56:38.508794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3761 10:56:38.553241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3762 10:56:38.554007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3764 10:56:38.604847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3765 10:56:38.605603 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3767 10:56:38.655762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3768 10:56:38.656559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3770 10:56:38.703007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3771 10:56:38.703751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3773 10:56:38.759810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3774 10:56:38.760605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3776 10:56:38.812319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3777 10:56:38.813087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3779 10:56:38.879168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3780 10:56:38.879959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3782 10:56:38.928552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3783 10:56:38.929312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3785 10:56:38.981337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3786 10:56:38.982101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3788 10:56:39.024760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3789 10:56:39.025555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3791 10:56:39.074580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3792 10:56:39.075321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3794 10:56:39.129403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3795 10:56:39.130220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3797 10:56:39.181451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3798 10:56:39.182252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3800 10:56:39.243155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3801 10:56:39.243956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3803 10:56:39.288720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3804 10:56:39.289518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3806 10:56:39.349457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3807 10:56:39.350267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3809 10:56:39.395602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3810 10:56:39.396157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3812 10:56:39.442022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3813 10:56:39.442810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3815 10:56:39.500097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3816 10:56:39.500920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3818 10:56:39.550981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3819 10:56:39.551781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3821 10:56:39.604161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3822 10:56:39.604999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3824 10:56:39.648607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3825 10:56:39.649413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3827 10:56:39.705739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3828 10:56:39.706578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3830 10:56:39.758889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3831 10:56:39.759770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3833 10:56:39.811947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3834 10:56:39.812805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3836 10:56:39.857597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3837 10:56:39.858462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3839 10:56:39.909556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3840 10:56:39.910360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3842 10:56:39.967233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3843 10:56:39.968094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3845 10:56:40.016743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3846 10:56:40.017532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3848 10:56:40.067128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3849 10:56:40.067931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3851 10:56:40.123585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3852 10:56:40.124411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3854 10:56:40.166742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3855 10:56:40.167534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3857 10:56:40.228189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3858 10:56:40.228982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3860 10:56:40.283527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3861 10:56:40.284331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3863 10:56:40.330739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3864 10:56:40.331507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3866 10:56:40.386304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3867 10:56:40.387069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3869 10:56:40.433661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3870 10:56:40.434440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3872 10:56:40.479626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3873 10:56:40.480432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3875 10:56:40.528715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3876 10:56:40.529541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3878 10:56:40.581337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3879 10:56:40.582136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3881 10:56:40.628988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3882 10:56:40.629735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3884 10:56:40.684860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3885 10:56:40.685622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3887 10:56:40.739739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3888 10:56:40.740543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3890 10:56:40.785741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3891 10:56:40.786478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3893 10:56:40.835490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3894 10:56:40.836087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3896 10:56:40.880208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3897 10:56:40.880839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3899 10:56:40.935502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3900 10:56:40.936143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3902 10:56:40.985801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3903 10:56:40.986951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3905 10:56:41.036584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3906 10:56:41.037502 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3908 10:56:41.093691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3909 10:56:41.094529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3911 10:56:41.143067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3912 10:56:41.143906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3914 10:56:41.183655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3915 10:56:41.184570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3917 10:56:41.232285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3918 10:56:41.233139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3920 10:56:41.285925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3921 10:56:41.286564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3923 10:56:41.338641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3924 10:56:41.339310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3926 10:56:41.388915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3927 10:56:41.389568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3929 10:56:41.439783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3930 10:56:41.440525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3932 10:56:41.486248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3933 10:56:41.487042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3935 10:56:41.535428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3936 10:56:41.536283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3938 10:56:41.586654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3939 10:56:41.587417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3941 10:56:41.642228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3942 10:56:41.643013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3944 10:56:41.688753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3945 10:56:41.689510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3947 10:56:41.741967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3948 10:56:41.742794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3950 10:56:41.786462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3951 10:56:41.787233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3953 10:56:41.831253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3954 10:56:41.832077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3956 10:56:41.878418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3957 10:56:41.879169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3959 10:56:41.927915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3960 10:56:41.928708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3962 10:56:41.979935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3963 10:56:41.980708 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3965 10:56:42.026899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3966 10:56:42.027628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3968 10:56:42.077755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3969 10:56:42.078550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3971 10:56:42.130366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3972 10:56:42.131126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3974 10:56:42.183660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3975 10:56:42.184444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3977 10:56:42.232324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3978 10:56:42.233072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3980 10:56:42.289697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3981 10:56:42.290461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3983 10:56:42.336055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3984 10:56:42.336819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3986 10:56:42.379806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3987 10:56:42.380566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3989 10:56:42.424267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3990 10:56:42.425000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3992 10:56:42.467325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3993 10:56:42.468084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3995 10:56:42.516400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3996 10:56:42.517152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3998 10:56:42.567491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3999 10:56:42.568380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
4001 10:56:42.612251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
4002 10:56:42.613060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
4004 10:56:42.663112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
4005 10:56:42.663896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
4007 10:56:42.714517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
4008 10:56:42.715238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
4010 10:56:42.760359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
4011 10:56:42.761111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
4013 10:56:42.809958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
4014 10:56:42.810684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
4016 10:56:42.865860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
4017 10:56:42.866641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
4019 10:56:42.910587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
4020 10:56:42.911318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
4022 10:56:42.962532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
4023 10:56:42.963295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
4025 10:56:43.009908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
4026 10:56:43.010649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
4028 10:56:43.057560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
4029 10:56:43.058287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
4031 10:56:43.112410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
4032 10:56:43.113194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
4034 10:56:43.164189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
4035 10:56:43.164950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
4037 10:56:43.211529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
4038 10:56:43.212359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
4040 10:56:43.262396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
4041 10:56:43.263239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
4043 10:56:43.315381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
4044 10:56:43.316196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
4046 10:56:43.367474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
4047 10:56:43.368374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
4049 10:56:43.416899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
4050 10:56:43.417689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
4052 10:56:43.468061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
4053 10:56:43.468913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
4055 10:56:43.514369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
4056 10:56:43.515188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
4058 10:56:43.561137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
4059 10:56:43.562093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
4061 10:56:43.611195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
4062 10:56:43.612207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
4064 10:56:43.668473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
4065 10:56:43.669258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
4067 10:56:43.721456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
4068 10:56:43.722225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
4070 10:56:43.764561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
4071 10:56:43.765343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
4073 10:56:43.819041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
4074 10:56:43.819819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
4076 10:56:43.878014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
4077 10:56:43.878839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
4079 10:56:43.931281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
4080 10:56:43.932074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
4082 10:56:43.972286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
4083 10:56:43.973032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
4085 10:56:44.208412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
4086 10:56:44.209220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
4088 10:56:44.259543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
4089 10:56:44.260326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
4091 10:56:44.315312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
4092 10:56:44.316074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
4094 10:56:44.356429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
4095 10:56:44.357179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
4097 10:56:44.399690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
4098 10:56:44.400447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
4100 10:56:44.457891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
4101 10:56:44.458616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
4103 10:56:44.509423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
4104 10:56:44.510159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
4106 10:56:44.562073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
4107 10:56:44.562819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
4109 10:56:44.613536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
4110 10:56:44.614366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
4112 10:56:44.666686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
4113 10:56:44.667612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
4115 10:56:44.716516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
4116 10:56:44.717393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
4118 10:56:44.769727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
4119 10:56:44.770506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
4121 10:56:44.822393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
4122 10:56:44.823125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
4124 10:56:44.874105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
4125 10:56:44.874891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
4127 10:56:44.924635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
4128 10:56:44.925376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
4130 10:56:44.970321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
4131 10:56:44.971047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
4133 10:56:45.022735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
4134 10:56:45.023463 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
4136 10:56:45.073943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
4137 10:56:45.074685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
4139 10:56:45.126194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
4140 10:56:45.126991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
4142 10:56:45.188681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
4143 10:56:45.189430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
4145 10:56:45.234064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
4146 10:56:45.234818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
4148 10:56:45.288220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
4149 10:56:45.288982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4151 10:56:45.334171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4152 10:56:45.334913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4154 10:56:45.384286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4155 10:56:45.385020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4157 10:56:45.429049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4158 10:56:45.429773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4160 10:56:45.483403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4161 10:56:45.484137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4163 10:56:45.531100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4164 10:56:45.531862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4166 10:56:45.582449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4167 10:56:45.583272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4169 10:56:45.628432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4170 10:56:45.629231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4172 10:56:45.690908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4173 10:56:45.691658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4175 10:56:45.739869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4176 10:56:45.740666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4178 10:56:45.787357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4179 10:56:45.788200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4181 10:56:45.833093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4182 10:56:45.833881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4184 10:56:45.884387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4185 10:56:45.885101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4187 10:56:45.937154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4188 10:56:45.937906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4190 10:56:45.982771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4191 10:56:45.983467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4193 10:56:46.030855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4194 10:56:46.031555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4196 10:56:46.086948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4197 10:56:46.087787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4199 10:56:46.133331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4200 10:56:46.134061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4202 10:56:46.186793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4203 10:56:46.187523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4205 10:56:46.232742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4206 10:56:46.233470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4208 10:56:46.290356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4209 10:56:46.291097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4211 10:56:46.342704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4212 10:56:46.343469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4214 10:56:46.390036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4215 10:56:46.390748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4217 10:56:46.450992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4218 10:56:46.451711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4220 10:56:46.499771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4221 10:56:46.500560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4223 10:56:46.557420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4224 10:56:46.558185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4226 10:56:46.601989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4227 10:56:46.602720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4229 10:56:46.660867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4230 10:56:46.661613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4232 10:56:46.711262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4233 10:56:46.712051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4235 10:56:46.763422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4236 10:56:46.764184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4238 10:56:46.808064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4239 10:56:46.808788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4241 10:56:46.866810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4242 10:56:46.867607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4244 10:56:46.919870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4245 10:56:46.920624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4247 10:56:46.975426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4248 10:56:46.976181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4250 10:56:47.024467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4251 10:56:47.025201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4253 10:56:47.076545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4254 10:56:47.077271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4256 10:56:47.133837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4257 10:56:47.134615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4259 10:56:47.185004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4260 10:56:47.185724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4262 10:56:47.238363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4263 10:56:47.239070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4265 10:56:47.292300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4266 10:56:47.293013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4268 10:56:47.343666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4269 10:56:47.344449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4271 10:56:47.398350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4272 10:56:47.399081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4274 10:56:47.441109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4275 10:56:47.441847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4277 10:56:47.493917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4278 10:56:47.494670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4280 10:56:47.547731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4281 10:56:47.548532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4283 10:56:47.596416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4284 10:56:47.597143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4286 10:56:47.651940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4287 10:56:47.652698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4289 10:56:47.699062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4290 10:56:47.699784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4292 10:56:47.755519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4293 10:56:47.756296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4295 10:56:47.799969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4296 10:56:47.800709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4298 10:56:47.847002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4299 10:56:47.847758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4301 10:56:47.902698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4302 10:56:47.903441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4304 10:56:47.949349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4305 10:56:47.950114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4307 10:56:47.994447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4308 10:56:47.995181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4310 10:56:48.044810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4311 10:56:48.045549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4313 10:56:48.109232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4314 10:56:48.110051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4316 10:56:48.171565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4317 10:56:48.172489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4319 10:56:48.224108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4320 10:56:48.224865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4322 10:56:48.275647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4323 10:56:48.276415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4325 10:56:48.322519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4326 10:56:48.323227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4328 10:56:48.376830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4329 10:56:48.377559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4331 10:56:48.431327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4332 10:56:48.432006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4334 10:56:48.476841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4335 10:56:48.477668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4337 10:56:48.532289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4338 10:56:48.533128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4340 10:56:48.590064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4341 10:56:48.590798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4343 10:56:48.646157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4344 10:56:48.646871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4346 10:56:48.690455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4347 10:56:48.691157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4349 10:56:48.734237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4350 10:56:48.734948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4352 10:56:48.780164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4353 10:56:48.780852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4355 10:56:48.820912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4357 10:56:48.823949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4358 10:56:48.873664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4359 10:56:48.874394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4361 10:56:48.918802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4362 10:56:48.919500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4364 10:56:48.964905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4365 10:56:48.965613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4367 10:56:49.011504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4368 10:56:49.012280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4370 10:56:49.063667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4371 10:56:49.064407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4373 10:56:49.105880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4374 10:56:49.106629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4376 10:56:49.150247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4377 10:56:49.151043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4379 10:56:49.195012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4380 10:56:49.195818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4382 10:56:49.240134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4383 10:56:49.241007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4385 10:56:49.298890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4386 10:56:49.299652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4388 10:56:49.343643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4389 10:56:49.344415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4391 10:56:49.388266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4392 10:56:49.389020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4394 10:56:49.443529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4395 10:56:49.444293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4397 10:56:49.494326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4398 10:56:49.494986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4400 10:56:49.540863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4401 10:56:49.541510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4403 10:56:49.589493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4404 10:56:49.590154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4406 10:56:49.642991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4407 10:56:49.643648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4409 10:56:49.698976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4410 10:56:49.699703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4412 10:56:49.743765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4413 10:56:49.744442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4415 10:56:49.792544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4416 10:56:49.793192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4418 10:56:49.852077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4419 10:56:49.852728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4421 10:56:49.905063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4422 10:56:49.905723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4424 10:56:49.950805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4425 10:56:49.951435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4427 10:56:50.007679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4428 10:56:50.008357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4430 10:56:50.058432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4431 10:56:50.059268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4433 10:56:50.106179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4434 10:56:50.107045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4436 10:56:50.157161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4437 10:56:50.157980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4439 10:56:50.202883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4440 10:56:50.203747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4442 10:56:50.247632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4443 10:56:50.248458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4445 10:56:50.294839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4446 10:56:50.295653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4448 10:56:50.341993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4449 10:56:50.342797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4451 10:56:50.396135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4452 10:56:50.396963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4454 10:56:50.448236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4455 10:56:50.449050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4457 10:56:50.493143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4458 10:56:50.493953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4460 10:56:50.545195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4461 10:56:50.546042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4463 10:56:50.592269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4464 10:56:50.593078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4466 10:56:50.636402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4467 10:56:50.637241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4469 10:56:50.677481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4470 10:56:50.678277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4472 10:56:50.723125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4473 10:56:50.723797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4475 10:56:50.772202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4476 10:56:50.773300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4478 10:56:50.820424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4479 10:56:50.821078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4481 10:56:50.876758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4482 10:56:50.877412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4484 10:56:50.926991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4485 10:56:50.927897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4487 10:56:50.976980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4488 10:56:50.977894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4490 10:56:51.031126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4491 10:56:51.031810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4493 10:56:51.083201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4494 10:56:51.083869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4496 10:56:51.127683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4497 10:56:51.128371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4499 10:56:51.179322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4500 10:56:51.180345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4502 10:56:51.230086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4503 10:56:51.230841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4505 10:56:51.295880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4506 10:56:51.296547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4508 10:56:51.348081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4509 10:56:51.348785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4511 10:56:51.396445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4513 10:56:51.401585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4514 10:56:51.402162 + set +x
4515 10:56:51.407540 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 913099_1.6.2.4.5>
4516 10:56:51.408194 <LAVA_TEST_RUNNER EXIT>
4517 10:56:51.408942 Received signal: <ENDRUN> 1_kselftest-alsa 913099_1.6.2.4.5
4518 10:56:51.409446 Ending use of test pattern.
4519 10:56:51.409902 Ending test lava.1_kselftest-alsa (913099_1.6.2.4.5), duration 41.70
4521 10:56:51.411532 ok: lava_test_shell seems to have completed
4522 10:56:51.431567 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4523 10:56:51.433566 end: 3.1 lava-test-shell (duration 00:00:43) [common]
4524 10:56:51.434228 end: 3 lava-test-retry (duration 00:00:43) [common]
4525 10:56:51.434860 start: 4 finalize (timeout 00:06:02) [common]
4526 10:56:51.435487 start: 4.1 power-off (timeout 00:00:30) [common]
4527 10:56:51.436569 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4528 10:56:51.472277 >> OK - accepted request
4529 10:56:51.474337 Returned 0 in 0 seconds
4530 10:56:51.575338 end: 4.1 power-off (duration 00:00:00) [common]
4532 10:56:51.577284 start: 4.2 read-feedback (timeout 00:06:02) [common]
4533 10:56:51.578467 Listened to connection for namespace 'common' for up to 1s
4534 10:56:52.579254 Finalising connection for namespace 'common'
4535 10:56:52.580077 Disconnecting from shell: Finalise
4536 10:56:52.580633 / #
4537 10:56:52.681737 end: 4.2 read-feedback (duration 00:00:01) [common]
4538 10:56:52.682518 end: 4 finalize (duration 00:00:01) [common]
4539 10:56:52.683212 Cleaning after the job
4540 10:56:52.683855 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/ramdisk
4541 10:56:52.699153 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/kernel
4542 10:56:52.729974 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/dtb
4543 10:56:52.731480 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/nfsrootfs
4544 10:56:52.770066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/913099/tftp-deploy-ij06ok07/modules
4545 10:56:52.776608 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/913099
4546 10:56:56.919097 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/913099
4547 10:56:56.919678 Job finished correctly