Boot log: beaglebone-black

    1 08:33:43.858028  lava-dispatcher, installed at version: 2023.08
    2 08:33:43.858454  start: 0 validate
    3 08:33:43.858690  Start time: 2024-10-31 08:33:43.858675+00:00 (UTC)
    4 08:33:43.858964  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
    5 08:33:44.165740  Validating that http://storage.kernelci.org/next/master/next-20241031/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
    6 08:33:44.317079  Validating that http://storage.kernelci.org/next/master/next-20241031/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
    7 08:33:44.469024  Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
    8 08:33:44.621583  Validating that http://storage.kernelci.org/next/master/next-20241031/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
    9 08:33:44.781148  validate duration: 0.92
   11 08:33:44.782221  start: 1 tftp-deploy (timeout 00:10:00) [common]
   12 08:33:44.782686  start: 1.1 download-retry (timeout 00:10:00) [common]
   13 08:33:44.783123  start: 1.1.1 http-download (timeout 00:10:00) [common]
   14 08:33:44.783840  Not decompressing ramdisk as can be used compressed.
   15 08:33:44.784265  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   16 08:33:44.784600  saving as /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/ramdisk/initrd.cpio.gz
   17 08:33:44.784965  total size: 4775763 (4 MB)
   18 08:33:45.088633  progress   0 % (0 MB)
   19 08:33:45.538746  progress   5 % (0 MB)
   20 08:33:45.687841  progress  10 % (0 MB)
   21 08:33:45.871749  progress  15 % (0 MB)
   22 08:33:46.032523  progress  20 % (0 MB)
   23 08:33:46.036976  progress  25 % (1 MB)
   24 08:33:46.040402  progress  30 % (1 MB)
   25 08:33:46.044302  progress  35 % (1 MB)
   26 08:33:46.142834  progress  40 % (1 MB)
   27 08:33:46.177496  progress  45 % (2 MB)
   28 08:33:46.312779  progress  50 % (2 MB)
   29 08:33:46.450294  progress  55 % (2 MB)
   30 08:33:46.584436  progress  60 % (2 MB)
   31 08:33:46.625036  progress  65 % (2 MB)
   32 08:33:46.755856  progress  70 % (3 MB)
   33 08:33:46.890461  progress  75 % (3 MB)
   34 08:33:46.928412  progress  80 % (3 MB)
   35 08:33:47.054759  progress  85 % (3 MB)
   36 08:33:47.192473  progress  90 % (4 MB)
   37 08:33:47.229190  progress  95 % (4 MB)
   38 08:33:47.356067  progress 100 % (4 MB)
   39 08:33:47.357153  4 MB downloaded in 2.57 s (1.77 MB/s)
   40 08:33:47.357863  end: 1.1.1 http-download (duration 00:00:03) [common]
   42 08:33:47.359010  end: 1.1 download-retry (duration 00:00:03) [common]
   43 08:33:47.359426  start: 1.2 download-retry (timeout 00:09:57) [common]
   44 08:33:47.359829  start: 1.2.1 http-download (timeout 00:09:57) [common]
   45 08:33:47.360460  downloading http://storage.kernelci.org/next/master/next-20241031/arm/multi_v7_defconfig/gcc-12/kernel/zImage
   46 08:33:47.360796  saving as /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/kernel/zImage
   47 08:33:47.361107  total size: 11502080 (10 MB)
   48 08:33:47.361415  No compression specified
   49 08:33:47.516370  progress   0 % (0 MB)
   50 08:33:47.699154  progress   5 % (0 MB)
   51 08:33:48.111841  progress  10 % (1 MB)
   52 08:33:48.413713  progress  15 % (1 MB)
   53 08:33:48.718788  progress  20 % (2 MB)
   54 08:33:49.013945  progress  25 % (2 MB)
   55 08:33:49.314475  progress  30 % (3 MB)
   56 08:33:49.606212  progress  35 % (3 MB)
   57 08:33:49.868018  progress  40 % (4 MB)
   58 08:33:50.093706  progress  45 % (4 MB)
   59 08:33:50.390291  progress  50 % (5 MB)
   60 08:33:50.688191  progress  55 % (6 MB)
   61 08:33:50.975389  progress  60 % (6 MB)
   62 08:33:51.270315  progress  65 % (7 MB)
   63 08:33:51.561826  progress  70 % (7 MB)
   64 08:33:51.853596  progress  75 % (8 MB)
   65 08:33:52.043970  progress  80 % (8 MB)
   66 08:33:52.340320  progress  85 % (9 MB)
   67 08:33:52.629315  progress  90 % (9 MB)
   68 08:33:52.924064  progress  95 % (10 MB)
   69 08:33:53.213464  progress 100 % (10 MB)
   70 08:33:53.214380  10 MB downloaded in 5.85 s (1.87 MB/s)
   71 08:33:53.216461  end: 1.2.1 http-download (duration 00:00:06) [common]
   73 08:33:53.218009  end: 1.2 download-retry (duration 00:00:06) [common]
   74 08:33:53.218522  start: 1.3 download-retry (timeout 00:09:52) [common]
   75 08:33:53.219035  start: 1.3.1 http-download (timeout 00:09:52) [common]
   76 08:33:53.219932  downloading http://storage.kernelci.org/next/master/next-20241031/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
   77 08:33:53.220282  saving as /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/dtb/am335x-boneblack.dtb
   78 08:33:53.220611  total size: 70544 (0 MB)
   79 08:33:53.220942  No compression specified
   80 08:33:53.380347  progress  46 % (0 MB)
   81 08:33:53.383284  progress  92 % (0 MB)
   82 08:33:53.384652  progress 100 % (0 MB)
   83 08:33:53.385240  0 MB downloaded in 0.16 s (0.41 MB/s)
   84 08:33:53.385849  end: 1.3.1 http-download (duration 00:00:00) [common]
   86 08:33:53.386937  end: 1.3 download-retry (duration 00:00:00) [common]
   87 08:33:53.387330  start: 1.4 download-retry (timeout 00:09:51) [common]
   88 08:33:53.387762  start: 1.4.1 http-download (timeout 00:09:51) [common]
   89 08:33:53.388335  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   90 08:33:53.388650  saving as /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/nfsrootfs/full.rootfs.tar
   91 08:33:53.388975  total size: 117747780 (112 MB)
   92 08:33:53.389337  Using unxz to decompress xz
   93 08:33:53.545153  progress   0 % (0 MB)
   94 08:33:56.717538  progress   5 % (5 MB)
   95 08:33:59.606935  progress  10 % (11 MB)
   96 08:34:02.435968  progress  15 % (16 MB)
   97 08:34:04.844455  progress  20 % (22 MB)
   98 08:34:06.717466  progress  25 % (28 MB)
   99 08:34:08.337288  progress  30 % (33 MB)
  100 08:34:10.281631  progress  35 % (39 MB)
  101 08:34:12.284713  progress  40 % (44 MB)
  102 08:34:14.190450  progress  45 % (50 MB)
  103 08:34:16.088064  progress  50 % (56 MB)
  104 08:34:17.969324  progress  55 % (61 MB)
  105 08:34:19.682987  progress  60 % (67 MB)
  106 08:34:21.437230  progress  65 % (73 MB)
  107 08:34:24.744150  progress  70 % (78 MB)
  108 08:34:28.031926  progress  75 % (84 MB)
  109 08:34:31.077496  progress  80 % (89 MB)
  110 08:34:33.629986  progress  85 % (95 MB)
  111 08:34:36.192847  progress  90 % (101 MB)
  112 08:34:38.963886  progress  95 % (106 MB)
  113 08:34:41.592498  progress 100 % (112 MB)
  114 08:34:41.594549  112 MB downloaded in 48.21 s (2.33 MB/s)
  115 08:34:41.594841  end: 1.4.1 http-download (duration 00:00:48) [common]
  117 08:34:41.595294  end: 1.4 download-retry (duration 00:00:48) [common]
  118 08:34:41.595457  start: 1.5 download-retry (timeout 00:09:03) [common]
  119 08:34:41.595638  start: 1.5.1 http-download (timeout 00:09:03) [common]
  120 08:34:41.595931  downloading http://storage.kernelci.org/next/master/next-20241031/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
  121 08:34:41.596062  saving as /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/modules/modules.tar
  122 08:34:41.596197  total size: 6619440 (6 MB)
  123 08:34:41.596322  Using unxz to decompress xz
  124 08:34:41.749507  progress   0 % (0 MB)
  125 08:34:42.075348  progress   5 % (0 MB)
  126 08:34:42.101054  progress  10 % (0 MB)
  127 08:34:42.217395  progress  15 % (0 MB)
  128 08:34:42.377524  progress  20 % (1 MB)
  129 08:34:42.655362  progress  25 % (1 MB)
  130 08:34:42.813892  progress  30 % (1 MB)
  131 08:34:42.969031  progress  35 % (2 MB)
  132 08:34:43.126720  progress  40 % (2 MB)
  133 08:34:43.399311  progress  45 % (2 MB)
  134 08:34:43.556150  progress  50 % (3 MB)
  135 08:34:43.708817  progress  55 % (3 MB)
  136 08:34:43.861971  progress  60 % (3 MB)
  137 08:34:44.013809  progress  65 % (4 MB)
  138 08:34:44.165609  progress  70 % (4 MB)
  139 08:34:44.318983  progress  75 % (4 MB)
  140 08:34:44.469629  progress  80 % (5 MB)
  141 08:34:44.620275  progress  85 % (5 MB)
  142 08:34:44.770325  progress  90 % (5 MB)
  143 08:34:44.920699  progress  95 % (6 MB)
  144 08:34:45.071247  progress 100 % (6 MB)
  145 08:34:45.074717  6 MB downloaded in 3.48 s (1.81 MB/s)
  146 08:34:45.075005  end: 1.5.1 http-download (duration 00:00:03) [common]
  148 08:34:45.075463  end: 1.5 download-retry (duration 00:00:03) [common]
  149 08:34:45.075672  start: 1.6 prepare-tftp-overlay (timeout 00:09:00) [common]
  150 08:34:45.075903  start: 1.6.1 extract-nfsrootfs (timeout 00:09:00) [common]
  151 08:34:52.337251  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1214309/extract-nfsrootfs-oe4lua6x
  152 08:34:52.337568  end: 1.6.1 extract-nfsrootfs (duration 00:00:07) [common]
  153 08:34:52.337724  start: 1.6.2 lava-overlay (timeout 00:08:52) [common]
  154 08:34:52.338044  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk
  155 08:34:52.338292  makedir: /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin
  156 08:34:52.338467  makedir: /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/tests
  157 08:34:52.338634  makedir: /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/results
  158 08:34:52.338800  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-add-keys
  159 08:34:52.339053  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-add-sources
  160 08:34:52.339279  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-background-process-start
  161 08:34:52.339507  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-background-process-stop
  162 08:34:52.339751  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-common-functions
  163 08:34:52.339977  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-echo-ipv4
  164 08:34:52.340200  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-install-packages
  165 08:34:52.340418  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-installed-packages
  166 08:34:52.340635  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-os-build
  167 08:34:52.340885  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-probe-channel
  168 08:34:52.341123  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-probe-ip
  169 08:34:52.341347  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-target-ip
  170 08:34:52.341567  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-target-mac
  171 08:34:52.341787  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-target-storage
  172 08:34:52.342025  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-test-case
  173 08:34:52.342247  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-test-event
  174 08:34:52.342464  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-test-feedback
  175 08:34:52.342683  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-test-raise
  176 08:34:52.342905  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-test-reference
  177 08:34:52.343126  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-test-runner
  178 08:34:52.343358  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-test-set
  179 08:34:52.343578  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-test-shell
  180 08:34:52.343801  Updating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-add-keys (debian)
  181 08:34:52.383486  Updating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-add-sources (debian)
  182 08:34:52.383803  Updating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-install-packages (debian)
  183 08:34:52.384071  Updating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-installed-packages (debian)
  184 08:34:52.384342  Updating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/bin/lava-os-build (debian)
  185 08:34:52.384564  Creating /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/environment
  186 08:34:52.384734  LAVA metadata
  187 08:34:52.384899  - LAVA_JOB_ID=1214309
  188 08:34:52.385018  - LAVA_DISPATCHER_IP=172.16.3.3
  189 08:34:52.385215  start: 1.6.2.1 ssh-authorize (timeout 00:08:52) [common]
  190 08:34:52.385668  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  191 08:34:52.385826  start: 1.6.2.2 lava-vland-overlay (timeout 00:08:52) [common]
  192 08:34:52.385937  skipped lava-vland-overlay
  193 08:34:52.386068  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  194 08:34:52.386206  start: 1.6.2.3 lava-multinode-overlay (timeout 00:08:52) [common]
  195 08:34:52.386322  skipped lava-multinode-overlay
  196 08:34:52.386453  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  197 08:34:52.386587  start: 1.6.2.4 test-definition (timeout 00:08:52) [common]
  198 08:34:52.386707  Loading test definitions
  199 08:34:52.386869  start: 1.6.2.4.1 inline-repo-action (timeout 00:08:52) [common]
  200 08:34:52.386989  Using /lava-1214309 at stage 0
  201 08:34:52.387593  uuid=1214309_1.6.2.4.1 testdef=None
  202 08:34:52.387753  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  203 08:34:52.387891  start: 1.6.2.4.2 test-overlay (timeout 00:08:52) [common]
  204 08:34:52.388713  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  206 08:34:52.389147  start: 1.6.2.4.3 test-install-overlay (timeout 00:08:52) [common]
  207 08:34:52.390081  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  209 08:34:52.390477  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:08:52) [common]
  210 08:34:52.407514  runner path: /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/0/tests/0_timesync-off test_uuid 1214309_1.6.2.4.1
  211 08:34:52.407813  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  213 08:34:52.408217  start: 1.6.2.4.5 git-repo-action (timeout 00:08:52) [common]
  214 08:34:52.408354  Using /lava-1214309 at stage 0
  215 08:34:52.408528  Fetching tests from https://github.com/kernelci/test-definitions.git
  216 08:34:52.408669  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/0/tests/1_kselftest-dt'
  217 08:34:58.098476  Running '/usr/bin/git checkout kernelci.org
  218 08:34:58.430204  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  219 08:34:58.431577  uuid=1214309_1.6.2.4.5 testdef=None
  220 08:34:58.431932  end: 1.6.2.4.5 git-repo-action (duration 00:00:06) [common]
  222 08:34:58.432722  start: 1.6.2.4.6 test-overlay (timeout 00:08:46) [common]
  223 08:34:58.435307  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  225 08:34:58.436129  start: 1.6.2.4.7 test-install-overlay (timeout 00:08:46) [common]
  226 08:34:58.439172  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  228 08:34:58.439947  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:08:46) [common]
  229 08:34:58.443061  runner path: /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/0/tests/1_kselftest-dt test_uuid 1214309_1.6.2.4.5
  230 08:34:58.443350  BOARD='beaglebone-black'
  231 08:34:58.443584  BRANCH='next'
  232 08:34:58.443809  SKIPFILE='/dev/null'
  233 08:34:58.444029  SKIP_INSTALL='True'
  234 08:34:58.444244  TESTPROG_URL='http://storage.kernelci.org/next/master/next-20241031/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
  235 08:34:58.444464  TST_CASENAME=''
  236 08:34:58.444678  TST_CMDFILES='dt'
  237 08:34:58.445104  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  239 08:34:58.445854  Creating lava-test-runner.conf files
  240 08:34:58.446076  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1214309/lava-overlay-f1fh53mk/lava-1214309/0 for stage 0
  241 08:34:58.446416  - 0_timesync-off
  242 08:34:58.446652  - 1_kselftest-dt
  243 08:34:58.447001  end: 1.6.2.4 test-definition (duration 00:00:06) [common]
  244 08:34:58.447293  start: 1.6.2.5 compress-overlay (timeout 00:08:46) [common]
  245 08:35:08.353228  end: 1.6.2.5 compress-overlay (duration 00:00:10) [common]
  246 08:35:08.353475  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:36) [common]
  247 08:35:08.353619  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  248 08:35:08.353767  end: 1.6.2 lava-overlay (duration 00:00:16) [common]
  249 08:35:08.353910  start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:36) [common]
  250 08:35:08.492184  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  251 08:35:08.492438  start: 1.6.4 extract-modules (timeout 00:08:36) [common]
  252 08:35:08.492585  extracting modules file /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1214309/extract-nfsrootfs-oe4lua6x
  253 08:35:08.889783  extracting modules file /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1214309/extract-overlay-ramdisk-lxzr7_h2/ramdisk
  254 08:35:09.273502  end: 1.6.4 extract-modules (duration 00:00:01) [common]
  255 08:35:09.273765  start: 1.6.5 apply-overlay-tftp (timeout 00:08:36) [common]
  256 08:35:09.273895  [common] Applying overlay to NFS
  257 08:35:09.274003  [common] Applying overlay /var/lib/lava/dispatcher/tmp/1214309/compress-overlay-cqgla4h5/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1214309/extract-nfsrootfs-oe4lua6x
  258 08:35:10.582639  end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
  259 08:35:10.582884  start: 1.6.6 prepare-kernel (timeout 00:08:34) [common]
  260 08:35:10.583027  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:34) [common]
  261 08:35:10.583171  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  262 08:35:10.583305  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  263 08:35:10.583443  start: 1.6.7 configure-preseed-file (timeout 00:08:34) [common]
  264 08:35:10.583572  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  265 08:35:10.583705  start: 1.6.8 compress-ramdisk (timeout 00:08:34) [common]
  266 08:35:10.583822  Building ramdisk /var/lib/lava/dispatcher/tmp/1214309/extract-overlay-ramdisk-lxzr7_h2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1214309/extract-overlay-ramdisk-lxzr7_h2/ramdisk
  267 08:35:10.897767  >> 75300 blocks

  268 08:35:13.007779  Adding RAMdisk u-boot header.
  269 08:35:13.008108  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1214309/extract-overlay-ramdisk-lxzr7_h2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1214309/extract-overlay-ramdisk-lxzr7_h2/ramdisk.cpio.gz.uboot
  270 08:35:13.257522  output: Image Name:   
  271 08:35:13.257873  output: Created:      Thu Oct 31 08:35:13 2024
  272 08:35:13.258129  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  273 08:35:13.258434  output: Data Size:    14833349 Bytes = 14485.69 KiB = 14.15 MiB
  274 08:35:13.258729  output: Load Address: 00000000
  275 08:35:13.259016  output: Entry Point:  00000000
  276 08:35:13.259304  output: 
  277 08:35:13.259786  rename /var/lib/lava/dispatcher/tmp/1214309/extract-overlay-ramdisk-lxzr7_h2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/ramdisk/ramdisk.cpio.gz.uboot
  278 08:35:13.260278  end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
  279 08:35:13.260686  end: 1.6 prepare-tftp-overlay (duration 00:00:28) [common]
  280 08:35:13.260965  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:32) [common]
  281 08:35:13.261136  No LXC device requested
  282 08:35:13.261507  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  283 08:35:13.261894  start: 1.8 deploy-device-env (timeout 00:08:32) [common]
  284 08:35:13.262269  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  285 08:35:13.262569  Checking files for TFTP limit of 4294967296 bytes.
  286 08:35:13.264446  end: 1 tftp-deploy (duration 00:01:28) [common]
  287 08:35:13.264866  start: 2 uboot-action (timeout 00:05:00) [common]
  288 08:35:13.265032  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  289 08:35:13.265362  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  290 08:35:13.265747  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  291 08:35:13.266299  substitutions:
  292 08:35:13.266607  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  293 08:35:13.266908  - {DTB_ADDR}: 0x88000000
  294 08:35:13.267199  - {DTB}: 1214309/tftp-deploy-z6iehxvg/dtb/am335x-boneblack.dtb
  295 08:35:13.267493  - {INITRD}: 1214309/tftp-deploy-z6iehxvg/ramdisk/ramdisk.cpio.gz.uboot
  296 08:35:13.267784  - {KERNEL_ADDR}: 0x82000000
  297 08:35:13.268069  - {KERNEL}: 1214309/tftp-deploy-z6iehxvg/kernel/zImage
  298 08:35:13.268353  - {LAVA_MAC}: None
  299 08:35:13.268652  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1214309/extract-nfsrootfs-oe4lua6x
  300 08:35:13.268902  - {NFS_SERVER_IP}: 172.16.3.3
  301 08:35:13.269015  - {PRESEED_CONFIG}: None
  302 08:35:13.269286  - {PRESEED_LOCAL}: None
  303 08:35:13.269565  - {RAMDISK_ADDR}: 0x83000000
  304 08:35:13.269845  - {RAMDISK}: 1214309/tftp-deploy-z6iehxvg/ramdisk/ramdisk.cpio.gz.uboot
  305 08:35:13.270126  - {ROOT_PART}: None
  306 08:35:13.270401  - {ROOT}: None
  307 08:35:13.270675  - {SERVER_IP}: 172.16.3.3
  308 08:35:13.270947  - {TEE_ADDR}: 0x83000000
  309 08:35:13.271221  - {TEE}: None
  310 08:35:13.271497  Parsed boot commands:
  311 08:35:13.271765  - setenv autoload no
  312 08:35:13.272038  - setenv initrd_high 0xffffffff
  313 08:35:13.272311  - setenv fdt_high 0xffffffff
  314 08:35:13.272582  - dhcp
  315 08:35:13.272866  - setenv serverip 172.16.3.3
  316 08:35:13.272976  - tftp 0x82000000 1214309/tftp-deploy-z6iehxvg/kernel/zImage
  317 08:35:13.273182  - tftp 0x83000000 1214309/tftp-deploy-z6iehxvg/ramdisk/ramdisk.cpio.gz.uboot
  318 08:35:13.273460  - setenv initrd_size ${filesize}
  319 08:35:13.273729  - tftp 0x88000000 1214309/tftp-deploy-z6iehxvg/dtb/am335x-boneblack.dtb
  320 08:35:13.274002  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214309/extract-nfsrootfs-oe4lua6x,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  321 08:35:13.274292  - bootz 0x82000000 0x83000000 0x88000000
  322 08:35:13.274652  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  324 08:35:13.275416  start: 2.3 connect-device (timeout 00:05:00) [common]
  325 08:35:13.275679  [common] connect-device Connecting to device using 'telnet ts5 2002'
  326 08:35:13.282561  Setting prompt string to ['lava-test: # ']
  327 08:35:13.283008  end: 2.3 connect-device (duration 00:00:00) [common]
  328 08:35:13.283198  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  329 08:35:13.283373  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  330 08:35:13.283542  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  331 08:35:13.283818  Calling: 'drpm' 'lf-bbb-02' 'powercycle'
  332 08:35:13.724866  >> OFF

  333 08:35:29.013403  >> ON

  334 08:35:29.014436  Returned 0 in 15 seconds
  335 08:35:29.115414  end: 2.4.1.1 pdu-reboot (duration 00:00:16) [common]
  337 08:35:29.116556  end: 2.4.1 reset-device (duration 00:00:16) [common]
  338 08:35:29.117017  start: 2.4.2 bootloader-interrupt (timeout 00:04:44) [common]
  339 08:35:29.117410  Setting prompt string to ['Hit any key to stop autoboot']
  340 08:35:29.117751  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  341 08:35:29.118684  Trying 192.168.1.205...
  342 08:35:29.118998  Connected to ts5.
  343 08:35:29.119288  Escape character is '^]'.
  344 08:35:29.119575  
  345 08:35:29.119864  ser2net port telnet,2002 device serialdev,/dev/ttyUSB-lf-bbb-02,115200n81,local [] (Debian GNU/Linux)
  346 08:35:29.120157  
  347 08:35:29.602610  
  348 08:35:29.611720  U-Boot SPL 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  349 08:35:29.612110  Trying to boot from MMC2
  350 08:35:30.124744  
  351 08:35:30.125168  
  352 08:35:30.129563  U-Boot 2021.10-nethacked-for-LAVA_hws@denx.de-dirty (Oct 19 2021 - 19:02:35 +0200)
  353 08:35:30.129953  
  354 08:35:30.130277  CPU  : AM335X-GP rev 2.1
  355 08:35:30.136264  Model: TI AM335x BeagleBone Black
  356 08:35:30.136657  DRAM:  512 MiB
  357 08:35:30.217322  WDT:   Started with servicing (60s timeout)
  358 08:35:30.622206  NAND:  0 MiB
  359 08:35:30.631605  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  360 08:35:30.666112  Loading Environment from FAT... <ethaddr> not set. Validating first E-fuse MAC
  361 08:35:30.696515  Net:   eth2: ethernet@4a100000, eth3: usb_ether
  362 08:35:30.754159  end: 2.4.2 bootloader-interrupt (duration 00:00:02) [common]
  363 08:35:30.754657  start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
  364 08:35:30.755031  Setting prompt string to ['=> ']
  365 08:35:30.755396  bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:43)
  366 08:35:30.764000  Hit any key to stop autoboot:  2   0 
  367 08:35:30.764768  Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  368 08:35:30.765188  Sending with 10 millisecond of delay
  370 08:35:31.900318  => setenv autoload no
  371 08:35:31.911002  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:41)
  372 08:35:31.914152  setenv autoload no
  373 08:35:31.914783  Sending with 10 millisecond of delay
  375 08:35:33.712483  => setenv initrd_high 0xffffffff
  376 08:35:33.723117  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:40)
  377 08:35:33.723734  setenv initrd_high 0xffffffff
  378 08:35:33.724306  Sending with 10 millisecond of delay
  380 08:35:35.343350  => setenv fdt_high 0xffffffff
  381 08:35:35.353965  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  382 08:35:35.354611  setenv fdt_high 0xffffffff
  383 08:35:35.355194  Sending with 10 millisecond of delay
  385 08:35:35.647016  => dhcp
  386 08:35:35.657560  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:38)
  387 08:35:35.658580  dhcp
  388 08:35:35.658909  link up on port 0, speed 100, full duplex
  389 08:35:35.659214  BOOTP broadcast 1
  390 08:35:35.725908  DHCP client bound to address 172.16.3.187 (61 ms)
  391 08:35:35.726537  Sending with 10 millisecond of delay
  393 08:35:37.344083  => setenv serverip 172.16.3.3
  394 08:35:37.354652  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:36)
  395 08:35:37.355285  setenv serverip 172.16.3.3
  396 08:35:37.355964  Sending with 10 millisecond of delay
  398 08:35:40.903579  => tftp 0x82000000 1214309/tftp-deploy-z6iehxvg/kernel/zImage
  399 08:35:40.914059  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
  400 08:35:40.914815  tftp 0x82000000 1214309/tftp-deploy-z6iehxvg/kernel/zImage
  401 08:35:40.914998  link up on port 0, speed 100, full duplex
  402 08:35:40.919717  Using ethernet@4a100000 device
  403 08:35:40.925911  TFTP from server 172.16.3.3; our IP address is 172.16.3.187
  404 08:35:40.932607  Filename '1214309/tftp-deploy-z6iehxvg/kernel/zImage'.
  405 08:35:40.932856  Load address: 0x82000000
  406 08:35:43.827058  Loading: *##################################################  11 MiB
  407 08:35:43.827549  	 3.8 MiB/s
  408 08:35:43.827860  done
  409 08:35:43.830436  Bytes transferred = 11502080 (af8200 hex)
  410 08:35:43.831078  Sending with 10 millisecond of delay
  412 08:35:48.345778  => tftp 0x83000000 1214309/tftp-deploy-z6iehxvg/ramdisk/ramdisk.cpio.gz.uboot
  413 08:35:48.356371  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:25)
  414 08:35:48.357351  tftp 0x83000000 1214309/tftp-deploy-z6iehxvg/ramdisk/ramdisk.cpio.gz.uboot
  415 08:35:48.357688  link up on port 0, speed 100, full duplex
  416 08:35:48.362464  Using ethernet@4a100000 device
  417 08:35:48.368376  TFTP from server 172.16.3.3; our IP address is 172.16.3.187
  418 08:35:48.376205  Filename '1214309/tftp-deploy-z6iehxvg/ramdisk/ramdisk.cpio.gz.uboot'.
  419 08:35:48.376527  Load address: 0x83000000
  420 08:35:52.175331  Loading: *##################################################  14.1 MiB
  421 08:35:52.175763  	 3.7 MiB/s
  422 08:35:52.176078  done
  423 08:35:52.178624  Bytes transferred = 14833413 (e25705 hex)
  424 08:35:52.179275  Sending with 10 millisecond of delay
  426 08:35:54.039370  => setenv initrd_size ${filesize}
  427 08:35:54.049984  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:19)
  428 08:35:54.050617  setenv initrd_size ${filesize}
  429 08:35:54.051180  Sending with 10 millisecond of delay
  431 08:35:58.263022  => tftp 0x88000000 1214309/tftp-deploy-z6iehxvg/dtb/am335x-boneblack.dtb
  432 08:35:58.273634  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
  433 08:35:58.275336  tftp 0x88000000 1214309/tftp-deploy-z6iehxvg/dtb/am335x-boneblack.dtb
  434 08:35:58.275724  link up on port 0, speed 100, full duplex
  435 08:35:58.279194  Using ethernet@4a100000 device
  436 08:35:58.285308  TFTP from server 172.16.3.3; our IP address is 172.16.3.187
  437 08:35:58.297298  Filename '1214309/tftp-deploy-z6iehxvg/dtb/am335x-boneblack.dtb'.
  438 08:35:58.297559  Load address: 0x88000000
  439 08:35:58.317450  Loading: *##################################################  68.9 KiB
  440 08:35:58.317842  	 3.1 MiB/s
  441 08:35:58.318158  done
  442 08:35:58.320709  Bytes transferred = 70544 (11390 hex)
  443 08:35:58.321250  Sending with 10 millisecond of delay
  445 08:36:11.700483  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214309/extract-nfsrootfs-oe4lua6x,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  446 08:36:11.711203  bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:02)
  447 08:36:11.711853  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214309/extract-nfsrootfs-oe4lua6x,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  448 08:36:11.712461  Sending with 10 millisecond of delay
  450 08:36:14.053962  => bootz 0x82000000 0x83000000 0x88000000
  451 08:36:14.064550  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  452 08:36:14.065033  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:03:59)
  453 08:36:14.065755  bootz 0x82000000 0x83000000 0x88000000
  454 08:36:14.066088  Kernel image @ 0x82000000 [ 0x000000 - 0xaf8200 ]
  455 08:36:14.068465  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  456 08:36:14.073455     Image Name:   
  457 08:36:14.073838     Created:      2024-10-31   8:35:13 UTC
  458 08:36:14.081067     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  459 08:36:14.081463     Data Size:    14833349 Bytes = 14.1 MiB
  460 08:36:14.087232     Load Address: 00000000
  461 08:36:14.087627     Entry Point:  00000000
  462 08:36:14.259369     Verifying Checksum ... OK
  463 08:36:14.259755  ## Flattened Device Tree blob at 88000000
  464 08:36:14.266694     Booting using the fdt blob at 0x88000000
  465 08:36:14.272272     Using Device Tree in place at 88000000, end 8801438f
  466 08:36:14.284348  
  467 08:36:14.284741  Starting kernel ...
  468 08:36:14.285081  
  469 08:36:14.285785  end: 2.4.3 bootloader-commands (duration 00:00:44) [common]
  470 08:36:14.286220  start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
  471 08:36:14.286575  Setting prompt string to ['Linux version [0-9]']
  472 08:36:14.286926  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
  473 08:36:14.287270  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
  474 08:36:15.130264  [    0.000000] Booting Linux on physical CPU 0x0
  475 08:36:15.135473  start: 2.4.4.1 login-action (timeout 00:03:58) [common]
  476 08:36:15.135900  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  477 08:36:15.136249  Setting prompt string to []
  478 08:36:15.136603  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  479 08:36:15.136974  Using line separator: #'\n'#
  480 08:36:15.137273  No login prompt set.
  481 08:36:15.137577  Parsing kernel messages
  482 08:36:15.137857  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  483 08:36:15.138373  [login-action] Waiting for messages, (timeout 00:03:58)
  484 08:36:15.153324  [    0.000000] Linux version 6.12.0-rc5-next-20241031 (KernelCI@build-j358071-arm-gcc-12-multi-v7-defconfig-klsj8) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Oct 31 07:52:56 UTC 2024
  485 08:36:15.162024  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  486 08:36:15.168122  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  487 08:36:15.174238  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  488 08:36:15.182797  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  489 08:36:15.189014  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  490 08:36:15.189397  [    0.000000] Memory policy: Data cache writeback
  491 08:36:15.195031  [    0.000000] efi: UEFI not found.
  492 08:36:15.197947  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  493 08:36:15.206836  [    0.000000] Zone ranges:
  494 08:36:15.213014  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  495 08:36:15.219106  [    0.000000]   Normal   empty
  496 08:36:15.219485  [    0.000000]   HighMem  empty
  497 08:36:15.221386  [    0.000000] Movable zone start for each node
  498 08:36:15.226402  [    0.000000] Early memory node ranges
  499 08:36:15.232510  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  500 08:36:15.240696  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  501 08:36:15.263228  [    0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
  502 08:36:15.274179  [    0.000000] CPU: All CPU(s) started in SVC mode.
  503 08:36:15.278717  [    0.000000] AM335X ES2.1 (sgx neon)
  504 08:36:15.291258  [    0.000000] percpu: Embedded 17 pages/cpu s39884 r8192 d21556 u69632
  505 08:36:15.312015  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=172.16.3.3:/var/lib/lava/dispatcher/tmp/1214309/extract-nfsrootfs-oe4lua6x,tcp,hard,v3 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  506 08:36:15.317156  <6>[    0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
  507 08:36:15.326776  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  508 08:36:15.338965  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  509 08:36:15.342537  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  510 08:36:15.350226  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  511 08:36:15.380105  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  512 08:36:15.386203  <6>[    0.000000] trace event string verifier disabled
  513 08:36:15.386588  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  514 08:36:15.393476  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  515 08:36:15.399539  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  516 08:36:15.405660  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.
  517 08:36:15.414229  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  518 08:36:15.420252  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  519 08:36:15.430062  <6>[    0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
  520 08:36:15.445611  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  521 08:36:15.463086  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  522 08:36:15.469779  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  523 08:36:15.561629  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  524 08:36:15.570033  <6>[    0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  525 08:36:15.581149  <6>[    0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  526 08:36:15.590994  <6>[    0.019148] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  527 08:36:15.599431  <6>[    0.033984] Console: colour dummy device 80x30
  528 08:36:15.605952  Matched prompt #6: WARNING:
  529 08:36:15.606362  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  530 08:36:15.611637  <3>[    0.038885] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  531 08:36:15.614120  <3>[    0.045955] This ensures that you still see kernel messages. Please
  532 08:36:15.621061  <3>[    0.052681] update your kernel commandline.
  533 08:36:15.660909  <6>[    0.057299] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  534 08:36:15.665913  <6>[    0.096159] CPU: Testing write buffer coherency: ok
  535 08:36:15.669378  <6>[    0.101528] CPU0: Spectre v2: using BPIALL workaround
  536 08:36:15.674502  <6>[    0.106994] pid_max: default: 32768 minimum: 301
  537 08:36:15.680721  <6>[    0.112199] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  538 08:36:15.690266  <6>[    0.120025] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  539 08:36:15.697574  <6>[    0.129394] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  540 08:36:15.710767  <6>[    0.136552] Setting up static identity map for 0x80300000 - 0x803000ac
  541 08:36:15.715956  <6>[    0.146196] rcu: Hierarchical SRCU implementation.
  542 08:36:15.720265  <6>[    0.151479] rcu: 	Max phase no-delay instances is 1000.
  543 08:36:15.728714  <6>[    0.162558] EFI services will not be available.
  544 08:36:15.734944  <6>[    0.167840] smp: Bringing up secondary CPUs ...
  545 08:36:15.741181  <6>[    0.172884] smp: Brought up 1 node, 1 CPU
  546 08:36:15.748336  <6>[    0.177284] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  547 08:36:15.754715  <6>[    0.184056] CPU: All CPU(s) started in SVC mode.
  548 08:36:15.772119  <6>[    0.189234] Memory: 405952K/522240K available (16384K kernel code, 2544K rwdata, 6824K rodata, 2048K init, 429K bss, 49092K reserved, 65536K cma-reserved, 0K highmem)
  549 08:36:15.772525  <6>[    0.205517] devtmpfs: initialized
  550 08:36:15.795214  <6>[    0.222767] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  551 08:36:15.803606  <6>[    0.231344] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  552 08:36:15.811822  <6>[    0.241799] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  553 08:36:15.822583  <6>[    0.254111] pinctrl core: initialized pinctrl subsystem
  554 08:36:15.833058  <6>[    0.264768] DMI not present or invalid.
  555 08:36:15.840243  <6>[    0.270661] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  556 08:36:15.848649  <6>[    0.279654] DMA: preallocated 256 KiB pool for atomic coherent allocations
  557 08:36:15.864977  <6>[    0.291178] thermal_sys: Registered thermal governor 'step_wise'
  558 08:36:15.865360  <6>[    0.291341] cpuidle: using governor menu
  559 08:36:15.892467  <6>[    0.326861] No ATAGs?
  560 08:36:15.898154  <6>[    0.329593] hw-breakpoint: debug architecture 0x4 unsupported.
  561 08:36:15.907725  <6>[    0.341547] Serial: AMBA PL011 UART driver
  562 08:36:15.941143  <6>[    0.375044] iommu: Default domain type: Translated
  563 08:36:15.950569  <6>[    0.380388] iommu: DMA domain TLB invalidation policy: strict mode
  564 08:36:15.978088  <5>[    0.410986] SCSI subsystem initialized
  565 08:36:15.984226  <6>[    0.415873] usbcore: registered new interface driver usbfs
  566 08:36:15.989249  <6>[    0.421899] usbcore: registered new interface driver hub
  567 08:36:15.997696  <6>[    0.427683] usbcore: registered new device driver usb
  568 08:36:16.003967  <6>[    0.434177] pps_core: LinuxPPS API ver. 1 registered
  569 08:36:16.010070  <6>[    0.439606] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  570 08:36:16.016218  <6>[    0.449290] PTP clock support registered
  571 08:36:16.020509  <6>[    0.453751] EDAC MC: Ver: 3.0.0
  572 08:36:16.070169  <6>[    0.502039] scmi_core: SCMI protocol bus registered
  573 08:36:16.086106  <6>[    0.519512] vgaarb: loaded
  574 08:36:16.091084  <6>[    0.523289] clocksource: Switched to clocksource dmtimer
  575 08:36:16.125564  <6>[    0.559810] NET: Registered PF_INET protocol family
  576 08:36:16.138948  <6>[    0.565523] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  577 08:36:16.145192  <6>[    0.574377] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  578 08:36:16.156212  <6>[    0.583302] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  579 08:36:16.160714  <6>[    0.591547] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  580 08:36:16.172231  <6>[    0.599832] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  581 08:36:16.178364  <6>[    0.607549] TCP: Hash tables configured (established 4096 bind 4096)
  582 08:36:16.187108  <6>[    0.614469] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  583 08:36:16.193225  <6>[    0.621478] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  584 08:36:16.198705  <6>[    0.629104] NET: Registered PF_UNIX/PF_LOCAL protocol family
  585 08:36:16.285211  <6>[    0.713137] RPC: Registered named UNIX socket transport module.
  586 08:36:16.285594  <6>[    0.719569] RPC: Registered udp transport module.
  587 08:36:16.290134  <6>[    0.724691] RPC: Registered tcp transport module.
  588 08:36:16.298949  <6>[    0.729796] RPC: Registered tcp-with-tls transport module.
  589 08:36:16.305131  <6>[    0.735723] RPC: Registered tcp NFSv4.1 backchannel transport module.
  590 08:36:16.311484  <6>[    0.742632] PCI: CLS 0 bytes, default 64
  591 08:36:16.316972  <5>[    0.748416] Initialise system trusted keyrings
  592 08:36:16.337420  <6>[    0.768626] Trying to unpack rootfs image as initramfs...
  593 08:36:16.415377  <6>[    0.843624] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  594 08:36:16.420895  <6>[    0.851153] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  595 08:36:16.459951  <5>[    0.893999] NFS: Registering the id_resolver key type
  596 08:36:16.466269  <5>[    0.899585] Key type id_resolver registered
  597 08:36:16.471315  <5>[    0.904227] Key type id_legacy registered
  598 08:36:16.480081  <6>[    0.908665] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  599 08:36:16.485993  <6>[    0.915856] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  600 08:36:16.555583  <5>[    0.989449] Key type asymmetric registered
  601 08:36:16.560449  <5>[    0.994016] Asymmetric key parser 'x509' registered
  602 08:36:16.570303  <6>[    0.999436] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  603 08:36:16.575588  <6>[    1.007362] io scheduler mq-deadline registered
  604 08:36:16.583450  <6>[    1.012294] io scheduler kyber registered
  605 08:36:16.583834  <6>[    1.016780] io scheduler bfq registered
  606 08:36:16.673321  <6>[    1.103924] ledtrig-cpu: registered to indicate activity on CPUs
  607 08:36:16.965835  <6>[    1.396088] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  608 08:36:17.014486  <6>[    1.448620] msm_serial: driver initialized
  609 08:36:17.020609  <6>[    1.453628] SuperH (H)SCI(F) driver initialized
  610 08:36:17.026856  <6>[    1.458756] STMicroelectronics ASC driver initialized
  611 08:36:17.029135  <6>[    1.464429] STM32 USART driver initialized
  612 08:36:17.142746  <6>[    1.577231] brd: module loaded
  613 08:36:17.176685  <6>[    1.610784] loop: module loaded
  614 08:36:17.217436  <6>[    1.651317] CAN device driver interface
  615 08:36:17.224743  <6>[    1.656600] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  616 08:36:17.231090  <6>[    1.663728] e1000e: Intel(R) PRO/1000 Network Driver
  617 08:36:17.237191  <6>[    1.669115] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  618 08:36:17.243360  <6>[    1.675584] igb: Intel(R) Gigabit Ethernet Network Driver
  619 08:36:17.249419  <6>[    1.681406] igb: Copyright (c) 2007-2014 Intel Corporation.
  620 08:36:17.262726  <6>[    1.690980] pegasus: Pegasus/Pegasus II USB Ethernet driver
  621 08:36:17.269086  <6>[    1.697142] usbcore: registered new interface driver pegasus
  622 08:36:17.271329  <6>[    1.703303] usbcore: registered new interface driver asix
  623 08:36:17.276374  <6>[    1.709155] usbcore: registered new interface driver ax88179_178a
  624 08:36:17.282640  <6>[    1.715747] usbcore: registered new interface driver cdc_ether
  625 08:36:17.288761  <6>[    1.722043] usbcore: registered new interface driver smsc75xx
  626 08:36:17.297282  <6>[    1.728268] usbcore: registered new interface driver smsc95xx
  627 08:36:17.303429  <6>[    1.734496] usbcore: registered new interface driver net1080
  628 08:36:17.309573  <6>[    1.740620] usbcore: registered new interface driver cdc_subset
  629 08:36:17.318204  <6>[    1.747029] usbcore: registered new interface driver zaurus
  630 08:36:17.321449  <6>[    1.753081] usbcore: registered new interface driver cdc_ncm
  631 08:36:17.332192  <6>[    1.762846] usbcore: registered new interface driver usb-storage
  632 08:36:17.341452  <6>[    1.774573] i2c_dev: i2c /dev entries driver
  633 08:36:17.367567  <5>[    1.793795] cpuidle: enable-method property 'ti,am3352' found operations
  634 08:36:17.373582  <6>[    1.803149] sdhci: Secure Digital Host Controller Interface driver
  635 08:36:17.381208  <6>[    1.809926] sdhci: Copyright(c) Pierre Ossman
  636 08:36:17.387124  <6>[    1.816449] Synopsys Designware Multimedia Card Interface Driver
  637 08:36:17.392953  <6>[    1.824454] sdhci-pltfm: SDHCI platform and OF driver helper
  638 08:36:17.408161  <6>[    1.834409] usbcore: registered new interface driver usbhid
  639 08:36:17.408545  <6>[    1.840434] usbhid: USB HID core driver
  640 08:36:17.420698  <6>[    1.852110] NET: Registered PF_INET6 protocol family
  641 08:36:17.891187  <6>[    2.325408] Segment Routing with IPv6
  642 08:36:17.897308  <6>[    2.329561] In-situ OAM (IOAM) with IPv6
  643 08:36:17.903500  <6>[    2.334092] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  644 08:36:17.910891  <6>[    2.341352] NET: Registered PF_PACKET protocol family
  645 08:36:17.917028  <6>[    2.346930] can: controller area network core
  646 08:36:17.923080  <6>[    2.351751] NET: Registered PF_CAN protocol family
  647 08:36:17.923461  <6>[    2.356979] can: raw protocol
  648 08:36:17.926612  <6>[    2.360305] can: broadcast manager protocol
  649 08:36:17.932932  <6>[    2.364902] can: netlink gateway - max_hops=1
  650 08:36:17.939008  <5>[    2.370398] Key type dns_resolver registered
  651 08:36:17.945112  <6>[    2.375463] ThumbEE CPU extension supported.
  652 08:36:17.947448  <5>[    2.380156] Registering SWP/SWPB emulation handler
  653 08:36:17.955567  <3>[    2.385848] omap_voltage_late_init: Voltage driver support not added
  654 08:36:18.151634  <5>[    2.583882] Loading compiled-in X.509 certificates
  655 08:36:18.292914  <6>[    2.714099] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  656 08:36:18.299620  <6>[    2.730711] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  657 08:36:18.326532  <3>[    2.754602] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  658 08:36:18.505139  <3>[    2.932745] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  659 08:36:18.701159  <6>[    3.134639] OMAP GPIO hardware version 0.1
  660 08:36:18.722465  <6>[    3.153220] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  661 08:36:18.825739  <4>[    3.256258] at24 2-0054: supply vcc not found, using dummy regulator
  662 08:36:18.877533  <4>[    3.307688] at24 2-0055: supply vcc not found, using dummy regulator
  663 08:36:18.924156  <4>[    3.353562] at24 2-0056: supply vcc not found, using dummy regulator
  664 08:36:18.961333  <4>[    3.391761] at24 2-0057: supply vcc not found, using dummy regulator
  665 08:36:18.998167  <6>[    3.429223] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  666 08:36:19.072535  <3>[    3.499668] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  667 08:36:19.096648  <6>[    3.520415] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  668 08:36:19.119971  <4>[    3.546680] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  669 08:36:19.126773  <4>[    3.555906] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  670 08:36:19.283407  <6>[    3.713774] omap_rng 48310000.rng: Random Number Generator ver. 20
  671 08:36:19.307253  <5>[    3.739863] random: crng init done
  672 08:36:19.365305  <6>[    3.800106] Freeing initrd memory: 14488K
  673 08:36:19.375775  <6>[    3.804871] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  674 08:36:19.422962  <6>[    3.851437] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  675 08:36:19.433959  <6>[    3.861803] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  676 08:36:19.440045  <6>[    3.869158] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  677 08:36:19.445090  <6>[    3.876661] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  678 08:36:19.456063  <6>[    3.884792] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  679 08:36:19.469508  <6>[    3.896429] cpsw-switch 4a100000.switch: Detected MACID = 04:79:b7:e7:06:e0
  680 08:36:19.478747  <5>[    3.905436] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  681 08:36:19.505966  <3>[    3.935227] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  682 08:36:19.512773  <6>[    3.943767] edma 49000000.dma: TI EDMA DMA engine driver
  683 08:36:19.584219  <3>[    4.011271] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  684 08:36:19.598409  <6>[    4.026003] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  685 08:36:19.612088  <3>[    4.043017] l3-aon-clkctrl:0000:0: failed to disable
  686 08:36:19.656175  <6>[    4.084471] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  687 08:36:19.661114  <6>[    4.093936] printk: legacy console [ttyS0] enabled
  688 08:36:19.664664  <6>[    4.093936] printk: legacy console [ttyS0] enabled
  689 08:36:19.675718  <6>[    4.104261] printk: legacy bootconsole [omap8250] disabled
  690 08:36:19.678033  <6>[    4.104261] printk: legacy bootconsole [omap8250] disabled
  691 08:36:19.716671  <4>[    4.144088] tps65217-pmic: Failed to locate of_node [id: -1]
  692 08:36:19.719878  <4>[    4.151463] tps65217-bl: Failed to locate of_node [id: -1]
  693 08:36:19.736662  <6>[    4.170985] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  694 08:36:19.754960  <6>[    4.177919] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  695 08:36:19.764763  <6>[    4.191645] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  696 08:36:19.771990  <6>[    4.203546] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  697 08:36:19.795756  <6>[    4.224714] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  698 08:36:19.801922  <6>[    4.233878] sdhci-omap 48060000.mmc: Got CD GPIO
  699 08:36:19.809875  <4>[    4.239001] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  700 08:36:19.825719  <4>[    4.252243] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  701 08:36:19.831951  <4>[    4.262851] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  702 08:36:19.842505  <4>[    4.271978] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  703 08:36:19.964270  <6>[    4.393703] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  704 08:36:20.012121  <6>[    4.440525] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  705 08:36:20.045718  <6>[    4.474329] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  706 08:36:20.052382  <6>[    4.483002] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  707 08:36:20.120736  <6>[    4.544826] mmc1: new high speed MMC card at address 0001
  708 08:36:20.121145  <6>[    4.553424] mmcblk1: mmc1:0001 M62704 3.56 GiB
  709 08:36:20.132514  <6>[    4.564880]  mmcblk1: p1
  710 08:36:20.136971  <6>[    4.569478] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
  711 08:36:20.149697  <6>[    4.577715] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  712 08:36:20.156506  <6>[    4.589025] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
  713 08:36:20.174523  <6>[    4.604917] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
  714 08:36:22.255175  <6>[    6.684339] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  715 08:36:22.358564  <5>[    6.713315] Sending DHCP requests ., OK
  716 08:36:22.370759  <6>[    6.797726] IP-Config: Got DHCP answer from 172.16.3.3, my address is 172.16.3.187
  717 08:36:22.371156  <6>[    6.805816] IP-Config: Complete:
  718 08:36:22.384126  <6>[    6.809358]      device=eth0, hwaddr=04:79:b7:e7:06:e0, ipaddr=172.16.3.187, mask=255.255.255.0, gw=172.16.3.3
  719 08:36:22.389101  <6>[    6.819782]      host=172.16.3.187, domain=denx.de, nis-domain=(none)
  720 08:36:22.398825  <6>[    6.826601]      bootserver=172.16.3.33, rootserver=172.16.3.3, rootpath=
  721 08:36:22.399208  <6>[    6.826635]      nameserver0=172.16.3.3
  722 08:36:22.405053  <6>[    6.837941]      ntpserver0=172.16.3.3
  723 08:36:22.411029  <6>[    6.843512] clk: Disabling unused clocks
  724 08:36:22.414680  <6>[    6.848126] PM: genpd: Disabling unused power domains
  725 08:36:22.436040  <6>[    6.866643] Freeing unused kernel image (initmem) memory: 2048K
  726 08:36:22.442815  <6>[    6.876364] Run /init as init process
  727 08:36:22.465445  Loading, please wait...
  728 08:36:22.541445  Starting systemd-udevd version 252.22-1~deb12u1
  729 08:36:25.535030  <4>[    9.961836] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  730 08:36:25.698214  <4>[   10.124874] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  731 08:36:25.867068  <6>[   10.302575] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  732 08:36:25.878821  <6>[   10.308457] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  733 08:36:26.109326  <6>[   10.543223] hub 1-0:1.0: USB hub found
  734 08:36:26.171499  <6>[   10.604503] hub 1-0:1.0: 1 port detected
  735 08:36:26.284306  <6>[   10.717464] tda998x 0-0070: found TDA19988
  736 08:36:29.396077  Begin: Loading essential drivers ... done.
  737 08:36:29.402408  Begin: Running /scripts/init-premount ... done.
  738 08:36:29.408408  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  739 08:36:29.422689  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  740 08:36:29.423075  Device /sys/class/net/eth0 found
  741 08:36:29.423379  done.
  742 08:36:29.482243  Begin: Waiting up to 180 secs for any network device to become available ... done.
  743 08:36:29.552016  IP-Config: eth0 hardware address 04:79:b7:e7:06:e0 mtu 1500 DHCP
  744 08:36:29.636462  IP-Config: eth0 complete (dhcp from 172.16.3.3):
  745 08:36:29.647530   address: 172.16.3.187     broadcast: 172.16.3.255     netmask: 255.255.255.0   
  746 08:36:29.651012   gateway: 172.16.3.3       dns0     : 172.16.3.3       dns1   : 0.0.0.0         
  747 08:36:29.656027   domain : denx.de                                                         
  748 08:36:29.662177   rootserver: 172.16.3.33 rootpath: 
  749 08:36:29.666472   filename  : this-host-is-not-configured.kpxe
  750 08:36:29.710090  done.
  751 08:36:29.718697  Begin: Running /scripts/nfs-bottom ... done.
  752 08:36:29.783519  Begin: Running /scripts/init-bottom ... done.
  753 08:36:31.325770  <30>[   15.756025] systemd[1]: System time before build time, advancing clock.
  754 08:36:31.503605  <30>[   15.908592] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  755 08:36:31.511883  <30>[   15.945355] systemd[1]: Detected architecture arm.
  756 08:36:31.525359  
  757 08:36:31.525744  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  758 08:36:31.526060  
  759 08:36:31.552916  <30>[   15.984030] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  760 08:36:33.884238  <30>[   18.314426] systemd[1]: Queued start job for default target graphical.target.
  761 08:36:33.900765  <30>[   18.329057] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  762 08:36:33.907710  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  763 08:36:33.941268  <30>[   18.369164] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  764 08:36:33.948317  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  765 08:36:33.978092  <30>[   18.406114] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  766 08:36:33.985395  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  767 08:36:34.018973  <30>[   18.447090] systemd[1]: Created slice user.slice - User and Session Slice.
  768 08:36:34.025674  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  769 08:36:34.051702  <30>[   18.474537] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  770 08:36:34.057311  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  771 08:36:34.075098  <30>[   18.504402] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  772 08:36:34.086811  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  773 08:36:34.113992  <30>[   18.534452] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  774 08:36:34.126308  <30>[   18.554942] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  775 08:36:34.131906           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  776 08:36:34.154906  <30>[   18.583869] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  777 08:36:34.163573  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  778 08:36:34.185162  <30>[   18.614111] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  779 08:36:34.193487  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  780 08:36:34.215247  <30>[   18.644335] systemd[1]: Reached target paths.target - Path Units.
  781 08:36:34.220871  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  782 08:36:34.245093  <30>[   18.673953] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  783 08:36:34.253021  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  784 08:36:34.274049  <30>[   18.703851] systemd[1]: Reached target slices.target - Slice Units.
  785 08:36:34.280682  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  786 08:36:34.304998  <30>[   18.734078] systemd[1]: Reached target swap.target - Swaps.
  787 08:36:34.309247  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  788 08:36:34.335675  <30>[   18.764064] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  789 08:36:34.345036  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  790 08:36:34.365973  <30>[   18.794889] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  791 08:36:34.375926  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  792 08:36:34.456501  <30>[   18.880741] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  793 08:36:34.468943  <30>[   18.898308] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  794 08:36:34.479377  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  795 08:36:34.506801  <30>[   18.935037] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  796 08:36:34.513752  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  797 08:36:34.537966  <30>[   18.967076] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  798 08:36:34.546256  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  799 08:36:34.570321  <30>[   18.998555] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  800 08:36:34.575283  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  801 08:36:34.606651  <30>[   19.036710] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  802 08:36:34.620222  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  803 08:36:34.652757  <30>[   19.075055] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  804 08:36:34.669266  <30>[   19.091749] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  805 08:36:34.720248  <30>[   19.150351] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  806 08:36:34.749152           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  807 08:36:34.807438  <30>[   19.237349] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  808 08:36:34.832021           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  809 08:36:34.888385  <30>[   19.316718] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  810 08:36:34.908503           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  811 08:36:34.975184  <30>[   19.404739] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  812 08:36:34.996767           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  813 08:36:35.055177  <30>[   19.486157] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  814 08:36:35.082707           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  815 08:36:35.136817  <30>[   19.566799] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  816 08:36:35.170505           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  817 08:36:35.228025  <30>[   19.657426] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  818 08:36:35.247277           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  819 08:36:35.298196  <30>[   19.726970] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  820 08:36:35.312065           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  821 08:36:35.347602  <30>[   19.778119] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  822 08:36:35.369732           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  823 08:36:35.402043  <28>[   19.825521] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  824 08:36:35.410031  <28>[   19.839907] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  825 08:36:35.454541  <30>[   19.884730] systemd[1]: Starting systemd-journald.service - Journal Service...
  826 08:36:35.472841           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  827 08:36:35.555490  <30>[   19.985241] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  828 08:36:35.587218           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  829 08:36:35.647009  <30>[   20.077216] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  830 08:36:35.686330           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  831 08:36:35.762622  <30>[   20.191010] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  832 08:36:35.809256           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  833 08:36:35.862307  <30>[   20.291753] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  834 08:36:35.915183           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  835 08:36:35.976635  <30>[   20.407036] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  836 08:36:36.028988  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  837 08:36:36.045322  <30>[   20.475562] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  838 08:36:36.077487  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  839 08:36:36.097782  <30>[   20.526673] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  840 08:36:36.130833  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  841 08:36:36.298000  <30>[   20.727683] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  842 08:36:36.335173  <30>[   20.765240] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  843 08:36:36.354437  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  844 08:36:36.375366  <30>[   20.805074] systemd[1]: Started systemd-journald.service - Journal Service.
  845 08:36:36.382717  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  846 08:36:36.416455  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  847 08:36:36.447471  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  848 08:36:36.471010  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  849 08:36:36.506131  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  850 08:36:36.539097  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  851 08:36:36.574206  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  852 08:36:36.605081  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  853 08:36:36.628748  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  854 08:36:36.659636  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  855 08:36:36.728428           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  856 08:36:36.777212           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  857 08:36:36.840081           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  858 08:36:36.919021           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  859 08:36:36.985793           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  860 08:36:37.119145  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  861 08:36:37.174266  <46>[   21.604247] systemd-journald[163]: Received client request to flush runtime journal.
  862 08:36:37.359308  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  863 08:36:37.402893  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  864 08:36:37.464889           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  865 08:36:37.499474  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  866 08:36:38.806188  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  867 08:36:38.825468  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  868 08:36:38.854089  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  869 08:36:39.094996           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  870 08:36:39.228390  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  871 08:36:39.287757           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  872 08:36:40.056434  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  873 08:36:40.113367           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  874 08:36:41.437144  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  875 08:36:42.391138  [[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  876 08:36:43.198408  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  877 08:36:43.270703  <5>[   27.702133] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  878 08:36:44.434493  <5>[   28.866975] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  879 08:36:44.496917  <5>[   28.926883] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  880 08:36:44.533546  <4>[   28.963888] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  881 08:36:44.538493  <6>[   28.972871] cfg80211: failed to load regulatory.db
  882 08:36:45.276910  [[0m[0;31m*     [0m] Job systemd-networkd.service/start running (11s / 1min 36s)
  883 08:36:45.380502  M[K[[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  884 08:36:52.709065  [K[[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  885 08:36:52.736868  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  886 08:36:52.756152  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  887 08:36:52.823924           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  888 08:36:52.886534           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  889 08:36:52.964857           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  890 08:36:53.009545           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  891 08:36:53.214592           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  892 08:36:53.243378           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  893 08:36:53.286940  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  894 08:36:53.334854  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  895 08:36:53.364824  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  896 08:36:53.398831  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  897 08:36:53.596549  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  898 08:36:54.077084  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  899 08:36:54.106008  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  900 08:36:54.126355  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  901 08:36:54.145794  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  902 08:36:54.364442  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  903 08:36:54.451218  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  904 08:36:54.475960  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  905 08:36:54.553339  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  906 08:36:54.645387  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  907 08:36:54.663647  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  908 08:36:54.690293  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  909 08:36:54.715915  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  910 08:36:54.737354  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  911 08:36:54.799926           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  912 08:36:54.848527           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  913 08:36:54.995361           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  914 08:36:55.212878           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  915 08:36:55.254226           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  916 08:36:55.284024  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  917 08:36:55.405847  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  918 08:36:55.441955  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  919 08:36:55.503741  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  920 08:36:55.573328  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  921 08:36:55.642407  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  922 08:36:55.664971  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  923 08:36:55.804244           Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
  924 08:36:55.897392  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  925 08:36:56.402758  [[0;32m  OK  [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
  926 08:36:56.498567  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  927 08:36:56.551617  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  928 08:36:56.581367  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  929 08:36:56.669293           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  930 08:36:56.882961  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  931 08:36:57.089994  
  932 08:36:57.090379  Debian GNU/Linux 12 debian-bookworm-armhf t
  933 08:36:57.096768  debian-bookworm-armhf login: root (automatic login)
  934 08:36:57.097185  
  935 08:36:57.471112  Linux debian-bookworm-armhf 6.12.0-rc5-next-20241031 #1 SMP Thu Oct 31 07:52:56 UTC 2024 armv7l
  936 08:36:57.471496  
  937 08:36:57.477204  The programs included with the Debian GNU/Linux system are free software;
  938 08:36:57.485744  the exact distribution terms for each program are described in the
  939 08:36:57.491773  individual files in /usr/share/doc/*/copyright.
  940 08:36:57.492161  
  941 08:36:57.497290  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  942 08:36:57.497674  permitted by applicable law.
  943 08:37:02.332280  Unable to match end of the kernel message
  945 08:37:02.333350  Setting prompt string to ['/ #']
  946 08:37:02.333776  end: 2.4.4.1 login-action (duration 00:00:47) [common]
  948 08:37:02.334711  end: 2.4.4 auto-login-action (duration 00:00:48) [common]
  949 08:37:02.335134  start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
  950 08:37:02.335489  Setting prompt string to ['/ #']
  951 08:37:02.335787  Forcing a shell prompt, looking for ['/ #']
  953 08:37:02.386545  / # 
  954 08:37:02.387062  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  955 08:37:02.387428  Waiting using forced prompt support (timeout 00:02:30)
  956 08:37:02.394053  
  957 08:37:02.403194  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  958 08:37:02.403681  start: 2.4.6 export-device-env (timeout 00:03:11) [common]
  959 08:37:02.404062  Sending with 10 millisecond of delay
  961 08:37:07.458391  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1214309/extract-nfsrootfs-oe4lua6x'
  962 08:37:07.469119  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1214309/extract-nfsrootfs-oe4lua6x'
  963 08:37:07.471946  Sending with 10 millisecond of delay
  965 08:37:09.512283  / # export NFS_SERVER_IP='172.16.3.3'
  966 08:37:09.522947  export NFS_SERVER_IP='172.16.3.3'
  967 08:37:09.526555  end: 2.4.6 export-device-env (duration 00:00:07) [common]
  968 08:37:09.527036  end: 2.4 uboot-commands (duration 00:01:56) [common]
  969 08:37:09.527484  end: 2 uboot-action (duration 00:01:56) [common]
  970 08:37:09.527914  start: 3 lava-test-retry (timeout 00:06:35) [common]
  971 08:37:09.528356  start: 3.1 lava-test-shell (timeout 00:06:35) [common]
  972 08:37:09.528699  Using namespace: common
  974 08:37:09.629688  / # #
  975 08:37:09.630193  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
  976 08:37:09.637470  #
  977 08:37:09.643332  Using /lava-1214309
  979 08:37:09.744355  / # export SHELL=/bin/bash
  980 08:37:09.751526  export SHELL=/bin/bash
  982 08:37:09.859103  / # . /lava-1214309/environment
  983 08:37:09.866807  . /lava-1214309/environment
  985 08:37:09.979729  / # /lava-1214309/bin/lava-test-runner /lava-1214309/0
  986 08:37:09.980240  Test shell timeout: 10s (minimum of the action and connection timeout)
  987 08:37:09.987394  /lava-1214309/bin/lava-test-runner /lava-1214309/0
  988 08:37:10.545880  + export TESTRUN_ID=0_timesync-off
  989 08:37:10.553819  + TESTRUN_ID=0_timesync-off
  990 08:37:10.554207  + cd /lava-1214309/0/tests/0_timesync-off
  991 08:37:10.554524  ++ cat uuid
  992 08:37:10.577993  + UUID=1214309_1.6.2.4.1
  993 08:37:10.578383  + set +x
  994 08:37:10.582907  <LAVA_SIGNAL_STARTRUN 0_timesync-off 1214309_1.6.2.4.1>
  995 08:37:10.583546  Received signal: <STARTRUN> 0_timesync-off 1214309_1.6.2.4.1
  996 08:37:10.583888  Starting test lava.0_timesync-off (1214309_1.6.2.4.1)
  997 08:37:10.584264  Skipping test definition patterns.
  998 08:37:10.586192  + systemctl stop systemd-timesyncd
  999 08:37:10.897755  + set +x
 1000 08:37:10.898375  Received signal: <ENDRUN> 0_timesync-off 1214309_1.6.2.4.1
 1001 08:37:10.898752  Ending use of test pattern.
 1002 08:37:10.899053  Ending test lava.0_timesync-off (1214309_1.6.2.4.1), duration 0.32
 1004 08:37:10.900827  <LAVA_SIGNAL_ENDRUN 0_timesync-off 1214309_1.6.2.4.1>
 1005 08:37:11.235526  + export TESTRUN_ID=1_kselftest-dt
 1006 08:37:11.243526  + TESTRUN_ID=1_kselftest-dt
 1007 08:37:11.243912  + cd /lava-1214309/0/tests/1_kselftest-dt
 1008 08:37:11.244228  ++ cat uuid
 1009 08:37:11.265614  + UUID=1214309_1.6.2.4.5
 1010 08:37:11.266001  + set +x
 1011 08:37:11.270591  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1214309_1.6.2.4.5>
 1012 08:37:11.270974  + cd ./automated/linux/kselftest/
 1013 08:37:11.271528  Received signal: <STARTRUN> 1_kselftest-dt 1214309_1.6.2.4.5
 1014 08:37:11.271846  Starting test lava.1_kselftest-dt (1214309_1.6.2.4.5)
 1015 08:37:11.272213  Skipping test definition patterns.
 1016 08:37:11.296907  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/master/next-20241031/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1017 08:37:11.456820  INFO: install_deps skipped
 1018 08:37:12.171107  --2024-01-26 21:49:16--  http://storage.kernelci.org/next/master/next-20241031/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
 1019 08:37:12.231767  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1020 08:37:12.391258  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1021 08:37:12.547632  HTTP request sent, awaiting response... 200 OK
 1022 08:37:12.548018  Length: 4170664 (4.0M) [application/octet-stream]
 1023 08:37:12.553599  Saving to: 'kselftest_armhf.tar.gz'
 1024 08:37:12.553976  
 1025 08:37:15.128765  kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               kselftest_armhf.tar   1%[                    ]  47.54K   154KB/s               kselftest_armhf.tar   5%[>                   ] 218.67K   351KB/s               kselftest_armhf.tar  16%[==>                 ] 668.67K   681KB/s               kselftest_armhf.tar  45%[========>           ]   1.79M  1.45MB/s               kselftest_armhf.tar  53%[=========>          ]   2.13M  1.44MB/s               kselftest_armhf.tar  66%[============>       ]   2.66M  1.55MB/s               kselftest_armhf.tar  74%[=============>      ]   2.96M  1.55MB/s               kselftest_armhf.tar  82%[===============>    ]   3.28M  1.55MB/s               kselftest_armhf.tar  90%[=================>  ]   3.58M  1.53MB/s               kselftest_armhf.tar  98%[==================> ]   3.91M  1.54MB/s               kselftest_armhf.tar 100%[===================>]   3.98M  1.54MB/s    in 2.6s    
 1026 08:37:15.129234  
 1027 08:37:15.963169  2024-01-26 21:49:19 (1.54 MB/s) - 'kselftest_armhf.tar.gz' saved [4170664/4170664]
 1028 08:37:15.963591  
 1029 08:37:16.322783  tar: ./proc/fd-003-kthread: time stamp 2024-10-31 08:10:37 is 24056476.004512953 s in the future
 1030 08:37:16.586819  tar: ./proc/config: time stamp 2024-10-28 11:31:42 is 23809340.736832203 s in the future
 1031 08:37:16.840470  tar: ./proc/proc-tid0: time stamp 2024-10-31 08:10:38 is 24056476.484568412 s in the future
 1032 08:37:17.094315  tar: ./proc/proc-loadavg-001: time stamp 2024-10-31 08:10:37 is 24056475.230744995 s in the future
 1033 08:37:17.419802  tar: ./proc/proc-self-syscall: time stamp 2024-10-31 08:10:38 is 24056475.905454037 s in the future
 1034 08:37:17.688207  tar: ./proc/setns-dcache: time stamp 2024-10-31 08:10:40 is 24056477.63647862 s in the future
 1035 08:37:17.913281  tar: ./proc/setns-sysvipc: time stamp 2024-10-31 08:10:40 is 24056477.411327453 s in the future
 1036 08:37:18.155544  tar: ./proc/proc-uptime-001: time stamp 2024-10-31 08:10:39 is 24056476.16967237 s in the future
 1037 08:37:18.404918  tar: ./proc/fd-001-lookup: time stamp 2024-10-31 08:10:37 is 24056473.919787495 s in the future
 1038 08:37:18.637685  tar: ./proc/proc-uptime-002: time stamp 2024-10-31 08:10:39 is 24056475.687695537 s in the future
 1039 08:37:18.868322  tar: ./proc/fd-002-posix-eq: time stamp 2024-10-31 08:10:37 is 24056473.456907078 s in the future
 1040 08:37:19.106405  tar: ./proc/thread-self: time stamp 2024-10-31 08:10:40 is 24056476.218480411 s in the future
 1041 08:37:19.377699  tar: ./proc/read: time stamp 2024-10-31 08:10:40 is 24056475.94518762 s in the future
 1042 08:37:19.628064  tar: ./proc/self: time stamp 2024-10-31 08:10:40 is 24056475.695251411 s in the future
 1043 08:37:19.868050  tar: ./proc/proc-pid-vm: time stamp 2024-10-31 08:10:38 is 24056473.456042203 s in the future
 1044 08:37:20.098500  tar: ./proc/proc-multiple-procfs: time stamp 2024-10-31 08:10:40 is 24056475.225854203 s in the future
 1045 08:37:20.370543  tar: ./proc/proc-self-isnt-kthread: time stamp 2024-10-31 08:10:38 is 24056472.955510661 s in the future
 1046 08:37:20.636183  tar: ./proc/proc-subset-pid: time stamp 2024-10-31 08:10:38 is 24056472.688844745 s in the future
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 1356 08:38:36.553685  tar: ./net/tcp_ao/seq-ext_ipv4: time stamp 2024-10-31 08:10:26 is 24056384.767489444 s in the future
 1357 08:38:36.796025  tar: ./net/tcp_ao/config: time stamp 2024-10-28 11:31:42 is 23809260.525024402 s in the future
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 1372 08:38:41.548610  tar: ./net/tcp_ao/rst_ipv4: time stamp 2024-10-31 08:10:25 is 24056378.771714485 s in the future
 1373 08:38:41.650391  tar: ./net/tcp_ao: time stamp 2024-10-31 08:11:32 is 24056445.670165568 s in the future
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 1379 08:38:43.193970  tar: ./net/forwarding/vxlan_symmetric.sh: time stamp 2024-10-28 11:31:42 is 23809254.127054318 s in the future
 1380 08:38:43.422395  tar: ./net/forwarding/ip6gre_hier.sh: time stamp 2024-10-28 11:31:42 is 23809253.89814811 s in the future
 1381 08:38:43.693239  tar: ./net/forwarding/sch_tbf_prio.sh: time stamp 2024-10-28 11:31:42 is 23809253.627849818 s in the future
 1382 08:38:43.926156  tar: ./net/forwarding/tc_actions.sh: time stamp 2024-10-28 11:31:42 is 23809253.394289735 s in the future
 1383 08:38:44.187520  tar: ./net/forwarding/tc_flower_port_range.sh: time stamp 2024-10-28 11:31:42 is 23809253.134476735 s in the future
 1384 08:38:44.408915  tar: ./net/forwarding/vxlan_bridge_1d_port_8472_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809252.913859151 s in the future
 1385 08:38:44.646004  tar: ./net/forwarding/gre_multipath_nh_res.sh: time stamp 2024-10-28 11:31:42 is 23809252.67551786 s in the future
 1386 08:38:44.860621  tar: ./net/forwarding/devlink_lib.sh: time stamp 2024-10-28 11:31:42 is 23809252.460096401 s in the future
 1387 08:38:45.103811  tar: ./net/forwarding/ipip_hier_gre_key.sh: time stamp 2024-10-28 11:31:42 is 23809252.216754485 s in the future
 1388 08:38:45.399882  tar: ./net/forwarding/tc_flower_router.sh: time stamp 2024-10-28 11:31:42 is 23809251.921322068 s in the future
 1389 08:38:45.662322  tar: ./net/forwarding/lib.sh: time stamp 2024-10-28 11:31:42 is 23809251.657911984 s in the future
 1390 08:38:45.901697  tar: ./net/forwarding/mirror_gre_bridge_1q_lag.sh: time stamp 2024-10-28 11:31:42 is 23809251.420766859 s in the future
 1391 08:38:46.155845  tar: ./net/forwarding/router_bridge_lag.sh: time stamp 2024-10-28 11:31:42 is 23809251.165795151 s in the future
 1392 08:38:46.384709  tar: ./net/forwarding/ipip_flat_gre.sh: time stamp 2024-10-28 11:31:42 is 23809250.937020318 s in the future
 1393 08:38:46.630296  tar: ./net/forwarding/sch_tbf_root.sh: time stamp 2024-10-28 11:31:42 is 23809250.690355693 s in the future
 1394 08:38:46.884113  tar: ./net/forwarding/skbedit_priority.sh: time stamp 2024-10-28 11:31:42 is 23809250.436587651 s in the future
 1395 08:38:47.131776  tar: ./net/forwarding/bridge_mdb_max.sh: time stamp 2024-10-28 11:31:42 is 23809250.190014734 s in the future
 1396 08:38:47.378519  tar: ./net/forwarding/ip6gre_custom_multipath_hash.sh: time stamp 2024-10-28 11:31:42 is 23809249.944439401 s in the future
 1397 08:38:47.656901  tar: ./net/forwarding/router_multicast.sh: time stamp 2024-10-28 11:31:42 is 23809249.664297318 s in the future
 1398 08:38:47.910831  tar: ./net/forwarding/mirror_gre_flower.sh: time stamp 2024-10-28 11:31:42 is 23809249.410621193 s in the future
 1399 08:38:48.190027  tar: ./net/forwarding/router_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809249.130511484 s in the future
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 1401 08:38:48.682255  tar: ./net/forwarding/tc_shblocks.sh: time stamp 2024-10-28 11:31:42 is 23809248.638329234 s in the future
 1402 08:38:48.930779  tar: ./net/forwarding/config: time stamp 2024-10-28 11:31:42 is 23809248.389799776 s in the future
 1403 08:38:49.182736  tar: ./net/forwarding/dual_vxlan_bridge.sh: time stamp 2024-10-28 11:31:42 is 23809248.137852151 s in the future
 1404 08:38:49.461882  tar: ./net/forwarding/mirror_gre_vlan_bridge_1q.sh: time stamp 2024-10-28 11:31:42 is 23809247.859209151 s in the future
 1405 08:38:49.716774  tar: ./net/forwarding/sch_ets_tests.sh: time stamp 2024-10-28 11:31:42 is 23809247.603884984 s in the future
 1406 08:38:49.954889  tar: ./net/forwarding/ip6gre_inner_v4_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809247.366999151 s in the future
 1407 08:38:50.234237  tar: ./net/forwarding/mirror_vlan.sh: time stamp 2024-10-28 11:31:42 is 23809247.086618234 s in the future
 1408 08:38:50.549237  tar: ./net/forwarding/fib_offload_lib.sh: time stamp 2024-10-28 11:31:42 is 23809246.771469484 s in the future
 1409 08:38:50.799840  tar: ./net/forwarding/bridge_mdb.sh: time stamp 2024-10-28 11:31:42 is 23809246.519722817 s in the future
 1410 08:38:51.037665  tar: ./net/forwarding/bridge_vlan_aware.sh: time stamp 2024-10-28 11:31:42 is 23809246.282495026 s in the future
 1411 08:38:51.310698  tar: ./net/forwarding/router_bridge_1d.sh: time stamp 2024-10-28 11:31:42 is 23809246.010692942 s in the future
 1412 08:38:51.539464  tar: ./net/forwarding/bridge_vlan_mcast.sh: time stamp 2024-10-28 11:31:42 is 23809245.781990984 s in the future
 1413 08:38:51.776319  tar: ./net/forwarding/router.sh: time stamp 2024-10-28 11:31:42 is 23809245.54354815 s in the future
 1414 08:38:51.998536  tar: ./net/forwarding/ipip_flat_gre_key.sh: time stamp 2024-10-28 11:31:42 is 23809245.323206234 s in the future
 1415 08:38:52.248114  tar: ./net/forwarding/vxlan_asymmetric_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809245.0729474 s in the future
 1416 08:38:52.490337  tar: ./net/forwarding/router_broadcast.sh: time stamp 2024-10-28 11:31:42 is 23809244.831104942 s in the future
 1417 08:38:52.736753  tar: ./net/forwarding/ip6gre_hier_key.sh: time stamp 2024-10-28 11:31:42 is 23809244.584994192 s in the future
 1418 08:38:52.977042  tar: ./net/forwarding/bridge_fdb_learning_limit.sh: time stamp 2024-10-28 11:31:42 is 23809244.344203317 s in the future
 1419 08:38:53.223457  tar: ./net/forwarding/ip6gre_flat_key.sh: time stamp 2024-10-28 11:31:42 is 23809244.097221734 s in the future
 1420 08:38:53.491330  tar: ./net/forwarding/tc_flower_l2_miss.sh: time stamp 2024-10-28 11:31:42 is 23809243.830097817 s in the future
 1421 08:38:53.747447  tar: ./net/forwarding/ip6gre_inner_v6_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809243.574833609 s in the future
 1422 08:38:53.966610  tar: ./net/forwarding/tc_tunnel_key.sh: time stamp 2024-10-28 11:31:42 is 23809243.354556567 s in the future
 1423 08:38:54.224589  tar: ./net/forwarding/no_forwarding.sh: time stamp 2024-10-28 11:31:42 is 23809243.096470983 s in the future
 1424 08:38:54.469987  tar: ./net/forwarding/router_mpath_seed.sh: time stamp 2024-10-28 11:31:42 is 23809242.851116275 s in the future
 1425 08:38:54.764002  tar: ./net/forwarding/vxlan_bridge_1q_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809242.557174858 s in the future
 1426 08:38:55.016702  tar: ./net/forwarding/vxlan_asymmetric.sh: time stamp 2024-10-28 11:31:42 is 23809242.303177983 s in the future
 1427 08:38:55.303339  tar: ./net/forwarding/sch_tbf_core.sh: time stamp 2024-10-28 11:31:42 is 23809242.0170334 s in the future
 1428 08:38:55.578396  tar: ./net/forwarding/gre_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809241.741802983 s in the future
 1429 08:38:55.838765  tar: ./net/forwarding/sch_ets_core.sh: time stamp 2024-10-28 11:31:42 is 23809241.481243817 s in the future
 1430 08:38:56.076740  tar: ./net/forwarding/gre_inner_v6_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809241.243838108 s in the future
 1431 08:38:56.306108  tar: ./net/forwarding/mirror_gre_lib.sh: time stamp 2024-10-28 11:31:42 is 23809241.014089275 s in the future
 1432 08:38:56.551394  tar: ./net/forwarding/sch_red.sh: time stamp 2024-10-28 11:31:42 is 23809240.768923233 s in the future
 1433 08:38:56.800982  tar: ./net/forwarding/ip6gre_flat_keys.sh: time stamp 2024-10-28 11:31:42 is 23809240.519354066 s in the future
 1434 08:38:57.035029  tar: ./net/forwarding/router_mpath_nh.sh: time stamp 2024-10-28 11:31:42 is 23809240.28507865 s in the future
 1435 08:38:57.293001  tar: ./net/forwarding/ipip_flat_gre_keys.sh: time stamp 2024-10-28 11:31:42 is 23809240.027293983 s in the future
 1436 08:38:57.568765  tar: ./net/forwarding/ip6gre_lib.sh: time stamp 2024-10-28 11:31:42 is 23809239.751327941 s in the future
 1437 08:38:57.802683  tar: ./net/forwarding/bridge_sticky_fdb.sh: time stamp 2024-10-28 11:31:42 is 23809239.518644025 s in the future
 1438 08:38:58.045237  tar: ./net/forwarding/vxlan_bridge_1q_port_8472_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809239.276961566 s in the future
 1439 08:38:58.303441  tar: ./net/forwarding/mirror_gre_bridge_1d_vlan.sh: time stamp 2024-10-28 11:31:42 is 23809239.018210025 s in the future
 1440 08:38:58.551065  tar: ./net/forwarding/tc_police.sh: time stamp 2024-10-28 11:31:42 is 23809238.768607191 s in the future
 1441 08:38:58.841870  tar: ./net/forwarding/gre_multipath_nh.sh: time stamp 2024-10-28 11:31:42 is 23809238.478076733 s in the future
 1442 08:38:59.091326  tar: ./net/forwarding/vxlan_bridge_1d_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809238.229982316 s in the future
 1443 08:38:59.335569  tar: ./net/forwarding/q_in_vni_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809237.98423465 s in the future
 1444 08:38:59.592601  tar: ./net/forwarding/vxlan_bridge_1q_port_8472.sh: time stamp 2024-10-28 11:31:42 is 23809237.727859149 s in the future
 1445 08:38:59.852669  tar: ./net/forwarding/mirror_lib.sh: time stamp 2024-10-28 11:31:42 is 23809237.467210566 s in the future
 1446 08:39:00.108717  tar: ./net/forwarding/vxlan_symmetric_ipv6.sh: time stamp 2024-10-28 11:31:42 is 23809237.212263608 s in the future
 1447 08:39:00.365925  tar: ./net/forwarding/pedit_dsfield.sh: time stamp 2024-10-28 11:31:42 is 23809236.954333191 s in the future
 1448 08:39:00.615698  tar: ./net/forwarding/settings: time stamp 2024-10-28 11:31:42 is 23809236.703710399 s in the future
 1449 08:39:00.894825  tar: ./net/forwarding/mirror_gre_nh.sh: time stamp 2024-10-28 11:31:42 is 23809236.424898983 s in the future
 1450 08:39:01.142363  tar: ./net/forwarding/ip6gre_flat.sh: time stamp 2024-10-28 11:31:42 is 23809236.178232941 s in the future
 1451 08:39:01.404661  tar: ./net/forwarding/tc_chains.sh: time stamp 2024-10-28 11:31:42 is 23809235.916139566 s in the future
 1452 08:39:01.668259  tar: ./net/forwarding/bridge_mdb_port_down.sh: time stamp 2024-10-28 11:31:42 is 23809235.652726566 s in the future
 1453 08:39:01.922331  tar: ./net/forwarding/gre_custom_multipath_hash.sh: time stamp 2024-10-28 11:31:42 is 23809235.399118066 s in the future
 1454 08:39:02.158272  tar: ./net/forwarding/mirror_gre_bound.sh: time stamp 2024-10-28 11:31:42 is 23809235.162412649 s in the future
 1455 08:39:02.394103  tar: ./net/forwarding/ip6_forward_instats_vrf.sh: time stamp 2024-10-28 11:31:42 is 23809234.926758066 s in the future
 1456 08:39:02.727136  tar: ./net/forwarding/tc_vlan_modify.sh: time stamp 2024-10-28 11:31:42 is 23809234.593240566 s in the future
 1457 08:39:02.955679  tar: ./net/forwarding/bridge_vlan_unaware.sh: time stamp 2024-10-28 11:31:42 is 23809234.365156816 s in the future
 1458 08:39:03.219121  tar: ./net/forwarding/bridge_mld.sh: time stamp 2024-10-28 11:31:42 is 23809234.100954524 s in the future
 1459 08:39:03.475302  tar: ./net/forwarding/gre_inner_v4_multipath.sh: time stamp 2024-10-28 11:31:42 is 23809233.845682857 s in the future
 1460 08:39:03.715455  tar: ./net/forwarding/router_nh.sh: time stamp 2024-10-28 11:31:42 is 23809233.603786441 s in the future
 1461 08:39:03.964461  tar: ./net/forwarding/mirror_topo_lib.sh: time stamp 2024-10-28 11:31:42 is 23809233.356048774 s in the future
 1462 08:39:04.213090  tar: ./net/forwarding/bridge_port_isolation.sh: time stamp 2024-10-28 11:31:42 is 23809233.108002524 s in the future
 1463 08:39:04.463696  tar: ./net/forwarding/sch_tbf_ets.sh: time stamp 2024-10-28 11:31:42 is 23809232.855669066 s in the future
 1464 08:39:04.690218  tar: ./net/forwarding/router_bridge_vlan_upper.sh: time stamp 2024-10-28 11:31:42 is 23809232.630500899 s in the future
 1465 08:39:04.956778  tar: ./net/forwarding/router_bridge_1d_lag.sh: time stamp 2024-10-28 11:31:42 is 23809232.363613066 s in the future
 1466 08:39:05.224604  tar: ./net/forwarding/custom_multipath_hash.sh: time stamp 2024-10-28 11:31:42 is 23809232.096817857 s in the future
 1467 08:39:05.457317  tar: ./net/forwarding/mirror_gre_lag_lacp.sh: time stamp 2024-10-28 11:31:42 is 23809231.863255607 s in the future
 1468 08:39:05.713182  tar: ./net/forwarding/min_max_mtu.sh: time stamp 2024-10-28 11:31:42 is 23809231.606342524 s in the future
 1469 08:39:06.014530  tar: ./net/forwarding/sch_ets.sh: time stamp 2024-10-28 11:31:42 is 23809231.304385774 s in the future
 1470 08:39:06.299061  tar: ./net/forwarding/tc_flower_cfm.sh: time stamp 2024-10-28 11:31:42 is 23809231.020858774 s in the future
 1471 08:39:06.532825  tar: ./net/forwarding/router_bridge_vlan.sh: time stamp 2024-10-28 11:31:42 is 23809230.787228899 s in the future
 1472 08:39:06.799402  tar: ./net/forwarding/local_termination.sh: time stamp 2024-10-28 11:31:42 is 23809230.520387982 s in the future
 1473 08:39:07.041391  tar: ./net/forwarding/mirror_gre_vlan.sh: time stamp 2024-10-28 11:31:42 is 23809230.278456565 s in the future
 1474 08:39:07.283717  tar: ./net/forwarding/router_bridge_vlan_upper_pvid.sh: time stamp 2024-10-28 11:31:42 is 23809230.036737065 s in the future
 1475 08:39:07.516489  tar: ./net/forwarding/mirror_gre_changes.sh: time stamp 2024-10-28 11:31:42 is 23809229.803129899 s in the future
 1476 08:39:07.732097  tar: ./net/forwarding/tc_common.sh: time stamp 2024-10-28 11:31:42 is 23809229.58724594 s in the future
 1477 08:39:07.866775  tar: ./net/forwarding/router_vid_1.sh: time stamp 2024-10-28 11:31:42 is 23809229.452461274 s in the future
 1478 08:39:07.995000  tar: ./net/forwarding/bridge_mdb_host.sh: time stamp 2024-10-28 11:31:42 is 23809229.324610648 s in the future
 1479 08:39:08.268090  tar: ./net/forwarding/ipip_hier_gre_keys.sh: time stamp 2024-10-28 11:31:42 is 23809229.052748065 s in the future
 1480 08:39:08.438567  tar: ./net/forwarding/mirror_gre_topo_lib.sh: time stamp 2024-10-28 11:31:42 is 23809228.882457232 s in the future
 1481 08:39:08.610249  tar: ./net/forwarding/forwarding.config.sample: time stamp 2024-10-28 11:31:42 is 23809228.710348773 s in the future
 1482 08:39:08.850207  tar: ./net/forwarding/pedit_l4port.sh: time stamp 2024-10-28 11:31:42 is 23809228.469459898 s in the future
 1483 08:39:08.976141  tar: ./net/forwarding/lib_sh_test.sh: time stamp 2024-10-28 11:31:42 is 23809228.343379648 s in the future
 1484 08:39:09.184755  tar: ./net/forwarding/ip6gre_hier_keys.sh: time stamp 2024-10-28 11:31:42 is 23809228.134850107 s in the future
 1485 08:39:09.421734  tar: ./net/forwarding/router_mpath_nh_lib.sh: time stamp 2024-10-28 11:31:42 is 23809227.898384565 s in the future
 1486 08:39:09.677807  tar: ./net/forwarding/mirror_gre_bridge_1q.sh: time stamp 2024-10-28 11:31:42 is 23809227.642723148 s in the future
 1487 08:39:09.815421  tar: ./net/forwarding/ipip_hier_gre.sh: time stamp 2024-10-28 11:31:42 is 23809227.503562107 s in the future
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 2084 08:41:26.486433  tar: ./tc-testing/tc-tests/qdiscs/ingress.json: time stamp 2024-10-28 11:31:42 is 23809090.82591284 s in the future
 2085 08:41:26.624388  tar: ./tc-testing/tc-tests/qdiscs/tbf.json: time stamp 2024-10-28 11:31:42 is 23809090.688612549 s in the future
 2086 08:41:26.767488  tar: ./tc-testing/tc-tests/qdiscs/skbprio.json: time stamp 2024-10-28 11:31:42 is 23809090.545217799 s in the future
 2087 08:41:26.918158  tar: ./tc-testing/tc-tests/qdiscs/hhf.json: time stamp 2024-10-28 11:31:42 is 23809090.395115299 s in the future
 2088 08:41:27.043390  tar: ./tc-testing/tc-tests/qdiscs/codel.json: time stamp 2024-10-28 11:31:42 is 23809090.269961299 s in the future
 2089 08:41:27.174837  tar: ./tc-testing/tc-tests/qdiscs/ets.json: time stamp 2024-10-28 11:31:42 is 23809090.138017257 s in the future
 2090 08:41:27.328340  tar: ./tc-testing/tc-tests/qdiscs/pfifo_fast.json: time stamp 2024-10-28 11:31:42 is 23809089.985168299 s in the future
 2091 08:41:27.486301  tar: ./tc-testing/tc-tests/qdiscs/qfq.json: time stamp 2024-10-28 11:31:42 is 23809089.82661534 s in the future
 2092 08:41:27.627246  tar: ./tc-testing/tc-tests/qdiscs/etf.json: time stamp 2024-10-28 11:31:42 is 23809089.686137132 s in the future
 2093 08:41:27.747203  tar: ./tc-testing/tc-tests/qdiscs/cake.json: time stamp 2024-10-28 11:31:42 is 23809089.566331673 s in the future
 2094 08:41:27.910251  tar: ./tc-testing/tc-tests/qdiscs/taprio.json: time stamp 2024-10-28 11:31:42 is 23809089.402370007 s in the future
 2095 08:41:28.061972  tar: ./tc-testing/tc-tests/qdiscs/drr.json: time stamp 2024-10-28 11:31:42 is 23809089.251249673 s in the future
 2096 08:41:28.211377  tar: ./tc-testing/tc-tests/qdiscs/prio.json: time stamp 2024-10-28 11:31:42 is 23809089.102143007 s in the future
 2097 08:41:28.355438  tar: ./tc-testing/tc-tests/qdiscs/fq_pie.json: time stamp 2024-10-28 11:31:42 is 23809088.957647882 s in the future
 2098 08:41:28.501713  tar: ./tc-testing/tc-tests/qdiscs/mq.json: time stamp 2024-10-28 11:31:42 is 23809088.810445923 s in the future
 2099 08:41:28.652173  tar: ./tc-testing/tc-tests/qdiscs/plug.json: time stamp 2024-10-28 11:31:42 is 23809088.659382132 s in the future
 2100 08:41:28.781504  tar: ./tc-testing/tc-tests/qdiscs/mqprio.json: time stamp 2024-10-28 11:31:42 is 23809088.532144048 s in the future
 2101 08:41:28.838099  tar: ./tc-testing/tc-tests/qdiscs: time stamp 2024-10-28 11:31:42 is 23809088.473884298 s in the future
 2102 08:41:28.996941  tar: ./tc-testing/tc-tests/actions/sample.json: time stamp 2024-10-28 11:31:42 is 23809088.316303798 s in the future
 2103 08:41:29.125246  tar: ./tc-testing/tc-tests/actions/connmark.json: time stamp 2024-10-28 11:31:42 is 23809088.187763507 s in the future
 2104 08:41:29.273822  tar: ./tc-testing/tc-tests/actions/tunnel_key.json: time stamp 2024-10-28 11:31:42 is 23809088.039877215 s in the future
 2105 08:41:29.430395  tar: ./tc-testing/tc-tests/actions/mpls.json: time stamp 2024-10-28 11:31:42 is 23809087.88170634 s in the future
 2106 08:41:29.580831  tar: ./tc-testing/tc-tests/actions/skbedit.json: time stamp 2024-10-28 11:31:42 is 23809087.731934215 s in the future
 2107 08:41:29.716447  tar: ./tc-testing/tc-tests/actions/skbmod.json: time stamp 2024-10-28 11:31:42 is 23809087.595591632 s in the future
 2108 08:41:29.875463  tar: ./tc-testing/tc-tests/actions/ife.json: time stamp 2024-10-28 11:31:42 is 23809087.43713934 s in the future
 2109 08:41:30.006795  tar: ./tc-testing/tc-tests/actions/gact.json: time stamp 2024-10-28 11:31:42 is 23809087.306183465 s in the future
 2110 08:41:30.139857  tar: ./tc-testing/tc-tests/actions/gate.json: time stamp 2024-10-28 11:31:42 is 23809087.173226507 s in the future
 2111 08:41:30.282264  tar: ./tc-testing/tc-tests/actions/pedit.json: time stamp 2024-10-28 11:31:42 is 23809087.030938798 s in the future
 2112 08:41:30.448815  tar: ./tc-testing/tc-tests/actions/bpf.json: time stamp 2024-10-28 11:31:42 is 23809086.864136423 s in the future
 2113 08:41:30.606512  tar: ./tc-testing/tc-tests/actions/simple.json: time stamp 2024-10-28 11:31:42 is 23809086.705722131 s in the future
 2114 08:41:30.748580  tar: ./tc-testing/tc-tests/actions/police.json: time stamp 2024-10-28 11:31:42 is 23809086.564260756 s in the future
 2115 08:41:30.916086  tar: ./tc-testing/tc-tests/actions/nat.json: time stamp 2024-10-28 11:31:42 is 23809086.397173465 s in the future
 2116 08:41:31.054906  tar: ./tc-testing/tc-tests/actions/csum.json: time stamp 2024-10-28 11:31:42 is 23809086.258314131 s in the future
 2117 08:41:31.190471  tar: ./tc-testing/tc-tests/actions/ctinfo.json: time stamp 2024-10-28 11:31:42 is 23809086.121931215 s in the future
 2118 08:41:31.339317  tar: ./tc-testing/tc-tests/actions/vlan.json: time stamp 2024-10-28 11:31:42 is 23809085.97215909 s in the future
 2119 08:41:31.483158  tar: ./tc-testing/tc-tests/actions/mirred.json: time stamp 2024-10-28 11:31:42 is 23809085.829994131 s in the future
 2120 08:41:31.607199  tar: ./tc-testing/tc-tests/actions/ct.json: time stamp 2024-10-28 11:31:42 is 23809085.705101173 s in the future
 2121 08:41:31.671102  tar: ./tc-testing/tc-tests/actions: time stamp 2024-10-28 11:31:42 is 23809085.641215256 s in the future
 2122 08:41:31.742197  tar: ./tc-testing/tc-tests: time stamp 2024-10-28 11:31:42 is 23809085.569033215 s in the future
 2123 08:41:31.861815  tar: ./tc-testing/config: time stamp 2024-10-28 11:31:42 is 23809085.449121006 s in the future
 2124 08:41:31.987878  tar: ./tc-testing/TdcPlugin.py: time stamp 2024-10-28 11:31:42 is 23809085.323962131 s in the future
 2125 08:41:32.166833  tar: ./tc-testing/tdc_helper.py: time stamp 2024-10-28 11:31:42 is 23809085.144544631 s in the future
 2126 08:41:32.306395  tar: ./tc-testing/tdc.sh: time stamp 2024-10-28 11:31:42 is 23809085.004291631 s in the future
 2127 08:41:32.442830  tar: ./tc-testing/tdc_config.py: time stamp 2024-10-28 11:31:42 is 23809084.868413465 s in the future
 2128 08:41:32.573173  tar: ./tc-testing/settings: time stamp 2024-10-28 11:31:42 is 23809084.740465965 s in the future
 2129 08:41:32.736328  tar: ./tc-testing/plugin-lib/scapyPlugin.py: time stamp 2024-10-28 11:31:42 is 23809084.57633459 s in the future
 2130 08:41:32.855149  tar: ./tc-testing/plugin-lib/README-PLUGINS: time stamp 2024-10-28 11:31:42 is 23809084.457952798 s in the future
 2131 08:41:32.980814  tar: ./tc-testing/plugin-lib/rootPlugin.py: time stamp 2024-10-28 11:31:42 is 23809084.331613006 s in the future
 2132 08:41:33.125277  tar: ./tc-testing/plugin-lib/nsPlugin.py: time stamp 2024-10-28 11:31:42 is 23809084.186689006 s in the future
 2133 08:41:33.267354  tar: ./tc-testing/plugin-lib/valgrindPlugin.py: time stamp 2024-10-28 11:31:42 is 23809084.044930881 s in the future
 2134 08:41:33.355290  tar: ./tc-testing/plugin-lib: time stamp 2024-10-28 11:31:42 is 23809083.956444214 s in the future
 2135 08:41:33.482268  tar: ./tc-testing/action-ebpf: time stamp 2024-10-28 11:31:42 is 23809083.828003673 s in the future
 2136 08:41:33.642352  tar: ./tc-testing/scripts/taprio_wait_for_admin.sh: time stamp 2024-10-28 11:31:42 is 23809083.670639214 s in the future
 2137 08:41:33.699573  tar: ./tc-testing/scripts: time stamp 2024-10-28 11:31:42 is 23809083.611189673 s in the future
 2138 08:41:33.834155  tar: ./tc-testing/tdc_config_local_template.py: time stamp 2024-10-28 11:31:42 is 23809083.477566881 s in the future
 2139 08:41:33.946325  tar: ./tc-testing/tdc_batch.py: time stamp 2024-10-28 11:31:42 is 23809083.365254506 s in the future
 2140 08:41:34.080901  tar: ./tc-testing/tdc_multibatch.py: time stamp 2024-10-28 11:31:42 is 23809083.231341631 s in the future
 2141 08:41:34.222918  tar: ./tc-testing/plugins/__init__.py: time stamp 2024-10-28 11:31:42 is 23809083.088965464 s in the future
 2142 08:41:34.275014  tar: ./tc-testing/plugins: time stamp 2024-10-28 11:31:42 is 23809083.035909589 s in the future
 2143 08:41:34.324903  tar: ./tc-testing: time stamp 2024-10-31 08:11:35 is 24056275.985391214 s in the future
 2144 08:41:34.487985  tar: ./kselftest/runner.sh: time stamp 2024-10-31 08:11:23 is 24056263.823338756 s in the future
 2145 08:41:34.645573  tar: ./kselftest/ktap_helpers.sh: time stamp 2024-10-28 11:31:42 is 23809082.665968756 s in the future
 2146 08:41:34.797108  tar: ./kselftest/module.sh: time stamp 2024-10-31 08:11:23 is 24056263.513283714 s in the future
 2147 08:41:35.018035  tar: ./kselftest/ksft.py: time stamp 2024-10-31 08:11:23 is 24056263.293211756 s in the future
 2148 08:41:35.209857  tar: ./kselftest/prefix.pl: time stamp 2024-10-31 08:11:23 is 24056263.101235631 s in the future
 2149 08:41:35.288145  tar: ./kselftest: time stamp 2024-10-28 11:31:42 is 23809082.021004214 s in the future
 2150 08:41:35.919808  tar: ./fchmodat2/fchmodat2_test: time stamp 2024-10-31 08:09:28 is 24056147.392035714 s in the future
 2151 08:41:36.096221  tar: ./fchmodat2: time stamp 2024-10-31 08:11:26 is 24056265.213497964 s in the future
 2152 08:41:36.316200  tar: ./tty/tty_tstamp_update: time stamp 2024-10-31 08:11:03 is 24056241.995357547 s in the future
 2153 08:41:36.375391  tar: ./tty: time stamp 2024-10-31 08:11:36 is 24056274.933660839 s in the future
 2154 08:41:36.450389  tar: .: time stamp 2024-10-31 08:11:39 is 24056277.858008339 s in the future
 2155 08:41:36.820013  skiplist:
 2156 08:41:36.820405  ========================================
 2157 08:41:36.824197  ========================================
 2158 08:41:37.259561  dt:test_unprobed_devices.sh
 2159 08:41:37.393293  ============== Tests to run ===============
 2160 08:41:37.403010  dt:test_unprobed_devices.sh
 2161 08:41:37.407225  ===========End Tests to run ===============
 2162 08:41:37.455264  shardfile-dt pass
 2163 08:41:37.785342  <12>[  322.235536] kselftest: Running tests in dt
 2164 08:41:37.818570  TAP version 13
 2165 08:41:37.843263  1..1
 2166 08:41:37.898093  # timeout set to 45
 2167 08:41:37.898522  # selftests: dt: test_unprobed_devices.sh
 2168 08:41:38.738988  # TAP version 13
 2169 08:42:04.009394  # 1..257
 2170 08:42:04.208369  # ok 1 / # SKIP
 2171 08:42:04.235385  # ok 2 /clk_mcasp0
 2172 08:42:04.304708  # ok 3 /clk_mcasp0_fixed # SKIP
 2173 08:42:04.380554  # ok 4 /cpus/cpu@0 # SKIP
 2174 08:42:04.458924  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 2175 08:42:04.478633  # ok 6 /fixedregulator0
 2176 08:42:04.499537  # ok 7 /leds
 2177 08:42:04.517002  # ok 8 /ocp
 2178 08:42:04.543093  # ok 9 /ocp/interconnect@44c00000
 2179 08:42:04.567414  # ok 10 /ocp/interconnect@44c00000/segment@0
 2180 08:42:04.592087  # ok 11 /ocp/interconnect@44c00000/segment@100000
 2181 08:42:04.615318  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 2182 08:42:04.689505  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 2183 08:42:04.710491  # ok 14 /ocp/interconnect@44c00000/segment@200000
 2184 08:42:04.736059  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 2185 08:42:04.848145  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 2186 08:42:04.920061  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 2187 08:42:05.011262  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 2188 08:42:05.079018  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 2189 08:42:05.152414  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 2190 08:42:05.226033  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 2191 08:42:05.298600  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 2192 08:42:05.372185  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 2193 08:42:05.447834  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 2194 08:42:05.522224  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 2195 08:42:05.601203  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 2196 08:42:05.672522  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 2197 08:42:05.750247  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 2198 08:42:05.827030  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 2199 08:42:05.903039  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 2200 08:42:05.971044  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 2201 08:42:06.049672  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 2202 08:42:06.125197  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 2203 08:42:06.195275  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 2204 08:42:06.270928  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 2205 08:42:06.343081  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 2206 08:42:06.418227  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 2207 08:42:06.493906  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 2208 08:42:06.572853  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 2209 08:42:06.646217  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 2210 08:42:06.718700  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 2211 08:42:06.794572  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 2212 08:42:06.868058  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 2213 08:42:06.943830  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 2214 08:42:07.022841  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 2215 08:42:07.093186  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 2216 08:42:07.168943  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 2217 08:42:07.243719  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 2218 08:42:07.322725  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 2219 08:42:07.393011  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 2220 08:42:07.469882  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 2221 08:42:07.543688  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 2222 08:42:07.623949  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 2223 08:42:07.697662  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 2224 08:42:07.773460  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 2225 08:42:07.847021  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 2226 08:42:07.920210  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 2227 08:42:07.993580  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 2228 08:42:08.069960  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 2229 08:42:08.145787  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 2230 08:42:08.219015  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 2231 08:42:08.293771  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 2232 08:42:08.372845  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 2233 08:42:08.446308  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 2234 08:42:08.517782  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 2235 08:42:08.596608  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 2236 08:42:08.668016  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 2237 08:42:08.742654  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 2238 08:42:08.820960  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 2239 08:42:08.893422  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 2240 08:42:08.968276  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 2241 08:42:09.041693  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 2242 08:42:09.121499  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 2243 08:42:09.193648  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 2244 08:42:09.268525  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 2245 08:42:09.343221  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 2246 08:42:09.423533  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 2247 08:42:09.493036  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 2248 08:42:09.568971  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 2249 08:42:09.642304  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 2250 08:42:09.721133  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 2251 08:42:09.796779  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 2252 08:42:09.874792  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 2253 08:42:09.993662  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 2254 08:42:10.025247  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 2255 08:42:10.101191  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 2256 08:42:10.172553  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 2257 08:42:10.250704  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 2258 08:42:10.323367  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 2259 08:42:10.404827  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 2260 08:42:10.476165  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 2261 08:42:10.549850  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 2262 08:42:10.623577  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 2263 08:42:10.703808  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 2264 08:42:10.724264  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 2265 08:42:10.747754  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 2266 08:42:10.771407  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 2267 08:42:10.796029  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 2268 08:42:10.824167  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 2269 08:42:10.845637  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 2270 08:42:10.870271  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 2271 08:42:10.898236  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 2272 08:42:11.005550  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 2273 08:42:11.029004  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 2274 08:42:11.054865  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 2275 08:42:11.079745  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 2276 08:42:11.189092  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 2277 08:42:11.265868  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 2278 08:42:11.341756  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 2279 08:42:11.416510  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 2280 08:42:11.491206  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 2281 08:42:11.566078  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 2282 08:42:11.642985  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 2283 08:42:11.717668  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 2284 08:42:11.792566  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 2285 08:42:11.871008  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 2286 08:42:11.944874  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 2287 08:42:12.021036  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 2288 08:42:12.094840  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 2289 08:42:12.172899  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 2290 08:42:12.248138  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 2291 08:42:12.323102  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 2292 08:42:12.345830  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 2293 08:42:12.418438  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 2294 08:42:12.490651  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 2295 08:42:12.567170  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 2296 08:42:12.593000  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 2297 08:42:12.664069  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 2298 08:42:12.686292  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 2299 08:42:12.759579  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 2300 08:42:12.782100  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 2301 08:42:12.807484  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 2302 08:42:12.833160  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 2303 08:42:12.856427  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 2304 08:42:12.878983  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 2305 08:42:12.910455  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 2306 08:42:12.929864  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50
 2307 08:42:13.013183  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/eeprom@50/nvmem-layout # SKIP
 2308 08:42:13.035984  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 2309 08:42:13.056613  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 2310 08:42:13.131056  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 2311 08:42:13.204552  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 2312 08:42:13.227148  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 2313 08:42:13.336865  # not ok 144 /ocp/interconnect@47c00000
 2314 08:42:13.408691  # not ok 145 /ocp/interconnect@47c00000/segment@0
 2315 08:42:13.430856  # ok 146 /ocp/interconnect@48000000
 2316 08:42:13.456282  # ok 147 /ocp/interconnect@48000000/segment@0
 2317 08:42:13.482060  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 2318 08:42:13.503433  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 2319 08:42:13.525639  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 2320 08:42:13.549064  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 2321 08:42:13.573531  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 2322 08:42:13.597107  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 2323 08:42:13.623974  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 2324 08:42:13.698155  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 2325 08:42:13.774490  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 2326 08:42:13.791925  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 2327 08:42:13.821735  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 2328 08:42:13.843081  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 2329 08:42:13.866340  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 2330 08:42:13.888823  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 2331 08:42:13.915730  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 2332 08:42:13.941484  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 2333 08:42:13.963819  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 2334 08:42:13.985184  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 2335 08:42:14.009692  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 2336 08:42:14.037432  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 2337 08:42:14.061111  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 2338 08:42:14.083492  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 2339 08:42:14.106655  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 2340 08:42:14.127549  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 2341 08:42:14.155890  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 2342 08:42:14.181675  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 2343 08:42:14.204158  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 2344 08:42:14.224017  # ok 175 /ocp/interconnect@48000000/segment@100000
 2345 08:42:14.253113  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 2346 08:42:14.274214  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 2347 08:42:14.349736  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54
 2348 08:42:14.425357  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@54/nvmem-layout # SKIP
 2349 08:42:14.498469  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55
 2350 08:42:14.573017  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@55/nvmem-layout # SKIP
 2351 08:42:14.649953  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56
 2352 08:42:14.722500  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@56/nvmem-layout # SKIP
 2353 08:42:14.793709  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57
 2354 08:42:14.871494  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/eeprom@57/nvmem-layout # SKIP
 2355 08:42:14.891922  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 2356 08:42:14.916204  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 2357 08:42:14.943080  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 2358 08:42:15.045206  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 2359 08:42:15.051258  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 2360 08:42:15.054838  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 2361 08:42:15.059851  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 2362 08:42:15.069162  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 2363 08:42:15.084165  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 2364 08:42:15.108614  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 2365 08:42:15.132408  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 2366 08:42:15.157819  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 2367 08:42:15.176977  # ok 198 /ocp/interconnect@48000000/segment@200000
 2368 08:42:15.208137  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 2369 08:42:15.279028  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 2370 08:42:15.299156  # ok 201 /ocp/interconnect@48000000/segment@300000
 2371 08:42:15.325806  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 2372 08:42:15.349205  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 2373 08:42:15.373932  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 2374 08:42:15.396462  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 2375 08:42:15.423254  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 2376 08:42:15.445785  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 2377 08:42:15.524255  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 2378 08:42:15.539863  # ok 209 /ocp/interconnect@4a000000
 2379 08:42:15.568485  # ok 210 /ocp/interconnect@4a000000/segment@0
 2380 08:42:15.593080  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 2381 08:42:15.619865  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 2382 08:42:15.644586  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 2383 08:42:15.664217  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 2384 08:42:15.739532  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 2385 08:42:15.848824  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 2386 08:42:15.926565  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 2387 08:42:16.034874  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 2388 08:42:16.106248  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 2389 08:42:16.180697  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 2390 08:42:16.283793  # not ok 221 /ocp/interconnect@4b140000
 2391 08:42:16.356755  # not ok 222 /ocp/interconnect@4b140000/segment@0
 2392 08:42:16.430692  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 2393 08:42:16.455922  # ok 224 /ocp/target-module@40300000
 2394 08:42:16.479085  # ok 225 /ocp/target-module@40300000/sram@0
 2395 08:42:16.550893  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 2396 08:42:16.629116  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 2397 08:42:16.649854  # ok 228 /ocp/target-module@47400000
 2398 08:42:16.674419  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 2399 08:42:16.692155  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 2400 08:42:16.716207  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 2401 08:42:16.739378  # ok 232 /ocp/target-module@47400000/usb@1400
 2402 08:42:16.767911  # ok 233 /ocp/target-module@47400000/usb@1800
 2403 08:42:16.785659  # ok 234 /ocp/target-module@47810000
 2404 08:42:16.810981  # ok 235 /ocp/target-module@49000000
 2405 08:42:16.835334  # ok 236 /ocp/target-module@49000000/dma@0
 2406 08:42:16.857425  # ok 237 /ocp/target-module@49800000
 2407 08:42:16.881791  # ok 238 /ocp/target-module@49800000/dma@0
 2408 08:42:16.899534  # ok 239 /ocp/target-module@49900000
 2409 08:42:16.923739  # ok 240 /ocp/target-module@49900000/dma@0
 2410 08:42:16.946889  # ok 241 /ocp/target-module@49a00000
 2411 08:42:16.971285  # ok 242 /ocp/target-module@49a00000/dma@0
 2412 08:42:16.991918  # ok 243 /ocp/target-module@4c000000
 2413 08:42:17.066864  # not ok 244 /ocp/target-module@4c000000/emif@0
 2414 08:42:17.090156  # ok 245 /ocp/target-module@50000000
 2415 08:42:17.112261  # ok 246 /ocp/target-module@53100000
 2416 08:42:17.186054  # not ok 247 /ocp/target-module@53100000/sham@0
 2417 08:42:17.210190  # ok 248 /ocp/target-module@53500000
 2418 08:42:17.282942  # not ok 249 /ocp/target-module@53500000/aes@0
 2419 08:42:17.304846  # ok 250 /ocp/target-module@56000000
 2420 08:42:17.413328  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 2421 08:42:17.489196  # ok 252 /opp-table # SKIP
 2422 08:42:17.562807  # ok 253 /soc # SKIP
 2423 08:42:17.585763  # ok 254 /sound
 2424 08:42:17.604462  # ok 255 /target-module@4b000000
 2425 08:42:17.630904  # ok 256 /target-module@4b000000/target-module@140000
 2426 08:42:17.652040  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 2427 08:42:17.660528  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 2428 08:42:17.666554  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 2429 08:42:20.129135  dt_test_unprobed_devices_sh_ skip
 2430 08:42:20.135243  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 2431 08:42:20.138977  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 2432 08:42:20.142614  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 2433 08:42:20.148746  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 2434 08:42:20.153627  dt_test_unprobed_devices_sh_fixedregulator0 pass
 2435 08:42:20.154002  dt_test_unprobed_devices_sh_leds pass
 2436 08:42:20.159556  dt_test_unprobed_devices_sh_ocp pass
 2437 08:42:20.164625  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 2438 08:42:20.170660  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 2439 08:42:20.175533  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 2440 08:42:20.185252  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 2441 08:42:20.191459  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 2442 08:42:20.201066  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 2443 08:42:20.206111  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 2444 08:42:20.217216  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 2445 08:42:20.226913  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 2446 08:42:20.233029  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 2447 08:42:20.247763  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 2448 08:42:20.253756  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 2449 08:42:20.268504  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 2450 08:42:20.274755  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 2451 08:42:20.284327  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 2452 08:42:20.295476  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 2453 08:42:20.305100  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 2454 08:42:20.316217  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 2455 08:42:20.325917  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 2456 08:42:20.337190  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 2457 08:42:20.346657  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 2458 08:42:20.357780  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 2459 08:42:20.367462  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 2460 08:42:20.372488  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 2461 08:42:20.383495  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 2462 08:42:20.393232  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 2463 08:42:20.404258  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 2464 08:42:20.414046  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 2465 08:42:20.425070  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 2466 08:42:20.434913  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 2467 08:42:20.445911  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 2468 08:42:20.455706  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 2469 08:42:20.466723  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 2470 08:42:20.476435  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 2471 08:42:20.487585  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 2472 08:42:20.503685  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 2473 08:42:20.513156  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 2474 08:42:20.524379  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 2475 08:42:20.534131  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 2476 08:42:20.545250  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 2477 08:42:20.554932  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 2478 08:42:20.566049  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 2479 08:42:20.580769  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 2480 08:42:20.591696  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 2481 08:42:20.601646  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 2482 08:42:20.612817  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 2483 08:42:20.621635  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 2484 08:42:20.632830  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 2485 08:42:20.643973  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 2486 08:42:20.656305  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 2487 08:42:20.666277  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 2488 08:42:20.677374  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 2489 08:42:20.687051  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 2490 08:42:20.698262  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 2491 08:42:20.707905  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 2492 08:42:20.719205  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 2493 08:42:20.729104  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 2494 08:42:20.740442  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 2495 08:42:20.755170  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 2496 08:42:20.761196  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 2497 08:42:20.776074  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 2498 08:42:20.787305  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 2499 08:42:20.797189  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 2500 08:42:20.808162  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 2501 08:42:20.817902  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 2502 08:42:20.829168  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 2503 08:42:20.838915  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 2504 08:42:20.850036  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 2505 08:42:20.860171  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 2506 08:42:20.871422  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 2507 08:42:20.881189  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 2508 08:42:20.892179  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 2509 08:42:20.908194  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 2510 08:42:20.918178  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 2511 08:42:20.929434  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 2512 08:42:20.934688  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 2513 08:42:20.944551  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 2514 08:42:20.955561  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 2515 08:42:20.965263  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 2516 08:42:20.976550  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 2517 08:42:20.986256  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 2518 08:42:21.002257  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 2519 08:42:21.013534  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 2520 08:42:21.023164  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 2521 08:42:21.034315  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 2522 08:42:21.044188  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 2523 08:42:21.055552  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 2524 08:42:21.065184  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 2525 08:42:21.076298  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 2526 08:42:21.081193  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 2527 08:42:21.091040  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 2528 08:42:21.102034  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 2529 08:42:21.112045  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 2530 08:42:21.118413  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 2531 08:42:21.127932  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 2532 08:42:21.140671  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 2533 08:42:21.150684  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 2534 08:42:21.155555  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 2535 08:42:21.166678  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 2536 08:42:21.177805  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 2537 08:42:21.193887  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 2538 08:42:21.203750  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 2539 08:42:21.215165  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 2540 08:42:21.229761  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 2541 08:42:21.239763  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 2542 08:42:21.250806  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 2543 08:42:21.261773  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 2544 08:42:21.277648  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 2545 08:42:21.287275  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 2546 08:42:21.298539  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 2547 08:42:21.313243  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 2548 08:42:21.324542  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 2549 08:42:21.340429  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 2550 08:42:21.350044  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 2551 08:42:21.361189  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 2552 08:42:21.371075  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 2553 08:42:21.382428  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 2554 08:42:21.387428  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 2555 08:42:21.397196  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 2556 08:42:21.408533  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 2557 08:42:21.413238  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 2558 08:42:21.424540  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 2559 08:42:21.429368  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 2560 08:42:21.439298  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 2561 08:42:21.450399  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 2562 08:42:21.460302  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 2563 08:42:21.466409  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 2564 08:42:21.476303  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 2565 08:42:21.486661  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 pass
 2566 08:42:21.492815  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout skip
 2567 08:42:21.502830  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 2568 08:42:21.515297  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 2569 08:42:21.524180  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 2570 08:42:21.536547  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 2571 08:42:21.541548  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 2572 08:42:21.546239  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 2573 08:42:21.551278  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 2574 08:42:21.557535  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 2575 08:42:21.562398  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 2576 08:42:21.572296  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 2577 08:42:21.583283  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 2578 08:42:21.588166  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 2579 08:42:21.599675  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 2580 08:42:21.604425  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 2581 08:42:21.615802  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 2582 08:42:21.620845  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 2583 08:42:21.627043  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 2584 08:42:21.638280  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 2585 08:42:21.643293  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 2586 08:42:21.655669  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 2587 08:42:21.660517  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 2588 08:42:21.671630  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 2589 08:42:21.677765  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 2590 08:42:21.688764  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 2591 08:42:21.693920  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 2592 08:42:21.704878  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 2593 08:42:21.711008  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 2594 08:42:21.722271  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 2595 08:42:21.727265  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 2596 08:42:21.738628  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 2597 08:42:21.744775  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 2598 08:42:21.750925  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 2599 08:42:21.760917  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 2600 08:42:21.767051  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 2601 08:42:21.778266  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 2602 08:42:21.783280  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 2603 08:42:21.794285  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 2604 08:42:21.800543  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 2605 08:42:21.811447  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 2606 08:42:21.821534  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 fail
 2607 08:42:21.832417  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout skip
 2608 08:42:21.842382  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 fail
 2609 08:42:21.848538  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout skip
 2610 08:42:21.858134  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 fail
 2611 08:42:21.869535  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout skip
 2612 08:42:21.879187  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 fail
 2613 08:42:21.890532  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout skip
 2614 08:42:21.900305  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 2615 08:42:21.911671  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 2616 08:42:21.916441  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 2617 08:42:21.926533  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 2618 08:42:21.932666  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 2619 08:42:21.942436  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 2620 08:42:21.953786  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 2621 08:42:21.957652  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 2622 08:42:21.968669  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 2623 08:42:21.974915  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 2624 08:42:21.984666  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 2625 08:42:21.994833  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 2626 08:42:21.999769  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 2627 08:42:22.005854  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 2628 08:42:22.017295  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 2629 08:42:22.022161  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 2630 08:42:22.032034  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 2631 08:42:22.038156  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 2632 08:42:22.047774  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 2633 08:42:22.057883  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 2634 08:42:22.062709  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 2635 08:42:22.073882  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 2636 08:42:22.078922  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 2637 08:42:22.083777  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 2638 08:42:22.095040  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 2639 08:42:22.101285  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 2640 08:42:22.111042  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 2641 08:42:22.116157  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 2642 08:42:22.127163  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 2643 08:42:22.137188  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 2644 08:42:22.144654  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 2645 08:42:22.155915  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 2646 08:42:22.167058  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 2647 08:42:22.173202  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 2648 08:42:22.184281  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 2649 08:42:22.189084  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 2650 08:42:22.194250  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 2651 08:42:22.200594  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 2652 08:42:22.205388  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 2653 08:42:22.215459  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 2654 08:42:22.221766  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 2655 08:42:22.225629  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 2656 08:42:22.235567  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 2657 08:42:22.241728  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 2658 08:42:22.247845  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 2659 08:42:22.252679  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 2660 08:42:22.257725  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 2661 08:42:22.267749  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 2662 08:42:22.272887  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 2663 08:42:22.278992  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 2664 08:42:22.285195  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 2665 08:42:22.290227  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 2666 08:42:22.294974  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 2667 08:42:22.300122  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 2668 08:42:22.306225  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 2669 08:42:22.311237  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 2670 08:42:22.315979  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 2671 08:42:22.321071  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 2672 08:42:22.327202  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 2673 08:42:22.332253  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 2674 08:42:22.337088  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 2675 08:42:22.342121  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 2676 08:42:22.348248  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 2677 08:42:22.353185  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 2678 08:42:22.362994  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 2679 08:42:22.369208  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 2680 08:42:22.369596  dt_test_unprobed_devices_sh_opp-table skip
 2681 08:42:22.374236  dt_test_unprobed_devices_sh_soc skip
 2682 08:42:22.374616  dt_test_unprobed_devices_sh_sound pass
 2683 08:42:22.384001  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 2684 08:42:22.390027  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 2685 08:42:22.394971  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 2686 08:42:22.399779  dt_test_unprobed_devices_sh fail
 2687 08:42:22.404361  + ../../utils/send-to-lava.sh ./output/result.txt
 2688 08:42:22.504594  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 2689 08:42:22.505869  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 2691 08:42:22.696981  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 2692 08:42:22.697609  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 2694 08:42:22.884882  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 2695 08:42:22.885499  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 2697 08:42:23.086775  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 2698 08:42:23.087391  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 2700 08:42:23.277181  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 2701 08:42:23.277805  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 2703 08:42:23.476929  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 2704 08:42:23.477306  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 2706 08:42:23.676861  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 2707 08:42:23.677301  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 2709 08:42:23.848084  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 2710 08:42:23.848807  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 2712 08:42:24.042597  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 2713 08:42:24.043216  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 2715 08:42:24.253079  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 2716 08:42:24.253703  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 2718 08:42:24.422564  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 2719 08:42:24.423184  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 2721 08:42:24.606779  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 2722 08:42:24.607410  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 2724 08:42:24.780667  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 2725 08:42:24.781314  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 2727 08:42:24.965296  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 2728 08:42:24.965921  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 2730 08:42:25.138829  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 2731 08:42:25.139447  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 2733 08:42:25.341422  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 2734 08:42:25.342043  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 2736 08:42:25.524958  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 2737 08:42:25.525579  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 2739 08:42:25.715775  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 2740 08:42:25.716405  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 2742 08:42:25.893270  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 2743 08:42:25.893888  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 2745 08:42:26.067719  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 2746 08:42:26.068366  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 2748 08:42:26.244193  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 2749 08:42:26.244836  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 2751 08:42:26.453546  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 2752 08:42:26.454163  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 2754 08:42:26.642777  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 2755 08:42:26.643395  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 2757 08:42:26.808625  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 2758 08:42:26.809268  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 2760 08:42:27.011504  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 2761 08:42:27.012139  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 2763 08:42:27.198544  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 2764 08:42:27.199164  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 2766 08:42:27.368384  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 2767 08:42:27.369004  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 2769 08:42:27.626210  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 2770 08:42:27.626846  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 2772 08:42:27.818744  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 2773 08:42:27.819374  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 2775 08:42:27.992998  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 2776 08:42:27.993626  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 2778 08:42:28.213416  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 2779 08:42:28.214033  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 2781 08:42:28.383737  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 2782 08:42:28.384361  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 2784 08:42:28.551756  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 2785 08:42:28.552416  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 2787 08:42:28.735520  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 2788 08:42:28.736139  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 2790 08:42:28.909520  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 2791 08:42:28.910177  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 2793 08:42:29.093142  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 2794 08:42:29.093765  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 2796 08:42:29.268375  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 2797 08:42:29.268991  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 2799 08:42:29.447831  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 2800 08:42:29.448452  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 2802 08:42:29.640250  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 2803 08:42:29.640896  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 2805 08:42:29.836578  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 2806 08:42:29.837242  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 2808 08:42:30.044613  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 2809 08:42:30.045258  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 2811 08:42:30.237926  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 2812 08:42:30.238545  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 2814 08:42:30.430468  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 2815 08:42:30.431089  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 2817 08:42:30.613213  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 2818 08:42:30.613836  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 2820 08:42:30.798058  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 2821 08:42:30.798676  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 2823 08:42:30.979745  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 2824 08:42:30.980370  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 2826 08:42:31.164035  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 2827 08:42:31.164655  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 2829 08:42:31.347543  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 2830 08:42:31.348165  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 2832 08:42:31.520043  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 2833 08:42:31.520672  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 2835 08:42:31.697685  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 2836 08:42:31.698304  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 2838 08:42:31.875461  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 2839 08:42:31.876097  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 2841 08:42:32.091146  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 2842 08:42:32.091768  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 2844 08:42:32.289049  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 2845 08:42:32.289672  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 2847 08:42:32.479479  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 2848 08:42:32.480132  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 2850 08:42:32.665613  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 2851 08:42:32.666251  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 2853 08:42:32.848490  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 2854 08:42:32.849138  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 2856 08:42:33.039860  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 2857 08:42:33.040487  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 2859 08:42:33.237463  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 2860 08:42:33.238083  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 2862 08:42:33.404645  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 2863 08:42:33.405290  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 2865 08:42:33.611705  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 2866 08:42:33.612327  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 2868 08:42:33.796871  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 2869 08:42:33.797498  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 2871 08:42:33.988013  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 2872 08:42:33.988635  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 2874 08:42:34.169936  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 2875 08:42:34.170560  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 2877 08:42:34.359746  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 2878 08:42:34.360367  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 2880 08:42:34.538484  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 2881 08:42:34.539103  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 2883 08:42:34.710876  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 2884 08:42:34.711519  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 2886 08:42:34.914826  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 2887 08:42:34.915449  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 2889 08:42:35.112500  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 2890 08:42:35.113153  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 2892 08:42:35.311953  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 2893 08:42:35.312612  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 2895 08:42:35.496679  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 2896 08:42:35.497328  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 2898 08:42:35.685112  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 2899 08:42:35.685741  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 2901 08:42:35.877516  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 2902 08:42:35.878151  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 2904 08:42:36.060167  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 2905 08:42:36.060808  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 2907 08:42:36.254797  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 2908 08:42:36.255429  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 2910 08:42:36.475505  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 2911 08:42:36.476076  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 2913 08:42:36.674574  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 2914 08:42:36.675194  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 2916 08:42:36.863771  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 2917 08:42:36.864394  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 2919 08:42:37.039238  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 2920 08:42:37.039860  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 2922 08:42:37.224211  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 2923 08:42:37.224796  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 2925 08:42:37.413311  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 2926 08:42:37.413837  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 2928 08:42:37.623725  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 2929 08:42:37.624348  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 2931 08:42:37.903693  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 2932 08:42:37.904396  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 2934 08:42:38.090649  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 2935 08:42:38.091271  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 2937 08:42:38.282796  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 2938 08:42:38.283429  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 2940 08:42:38.512934  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 2941 08:42:38.513558  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 2943 08:42:38.701233  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 2944 08:42:38.701854  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 2946 08:42:38.915615  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 2947 08:42:38.916259  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 2949 08:42:39.105650  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 2950 08:42:39.106292  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 2952 08:42:39.287407  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 2953 08:42:39.288025  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 2955 08:42:39.480121  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 2956 08:42:39.480744  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 2958 08:42:39.668469  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 2959 08:42:39.669134  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 2961 08:42:39.857552  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 2962 08:42:39.858175  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 2964 08:42:40.035540  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 2965 08:42:40.036207  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 2967 08:42:40.222514  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 2968 08:42:40.223135  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 2970 08:42:40.420461  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 2971 08:42:40.421109  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 2973 08:42:40.614737  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 2974 08:42:40.615370  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 2976 08:42:40.812114  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 2977 08:42:40.812738  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 2979 08:42:40.988250  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 2980 08:42:40.988871  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 2982 08:42:41.173052  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 2983 08:42:41.173633  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 2985 08:42:41.361974  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 2986 08:42:41.362608  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 2988 08:42:41.575233  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 2989 08:42:41.575857  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 2991 08:42:41.764085  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 2992 08:42:41.764722  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 2994 08:42:41.948872  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 2995 08:42:41.949506  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 2997 08:42:42.115668  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 2998 08:42:42.116223  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 3000 08:42:42.305841  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 3001 08:42:42.306480  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 3003 08:42:42.490762  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 3004 08:42:42.491390  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 3006 08:42:42.669200  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 3007 08:42:42.669821  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 3009 08:42:43.266723  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 3010 08:42:43.267456  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 3012 08:42:43.468545  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 3013 08:42:43.469215  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 3015 08:42:43.691480  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 3016 08:42:43.692143  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 3018 08:42:43.864979  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 3019 08:42:43.865605  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 3021 08:42:44.084837  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 3022 08:42:44.085470  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 3024 08:42:44.284693  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 3025 08:42:44.285352  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 3027 08:42:44.479125  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 3028 08:42:44.479748  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 3030 08:42:44.669604  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 3031 08:42:44.670225  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 3033 08:42:44.854736  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 3034 08:42:44.855365  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 3036 08:42:45.037883  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 3037 08:42:45.038505  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 3039 08:42:45.233437  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 3040 08:42:45.234070  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 3042 08:42:45.403884  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 3043 08:42:45.404543  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 3045 08:42:45.578229  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 3046 08:42:45.578889  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 3048 08:42:45.753388  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 3050 08:42:45.756259  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 3051 08:42:45.933179  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 3053 08:42:45.936003  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 3054 08:42:46.133107  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 3056 08:42:46.136089  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 3057 08:42:46.324026  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 3058 08:42:46.324649  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 3060 08:42:46.501339  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 3061 08:42:46.501989  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 3063 08:42:46.673105  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 3064 08:42:46.673753  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 3066 08:42:46.856873  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 3067 08:42:46.857488  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 3069 08:42:47.039088  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 3070 08:42:47.039717  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 3072 08:42:47.217443  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 3073 08:42:47.218077  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 3075 08:42:47.401000  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 3076 08:42:47.401624  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 3078 08:42:47.598449  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 3079 08:42:47.599082  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 3081 08:42:47.770058  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 3082 08:42:47.770673  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 3084 08:42:47.965197  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 3085 08:42:47.965840  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 3087 08:42:48.140312  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 3088 08:42:48.140960  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 3090 08:42:48.323960  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 3091 08:42:48.324615  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 3093 08:42:48.511748  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 3094 08:42:48.512374  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 3096 08:42:48.703705  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 3097 08:42:48.704302  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 3099 08:42:48.930489  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass>
 3100 08:42:48.931116  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50 RESULT=pass
 3102 08:42:49.147092  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip>
 3103 08:42:49.147718  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout RESULT=skip
 3105 08:42:49.328738  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 3106 08:42:49.329372  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 3108 08:42:49.521064  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 3109 08:42:49.521698  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 3111 08:42:49.713338  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 3112 08:42:49.713972  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 3114 08:42:49.901305  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 3115 08:42:49.901872  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 3117 08:42:50.113591  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 3118 08:42:50.114144  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 3120 08:42:50.308350  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 3121 08:42:50.308989  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 3123 08:42:50.489309  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 3124 08:42:50.489772  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 3126 08:42:50.651386  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 3127 08:42:50.651827  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 3129 08:42:50.839730  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 3130 08:42:50.840177  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 3132 08:42:51.020994  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 3133 08:42:51.021429  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 3135 08:42:51.196041  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 3136 08:42:51.196509  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 3138 08:42:51.361542  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 3139 08:42:51.361983  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 3141 08:42:51.546870  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 3142 08:42:51.547249  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 3144 08:42:51.738838  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 3145 08:42:51.739247  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 3147 08:42:51.940652  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 3148 08:42:51.941364  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 3150 08:42:52.104631  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 3151 08:42:52.105066  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 3153 08:42:52.267031  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 3154 08:42:52.267420  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 3156 08:42:52.433724  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 3157 08:42:52.434143  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 3159 08:42:52.603606  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 3160 08:42:52.604048  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 3162 08:42:52.773425  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 3163 08:42:52.774027  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 3165 08:42:52.943602  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 3166 08:42:52.944223  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 3168 08:42:53.131008  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 3169 08:42:53.131649  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 3171 08:42:53.303023  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 3172 08:42:53.303649  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 3174 08:42:53.481258  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 3175 08:42:53.481894  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 3177 08:42:53.688263  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 3178 08:42:53.688875  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 3180 08:42:53.879032  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 3181 08:42:53.879608  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 3183 08:42:54.060592  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 3184 08:42:54.061178  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 3186 08:42:54.238809  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 3187 08:42:54.239301  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 3189 08:42:54.447912  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 3190 08:42:54.448574  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 3192 08:42:54.649330  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 3193 08:42:54.649949  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 3195 08:42:54.834883  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 3196 08:42:54.835306  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 3198 08:42:55.010895  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 3199 08:42:55.011498  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 3201 08:42:55.211122  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 3202 08:42:55.211659  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 3204 08:42:55.396052  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 3205 08:42:55.396575  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 3207 08:42:55.585639  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 3208 08:42:55.586149  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 3210 08:42:55.776870  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 3211 08:42:55.777293  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 3213 08:42:55.971945  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 3214 08:42:55.972592  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 3216 08:42:56.156664  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 3217 08:42:56.157155  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 3219 08:42:56.353946  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 3220 08:42:56.354543  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 3222 08:42:56.533395  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail>
 3223 08:42:56.533886  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54 RESULT=fail
 3225 08:42:56.732065  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip>
 3226 08:42:56.732580  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout RESULT=skip
 3228 08:42:56.907573  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail>
 3229 08:42:56.908224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55 RESULT=fail
 3231 08:42:57.074428  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip>
 3232 08:42:57.074851  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout RESULT=skip
 3234 08:42:57.250713  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail>
 3235 08:42:57.251172  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56 RESULT=fail
 3237 08:42:57.421885  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip>
 3238 08:42:57.422490  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout RESULT=skip
 3240 08:42:57.613854  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail>
 3241 08:42:57.614345  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57 RESULT=fail
 3243 08:42:57.791334  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip>
 3244 08:42:57.791840  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout RESULT=skip
 3246 08:42:57.971546  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 3247 08:42:57.971951  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 3249 08:42:58.148824  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 3250 08:42:58.149223  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 3252 08:42:58.330190  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 3253 08:42:58.330627  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 3255 08:42:58.505347  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 3256 08:42:58.505797  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 3258 08:42:58.690827  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 3259 08:42:58.691236  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 3261 08:42:58.864754  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 3262 08:42:58.865282  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 3264 08:42:59.032384  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 3265 08:42:59.032841  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 3267 08:42:59.259358  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 3268 08:42:59.259784  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 3270 08:42:59.446103  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 3271 08:42:59.446601  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 3273 08:42:59.618221  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 3274 08:42:59.618870  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 3276 08:42:59.791370  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 3277 08:42:59.791998  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 3279 08:42:59.958778  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 3280 08:42:59.959300  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 3282 08:43:00.141029  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 3283 08:43:00.141488  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 3285 08:43:00.323386  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 3286 08:43:00.323802  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 3288 08:43:00.500472  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 3289 08:43:00.500916  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 3291 08:43:00.707162  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 3292 08:43:00.707587  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 3294 08:43:00.919213  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 3295 08:43:00.919687  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 3297 08:43:01.102591  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 3298 08:43:01.103224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 3300 08:43:01.276597  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 3301 08:43:01.277097  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 3303 08:43:01.452670  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 3304 08:43:01.453206  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 3306 08:43:01.668006  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 3307 08:43:01.668393  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 3309 08:43:01.828573  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 3310 08:43:01.829175  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 3312 08:43:02.006912  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 3313 08:43:02.007535  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 3315 08:43:02.215244  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 3316 08:43:02.215750  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 3318 08:43:02.395545  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 3319 08:43:02.395965  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 3321 08:43:02.607401  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 3322 08:43:02.607864  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 3324 08:43:02.779375  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 3325 08:43:02.779943  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 3327 08:43:02.966422  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 3328 08:43:02.967067  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 3330 08:43:03.149645  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 3331 08:43:03.150084  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 3333 08:43:03.569666  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 3334 08:43:03.570422  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 3336 08:43:03.748954  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 3337 08:43:03.749302  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 3339 08:43:03.927880  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 3340 08:43:03.928424  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 3342 08:43:04.125111  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 3343 08:43:04.125707  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 3345 08:43:04.311805  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 3346 08:43:04.312475  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 3348 08:43:04.520838  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 3349 08:43:04.521415  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 3351 08:43:04.710451  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 3352 08:43:04.711105  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 3354 08:43:04.904288  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 3355 08:43:04.904805  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 3357 08:43:05.095956  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 3358 08:43:05.096397  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 3360 08:43:05.296249  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
 3361 08:43:05.296890  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
 3363 08:43:05.470902  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
 3364 08:43:05.471532  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
 3366 08:43:05.662538  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
 3367 08:43:05.663180  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
 3369 08:43:05.836864  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
 3371 08:43:05.839790  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
 3372 08:43:06.024823  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
 3373 08:43:06.025301  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
 3375 08:43:06.200808  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
 3376 08:43:06.201231  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
 3378 08:43:06.379990  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
 3379 08:43:06.380620  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
 3381 08:43:06.576864  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
 3382 08:43:06.577283  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
 3384 08:43:06.768437  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
 3385 08:43:06.768916  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
 3387 08:43:06.956196  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
 3388 08:43:06.956666  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
 3390 08:43:07.143455  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
 3391 08:43:07.143857  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
 3393 08:43:07.320377  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
 3394 08:43:07.321006  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
 3396 08:43:07.501287  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
 3397 08:43:07.501716  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
 3399 08:43:07.686638  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
 3400 08:43:07.687101  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
 3402 08:43:07.885696  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
 3403 08:43:07.886223  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
 3405 08:43:08.061708  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
 3406 08:43:08.062338  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
 3408 08:43:08.237557  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
 3409 08:43:08.238182  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
 3411 08:43:09.433462  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
 3412 08:43:09.434237  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
 3414 08:43:10.326806  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
 3415 08:43:10.327230  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
 3417 08:43:10.510112  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
 3418 08:43:10.510462  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
 3420 08:43:10.683908  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
 3421 08:43:10.684371  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
 3423 08:43:10.874326  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
 3424 08:43:10.874711  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
 3426 08:43:11.055343  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
 3427 08:43:11.055717  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
 3429 08:43:11.240992  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
 3430 08:43:11.241337  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
 3432 08:43:11.411092  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
 3433 08:43:11.411432  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
 3435 08:43:11.578525  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
 3436 08:43:11.578865  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
 3438 08:43:11.752158  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
 3439 08:43:11.752497  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
 3441 08:43:11.946821  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
 3442 08:43:11.947160  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
 3444 08:43:12.127616  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
 3445 08:43:12.127958  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
 3447 08:43:12.307151  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
 3448 08:43:12.307489  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
 3450 08:43:12.493203  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
 3451 08:43:12.493540  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
 3453 08:43:12.703505  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
 3454 08:43:12.703843  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
 3456 08:43:12.896382  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
 3457 08:43:12.896721  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
 3459 08:43:13.066140  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
 3460 08:43:13.066478  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
 3462 08:43:13.235127  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
 3463 08:43:13.235466  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
 3465 08:43:13.241629  + set +x
 3466 08:43:13.244856  <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1214309_1.6.2.4.5>
 3467 08:43:13.245191  Received signal: <ENDRUN> 1_kselftest-dt 1214309_1.6.2.4.5
 3468 08:43:13.245337  Ending use of test pattern.
 3469 08:43:13.245461  Ending test lava.1_kselftest-dt (1214309_1.6.2.4.5), duration 361.97
 3471 08:43:13.303176  <LAVA_TEST_RUNNER EXIT>
 3472 08:43:13.303512  ok: lava_test_shell seems to have completed
 3473 08:43:13.306472  dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_eeprom_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass

 3474 08:43:13.307067  end: 3.1 lava-test-shell (duration 00:06:04) [common]
 3475 08:43:13.307236  end: 3 lava-test-retry (duration 00:06:04) [common]
 3476 08:43:13.307412  start: 4 finalize (timeout 00:00:31) [common]
 3477 08:43:13.307580  start: 4.1 power-off (timeout 00:00:30) [common]
 3478 08:43:13.307785  Calling: 'drpm' 'lf-bbb-02' 'off'
 3479 08:43:13.572623  >> OFF

 3480 08:43:13.573305  Returned 0 in 0 seconds
 3481 08:43:13.673710  end: 4.1 power-off (duration 00:00:00) [common]
 3483 08:43:13.674171  start: 4.2 read-feedback (timeout 00:00:31) [common]
 3484 08:43:13.674535  Listened to connection for namespace 'common' for up to 1s
 3485 08:43:13.674897  Listened to connection for namespace 'common' for up to 1s
 3486 08:43:14.674962  Finalising connection for namespace 'common'
 3487 08:43:14.675283  Disconnecting from shell: Finalise
 3488 08:43:14.675427  / # 
 3489 08:43:14.775775  end: 4.2 read-feedback (duration 00:00:01) [common]
 3490 08:43:14.775977  end: 4 finalize (duration 00:00:01) [common]
 3491 08:43:14.776157  Cleaning after the job
 3492 08:43:14.776328  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/ramdisk
 3493 08:43:14.778688  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/kernel
 3494 08:43:14.780608  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/dtb
 3495 08:43:14.780902  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/nfsrootfs
 3496 08:43:14.849526  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1214309/tftp-deploy-z6iehxvg/modules
 3497 08:43:14.854279  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1214309
 3498 08:43:15.837561  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1214309
 3499 08:43:15.837870  Job finished correctly