Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:38:48.024576 lava-dispatcher, installed at version: 2024.01
2 09:38:48.025357 start: 0 validate
3 09:38:48.025818 Start time: 2024-10-31 09:38:48.025789+00:00 (UTC)
4 09:38:48.026369 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:38:48.026905 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:38:48.063071 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:38:48.063728 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241031%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 09:38:48.096795 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:38:48.097472 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241031%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 09:38:49.149631 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:38:49.150133 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241031%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 09:38:49.187843 validate duration: 1.16
14 09:38:49.188728 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:38:49.189038 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:38:49.189324 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:38:49.189899 Not decompressing ramdisk as can be used compressed.
18 09:38:49.190383 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:38:49.190877 saving as /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/ramdisk/rootfs.cpio.gz
20 09:38:49.191370 total size: 8181887 (7 MB)
21 09:38:49.229616 progress 0 % (0 MB)
22 09:38:49.241326 progress 5 % (0 MB)
23 09:38:49.252525 progress 10 % (0 MB)
24 09:38:49.263657 progress 15 % (1 MB)
25 09:38:49.269070 progress 20 % (1 MB)
26 09:38:49.274681 progress 25 % (1 MB)
27 09:38:49.279845 progress 30 % (2 MB)
28 09:38:49.285447 progress 35 % (2 MB)
29 09:38:49.290631 progress 40 % (3 MB)
30 09:38:49.296202 progress 45 % (3 MB)
31 09:38:49.301463 progress 50 % (3 MB)
32 09:38:49.307008 progress 55 % (4 MB)
33 09:38:49.312189 progress 60 % (4 MB)
34 09:38:49.317768 progress 65 % (5 MB)
35 09:38:49.322981 progress 70 % (5 MB)
36 09:38:49.328571 progress 75 % (5 MB)
37 09:38:49.333804 progress 80 % (6 MB)
38 09:38:49.339445 progress 85 % (6 MB)
39 09:38:49.344546 progress 90 % (7 MB)
40 09:38:49.349696 progress 95 % (7 MB)
41 09:38:49.354472 progress 100 % (7 MB)
42 09:38:49.355322 7 MB downloaded in 0.16 s (47.60 MB/s)
43 09:38:49.355892 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:38:49.356802 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:38:49.357091 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:38:49.357359 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:38:49.357846 downloading http://storage.kernelci.org/next/master/next-20241031/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
49 09:38:49.358099 saving as /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/kernel/Image
50 09:38:49.358307 total size: 46258688 (44 MB)
51 09:38:49.358517 No compression specified
52 09:38:49.393902 progress 0 % (0 MB)
53 09:38:49.423573 progress 5 % (2 MB)
54 09:38:49.453143 progress 10 % (4 MB)
55 09:38:49.482776 progress 15 % (6 MB)
56 09:38:49.512410 progress 20 % (8 MB)
57 09:38:49.541973 progress 25 % (11 MB)
58 09:38:49.571565 progress 30 % (13 MB)
59 09:38:49.601355 progress 35 % (15 MB)
60 09:38:49.630965 progress 40 % (17 MB)
61 09:38:49.660911 progress 45 % (19 MB)
62 09:38:49.690369 progress 50 % (22 MB)
63 09:38:49.720050 progress 55 % (24 MB)
64 09:38:49.749168 progress 60 % (26 MB)
65 09:38:49.778612 progress 65 % (28 MB)
66 09:38:49.807489 progress 70 % (30 MB)
67 09:38:49.836831 progress 75 % (33 MB)
68 09:38:49.865915 progress 80 % (35 MB)
69 09:38:49.894940 progress 85 % (37 MB)
70 09:38:49.924698 progress 90 % (39 MB)
71 09:38:49.953744 progress 95 % (41 MB)
72 09:38:49.981241 progress 100 % (44 MB)
73 09:38:49.981968 44 MB downloaded in 0.62 s (70.74 MB/s)
74 09:38:49.982454 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:38:49.983265 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:38:49.983539 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:38:49.983800 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:38:49.984356 downloading http://storage.kernelci.org/next/master/next-20241031/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 09:38:49.984649 saving as /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 09:38:49.984854 total size: 53209 (0 MB)
82 09:38:49.985062 No compression specified
83 09:38:50.027620 progress 61 % (0 MB)
84 09:38:50.028499 progress 100 % (0 MB)
85 09:38:50.029031 0 MB downloaded in 0.04 s (1.15 MB/s)
86 09:38:50.029491 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:38:50.030295 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:38:50.030555 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:38:50.030816 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:38:50.031271 downloading http://storage.kernelci.org/next/master/next-20241031/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
92 09:38:50.031510 saving as /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/modules/modules.tar
93 09:38:50.031713 total size: 11589624 (11 MB)
94 09:38:50.031922 Using unxz to decompress xz
95 09:38:50.073803 progress 0 % (0 MB)
96 09:38:50.154017 progress 5 % (0 MB)
97 09:38:50.242834 progress 10 % (1 MB)
98 09:38:50.338307 progress 15 % (1 MB)
99 09:38:50.417013 progress 20 % (2 MB)
100 09:38:50.495170 progress 25 % (2 MB)
101 09:38:50.576223 progress 30 % (3 MB)
102 09:38:50.650946 progress 35 % (3 MB)
103 09:38:50.732359 progress 40 % (4 MB)
104 09:38:50.821023 progress 45 % (5 MB)
105 09:38:50.898948 progress 50 % (5 MB)
106 09:38:50.983732 progress 55 % (6 MB)
107 09:38:51.065892 progress 60 % (6 MB)
108 09:38:51.147225 progress 65 % (7 MB)
109 09:38:51.227435 progress 70 % (7 MB)
110 09:38:51.311275 progress 75 % (8 MB)
111 09:38:51.390250 progress 80 % (8 MB)
112 09:38:51.472353 progress 85 % (9 MB)
113 09:38:51.546159 progress 90 % (9 MB)
114 09:38:51.648371 progress 95 % (10 MB)
115 09:38:51.740678 progress 100 % (11 MB)
116 09:38:51.754047 11 MB downloaded in 1.72 s (6.42 MB/s)
117 09:38:51.755081 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:38:51.756912 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:38:51.757504 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 09:38:51.758079 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 09:38:51.758624 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:38:51.759181 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 09:38:51.760263 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb
125 09:38:51.761264 makedir: /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin
126 09:38:51.762061 makedir: /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/tests
127 09:38:51.762778 makedir: /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/results
128 09:38:51.763448 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-add-keys
129 09:38:51.764567 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-add-sources
130 09:38:51.765682 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-background-process-start
131 09:38:51.766751 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-background-process-stop
132 09:38:51.767950 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-common-functions
133 09:38:51.769045 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-echo-ipv4
134 09:38:51.770086 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-install-packages
135 09:38:51.771145 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-installed-packages
136 09:38:51.772210 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-os-build
137 09:38:51.773252 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-probe-channel
138 09:38:51.774301 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-probe-ip
139 09:38:51.775316 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-target-ip
140 09:38:51.776369 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-target-mac
141 09:38:51.777391 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-target-storage
142 09:38:51.778416 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-test-case
143 09:38:51.779428 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-test-event
144 09:38:51.780476 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-test-feedback
145 09:38:51.781491 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-test-raise
146 09:38:51.782538 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-test-reference
147 09:38:51.783562 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-test-runner
148 09:38:51.784624 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-test-set
149 09:38:51.785646 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-test-shell
150 09:38:51.786672 Updating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-install-packages (oe)
151 09:38:51.787779 Updating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/bin/lava-installed-packages (oe)
152 09:38:51.788824 Creating /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/environment
153 09:38:51.789641 LAVA metadata
154 09:38:51.790177 - LAVA_JOB_ID=916880
155 09:38:51.790650 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:38:51.791392 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 09:38:51.793487 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:38:51.794150 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 09:38:51.794609 skipped lava-vland-overlay
160 09:38:51.795147 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:38:51.795714 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 09:38:51.796273 skipped lava-multinode-overlay
163 09:38:51.796776 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:38:51.797310 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 09:38:51.797800 Loading test definitions
166 09:38:51.798351 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 09:38:51.798796 Using /lava-916880 at stage 0
168 09:38:51.800794 uuid=916880_1.5.2.4.1 testdef=None
169 09:38:51.801267 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:38:51.801854 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 09:38:51.805931 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:38:51.807727 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 09:38:51.812897 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:38:51.814797 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 09:38:51.819734 runner path: /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/0/tests/0_dmesg test_uuid 916880_1.5.2.4.1
178 09:38:51.820878 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:38:51.822443 Creating lava-test-runner.conf files
181 09:38:51.822870 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/916880/lava-overlay-304hlmrb/lava-916880/0 for stage 0
182 09:38:51.823603 - 0_dmesg
183 09:38:51.824277 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:38:51.824602 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 09:38:51.851426 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:38:51.851871 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 09:38:51.852222 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:38:51.852533 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:38:51.852833 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 09:38:52.854224 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:38:52.855033 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 09:38:52.855583 extracting modules file /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/916880/extract-overlay-ramdisk-kxw4h1x6/ramdisk
193 09:38:54.394473 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 09:38:54.395125 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 09:38:54.395423 [common] Applying overlay /var/lib/lava/dispatcher/tmp/916880/compress-overlay-cwgm5ncv/overlay-1.5.2.5.tar.gz to ramdisk
196 09:38:54.396114 [common] Applying overlay /var/lib/lava/dispatcher/tmp/916880/compress-overlay-cwgm5ncv/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/916880/extract-overlay-ramdisk-kxw4h1x6/ramdisk
197 09:38:54.444012 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:38:54.444635 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 09:38:54.445548 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 09:38:54.445870 Converting downloaded kernel to a uImage
201 09:38:54.446291 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/kernel/Image /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/kernel/uImage
202 09:38:55.002483 output: Image Name:
203 09:38:55.002905 output: Created: Thu Oct 31 09:38:54 2024
204 09:38:55.003114 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:38:55.003317 output: Data Size: 46258688 Bytes = 45174.50 KiB = 44.12 MiB
206 09:38:55.003519 output: Load Address: 01080000
207 09:38:55.003718 output: Entry Point: 01080000
208 09:38:55.003915 output:
209 09:38:55.004284 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 09:38:55.004550 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 09:38:55.004816 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 09:38:55.005065 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:38:55.005319 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 09:38:55.005579 Building ramdisk /var/lib/lava/dispatcher/tmp/916880/extract-overlay-ramdisk-kxw4h1x6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/916880/extract-overlay-ramdisk-kxw4h1x6/ramdisk
215 09:38:57.811495 >> 181912 blocks
216 09:39:06.343130 Adding RAMdisk u-boot header.
217 09:39:06.343778 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/916880/extract-overlay-ramdisk-kxw4h1x6/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/916880/extract-overlay-ramdisk-kxw4h1x6/ramdisk.cpio.gz.uboot
218 09:39:06.623696 output: Image Name:
219 09:39:06.624205 output: Created: Thu Oct 31 09:39:06 2024
220 09:39:06.624641 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:39:06.625052 output: Data Size: 26053389 Bytes = 25442.76 KiB = 24.85 MiB
222 09:39:06.625457 output: Load Address: 00000000
223 09:39:06.625856 output: Entry Point: 00000000
224 09:39:06.626247 output:
225 09:39:06.627325 rename /var/lib/lava/dispatcher/tmp/916880/extract-overlay-ramdisk-kxw4h1x6/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/ramdisk/ramdisk.cpio.gz.uboot
226 09:39:06.628069 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 09:39:06.628628 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 09:39:06.629156 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 09:39:06.629606 No LXC device requested
230 09:39:06.630105 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:39:06.630608 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 09:39:06.631099 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:39:06.631508 Checking files for TFTP limit of 4294967296 bytes.
234 09:39:06.634171 end: 1 tftp-deploy (duration 00:00:17) [common]
235 09:39:06.634742 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:39:06.635272 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:39:06.635771 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:39:06.636319 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:39:06.636853 Using kernel file from prepare-kernel: 916880/tftp-deploy-55bsg2hq/kernel/uImage
240 09:39:06.637482 substitutions:
241 09:39:06.637896 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:39:06.638301 - {DTB_ADDR}: 0x01070000
243 09:39:06.638697 - {DTB}: 916880/tftp-deploy-55bsg2hq/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 09:39:06.639094 - {INITRD}: 916880/tftp-deploy-55bsg2hq/ramdisk/ramdisk.cpio.gz.uboot
245 09:39:06.639487 - {KERNEL_ADDR}: 0x01080000
246 09:39:06.639876 - {KERNEL}: 916880/tftp-deploy-55bsg2hq/kernel/uImage
247 09:39:06.640306 - {LAVA_MAC}: None
248 09:39:06.640741 - {PRESEED_CONFIG}: None
249 09:39:06.641141 - {PRESEED_LOCAL}: None
250 09:39:06.641530 - {RAMDISK_ADDR}: 0x08000000
251 09:39:06.641915 - {RAMDISK}: 916880/tftp-deploy-55bsg2hq/ramdisk/ramdisk.cpio.gz.uboot
252 09:39:06.642308 - {ROOT_PART}: None
253 09:39:06.642697 - {ROOT}: None
254 09:39:06.643084 - {SERVER_IP}: 192.168.6.2
255 09:39:06.643471 - {TEE_ADDR}: 0x83000000
256 09:39:06.643857 - {TEE}: None
257 09:39:06.644287 Parsed boot commands:
258 09:39:06.644678 - setenv autoload no
259 09:39:06.645073 - setenv initrd_high 0xffffffff
260 09:39:06.645463 - setenv fdt_high 0xffffffff
261 09:39:06.645854 - dhcp
262 09:39:06.646243 - setenv serverip 192.168.6.2
263 09:39:06.646631 - tftpboot 0x01080000 916880/tftp-deploy-55bsg2hq/kernel/uImage
264 09:39:06.647021 - tftpboot 0x08000000 916880/tftp-deploy-55bsg2hq/ramdisk/ramdisk.cpio.gz.uboot
265 09:39:06.647411 - tftpboot 0x01070000 916880/tftp-deploy-55bsg2hq/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 09:39:06.647799 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:39:06.648253 - bootm 0x01080000 0x08000000 0x01070000
268 09:39:06.648757 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:39:06.650249 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:39:06.650699 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 09:39:06.665251 Setting prompt string to ['lava-test: # ']
273 09:39:06.666725 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:39:06.667336 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:39:06.667885 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:39:06.668466 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:39:06.669616 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 09:39:06.706504 >> OK - accepted request
279 09:39:06.708736 Returned 0 in 0 seconds
280 09:39:06.809834 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:39:06.811455 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:39:06.812093 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:39:06.812621 Setting prompt string to ['Hit any key to stop autoboot']
285 09:39:06.813086 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:39:06.814682 Trying 192.168.56.21...
287 09:39:06.815167 Connected to conserv1.
288 09:39:06.815598 Escape character is '^]'.
289 09:39:06.816060
290 09:39:06.816508 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 09:39:06.816940
292 09:39:14.097427 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 09:39:14.098101 bl2_stage_init 0x01
294 09:39:14.098592 bl2_stage_init 0x81
295 09:39:14.102812 hw id: 0x0000 - pwm id 0x01
296 09:39:14.103338 bl2_stage_init 0xc1
297 09:39:14.108431 bl2_stage_init 0x02
298 09:39:14.108981
299 09:39:14.109393 L0:00000000
300 09:39:14.109809 L1:00000703
301 09:39:14.110203 L2:00008067
302 09:39:14.110606 L3:15000000
303 09:39:14.113999 S1:00000000
304 09:39:14.114450 B2:20282000
305 09:39:14.114847 B1:a0f83180
306 09:39:14.115240
307 09:39:14.115633 TE: 67717
308 09:39:14.116063
309 09:39:14.119596 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 09:39:14.120069
311 09:39:14.125240 Board ID = 1
312 09:39:14.125682 Set cpu clk to 24M
313 09:39:14.126074 Set clk81 to 24M
314 09:39:14.130762 Use GP1_pll as DSU clk.
315 09:39:14.131204 DSU clk: 1200 Mhz
316 09:39:14.131597 CPU clk: 1200 MHz
317 09:39:14.136377 Set clk81 to 166.6M
318 09:39:14.141962 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 09:39:14.142404 board id: 1
320 09:39:14.148154 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:39:14.160010 fw parse done
322 09:39:14.165786 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:39:14.208206 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:39:14.220181 PIEI prepare done
325 09:39:14.220637 fastboot data load
326 09:39:14.221039 fastboot data verify
327 09:39:14.225732 verify result: 266
328 09:39:14.231432 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 09:39:14.231868 LPDDR4 probe
330 09:39:14.232311 ddr clk to 1584MHz
331 09:39:14.238589 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:39:14.276506
333 09:39:14.276959 dmc_version 0001
334 09:39:14.283294 Check phy result
335 09:39:14.290094 INFO : End of CA training
336 09:39:14.290543 INFO : End of initialization
337 09:39:14.295654 INFO : Training has run successfully!
338 09:39:14.296106 Check phy result
339 09:39:14.301239 INFO : End of initialization
340 09:39:14.301672 INFO : End of read enable training
341 09:39:14.304563 INFO : End of fine write leveling
342 09:39:14.310227 INFO : End of Write leveling coarse delay
343 09:39:14.315906 INFO : Training has run successfully!
344 09:39:14.316367 Check phy result
345 09:39:14.316762 INFO : End of initialization
346 09:39:14.321446 INFO : End of read dq deskew training
347 09:39:14.327052 INFO : End of MPR read delay center optimization
348 09:39:14.327482 INFO : End of write delay center optimization
349 09:39:14.332713 INFO : End of read delay center optimization
350 09:39:14.338349 INFO : End of max read latency training
351 09:39:14.338889 INFO : Training has run successfully!
352 09:39:14.343857 1D training succeed
353 09:39:14.349013 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:39:14.397532 Check phy result
355 09:39:14.397978 INFO : End of initialization
356 09:39:14.424601 INFO : End of 2D read delay Voltage center optimization
357 09:39:14.449251 INFO : End of 2D read delay Voltage center optimization
358 09:39:14.506265 INFO : End of 2D write delay Voltage center optimization
359 09:39:14.560452 INFO : End of 2D write delay Voltage center optimization
360 09:39:14.566081 INFO : Training has run successfully!
361 09:39:14.566508
362 09:39:14.566902 channel==0
363 09:39:14.571822 RxClkDly_Margin_A0==78 ps 8
364 09:39:14.572303 TxDqDly_Margin_A0==98 ps 10
365 09:39:14.574892 RxClkDly_Margin_A1==78 ps 8
366 09:39:14.575313 TxDqDly_Margin_A1==98 ps 10
367 09:39:14.580459 TrainedVREFDQ_A0==74
368 09:39:14.580896 TrainedVREFDQ_A1==75
369 09:39:14.586030 VrefDac_Margin_A0==24
370 09:39:14.586470 DeviceVref_Margin_A0==40
371 09:39:14.586859 VrefDac_Margin_A1==23
372 09:39:14.591636 DeviceVref_Margin_A1==39
373 09:39:14.592096
374 09:39:14.592490
375 09:39:14.592876 channel==1
376 09:39:14.593259 RxClkDly_Margin_A0==78 ps 8
377 09:39:14.595162 TxDqDly_Margin_A0==88 ps 9
378 09:39:14.600550 RxClkDly_Margin_A1==88 ps 9
379 09:39:14.600974 TxDqDly_Margin_A1==88 ps 9
380 09:39:14.601367 TrainedVREFDQ_A0==75
381 09:39:14.606194 TrainedVREFDQ_A1==75
382 09:39:14.606614 VrefDac_Margin_A0==22
383 09:39:14.611916 DeviceVref_Margin_A0==39
384 09:39:14.612367 VrefDac_Margin_A1==22
385 09:39:14.612758 DeviceVref_Margin_A1==39
386 09:39:14.613139
387 09:39:14.620926 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:39:14.621370
389 09:39:14.648934 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 09:39:14.649465 2D training succeed
391 09:39:14.654532 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:39:14.660109 auto size-- 65535DDR cs0 size: 2048MB
393 09:39:14.660542 DDR cs1 size: 2048MB
394 09:39:14.665725 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:39:14.666143 cs0 DataBus test pass
396 09:39:14.671218 cs1 DataBus test pass
397 09:39:14.671645 cs0 AddrBus test pass
398 09:39:14.672069 cs1 AddrBus test pass
399 09:39:14.676822
400 09:39:14.677253 100bdlr_step_size ps== 471
401 09:39:14.677653 result report
402 09:39:14.682406 boot times 0Enable ddr reg access
403 09:39:14.687916 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:39:14.702354 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 09:39:15.361392 bl2z: ptr: 05129330, size: 00001e40
406 09:39:15.370257 0.0;M3 CHK:0;cm4_sp_mode 0
407 09:39:15.370717 MVN_1=0x00000000
408 09:39:15.371121 MVN_2=0x00000000
409 09:39:15.381748 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 09:39:15.382191 OPS=0x04
411 09:39:15.382591 ring efuse init
412 09:39:15.384821 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 09:39:15.390150 [0.017354 Inits done]
414 09:39:15.390619 secure task start!
415 09:39:15.391016 high task start!
416 09:39:15.391403 low task start!
417 09:39:15.394184 run into bl31
418 09:39:15.403750 NOTICE: BL31: v1.3(release):4fc40b1
419 09:39:15.410995 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 09:39:15.411437 NOTICE: BL31: G12A normal boot!
421 09:39:15.427091 NOTICE: BL31: BL33 decompress pass
422 09:39:15.432796 ERROR: Error initializing runtime service opteed_fast
423 09:39:16.649701 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 09:39:16.650300 bl2_stage_init 0x01
425 09:39:16.650725 bl2_stage_init 0x81
426 09:39:16.655263 hw id: 0x0000 - pwm id 0x01
427 09:39:16.655758 bl2_stage_init 0xc1
428 09:39:16.660944 bl2_stage_init 0x02
429 09:39:16.661408
430 09:39:16.661823 L0:00000000
431 09:39:16.662229 L1:00000703
432 09:39:16.662629 L2:00008067
433 09:39:16.663024 L3:15000000
434 09:39:16.666473 S1:00000000
435 09:39:16.666909 B2:20282000
436 09:39:16.667309 B1:a0f83180
437 09:39:16.667703
438 09:39:16.668146 TE: 70240
439 09:39:16.668558
440 09:39:16.672056 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 09:39:16.672496
442 09:39:16.677700 Board ID = 1
443 09:39:16.678131 Set cpu clk to 24M
444 09:39:16.678531 Set clk81 to 24M
445 09:39:16.683213 Use GP1_pll as DSU clk.
446 09:39:16.683636 DSU clk: 1200 Mhz
447 09:39:16.684066 CPU clk: 1200 MHz
448 09:39:16.688968 Set clk81 to 166.6M
449 09:39:16.694464 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 09:39:16.694893 board id: 1
451 09:39:16.700769 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 09:39:16.712297 fw parse done
453 09:39:16.717291 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 09:39:16.760091 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 09:39:16.771862 PIEI prepare done
456 09:39:16.772336 fastboot data load
457 09:39:16.772746 fastboot data verify
458 09:39:16.777519 verify result: 266
459 09:39:16.783084 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 09:39:16.783519 LPDDR4 probe
461 09:39:16.783922 ddr clk to 1584MHz
462 09:39:18.148404 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 09:39:18.149077 bl2_stage_init 0x01
464 09:39:18.149502 bl2_stage_init 0x81
465 09:39:18.153956 hw id: 0x0000 - pwm id 0x01
466 09:39:18.154434 bl2_stage_init 0xc1
467 09:39:18.159617 bl2_stage_init 0x02
468 09:39:18.160178
469 09:39:18.160599 L0:00000000
470 09:39:18.160983 L1:00000703
471 09:39:18.161371 L2:00008067
472 09:39:18.161750 L3:15000000
473 09:39:18.165178 S1:00000000
474 09:39:18.165601 B2:20282000
475 09:39:18.165983 B1:a0f83180
476 09:39:18.166360
477 09:39:18.166739 TE: 69137
478 09:39:18.167120
479 09:39:18.170798 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 09:39:18.171223
481 09:39:18.176369 Board ID = 1
482 09:39:18.176814 Set cpu clk to 24M
483 09:39:18.177200 Set clk81 to 24M
484 09:39:18.181957 Use GP1_pll as DSU clk.
485 09:39:18.182373 DSU clk: 1200 Mhz
486 09:39:18.182755 CPU clk: 1200 MHz
487 09:39:18.187569 Set clk81 to 166.6M
488 09:39:18.193162 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 09:39:18.193596 board id: 1
490 09:39:18.199477 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 09:39:18.211289 fw parse done
492 09:39:18.216321 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 09:39:18.259544 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 09:39:18.271592 PIEI prepare done
495 09:39:18.272052 fastboot data load
496 09:39:18.272445 fastboot data verify
497 09:39:18.277107 verify result: 266
498 09:39:18.282727 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 09:39:18.283150 LPDDR4 probe
500 09:39:18.283534 ddr clk to 1584MHz
501 09:39:18.289773 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 09:39:18.328500
503 09:39:18.329023 dmc_version 0001
504 09:39:18.335464 Check phy result
505 09:39:18.341405 INFO : End of CA training
506 09:39:18.341827 INFO : End of initialization
507 09:39:18.347032 INFO : Training has run successfully!
508 09:39:18.347517 Check phy result
509 09:39:18.352643 INFO : End of initialization
510 09:39:18.353083 INFO : End of read enable training
511 09:39:18.358237 INFO : End of fine write leveling
512 09:39:18.363875 INFO : End of Write leveling coarse delay
513 09:39:18.364362 INFO : Training has run successfully!
514 09:39:18.364770 Check phy result
515 09:39:18.369453 INFO : End of initialization
516 09:39:18.369882 INFO : End of read dq deskew training
517 09:39:18.375004 INFO : End of MPR read delay center optimization
518 09:39:18.380611 INFO : End of write delay center optimization
519 09:39:18.386298 INFO : End of read delay center optimization
520 09:39:18.386726 INFO : End of max read latency training
521 09:39:18.391836 INFO : Training has run successfully!
522 09:39:18.392290 1D training succeed
523 09:39:18.401035 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 09:39:18.449395 Check phy result
525 09:39:18.449830 INFO : End of initialization
526 09:39:18.476692 INFO : End of 2D read delay Voltage center optimization
527 09:39:18.500985 INFO : End of 2D read delay Voltage center optimization
528 09:39:18.557691 INFO : End of 2D write delay Voltage center optimization
529 09:39:18.611736 INFO : End of 2D write delay Voltage center optimization
530 09:39:18.617432 INFO : Training has run successfully!
531 09:39:18.617876
532 09:39:18.618140 channel==0
533 09:39:18.622922 RxClkDly_Margin_A0==78 ps 8
534 09:39:18.623355 TxDqDly_Margin_A0==98 ps 10
535 09:39:18.628526 RxClkDly_Margin_A1==88 ps 9
536 09:39:18.629025 TxDqDly_Margin_A1==88 ps 9
537 09:39:18.629324 TrainedVREFDQ_A0==74
538 09:39:18.634146 TrainedVREFDQ_A1==74
539 09:39:18.634649 VrefDac_Margin_A0==24
540 09:39:18.634914 DeviceVref_Margin_A0==40
541 09:39:18.639717 VrefDac_Margin_A1==23
542 09:39:18.640362 DeviceVref_Margin_A1==40
543 09:39:18.640822
544 09:39:18.641371
545 09:39:18.641726 channel==1
546 09:39:18.645384 RxClkDly_Margin_A0==78 ps 8
547 09:39:18.646045 TxDqDly_Margin_A0==98 ps 10
548 09:39:18.650933 RxClkDly_Margin_A1==88 ps 9
549 09:39:18.651392 TxDqDly_Margin_A1==88 ps 9
550 09:39:18.656543 TrainedVREFDQ_A0==78
551 09:39:18.656996 TrainedVREFDQ_A1==75
552 09:39:18.657282 VrefDac_Margin_A0==22
553 09:39:18.662154 DeviceVref_Margin_A0==36
554 09:39:18.662781 VrefDac_Margin_A1==22
555 09:39:18.667710 DeviceVref_Margin_A1==39
556 09:39:18.668217
557 09:39:18.668477 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 09:39:18.668702
559 09:39:18.701115 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000015 00000017 dram_vref_reg_value 0x 00000062
560 09:39:18.701516 2D training succeed
561 09:39:18.706711 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 09:39:18.712326 auto size-- 65535DDR cs0 size: 2048MB
563 09:39:18.712586 DDR cs1 size: 2048MB
564 09:39:18.717981 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 09:39:18.718252 cs0 DataBus test pass
566 09:39:18.723564 cs1 DataBus test pass
567 09:39:18.723823 cs0 AddrBus test pass
568 09:39:18.724268 cs1 AddrBus test pass
569 09:39:18.724676
570 09:39:18.729220 100bdlr_step_size ps== 471
571 09:39:18.729687 result report
572 09:39:18.734769 boot times 0Enable ddr reg access
573 09:39:18.739968 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 09:39:18.753790 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 09:39:19.413189 bl2z: ptr: 05129330, size: 00001e40
576 09:39:19.421208 0.0;M3 CHK:0;cm4_sp_mode 0
577 09:39:19.421679 MVN_1=0x00000000
578 09:39:19.422094 MVN_2=0x00000000
579 09:39:19.432701 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 09:39:19.433151 OPS=0x04
581 09:39:19.433565 ring efuse init
582 09:39:19.438307 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 09:39:19.438752 [0.017354 Inits done]
584 09:39:19.439158 secure task start!
585 09:39:19.446417 high task start!
586 09:39:19.446855 low task start!
587 09:39:19.447258 run into bl31
588 09:39:19.455043 NOTICE: BL31: v1.3(release):4fc40b1
589 09:39:19.462609 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 09:39:19.463049 NOTICE: BL31: G12A normal boot!
591 09:39:19.478354 NOTICE: BL31: BL33 decompress pass
592 09:39:19.484041 ERROR: Error initializing runtime service opteed_fast
593 09:39:20.700350 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 09:39:20.700981 bl2_stage_init 0x01
595 09:39:20.701445 bl2_stage_init 0x81
596 09:39:20.705787 hw id: 0x0000 - pwm id 0x01
597 09:39:20.706306 bl2_stage_init 0xc1
598 09:39:20.706765 bl2_stage_init 0x02
599 09:39:20.707210
600 09:39:20.711368 L0:00000000
601 09:39:20.711875 L1:00000703
602 09:39:20.712364 L2:00008067
603 09:39:20.712811 L3:15000000
604 09:39:20.713320 S1:00000000
605 09:39:20.713819 B2:20282000
606 09:39:20.718685 B1:a0f83180
607 09:39:20.719219
608 09:39:20.719674 TE: 69784
609 09:39:20.720165
610 09:39:20.724418 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 09:39:20.724961
612 09:39:20.725433 Board ID = 1
613 09:39:20.729943 Set cpu clk to 24M
614 09:39:20.730221 Set clk81 to 24M
615 09:39:20.730432 Use GP1_pll as DSU clk.
616 09:39:20.733475 DSU clk: 1200 Mhz
617 09:39:20.734007 CPU clk: 1200 MHz
618 09:39:20.738954 Set clk81 to 166.6M
619 09:39:20.744513 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 09:39:20.745044 board id: 1
621 09:39:20.750876 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 09:39:20.762144 fw parse done
623 09:39:20.767149 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 09:39:20.810700 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 09:39:20.821695 PIEI prepare done
626 09:39:20.822238 fastboot data load
627 09:39:20.822701 fastboot data verify
628 09:39:20.827182 verify result: 266
629 09:39:20.832875 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 09:39:20.833453 LPDDR4 probe
631 09:39:20.834229 ddr clk to 1584MHz
632 09:39:20.840830 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 09:39:20.877121
634 09:39:20.877756 dmc_version 0001
635 09:39:20.884712 Check phy result
636 09:39:20.890637 INFO : End of CA training
637 09:39:20.891189 INFO : End of initialization
638 09:39:20.896134 INFO : Training has run successfully!
639 09:39:20.896670 Check phy result
640 09:39:20.901718 INFO : End of initialization
641 09:39:20.902230 INFO : End of read enable training
642 09:39:20.907334 INFO : End of fine write leveling
643 09:39:20.912925 INFO : End of Write leveling coarse delay
644 09:39:20.913431 INFO : Training has run successfully!
645 09:39:20.913830 Check phy result
646 09:39:20.918628 INFO : End of initialization
647 09:39:20.919162 INFO : End of read dq deskew training
648 09:39:20.924188 INFO : End of MPR read delay center optimization
649 09:39:20.929723 INFO : End of write delay center optimization
650 09:39:20.935331 INFO : End of read delay center optimization
651 09:39:20.935890 INFO : End of max read latency training
652 09:39:20.940949 INFO : Training has run successfully!
653 09:39:20.941484 1D training succeed
654 09:39:20.949889 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 09:39:20.996870 Check phy result
656 09:39:20.997639 INFO : End of initialization
657 09:39:21.024194 INFO : End of 2D read delay Voltage center optimization
658 09:39:21.038360 INFO : End of 2D read delay Voltage center optimization
659 09:39:21.091110 INFO : End of 2D write delay Voltage center optimization
660 09:39:21.140319 INFO : End of 2D write delay Voltage center optimization
661 09:39:21.145771 INFO : Training has run successfully!
662 09:39:21.146273
663 09:39:21.146699 channel==0
664 09:39:21.151388 RxClkDly_Margin_A0==78 ps 8
665 09:39:21.151874 TxDqDly_Margin_A0==98 ps 10
666 09:39:21.156998 RxClkDly_Margin_A1==88 ps 9
667 09:39:21.157482 TxDqDly_Margin_A1==88 ps 9
668 09:39:21.157821 TrainedVREFDQ_A0==74
669 09:39:21.162620 TrainedVREFDQ_A1==75
670 09:39:21.163099 VrefDac_Margin_A0==24
671 09:39:21.163510 DeviceVref_Margin_A0==40
672 09:39:21.168286 VrefDac_Margin_A1==23
673 09:39:21.168784 DeviceVref_Margin_A1==39
674 09:39:21.169202
675 09:39:21.169609
676 09:39:21.170014 channel==1
677 09:39:21.173808 RxClkDly_Margin_A0==78 ps 8
678 09:39:21.174343 TxDqDly_Margin_A0==88 ps 9
679 09:39:21.179418 RxClkDly_Margin_A1==88 ps 9
680 09:39:21.179933 TxDqDly_Margin_A1==78 ps 8
681 09:39:21.185005 TrainedVREFDQ_A0==77
682 09:39:21.185490 TrainedVREFDQ_A1==75
683 09:39:21.185907 VrefDac_Margin_A0==22
684 09:39:21.190687 DeviceVref_Margin_A0==37
685 09:39:21.191184 VrefDac_Margin_A1==22
686 09:39:21.191602 DeviceVref_Margin_A1==39
687 09:39:21.196216
688 09:39:21.196690 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 09:39:21.197105
690 09:39:21.229787 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
691 09:39:21.230361 2D training succeed
692 09:39:21.235393 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 09:39:21.240981 auto size-- 65535DDR cs0 size: 2048MB
694 09:39:21.241501 DDR cs1 size: 2048MB
695 09:39:21.246608 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 09:39:21.247082 cs0 DataBus test pass
697 09:39:21.252362 cs1 DataBus test pass
698 09:39:21.253135 cs0 AddrBus test pass
699 09:39:21.253694 cs1 AddrBus test pass
700 09:39:21.254220
701 09:39:21.257741 100bdlr_step_size ps== 471
702 09:39:21.258078 result report
703 09:39:21.263417 boot times 0Enable ddr reg access
704 09:39:21.268538 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 09:39:21.284768 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 09:39:21.937406 bl2z: ptr: 05129330, size: 00001e40
707 09:39:21.945930 0.0;M3 CHK:0;cm4_sp_mode 0
708 09:39:21.946532 MVN_1=0x00000000
709 09:39:21.947003 MVN_2=0x00000000
710 09:39:21.957518 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 09:39:21.958203 OPS=0x04
712 09:39:21.958678 ring efuse init
713 09:39:21.963128 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 09:39:21.963729 [0.017310 Inits done]
715 09:39:21.964259 secure task start!
716 09:39:21.970342 high task start!
717 09:39:21.970932 low task start!
718 09:39:21.971399 run into bl31
719 09:39:21.978895 NOTICE: BL31: v1.3(release):4fc40b1
720 09:39:21.986673 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 09:39:21.987265 NOTICE: BL31: G12A normal boot!
722 09:39:22.002288 NOTICE: BL31: BL33 decompress pass
723 09:39:22.007947 ERROR: Error initializing runtime service opteed_fast
724 09:39:22.803234
725 09:39:22.803904
726 09:39:22.808703 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 09:39:22.809231
728 09:39:22.812193 Model: Libre Computer AML-S905D3-CC Solitude
729 09:39:22.959327 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 09:39:22.973772 DRAM: 2 GiB (effective 3.8 GiB)
731 09:39:23.075558 Core: 406 devices, 33 uclasses, devicetree: separate
732 09:39:23.081455 WDT: Not starting watchdog@f0d0
733 09:39:23.106551 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 09:39:23.118696 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 09:39:23.123773 ** Bad device specification mmc 0 **
736 09:39:23.133785 Card did not respond to voltage select! : -110
737 09:39:23.141460 ** Bad device specification mmc 0 **
738 09:39:23.142005 Couldn't find partition mmc 0
739 09:39:23.149798 Card did not respond to voltage select! : -110
740 09:39:23.155322 ** Bad device specification mmc 0 **
741 09:39:23.155907 Couldn't find partition mmc 0
742 09:39:23.159429 Error: could not access storage.
743 09:39:23.457780 Net: eth0: ethernet@ff3f0000
744 09:39:23.458425 starting USB...
745 09:39:23.702439 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 09:39:23.703045 Starting the controller
747 09:39:23.709402 USB XHCI 1.10
748 09:39:25.263530 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 09:39:25.271923 scanning usb for storage devices... 0 Storage Device(s) found
751 09:39:25.323540 Hit any key to stop autoboot: 1
752 09:39:25.324551 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 09:39:25.325253 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 09:39:25.325780 Setting prompt string to ['=>']
755 09:39:25.326300 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 09:39:25.337932 0
757 09:39:25.338902 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 09:39:25.440217 => setenv autoload no
760 09:39:25.441285 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 09:39:25.446930 setenv autoload no
763 09:39:25.548535 => setenv initrd_high 0xffffffff
764 09:39:25.549686 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 09:39:25.553857 setenv initrd_high 0xffffffff
767 09:39:25.654946 => setenv fdt_high 0xffffffff
768 09:39:25.655858 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 09:39:25.659967 setenv fdt_high 0xffffffff
771 09:39:25.761290 => dhcp
772 09:39:25.762176 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 09:39:25.766006 dhcp
774 09:39:26.621775 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 09:39:26.622207 Speed: 1000, full duplex
776 09:39:26.622444 BOOTP broadcast 1
777 09:39:26.870138 BOOTP broadcast 2
778 09:39:26.884692 DHCP client bound to address 192.168.6.21 (263 ms)
780 09:39:26.986008 => setenv serverip 192.168.6.2
781 09:39:26.986509 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
782 09:39:26.990199 setenv serverip 192.168.6.2
784 09:39:27.091237 => tftpboot 0x01080000 916880/tftp-deploy-55bsg2hq/kernel/uImage
785 09:39:27.091872 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
786 09:39:27.098557 tftpboot 0x01080000 916880/tftp-deploy-55bsg2hq/kernel/uImage
787 09:39:27.099075 Speed: 1000, full duplex
788 09:39:27.099482 Using ethernet@ff3f0000 device
789 09:39:27.104147 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 09:39:27.109636 Filename '916880/tftp-deploy-55bsg2hq/kernel/uImage'.
791 09:39:27.113601 Load address: 0x1080000
792 09:39:30.295891 Loading: *################################################## 44.1 MiB
793 09:39:30.296591 13.9 MiB/s
794 09:39:30.297278 done
795 09:39:30.299394 Bytes transferred = 46258752 (2c1da40 hex)
797 09:39:30.400946 => tftpboot 0x08000000 916880/tftp-deploy-55bsg2hq/ramdisk/ramdisk.cpio.gz.uboot
798 09:39:30.401507 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
799 09:39:30.408220 tftpboot 0x08000000 916880/tftp-deploy-55bsg2hq/ramdisk/ramdisk.cpio.gz.uboot
800 09:39:30.408554 Speed: 1000, full duplex
801 09:39:30.408766 Using ethernet@ff3f0000 device
802 09:39:30.413702 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
803 09:39:30.423445 Filename '916880/tftp-deploy-55bsg2hq/ramdisk/ramdisk.cpio.gz.uboot'.
804 09:39:30.423752 Load address: 0x8000000
805 09:39:32.120513 Loading: *################################################# UDP wrong checksum 00000005 00002351
806 09:39:37.120087 T UDP wrong checksum 00000005 00002351
807 09:39:45.776104 T UDP wrong checksum 00000005 0000677c
808 09:39:46.366726 UDP wrong checksum 000000ff 00009f3c
809 09:39:46.402406 UDP wrong checksum 000000ff 0000362f
810 09:39:47.123275 T UDP wrong checksum 00000005 00002351
811 09:40:07.127486 T T T T UDP wrong checksum 00000005 00002351
812 09:40:27.132177 T T T
813 09:40:27.132829 Retry count exceeded; starting again
815 09:40:27.134397 end: 2.4.3 bootloader-commands (duration 00:01:02) [common]
818 09:40:27.136508 end: 2.4 uboot-commands (duration 00:01:20) [common]
820 09:40:27.138003 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
822 09:40:27.139158 end: 2 uboot-action (duration 00:01:21) [common]
824 09:40:27.140857 Cleaning after the job
825 09:40:27.141446 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/ramdisk
826 09:40:27.142740 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/kernel
827 09:40:27.190829 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/dtb
828 09:40:27.191743 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/916880/tftp-deploy-55bsg2hq/modules
829 09:40:27.210983 start: 4.1 power-off (timeout 00:00:30) [common]
830 09:40:27.211633 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
831 09:40:27.244266 >> OK - accepted request
832 09:40:27.246149 Returned 0 in 0 seconds
833 09:40:27.346885 end: 4.1 power-off (duration 00:00:00) [common]
835 09:40:27.347851 start: 4.2 read-feedback (timeout 00:10:00) [common]
836 09:40:27.348533 Listened to connection for namespace 'common' for up to 1s
837 09:40:28.349524 Finalising connection for namespace 'common'
838 09:40:28.350282 Disconnecting from shell: Finalise
839 09:40:28.350842 =>
840 09:40:28.451933 end: 4.2 read-feedback (duration 00:00:01) [common]
841 09:40:28.452733 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/916880
842 09:40:28.743090 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/916880
843 09:40:28.743657 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.