Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:37:30.283755 lava-dispatcher, installed at version: 2024.01
2 10:37:30.284565 start: 0 validate
3 10:37:30.285058 Start time: 2024-10-31 10:37:30.285028+00:00 (UTC)
4 10:37:30.285599 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:37:30.286155 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 10:37:30.331061 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:37:30.331912 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241031%2Farm64%2Fdefconfig%2Fclang-17%2Fkernel%2FImage exists
8 10:37:30.371384 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:37:30.372070 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241031%2Farm64%2Fdefconfig%2Fclang-17%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 10:37:30.419342 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:37:30.419851 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241031%2Farm64%2Fdefconfig%2Fclang-17%2Fmodules.tar.xz exists
12 10:37:30.459400 validate duration: 0.17
14 10:37:30.460306 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:37:30.460697 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:37:30.461024 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:37:30.461613 Not decompressing ramdisk as can be used compressed.
18 10:37:30.462063 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 10:37:30.462322 saving as /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/ramdisk/rootfs.cpio.gz
20 10:37:30.462599 total size: 47897469 (45 MB)
21 10:37:30.502469 progress 0 % (0 MB)
22 10:37:30.534372 progress 5 % (2 MB)
23 10:37:30.566012 progress 10 % (4 MB)
24 10:37:30.596755 progress 15 % (6 MB)
25 10:37:30.628324 progress 20 % (9 MB)
26 10:37:30.659110 progress 25 % (11 MB)
27 10:37:30.689777 progress 30 % (13 MB)
28 10:37:30.720257 progress 35 % (16 MB)
29 10:37:30.750813 progress 40 % (18 MB)
30 10:37:30.781443 progress 45 % (20 MB)
31 10:37:30.811884 progress 50 % (22 MB)
32 10:37:30.842652 progress 55 % (25 MB)
33 10:37:30.873492 progress 60 % (27 MB)
34 10:37:30.903847 progress 65 % (29 MB)
35 10:37:30.934743 progress 70 % (32 MB)
36 10:37:30.965060 progress 75 % (34 MB)
37 10:37:30.995408 progress 80 % (36 MB)
38 10:37:31.025863 progress 85 % (38 MB)
39 10:37:31.056796 progress 90 % (41 MB)
40 10:37:31.087196 progress 95 % (43 MB)
41 10:37:31.117022 progress 100 % (45 MB)
42 10:37:31.117763 45 MB downloaded in 0.66 s (69.72 MB/s)
43 10:37:31.118318 end: 1.1.1 http-download (duration 00:00:01) [common]
45 10:37:31.119205 end: 1.1 download-retry (duration 00:00:01) [common]
46 10:37:31.119496 start: 1.2 download-retry (timeout 00:09:59) [common]
47 10:37:31.119771 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 10:37:31.120277 downloading http://storage.kernelci.org/next/master/next-20241031/arm64/defconfig/clang-17/kernel/Image
49 10:37:31.120532 saving as /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/kernel/Image
50 10:37:31.120742 total size: 38009344 (36 MB)
51 10:37:31.120954 No compression specified
52 10:37:31.165933 progress 0 % (0 MB)
53 10:37:31.190052 progress 5 % (1 MB)
54 10:37:31.213536 progress 10 % (3 MB)
55 10:37:31.237079 progress 15 % (5 MB)
56 10:37:31.260479 progress 20 % (7 MB)
57 10:37:31.283684 progress 25 % (9 MB)
58 10:37:31.306996 progress 30 % (10 MB)
59 10:37:31.330308 progress 35 % (12 MB)
60 10:37:31.353476 progress 40 % (14 MB)
61 10:37:31.377256 progress 45 % (16 MB)
62 10:37:31.400344 progress 50 % (18 MB)
63 10:37:31.423504 progress 55 % (19 MB)
64 10:37:31.446816 progress 60 % (21 MB)
65 10:37:31.470027 progress 65 % (23 MB)
66 10:37:31.493397 progress 70 % (25 MB)
67 10:37:31.516669 progress 75 % (27 MB)
68 10:37:31.539843 progress 80 % (29 MB)
69 10:37:31.563089 progress 85 % (30 MB)
70 10:37:31.586561 progress 90 % (32 MB)
71 10:37:31.609692 progress 95 % (34 MB)
72 10:37:31.632324 progress 100 % (36 MB)
73 10:37:31.633097 36 MB downloaded in 0.51 s (70.75 MB/s)
74 10:37:31.633591 end: 1.2.1 http-download (duration 00:00:01) [common]
76 10:37:31.634419 end: 1.2 download-retry (duration 00:00:01) [common]
77 10:37:31.634696 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:37:31.634964 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:37:31.635435 downloading http://storage.kernelci.org/next/master/next-20241031/arm64/defconfig/clang-17/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 10:37:31.635713 saving as /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/dtb/meson-g12b-a311d-libretech-cc.dtb
81 10:37:31.635922 total size: 54703 (0 MB)
82 10:37:31.636169 No compression specified
83 10:37:31.675477 progress 59 % (0 MB)
84 10:37:31.676360 progress 100 % (0 MB)
85 10:37:31.676920 0 MB downloaded in 0.04 s (1.27 MB/s)
86 10:37:31.677384 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:37:31.678204 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:37:31.678467 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:37:31.678731 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:37:31.679271 downloading http://storage.kernelci.org/next/master/next-20241031/arm64/defconfig/clang-17/modules.tar.xz
92 10:37:31.679541 saving as /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/modules/modules.tar
93 10:37:31.679749 total size: 11742820 (11 MB)
94 10:37:31.679960 Using unxz to decompress xz
95 10:37:31.714926 progress 0 % (0 MB)
96 10:37:31.781753 progress 5 % (0 MB)
97 10:37:31.857421 progress 10 % (1 MB)
98 10:37:31.938502 progress 15 % (1 MB)
99 10:37:32.019577 progress 20 % (2 MB)
100 10:37:32.098457 progress 25 % (2 MB)
101 10:37:32.179455 progress 30 % (3 MB)
102 10:37:32.256886 progress 35 % (3 MB)
103 10:37:32.340326 progress 40 % (4 MB)
104 10:37:32.426148 progress 45 % (5 MB)
105 10:37:32.508326 progress 50 % (5 MB)
106 10:37:32.592508 progress 55 % (6 MB)
107 10:37:32.675410 progress 60 % (6 MB)
108 10:37:32.758620 progress 65 % (7 MB)
109 10:37:32.840677 progress 70 % (7 MB)
110 10:37:32.925470 progress 75 % (8 MB)
111 10:37:33.008262 progress 80 % (8 MB)
112 10:37:33.088486 progress 85 % (9 MB)
113 10:37:33.164697 progress 90 % (10 MB)
114 10:37:33.265524 progress 95 % (10 MB)
115 10:37:33.362254 progress 100 % (11 MB)
116 10:37:33.374008 11 MB downloaded in 1.69 s (6.61 MB/s)
117 10:37:33.374638 end: 1.4.1 http-download (duration 00:00:02) [common]
119 10:37:33.375485 end: 1.4 download-retry (duration 00:00:02) [common]
120 10:37:33.375759 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 10:37:33.376111 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 10:37:33.376688 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:37:33.377251 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 10:37:33.378548 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq
125 10:37:33.379508 makedir: /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin
126 10:37:33.380261 makedir: /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/tests
127 10:37:33.380952 makedir: /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/results
128 10:37:33.381624 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-add-keys
129 10:37:33.382672 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-add-sources
130 10:37:33.383691 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-background-process-start
131 10:37:33.384778 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-background-process-stop
132 10:37:33.385878 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-common-functions
133 10:37:33.386886 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-echo-ipv4
134 10:37:33.387873 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-install-packages
135 10:37:33.388900 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-installed-packages
136 10:37:33.389868 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-os-build
137 10:37:33.390841 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-probe-channel
138 10:37:33.391814 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-probe-ip
139 10:37:33.392848 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-target-ip
140 10:37:33.393827 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-target-mac
141 10:37:33.394797 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-target-storage
142 10:37:33.395794 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-test-case
143 10:37:33.396863 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-test-event
144 10:37:33.397839 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-test-feedback
145 10:37:33.398806 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-test-raise
146 10:37:33.399796 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-test-reference
147 10:37:33.400852 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-test-runner
148 10:37:33.401848 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-test-set
149 10:37:33.402833 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-test-shell
150 10:37:33.403825 Updating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-install-packages (oe)
151 10:37:33.404950 Updating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/bin/lava-installed-packages (oe)
152 10:37:33.405864 Creating /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/environment
153 10:37:33.406652 LAVA metadata
154 10:37:33.407199 - LAVA_JOB_ID=917040
155 10:37:33.407674 - LAVA_DISPATCHER_IP=192.168.6.2
156 10:37:33.408436 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 10:37:33.410392 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 10:37:33.411077 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 10:37:33.411538 skipped lava-vland-overlay
160 10:37:33.412123 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 10:37:33.412658 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 10:37:33.413093 skipped lava-multinode-overlay
163 10:37:33.413581 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 10:37:33.414085 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 10:37:33.414558 Loading test definitions
166 10:37:33.415104 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 10:37:33.415545 Using /lava-917040 at stage 0
168 10:37:33.417826 uuid=917040_1.5.2.4.1 testdef=None
169 10:37:33.418436 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 10:37:33.418968 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 10:37:33.421236 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 10:37:33.422090 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 10:37:33.424285 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 10:37:33.425194 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 10:37:33.427296 runner path: /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/0/tests/0_igt-gpu-panfrost test_uuid 917040_1.5.2.4.1
178 10:37:33.427901 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 10:37:33.428817 Creating lava-test-runner.conf files
181 10:37:33.429031 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/917040/lava-overlay-y2n4k_lq/lava-917040/0 for stage 0
182 10:37:33.429377 - 0_igt-gpu-panfrost
183 10:37:33.429747 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 10:37:33.430042 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 10:37:33.453647 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 10:37:33.454079 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 10:37:33.454358 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 10:37:33.454632 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 10:37:33.454901 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 10:37:40.202842 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 10:37:40.203315 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 10:37:40.203567 extracting modules file /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/917040/extract-overlay-ramdisk-e87xpa46/ramdisk
193 10:37:41.626755 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 10:37:41.627236 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 10:37:41.627517 [common] Applying overlay /var/lib/lava/dispatcher/tmp/917040/compress-overlay-j9xgkjxs/overlay-1.5.2.5.tar.gz to ramdisk
196 10:37:41.627733 [common] Applying overlay /var/lib/lava/dispatcher/tmp/917040/compress-overlay-j9xgkjxs/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/917040/extract-overlay-ramdisk-e87xpa46/ramdisk
197 10:37:41.657403 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 10:37:41.657793 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 10:37:41.658062 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 10:37:41.658289 Converting downloaded kernel to a uImage
201 10:37:41.658601 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/kernel/Image /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/kernel/uImage
202 10:37:42.062762 output: Image Name:
203 10:37:42.063179 output: Created: Thu Oct 31 10:37:41 2024
204 10:37:42.063390 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 10:37:42.063597 output: Data Size: 38009344 Bytes = 37118.50 KiB = 36.25 MiB
206 10:37:42.063800 output: Load Address: 01080000
207 10:37:42.064039 output: Entry Point: 01080000
208 10:37:42.064248 output:
209 10:37:42.064582 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 10:37:42.064844 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 10:37:42.065113 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 10:37:42.065365 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 10:37:42.065620 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 10:37:42.065871 Building ramdisk /var/lib/lava/dispatcher/tmp/917040/extract-overlay-ramdisk-e87xpa46/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/917040/extract-overlay-ramdisk-e87xpa46/ramdisk
215 10:37:48.664570 >> 509419 blocks
216 10:38:09.268489 Adding RAMdisk u-boot header.
217 10:38:09.269194 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/917040/extract-overlay-ramdisk-e87xpa46/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/917040/extract-overlay-ramdisk-e87xpa46/ramdisk.cpio.gz.uboot
218 10:38:09.967636 output: Image Name:
219 10:38:09.968091 output: Created: Thu Oct 31 10:38:09 2024
220 10:38:09.968557 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 10:38:09.969004 output: Data Size: 66432825 Bytes = 64875.81 KiB = 63.36 MiB
222 10:38:09.969448 output: Load Address: 00000000
223 10:38:09.969885 output: Entry Point: 00000000
224 10:38:09.970322 output:
225 10:38:09.971345 rename /var/lib/lava/dispatcher/tmp/917040/extract-overlay-ramdisk-e87xpa46/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/ramdisk/ramdisk.cpio.gz.uboot
226 10:38:09.972140 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 10:38:09.972739 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 10:38:09.973314 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 10:38:09.973812 No LXC device requested
230 10:38:09.974354 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 10:38:09.974905 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 10:38:09.975446 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 10:38:09.975898 Checking files for TFTP limit of 4294967296 bytes.
234 10:38:09.978833 end: 1 tftp-deploy (duration 00:00:40) [common]
235 10:38:09.979454 start: 2 uboot-action (timeout 00:05:00) [common]
236 10:38:09.980055 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 10:38:09.980610 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 10:38:09.981163 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 10:38:09.981737 Using kernel file from prepare-kernel: 917040/tftp-deploy-_1f3qnwr/kernel/uImage
240 10:38:09.982423 substitutions:
241 10:38:09.982876 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 10:38:09.983319 - {DTB_ADDR}: 0x01070000
243 10:38:09.983760 - {DTB}: 917040/tftp-deploy-_1f3qnwr/dtb/meson-g12b-a311d-libretech-cc.dtb
244 10:38:09.984241 - {INITRD}: 917040/tftp-deploy-_1f3qnwr/ramdisk/ramdisk.cpio.gz.uboot
245 10:38:09.984681 - {KERNEL_ADDR}: 0x01080000
246 10:38:09.985115 - {KERNEL}: 917040/tftp-deploy-_1f3qnwr/kernel/uImage
247 10:38:09.985552 - {LAVA_MAC}: None
248 10:38:09.986025 - {PRESEED_CONFIG}: None
249 10:38:09.986464 - {PRESEED_LOCAL}: None
250 10:38:09.986894 - {RAMDISK_ADDR}: 0x08000000
251 10:38:09.987324 - {RAMDISK}: 917040/tftp-deploy-_1f3qnwr/ramdisk/ramdisk.cpio.gz.uboot
252 10:38:09.987763 - {ROOT_PART}: None
253 10:38:09.988227 - {ROOT}: None
254 10:38:09.988667 - {SERVER_IP}: 192.168.6.2
255 10:38:09.989106 - {TEE_ADDR}: 0x83000000
256 10:38:09.989537 - {TEE}: None
257 10:38:09.989968 Parsed boot commands:
258 10:38:09.990388 - setenv autoload no
259 10:38:09.990818 - setenv initrd_high 0xffffffff
260 10:38:09.991247 - setenv fdt_high 0xffffffff
261 10:38:09.991673 - dhcp
262 10:38:09.992124 - setenv serverip 192.168.6.2
263 10:38:09.992558 - tftpboot 0x01080000 917040/tftp-deploy-_1f3qnwr/kernel/uImage
264 10:38:09.992992 - tftpboot 0x08000000 917040/tftp-deploy-_1f3qnwr/ramdisk/ramdisk.cpio.gz.uboot
265 10:38:09.993424 - tftpboot 0x01070000 917040/tftp-deploy-_1f3qnwr/dtb/meson-g12b-a311d-libretech-cc.dtb
266 10:38:09.993857 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 10:38:09.994294 - bootm 0x01080000 0x08000000 0x01070000
268 10:38:09.994835 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 10:38:09.996502 start: 2.3 connect-device (timeout 00:05:00) [common]
271 10:38:09.996986 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 10:38:10.012591 Setting prompt string to ['lava-test: # ']
273 10:38:10.014150 end: 2.3 connect-device (duration 00:00:00) [common]
274 10:38:10.014792 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 10:38:10.015385 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 10:38:10.015941 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 10:38:10.017215 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 10:38:10.053657 >> OK - accepted request
279 10:38:10.055741 Returned 0 in 0 seconds
280 10:38:10.156938 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 10:38:10.158590 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 10:38:10.159189 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 10:38:10.159729 Setting prompt string to ['Hit any key to stop autoboot']
285 10:38:10.160262 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 10:38:10.161935 Trying 192.168.56.21...
287 10:38:10.162448 Connected to conserv1.
288 10:38:10.162887 Escape character is '^]'.
289 10:38:10.163341
290 10:38:10.163802 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 10:38:10.164306
292 10:38:21.775774 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 10:38:21.776465 bl2_stage_init 0x01
294 10:38:21.776944 bl2_stage_init 0x81
295 10:38:21.781432 hw id: 0x0000 - pwm id 0x01
296 10:38:21.781936 bl2_stage_init 0xc1
297 10:38:21.782381 bl2_stage_init 0x02
298 10:38:21.782826
299 10:38:21.786978 L0:00000000
300 10:38:21.787452 L1:20000703
301 10:38:21.787898 L2:00008067
302 10:38:21.788365 L3:14000000
303 10:38:21.792626 B2:00402000
304 10:38:21.793085 B1:e0f83180
305 10:38:21.793524
306 10:38:21.793951 TE: 58124
307 10:38:21.794378
308 10:38:21.798325 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 10:38:21.798789
310 10:38:21.799217 Board ID = 1
311 10:38:21.803734 Set A53 clk to 24M
312 10:38:21.804223 Set A73 clk to 24M
313 10:38:21.804648 Set clk81 to 24M
314 10:38:21.809487 A53 clk: 1200 MHz
315 10:38:21.809940 A73 clk: 1200 MHz
316 10:38:21.810369 CLK81: 166.6M
317 10:38:21.810788 smccc: 00012a92
318 10:38:21.815052 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 10:38:21.820646 board id: 1
320 10:38:21.825597 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 10:38:21.837110 fw parse done
322 10:38:21.843135 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 10:38:21.885571 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 10:38:21.896445 PIEI prepare done
325 10:38:21.896897 fastboot data load
326 10:38:21.897326 fastboot data verify
327 10:38:21.902050 verify result: 266
328 10:38:21.907822 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 10:38:21.908329 LPDDR4 probe
330 10:38:21.908783 ddr clk to 1584MHz
331 10:38:21.914723 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 10:38:21.951928
333 10:38:21.952427 dmc_version 0001
334 10:38:21.958597 Check phy result
335 10:38:21.965461 INFO : End of CA training
336 10:38:21.965928 INFO : End of initialization
337 10:38:21.971067 INFO : Training has run successfully!
338 10:38:21.971532 Check phy result
339 10:38:21.976665 INFO : End of initialization
340 10:38:21.977140 INFO : End of read enable training
341 10:38:21.982245 INFO : End of fine write leveling
342 10:38:21.987906 INFO : End of Write leveling coarse delay
343 10:38:21.988398 INFO : Training has run successfully!
344 10:38:21.988837 Check phy result
345 10:38:21.993463 INFO : End of initialization
346 10:38:21.993923 INFO : End of read dq deskew training
347 10:38:21.999090 INFO : End of MPR read delay center optimization
348 10:38:22.004668 INFO : End of write delay center optimization
349 10:38:22.010254 INFO : End of read delay center optimization
350 10:38:22.010715 INFO : End of max read latency training
351 10:38:22.015909 INFO : Training has run successfully!
352 10:38:22.016430 1D training succeed
353 10:38:22.025105 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 10:38:22.072384 Check phy result
355 10:38:22.072893 INFO : End of initialization
356 10:38:22.093322 INFO : End of 2D read delay Voltage center optimization
357 10:38:22.113392 INFO : End of 2D read delay Voltage center optimization
358 10:38:22.166301 INFO : End of 2D write delay Voltage center optimization
359 10:38:22.215431 INFO : End of 2D write delay Voltage center optimization
360 10:38:22.221080 INFO : Training has run successfully!
361 10:38:22.221550
362 10:38:22.221999 channel==0
363 10:38:22.226626 RxClkDly_Margin_A0==88 ps 9
364 10:38:22.227087 TxDqDly_Margin_A0==98 ps 10
365 10:38:22.229952 RxClkDly_Margin_A1==88 ps 9
366 10:38:22.230419 TxDqDly_Margin_A1==98 ps 10
367 10:38:22.235550 TrainedVREFDQ_A0==74
368 10:38:22.236046 TrainedVREFDQ_A1==74
369 10:38:22.236496 VrefDac_Margin_A0==25
370 10:38:22.241126 DeviceVref_Margin_A0==40
371 10:38:22.241587 VrefDac_Margin_A1==25
372 10:38:22.246789 DeviceVref_Margin_A1==40
373 10:38:22.247247
374 10:38:22.247688
375 10:38:22.248161 channel==1
376 10:38:22.248593 RxClkDly_Margin_A0==98 ps 10
377 10:38:22.250079 TxDqDly_Margin_A0==98 ps 10
378 10:38:22.255656 RxClkDly_Margin_A1==98 ps 10
379 10:38:22.256162 TxDqDly_Margin_A1==88 ps 9
380 10:38:22.256607 TrainedVREFDQ_A0==77
381 10:38:22.261250 TrainedVREFDQ_A1==77
382 10:38:22.261743 VrefDac_Margin_A0==22
383 10:38:22.266842 DeviceVref_Margin_A0==37
384 10:38:22.267308 VrefDac_Margin_A1==22
385 10:38:22.267746 DeviceVref_Margin_A1==37
386 10:38:22.268217
387 10:38:22.272483 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 10:38:22.272949
389 10:38:22.306062 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 10:38:22.306602 2D training succeed
391 10:38:22.311651 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 10:38:22.317250 auto size-- 65535DDR cs0 size: 2048MB
393 10:38:22.317714 DDR cs1 size: 2048MB
394 10:38:22.322851 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 10:38:22.323308 cs0 DataBus test pass
396 10:38:22.323743 cs1 DataBus test pass
397 10:38:22.328450 cs0 AddrBus test pass
398 10:38:22.328919 cs1 AddrBus test pass
399 10:38:22.329353
400 10:38:22.334054 100bdlr_step_size ps== 420
401 10:38:22.334539 result report
402 10:38:22.334981 boot times 0Enable ddr reg access
403 10:38:22.344162 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 10:38:22.357496 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 10:38:22.929509 0.0;M3 CHK:0;cm4_sp_mode 0
406 10:38:22.930095 MVN_1=0x00000000
407 10:38:22.935107 MVN_2=0x00000000
408 10:38:22.940750 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 10:38:22.941215 OPS=0x10
410 10:38:22.941659 ring efuse init
411 10:38:22.942092 chipver efuse init
412 10:38:22.946325 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 10:38:22.951951 [0.018961 Inits done]
414 10:38:22.952451 secure task start!
415 10:38:22.952895 high task start!
416 10:38:22.955602 low task start!
417 10:38:22.956089 run into bl31
418 10:38:22.963166 NOTICE: BL31: v1.3(release):4fc40b1
419 10:38:22.970056 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 10:38:22.970524 NOTICE: BL31: G12A normal boot!
421 10:38:22.996299 NOTICE: BL31: BL33 decompress pass
422 10:38:23.001988 ERROR: Error initializing runtime service opteed_fast
423 10:38:24.234939
424 10:38:24.235585
425 10:38:24.243374 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 10:38:24.243872
427 10:38:24.244371 Model: Libre Computer AML-A311D-CC Alta
428 10:38:24.451253 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 10:38:24.474802 DRAM: 2 GiB (effective 3.8 GiB)
430 10:38:24.618108 Core: 408 devices, 31 uclasses, devicetree: separate
431 10:38:24.623029 WDT: Not starting watchdog@f0d0
432 10:38:24.656289 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 10:38:24.668725 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 10:38:24.673682 ** Bad device specification mmc 0 **
435 10:38:24.684057 Card did not respond to voltage select! : -110
436 10:38:24.691686 ** Bad device specification mmc 0 **
437 10:38:24.692330 Couldn't find partition mmc 0
438 10:38:24.700040 Card did not respond to voltage select! : -110
439 10:38:24.705528 ** Bad device specification mmc 0 **
440 10:38:24.705978 Couldn't find partition mmc 0
441 10:38:24.710582 Error: could not access storage.
442 10:38:25.976257 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 10:38:25.976895 bl2_stage_init 0x01
444 10:38:25.977380 bl2_stage_init 0x81
445 10:38:25.981768 hw id: 0x0000 - pwm id 0x01
446 10:38:25.982284 bl2_stage_init 0xc1
447 10:38:25.982740 bl2_stage_init 0x02
448 10:38:25.983185
449 10:38:25.987428 L0:00000000
450 10:38:25.987930 L1:20000703
451 10:38:25.988441 L2:00008067
452 10:38:25.988892 L3:14000000
453 10:38:25.992961 B2:00402000
454 10:38:25.993471 B1:e0f83180
455 10:38:25.993923
456 10:38:25.994372 TE: 58124
457 10:38:25.994814
458 10:38:25.998556 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 10:38:25.999070
460 10:38:25.999526 Board ID = 1
461 10:38:26.004167 Set A53 clk to 24M
462 10:38:26.004676 Set A73 clk to 24M
463 10:38:26.005122 Set clk81 to 24M
464 10:38:26.009783 A53 clk: 1200 MHz
465 10:38:26.010348 A73 clk: 1200 MHz
466 10:38:26.010808 CLK81: 166.6M
467 10:38:26.011253 smccc: 00012a92
468 10:38:26.015411 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 10:38:26.020925 board id: 1
470 10:38:26.025967 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 10:38:26.037589 fw parse done
472 10:38:26.043263 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 10:38:26.086073 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 10:38:26.096953 PIEI prepare done
475 10:38:26.097461 fastboot data load
476 10:38:26.097920 fastboot data verify
477 10:38:26.102662 verify result: 266
478 10:38:26.108229 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 10:38:26.108717 LPDDR4 probe
480 10:38:26.109166 ddr clk to 1584MHz
481 10:38:26.116201 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 10:38:26.153435
483 10:38:26.153923 dmc_version 0001
484 10:38:26.160137 Check phy result
485 10:38:26.165998 INFO : End of CA training
486 10:38:26.166483 INFO : End of initialization
487 10:38:26.171598 INFO : Training has run successfully!
488 10:38:26.172135 Check phy result
489 10:38:26.177205 INFO : End of initialization
490 10:38:26.177691 INFO : End of read enable training
491 10:38:26.180628 INFO : End of fine write leveling
492 10:38:26.186151 INFO : End of Write leveling coarse delay
493 10:38:26.191730 INFO : Training has run successfully!
494 10:38:26.192244 Check phy result
495 10:38:26.192694 INFO : End of initialization
496 10:38:26.197304 INFO : End of read dq deskew training
497 10:38:26.202928 INFO : End of MPR read delay center optimization
498 10:38:26.203408 INFO : End of write delay center optimization
499 10:38:26.208601 INFO : End of read delay center optimization
500 10:38:26.214099 INFO : End of max read latency training
501 10:38:26.214589 INFO : Training has run successfully!
502 10:38:26.219734 1D training succeed
503 10:38:26.225670 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 10:38:26.273217 Check phy result
505 10:38:26.273752 INFO : End of initialization
506 10:38:26.295707 INFO : End of 2D read delay Voltage center optimization
507 10:38:26.314852 INFO : End of 2D read delay Voltage center optimization
508 10:38:26.366445 INFO : End of 2D write delay Voltage center optimization
509 10:38:26.416066 INFO : End of 2D write delay Voltage center optimization
510 10:38:26.421667 INFO : Training has run successfully!
511 10:38:26.422480
512 10:38:26.422979 channel==0
513 10:38:26.427165 RxClkDly_Margin_A0==88 ps 9
514 10:38:26.427696 TxDqDly_Margin_A0==98 ps 10
515 10:38:26.430508 RxClkDly_Margin_A1==88 ps 9
516 10:38:26.430989 TxDqDly_Margin_A1==98 ps 10
517 10:38:26.436117 TrainedVREFDQ_A0==74
518 10:38:26.436610 TrainedVREFDQ_A1==74
519 10:38:26.437066 VrefDac_Margin_A0==25
520 10:38:26.441702 DeviceVref_Margin_A0==40
521 10:38:26.442184 VrefDac_Margin_A1==24
522 10:38:26.447300 DeviceVref_Margin_A1==40
523 10:38:26.447787
524 10:38:26.448276
525 10:38:26.448726 channel==1
526 10:38:26.449158 RxClkDly_Margin_A0==88 ps 9
527 10:38:26.452892 TxDqDly_Margin_A0==98 ps 10
528 10:38:26.453382 RxClkDly_Margin_A1==88 ps 9
529 10:38:26.458498 TxDqDly_Margin_A1==88 ps 9
530 10:38:26.458980 TrainedVREFDQ_A0==77
531 10:38:26.459428 TrainedVREFDQ_A1==77
532 10:38:26.464104 VrefDac_Margin_A0==23
533 10:38:26.464583 DeviceVref_Margin_A0==37
534 10:38:26.469717 VrefDac_Margin_A1==24
535 10:38:26.470206 DeviceVref_Margin_A1==37
536 10:38:26.470656
537 10:38:26.475303 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 10:38:26.475789
539 10:38:26.503307 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 10:38:26.508939 2D training succeed
541 10:38:26.514541 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 10:38:26.515107 auto size-- 65535DDR cs0 size: 2048MB
543 10:38:26.520092 DDR cs1 size: 2048MB
544 10:38:26.520596 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 10:38:26.525729 cs0 DataBus test pass
546 10:38:26.526217 cs1 DataBus test pass
547 10:38:26.526667 cs0 AddrBus test pass
548 10:38:26.531370 cs1 AddrBus test pass
549 10:38:26.531951
550 10:38:26.532500 100bdlr_step_size ps== 420
551 10:38:26.532969 result report
552 10:38:26.536932 boot times 0Enable ddr reg access
553 10:38:26.544228 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 10:38:26.556922 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 10:38:27.129907 0.0;M3 CHK:0;cm4_sp_mode 0
556 10:38:27.130548 MVN_1=0x00000000
557 10:38:27.135491 MVN_2=0x00000000
558 10:38:27.141252 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 10:38:27.141824 OPS=0x10
560 10:38:27.142317 ring efuse init
561 10:38:27.142799 chipver efuse init
562 10:38:27.149564 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 10:38:27.150134 [0.018960 Inits done]
564 10:38:27.156265 secure task start!
565 10:38:27.156823 high task start!
566 10:38:27.157255 low task start!
567 10:38:27.157677 run into bl31
568 10:38:27.163777 NOTICE: BL31: v1.3(release):4fc40b1
569 10:38:27.170523 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 10:38:27.171038 NOTICE: BL31: G12A normal boot!
571 10:38:27.196800 NOTICE: BL31: BL33 decompress pass
572 10:38:27.202447 ERROR: Error initializing runtime service opteed_fast
573 10:38:28.435385
574 10:38:28.436047
575 10:38:28.443894 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 10:38:28.444432
577 10:38:28.444892 Model: Libre Computer AML-A311D-CC Alta
578 10:38:28.652351 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 10:38:28.675686 DRAM: 2 GiB (effective 3.8 GiB)
580 10:38:28.818712 Core: 408 devices, 31 uclasses, devicetree: separate
581 10:38:28.824491 WDT: Not starting watchdog@f0d0
582 10:38:28.856791 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 10:38:28.869259 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 10:38:28.874336 ** Bad device specification mmc 0 **
585 10:38:28.884533 Card did not respond to voltage select! : -110
586 10:38:28.892196 ** Bad device specification mmc 0 **
587 10:38:28.892678 Couldn't find partition mmc 0
588 10:38:28.900509 Card did not respond to voltage select! : -110
589 10:38:28.906048 ** Bad device specification mmc 0 **
590 10:38:28.906530 Couldn't find partition mmc 0
591 10:38:28.911173 Error: could not access storage.
592 10:38:29.253597 Net: eth0: ethernet@ff3f0000
593 10:38:29.254142 starting USB...
594 10:38:29.505387 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 10:38:29.505911 Starting the controller
596 10:38:29.512419 USB XHCI 1.10
597 10:38:31.226479 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
598 10:38:31.227119 bl2_stage_init 0x81
599 10:38:31.231849 hw id: 0x0000 - pwm id 0x01
600 10:38:31.232403 bl2_stage_init 0xc1
601 10:38:31.232863 bl2_stage_init 0x02
602 10:38:31.233311
603 10:38:31.237530 L0:00000000
604 10:38:31.238029 L1:20000703
605 10:38:31.238477 L2:00008067
606 10:38:31.238917 L3:14000000
607 10:38:31.239355 B2:00402000
608 10:38:31.243145 B1:e0f83180
609 10:38:31.243638
610 10:38:31.244127 TE: 58150
611 10:38:31.244574
612 10:38:31.248700 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 10:38:31.249195
614 10:38:31.249646 Board ID = 1
615 10:38:31.254423 Set A53 clk to 24M
616 10:38:31.254905 Set A73 clk to 24M
617 10:38:31.255351 Set clk81 to 24M
618 10:38:31.259941 A53 clk: 1200 MHz
619 10:38:31.260453 A73 clk: 1200 MHz
620 10:38:31.260903 CLK81: 166.6M
621 10:38:31.261344 smccc: 00012aab
622 10:38:31.265610 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 10:38:31.271192 board id: 1
624 10:38:31.276943 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 10:38:31.287403 fw parse done
626 10:38:31.293440 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 10:38:31.336081 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 10:38:31.346905 PIEI prepare done
629 10:38:31.347386 fastboot data load
630 10:38:31.347838 fastboot data verify
631 10:38:31.352521 verify result: 266
632 10:38:31.358126 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 10:38:31.358621 LPDDR4 probe
634 10:38:31.359066 ddr clk to 1584MHz
635 10:38:31.366117 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 10:38:31.403405
637 10:38:31.403888 dmc_version 0001
638 10:38:31.410113 Check phy result
639 10:38:31.416013 INFO : End of CA training
640 10:38:31.416500 INFO : End of initialization
641 10:38:31.421567 INFO : Training has run successfully!
642 10:38:31.422047 Check phy result
643 10:38:31.427148 INFO : End of initialization
644 10:38:31.427628 INFO : End of read enable training
645 10:38:31.430483 INFO : End of fine write leveling
646 10:38:31.436025 INFO : End of Write leveling coarse delay
647 10:38:31.441649 INFO : Training has run successfully!
648 10:38:31.442134 Check phy result
649 10:38:31.442581 INFO : End of initialization
650 10:38:31.447319 INFO : End of read dq deskew training
651 10:38:31.450685 INFO : End of MPR read delay center optimization
652 10:38:31.456317 INFO : End of write delay center optimization
653 10:38:31.461835 INFO : End of read delay center optimization
654 10:38:31.462317 INFO : End of max read latency training
655 10:38:31.467412 INFO : Training has run successfully!
656 10:38:31.467884 1D training succeed
657 10:38:31.475590 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 10:38:31.523025 Check phy result
659 10:38:31.523509 INFO : End of initialization
660 10:38:31.545572 INFO : End of 2D read delay Voltage center optimization
661 10:38:31.565846 INFO : End of 2D read delay Voltage center optimization
662 10:38:31.617861 INFO : End of 2D write delay Voltage center optimization
663 10:38:31.667344 INFO : End of 2D write delay Voltage center optimization
664 10:38:31.672792 INFO : Training has run successfully!
665 10:38:31.673283
666 10:38:31.673736 channel==0
667 10:38:31.678404 RxClkDly_Margin_A0==88 ps 9
668 10:38:31.678887 TxDqDly_Margin_A0==98 ps 10
669 10:38:31.684044 RxClkDly_Margin_A1==88 ps 9
670 10:38:31.684535 TxDqDly_Margin_A1==88 ps 9
671 10:38:31.684989 TrainedVREFDQ_A0==74
672 10:38:31.689579 TrainedVREFDQ_A1==74
673 10:38:31.690073 VrefDac_Margin_A0==24
674 10:38:31.690526 DeviceVref_Margin_A0==40
675 10:38:31.695263 VrefDac_Margin_A1==24
676 10:38:31.695757 DeviceVref_Margin_A1==40
677 10:38:31.696248
678 10:38:31.696695
679 10:38:31.697131 channel==1
680 10:38:31.700774 RxClkDly_Margin_A0==98 ps 10
681 10:38:31.701261 TxDqDly_Margin_A0==98 ps 10
682 10:38:31.706395 RxClkDly_Margin_A1==98 ps 10
683 10:38:31.706877 TxDqDly_Margin_A1==108 ps 11
684 10:38:31.712005 TrainedVREFDQ_A0==77
685 10:38:31.712492 TrainedVREFDQ_A1==78
686 10:38:31.712941 VrefDac_Margin_A0==22
687 10:38:31.717581 DeviceVref_Margin_A0==37
688 10:38:31.718063 VrefDac_Margin_A1==22
689 10:38:31.723252 DeviceVref_Margin_A1==36
690 10:38:31.723736
691 10:38:31.724221 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 10:38:31.728759
693 10:38:31.756787 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
694 10:38:31.757302 2D training succeed
695 10:38:31.762377 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 10:38:31.768001 auto size-- 65535DDR cs0 size: 2048MB
697 10:38:31.768490 DDR cs1 size: 2048MB
698 10:38:31.773583 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 10:38:31.774067 cs0 DataBus test pass
700 10:38:31.779269 cs1 DataBus test pass
701 10:38:31.779747 cs0 AddrBus test pass
702 10:38:31.780229 cs1 AddrBus test pass
703 10:38:31.780669
704 10:38:31.784781 100bdlr_step_size ps== 420
705 10:38:31.785278 result report
706 10:38:31.790365 boot times 0Enable ddr reg access
707 10:38:31.795929 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 10:38:31.809386 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 10:38:32.383278 0.0;M3 CHK:0;cm4_sp_mode 0
710 10:38:32.383941 MVN_1=0x00000000
711 10:38:32.388838 MVN_2=0x00000000
712 10:38:32.394594 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 10:38:32.395192 OPS=0x10
714 10:38:32.395627 ring efuse init
715 10:38:32.396097 chipver efuse init
716 10:38:32.400078 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 10:38:32.405614 [0.018961 Inits done]
718 10:38:32.406116 secure task start!
719 10:38:32.406547 high task start!
720 10:38:32.410189 low task start!
721 10:38:32.410689 run into bl31
722 10:38:32.418416 NOTICE: BL31: v1.3(release):4fc40b1
723 10:38:32.424722 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 10:38:32.425222 NOTICE: BL31: G12A normal boot!
725 10:38:32.450049 NOTICE: BL31: BL33 decompress pass
726 10:38:32.458324 ERROR: Error initializing runtime service opteed_fast
727 10:38:33.688683
728 10:38:33.689271
729 10:38:33.696976 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 10:38:33.697468
731 10:38:33.697921 Model: Libre Computer AML-A311D-CC Alta
732 10:38:33.905357 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 10:38:33.928760 DRAM: 2 GiB (effective 3.8 GiB)
734 10:38:34.071760 Core: 408 devices, 31 uclasses, devicetree: separate
735 10:38:34.077654 WDT: Not starting watchdog@f0d0
736 10:38:34.109887 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 10:38:34.122377 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 10:38:34.127350 ** Bad device specification mmc 0 **
739 10:38:34.137704 Card did not respond to voltage select! : -110
740 10:38:34.145331 ** Bad device specification mmc 0 **
741 10:38:34.145811 Couldn't find partition mmc 0
742 10:38:34.153670 Card did not respond to voltage select! : -110
743 10:38:34.159197 ** Bad device specification mmc 0 **
744 10:38:34.159674 Couldn't find partition mmc 0
745 10:38:34.164280 Error: could not access storage.
746 10:38:34.507805 Net: eth0: ethernet@ff3f0000
747 10:38:34.508407 starting USB...
748 10:38:34.759546 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 10:38:34.760136 Starting the controller
750 10:38:34.766548 USB XHCI 1.10
751 10:38:36.928024 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 10:38:36.928691 bl2_stage_init 0x01
753 10:38:36.929161 bl2_stage_init 0x81
754 10:38:36.933513 hw id: 0x0000 - pwm id 0x01
755 10:38:36.934008 bl2_stage_init 0xc1
756 10:38:36.934465 bl2_stage_init 0x02
757 10:38:36.934908
758 10:38:36.939272 L0:00000000
759 10:38:36.939758 L1:20000703
760 10:38:36.940252 L2:00008067
761 10:38:36.940696 L3:14000000
762 10:38:36.944611 B2:00402000
763 10:38:36.945090 B1:e0f83180
764 10:38:36.945534
765 10:38:36.945977 TE: 58159
766 10:38:36.946421
767 10:38:36.950229 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 10:38:36.950724
769 10:38:36.951173 Board ID = 1
770 10:38:36.955940 Set A53 clk to 24M
771 10:38:36.956450 Set A73 clk to 24M
772 10:38:36.956897 Set clk81 to 24M
773 10:38:36.961505 A53 clk: 1200 MHz
774 10:38:36.961986 A73 clk: 1200 MHz
775 10:38:36.962434 CLK81: 166.6M
776 10:38:36.962870 smccc: 00012ab5
777 10:38:36.967240 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 10:38:36.972686 board id: 1
779 10:38:36.978619 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 10:38:36.989070 fw parse done
781 10:38:36.995077 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 10:38:37.037667 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 10:38:37.048575 PIEI prepare done
784 10:38:37.049062 fastboot data load
785 10:38:37.049514 fastboot data verify
786 10:38:37.054254 verify result: 266
787 10:38:37.059860 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 10:38:37.060418 LPDDR4 probe
789 10:38:37.060876 ddr clk to 1584MHz
790 10:38:37.067804 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 10:38:37.105034
792 10:38:37.105531 dmc_version 0001
793 10:38:37.111741 Check phy result
794 10:38:37.117607 INFO : End of CA training
795 10:38:37.118113 INFO : End of initialization
796 10:38:37.123212 INFO : Training has run successfully!
797 10:38:37.123692 Check phy result
798 10:38:37.128803 INFO : End of initialization
799 10:38:37.129284 INFO : End of read enable training
800 10:38:37.132109 INFO : End of fine write leveling
801 10:38:37.137640 INFO : End of Write leveling coarse delay
802 10:38:37.143237 INFO : Training has run successfully!
803 10:38:37.143721 Check phy result
804 10:38:37.144205 INFO : End of initialization
805 10:38:37.148833 INFO : End of read dq deskew training
806 10:38:37.154425 INFO : End of MPR read delay center optimization
807 10:38:37.154914 INFO : End of write delay center optimization
808 10:38:37.160083 INFO : End of read delay center optimization
809 10:38:37.165644 INFO : End of max read latency training
810 10:38:37.166123 INFO : Training has run successfully!
811 10:38:37.171236 1D training succeed
812 10:38:37.177203 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 10:38:37.224790 Check phy result
814 10:38:37.225302 INFO : End of initialization
815 10:38:37.246452 INFO : End of 2D read delay Voltage center optimization
816 10:38:37.266732 INFO : End of 2D read delay Voltage center optimization
817 10:38:37.318773 INFO : End of 2D write delay Voltage center optimization
818 10:38:37.368146 INFO : End of 2D write delay Voltage center optimization
819 10:38:37.373674 INFO : Training has run successfully!
820 10:38:37.374153
821 10:38:37.374599 channel==0
822 10:38:37.379272 RxClkDly_Margin_A0==88 ps 9
823 10:38:37.379753 TxDqDly_Margin_A0==98 ps 10
824 10:38:37.384870 RxClkDly_Margin_A1==88 ps 9
825 10:38:37.385360 TxDqDly_Margin_A1==98 ps 10
826 10:38:37.385828 TrainedVREFDQ_A0==74
827 10:38:37.390516 TrainedVREFDQ_A1==74
828 10:38:37.391053 VrefDac_Margin_A0==25
829 10:38:37.391506 DeviceVref_Margin_A0==40
830 10:38:37.396141 VrefDac_Margin_A1==25
831 10:38:37.396675 DeviceVref_Margin_A1==40
832 10:38:37.397101
833 10:38:37.397520
834 10:38:37.401677 channel==1
835 10:38:37.402144 RxClkDly_Margin_A0==98 ps 10
836 10:38:37.402570 TxDqDly_Margin_A0==98 ps 10
837 10:38:37.407279 RxClkDly_Margin_A1==98 ps 10
838 10:38:37.407743 TxDqDly_Margin_A1==88 ps 9
839 10:38:37.412877 TrainedVREFDQ_A0==77
840 10:38:37.413344 TrainedVREFDQ_A1==77
841 10:38:37.413771 VrefDac_Margin_A0==22
842 10:38:37.418480 DeviceVref_Margin_A0==37
843 10:38:37.418942 VrefDac_Margin_A1==22
844 10:38:37.424115 DeviceVref_Margin_A1==37
845 10:38:37.424571
846 10:38:37.424995 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 10:38:37.429668
848 10:38:37.457685 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
849 10:38:37.458175 2D training succeed
850 10:38:37.463282 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 10:38:37.468878 auto size-- 65535DDR cs0 size: 2048MB
852 10:38:37.469339 DDR cs1 size: 2048MB
853 10:38:37.474481 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 10:38:37.474938 cs0 DataBus test pass
855 10:38:37.480145 cs1 DataBus test pass
856 10:38:37.480605 cs0 AddrBus test pass
857 10:38:37.481028 cs1 AddrBus test pass
858 10:38:37.481446
859 10:38:37.485641 100bdlr_step_size ps== 432
860 10:38:37.486107 result report
861 10:38:37.491256 boot times 0Enable ddr reg access
862 10:38:37.496711 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 10:38:37.510255 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 10:38:38.083410 0.0;M3 CHK:0;cm4_sp_mode 0
865 10:38:38.084144 MVN_1=0x00000000
866 10:38:38.088814 MVN_2=0x00000000
867 10:38:38.094560 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 10:38:38.095250 OPS=0x10
869 10:38:38.095838 ring efuse init
870 10:38:38.096423 chipver efuse init
871 10:38:38.100254 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 10:38:38.105729 [0.018961 Inits done]
873 10:38:38.106275 secure task start!
874 10:38:38.106681 high task start!
875 10:38:38.110307 low task start!
876 10:38:38.110876 run into bl31
877 10:38:38.116991 NOTICE: BL31: v1.3(release):4fc40b1
878 10:38:38.124886 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 10:38:38.125466 NOTICE: BL31: G12A normal boot!
880 10:38:38.150430 NOTICE: BL31: BL33 decompress pass
881 10:38:38.156008 ERROR: Error initializing runtime service opteed_fast
882 10:38:39.388855
883 10:38:39.389466
884 10:38:39.397253 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 10:38:39.397793
886 10:38:39.398223 Model: Libre Computer AML-A311D-CC Alta
887 10:38:39.605651 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 10:38:39.629002 DRAM: 2 GiB (effective 3.8 GiB)
889 10:38:39.772141 Core: 408 devices, 31 uclasses, devicetree: separate
890 10:38:39.777934 WDT: Not starting watchdog@f0d0
891 10:38:39.810220 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 10:38:39.822615 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 10:38:39.827679 ** Bad device specification mmc 0 **
894 10:38:39.837976 Card did not respond to voltage select! : -110
895 10:38:39.845622 ** Bad device specification mmc 0 **
896 10:38:39.846154 Couldn't find partition mmc 0
897 10:38:39.853991 Card did not respond to voltage select! : -110
898 10:38:39.859548 ** Bad device specification mmc 0 **
899 10:38:39.860106 Couldn't find partition mmc 0
900 10:38:39.864613 Error: could not access storage.
901 10:38:40.206874 Net: eth0: ethernet@ff3f0000
902 10:38:40.207292 starting USB...
903 10:38:40.458843 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 10:38:40.459458 Starting the controller
905 10:38:40.465750 USB XHCI 1.10
906 10:38:42.019968 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 10:38:42.028244 scanning usb for storage devices... 0 Storage Device(s) found
909 10:38:42.079544 Hit any key to stop autoboot: 1
910 10:38:42.080349 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 10:38:42.081097 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 10:38:42.081643 Setting prompt string to ['=>']
913 10:38:42.082191 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 10:38:42.095639 0
915 10:38:42.096661 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 10:38:42.097222 Sending with 10 millisecond of delay
918 10:38:43.231939 => setenv autoload no
919 10:38:43.242840 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 10:38:43.248293 setenv autoload no
921 10:38:43.249103 Sending with 10 millisecond of delay
923 10:38:45.058104 => setenv initrd_high 0xffffffff
924 10:38:45.068934 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 10:38:45.069829 setenv initrd_high 0xffffffff
926 10:38:45.070583 Sending with 10 millisecond of delay
928 10:38:46.688021 => setenv fdt_high 0xffffffff
929 10:38:46.698922 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 10:38:46.699880 setenv fdt_high 0xffffffff
931 10:38:46.700719 Sending with 10 millisecond of delay
933 10:38:46.992769 => dhcp
934 10:38:47.003535 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 10:38:47.004111 dhcp
936 10:38:47.004351 Speed: 1000, full duplex
937 10:38:47.004560 BOOTP broadcast 1
938 10:38:47.012113 DHCP client bound to address 192.168.6.27 (8 ms)
939 10:38:47.012573 Sending with 10 millisecond of delay
941 10:38:48.688703 => setenv serverip 192.168.6.2
942 10:38:48.699532 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
943 10:38:48.700500 setenv serverip 192.168.6.2
944 10:38:48.701241 Sending with 10 millisecond of delay
946 10:38:52.425010 => tftpboot 0x01080000 917040/tftp-deploy-_1f3qnwr/kernel/uImage
947 10:38:52.435860 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
948 10:38:52.436786 tftpboot 0x01080000 917040/tftp-deploy-_1f3qnwr/kernel/uImage
949 10:38:52.437276 Speed: 1000, full duplex
950 10:38:52.437732 Using ethernet@ff3f0000 device
951 10:38:52.438514 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
952 10:38:52.444107 Filename '917040/tftp-deploy-_1f3qnwr/kernel/uImage'.
953 10:38:52.448136 Load address: 0x1080000
954 10:38:54.881515 Loading: *################################################## 36.2 MiB
955 10:38:54.882181 14.9 MiB/s
956 10:38:54.882659 done
957 10:38:54.885932 Bytes transferred = 38009408 (243fa40 hex)
958 10:38:54.886780 Sending with 10 millisecond of delay
960 10:38:59.578847 => tftpboot 0x08000000 917040/tftp-deploy-_1f3qnwr/ramdisk/ramdisk.cpio.gz.uboot
961 10:38:59.589593 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
962 10:38:59.590392 tftpboot 0x08000000 917040/tftp-deploy-_1f3qnwr/ramdisk/ramdisk.cpio.gz.uboot
963 10:38:59.590834 Speed: 1000, full duplex
964 10:38:59.591248 Using ethernet@ff3f0000 device
965 10:38:59.592268 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
966 10:38:59.604021 Filename '917040/tftp-deploy-_1f3qnwr/ramdisk/ramdisk.cpio.gz.uboot'.
967 10:38:59.604480 Load address: 0x8000000
968 10:39:08.795342 Loading: *###########T ###################################### UDP wrong checksum 0000000f 00000b1f
969 10:39:13.796526 T UDP wrong checksum 0000000f 00000b1f
970 10:39:23.799717 T T UDP wrong checksum 0000000f 00000b1f
971 10:39:43.803713 T T T T UDP wrong checksum 0000000f 00000b1f
972 10:39:58.807701 T T
973 10:39:58.808194 Retry count exceeded; starting again
975 10:39:58.809091 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
978 10:39:58.810057 end: 2.4 uboot-commands (duration 00:01:49) [common]
980 10:39:58.810790 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
982 10:39:58.811350 end: 2 uboot-action (duration 00:01:49) [common]
984 10:39:58.812237 Cleaning after the job
985 10:39:58.812559 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/ramdisk
986 10:39:58.813444 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/kernel
987 10:39:58.834700 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/dtb
988 10:39:58.835445 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/917040/tftp-deploy-_1f3qnwr/modules
989 10:39:58.856122 start: 4.1 power-off (timeout 00:00:30) [common]
990 10:39:58.856760 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
991 10:39:58.892536 >> OK - accepted request
992 10:39:58.894463 Returned 0 in 0 seconds
993 10:39:58.995146 end: 4.1 power-off (duration 00:00:00) [common]
995 10:39:58.996066 start: 4.2 read-feedback (timeout 00:10:00) [common]
996 10:39:58.996730 Listened to connection for namespace 'common' for up to 1s
997 10:39:59.996819 Finalising connection for namespace 'common'
998 10:39:59.997504 Disconnecting from shell: Finalise
999 10:39:59.998010 =>
1000 10:40:00.098964 end: 4.2 read-feedback (duration 00:00:01) [common]
1001 10:40:00.099622 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/917040
1002 10:40:00.708992 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/917040
1003 10:40:00.709612 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.