Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:39:01.540904 lava-dispatcher, installed at version: 2024.01
2 09:39:01.541664 start: 0 validate
3 09:39:01.542133 Start time: 2024-11-01 09:39:01.542103+00:00 (UTC)
4 09:39:01.542676 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:39:01.543205 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:39:01.582081 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:39:01.582677 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 09:39:01.612396 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:39:01.613025 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 09:39:02.664257 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:39:02.664853 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2BCONFIG_ARM64_16K_PAGES%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 09:39:02.706019 validate duration: 1.16
14 09:39:02.706879 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:39:02.707210 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:39:02.707515 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:39:02.708120 Not decompressing ramdisk as can be used compressed.
18 09:39:02.708559 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:39:02.708830 saving as /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/ramdisk/rootfs.cpio.gz
20 09:39:02.709104 total size: 8181887 (7 MB)
21 09:39:02.745119 progress 0 % (0 MB)
22 09:39:02.755900 progress 5 % (0 MB)
23 09:39:02.766516 progress 10 % (0 MB)
24 09:39:02.777113 progress 15 % (1 MB)
25 09:39:02.782627 progress 20 % (1 MB)
26 09:39:02.788667 progress 25 % (1 MB)
27 09:39:02.794007 progress 30 % (2 MB)
28 09:39:02.799927 progress 35 % (2 MB)
29 09:39:02.805252 progress 40 % (3 MB)
30 09:39:02.811203 progress 45 % (3 MB)
31 09:39:02.816916 progress 50 % (3 MB)
32 09:39:02.822825 progress 55 % (4 MB)
33 09:39:02.828144 progress 60 % (4 MB)
34 09:39:02.833898 progress 65 % (5 MB)
35 09:39:02.839249 progress 70 % (5 MB)
36 09:39:02.845076 progress 75 % (5 MB)
37 09:39:02.850492 progress 80 % (6 MB)
38 09:39:02.856333 progress 85 % (6 MB)
39 09:39:02.861692 progress 90 % (7 MB)
40 09:39:02.867454 progress 95 % (7 MB)
41 09:39:02.872667 progress 100 % (7 MB)
42 09:39:02.873320 7 MB downloaded in 0.16 s (47.52 MB/s)
43 09:39:02.873895 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:39:02.874826 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:39:02.875139 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:39:02.875426 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:39:02.875913 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/kernel/Image
49 09:39:02.876191 saving as /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/kernel/Image
50 09:39:02.876415 total size: 46260736 (44 MB)
51 09:39:02.876634 No compression specified
52 09:39:02.914805 progress 0 % (0 MB)
53 09:39:02.943198 progress 5 % (2 MB)
54 09:39:02.971663 progress 10 % (4 MB)
55 09:39:02.999799 progress 15 % (6 MB)
56 09:39:03.028643 progress 20 % (8 MB)
57 09:39:03.056597 progress 25 % (11 MB)
58 09:39:03.085210 progress 30 % (13 MB)
59 09:39:03.114000 progress 35 % (15 MB)
60 09:39:03.142149 progress 40 % (17 MB)
61 09:39:03.170608 progress 45 % (19 MB)
62 09:39:03.198293 progress 50 % (22 MB)
63 09:39:03.227045 progress 55 % (24 MB)
64 09:39:03.255149 progress 60 % (26 MB)
65 09:39:03.283221 progress 65 % (28 MB)
66 09:39:03.311608 progress 70 % (30 MB)
67 09:39:03.339794 progress 75 % (33 MB)
68 09:39:03.368414 progress 80 % (35 MB)
69 09:39:03.396889 progress 85 % (37 MB)
70 09:39:03.425201 progress 90 % (39 MB)
71 09:39:03.453323 progress 95 % (41 MB)
72 09:39:03.480595 progress 100 % (44 MB)
73 09:39:03.481315 44 MB downloaded in 0.60 s (72.94 MB/s)
74 09:39:03.481796 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:39:03.482594 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:39:03.482866 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:39:03.483129 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:39:03.483572 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 09:39:03.483838 saving as /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 09:39:03.484064 total size: 53209 (0 MB)
82 09:39:03.484274 No compression specified
83 09:39:03.528564 progress 61 % (0 MB)
84 09:39:03.529444 progress 100 % (0 MB)
85 09:39:03.529981 0 MB downloaded in 0.05 s (1.11 MB/s)
86 09:39:03.530449 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:39:03.531262 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:39:03.531521 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:39:03.531782 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:39:03.532251 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+CONFIG_ARM64_16K_PAGES=y/gcc-12/modules.tar.xz
92 09:39:03.532508 saving as /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/modules/modules.tar
93 09:39:03.532714 total size: 11589588 (11 MB)
94 09:39:03.532923 Using unxz to decompress xz
95 09:39:03.572700 progress 0 % (0 MB)
96 09:39:03.650478 progress 5 % (0 MB)
97 09:39:03.736308 progress 10 % (1 MB)
98 09:39:03.831841 progress 15 % (1 MB)
99 09:39:03.926794 progress 20 % (2 MB)
100 09:39:04.018844 progress 25 % (2 MB)
101 09:39:04.112977 progress 30 % (3 MB)
102 09:39:04.197282 progress 35 % (3 MB)
103 09:39:04.290054 progress 40 % (4 MB)
104 09:39:04.390840 progress 45 % (5 MB)
105 09:39:04.480701 progress 50 % (5 MB)
106 09:39:04.577860 progress 55 % (6 MB)
107 09:39:04.672103 progress 60 % (6 MB)
108 09:39:04.766119 progress 65 % (7 MB)
109 09:39:04.859686 progress 70 % (7 MB)
110 09:39:04.955488 progress 75 % (8 MB)
111 09:39:05.046958 progress 80 % (8 MB)
112 09:39:05.140224 progress 85 % (9 MB)
113 09:39:05.224917 progress 90 % (9 MB)
114 09:39:05.344884 progress 95 % (10 MB)
115 09:39:05.441870 progress 100 % (11 MB)
116 09:39:05.455056 11 MB downloaded in 1.92 s (5.75 MB/s)
117 09:39:05.456013 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:39:05.457769 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:39:05.458341 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 09:39:05.458908 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 09:39:05.459442 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:39:05.460011 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 09:39:05.461149 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd
125 09:39:05.462096 makedir: /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin
126 09:39:05.462788 makedir: /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/tests
127 09:39:05.463453 makedir: /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/results
128 09:39:05.464140 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-add-keys
129 09:39:05.465232 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-add-sources
130 09:39:05.466265 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-background-process-start
131 09:39:05.467291 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-background-process-stop
132 09:39:05.468400 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-common-functions
133 09:39:05.469443 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-echo-ipv4
134 09:39:05.470460 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-install-packages
135 09:39:05.471438 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-installed-packages
136 09:39:05.472450 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-os-build
137 09:39:05.473446 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-probe-channel
138 09:39:05.474421 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-probe-ip
139 09:39:05.475390 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-target-ip
140 09:39:05.476400 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-target-mac
141 09:39:05.477377 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-target-storage
142 09:39:05.478364 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-test-case
143 09:39:05.479347 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-test-event
144 09:39:05.480358 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-test-feedback
145 09:39:05.481346 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-test-raise
146 09:39:05.482321 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-test-reference
147 09:39:05.483290 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-test-runner
148 09:39:05.484324 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-test-set
149 09:39:05.485312 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-test-shell
150 09:39:05.486320 Updating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-install-packages (oe)
151 09:39:05.487395 Updating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/bin/lava-installed-packages (oe)
152 09:39:05.488340 Creating /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/environment
153 09:39:05.489133 LAVA metadata
154 09:39:05.489655 - LAVA_JOB_ID=922162
155 09:39:05.490127 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:39:05.490860 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 09:39:05.492860 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:39:05.493513 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 09:39:05.493965 skipped lava-vland-overlay
160 09:39:05.494502 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:39:05.495056 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 09:39:05.495527 skipped lava-multinode-overlay
163 09:39:05.496088 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:39:05.496645 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 09:39:05.497170 Loading test definitions
166 09:39:05.497766 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 09:39:05.498248 Using /lava-922162 at stage 0
168 09:39:05.500838 uuid=922162_1.5.2.4.1 testdef=None
169 09:39:05.501446 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:39:05.501960 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 09:39:05.504850 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:39:05.505681 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 09:39:05.507973 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:39:05.508856 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 09:39:05.511044 runner path: /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/0/tests/0_dmesg test_uuid 922162_1.5.2.4.1
178 09:39:05.511601 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:39:05.512397 Creating lava-test-runner.conf files
181 09:39:05.512600 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/922162/lava-overlay-pcy6pwhd/lava-922162/0 for stage 0
182 09:39:05.513005 - 0_dmesg
183 09:39:05.513362 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:39:05.513639 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 09:39:05.539810 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:39:05.540272 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 09:39:05.540538 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:39:05.540805 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:39:05.541068 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 09:39:06.524312 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:39:06.525105 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 09:39:06.525654 extracting modules file /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/922162/extract-overlay-ramdisk-z0fcgqyw/ramdisk
193 09:39:07.889472 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 09:39:07.889947 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 09:39:07.890239 [common] Applying overlay /var/lib/lava/dispatcher/tmp/922162/compress-overlay-pg0dimdm/overlay-1.5.2.5.tar.gz to ramdisk
196 09:39:07.890462 [common] Applying overlay /var/lib/lava/dispatcher/tmp/922162/compress-overlay-pg0dimdm/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/922162/extract-overlay-ramdisk-z0fcgqyw/ramdisk
197 09:39:07.921022 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:39:07.921460 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 09:39:07.921762 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 09:39:07.922007 Converting downloaded kernel to a uImage
201 09:39:07.922329 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/kernel/Image /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/kernel/uImage
202 09:39:08.391901 output: Image Name:
203 09:39:08.392345 output: Created: Fri Nov 1 09:39:07 2024
204 09:39:08.392556 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:39:08.392761 output: Data Size: 46260736 Bytes = 45176.50 KiB = 44.12 MiB
206 09:39:08.392962 output: Load Address: 01080000
207 09:39:08.393161 output: Entry Point: 01080000
208 09:39:08.393359 output:
209 09:39:08.393702 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 09:39:08.393969 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 09:39:08.394235 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 09:39:08.394484 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:39:08.394737 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 09:39:08.394991 Building ramdisk /var/lib/lava/dispatcher/tmp/922162/extract-overlay-ramdisk-z0fcgqyw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/922162/extract-overlay-ramdisk-z0fcgqyw/ramdisk
215 09:39:10.816715 >> 181912 blocks
216 09:39:19.227699 Adding RAMdisk u-boot header.
217 09:39:19.228430 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/922162/extract-overlay-ramdisk-z0fcgqyw/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/922162/extract-overlay-ramdisk-z0fcgqyw/ramdisk.cpio.gz.uboot
218 09:39:19.511329 output: Image Name:
219 09:39:19.511748 output: Created: Fri Nov 1 09:39:19 2024
220 09:39:19.511958 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:39:19.512430 output: Data Size: 26063007 Bytes = 25452.16 KiB = 24.86 MiB
222 09:39:19.512831 output: Load Address: 00000000
223 09:39:19.513243 output: Entry Point: 00000000
224 09:39:19.513633 output:
225 09:39:19.514592 rename /var/lib/lava/dispatcher/tmp/922162/extract-overlay-ramdisk-z0fcgqyw/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/ramdisk/ramdisk.cpio.gz.uboot
226 09:39:19.515281 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 09:39:19.515807 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 09:39:19.516367 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 09:39:19.516813 No LXC device requested
230 09:39:19.517304 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:39:19.517800 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 09:39:19.518283 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:39:19.518687 Checking files for TFTP limit of 4294967296 bytes.
234 09:39:19.521355 end: 1 tftp-deploy (duration 00:00:17) [common]
235 09:39:19.521934 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:39:19.522451 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:39:19.522940 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:39:19.523432 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:39:19.523957 Using kernel file from prepare-kernel: 922162/tftp-deploy-c5wdziwl/kernel/uImage
240 09:39:19.524609 substitutions:
241 09:39:19.525016 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:39:19.525416 - {DTB_ADDR}: 0x01070000
243 09:39:19.525807 - {DTB}: 922162/tftp-deploy-c5wdziwl/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 09:39:19.526201 - {INITRD}: 922162/tftp-deploy-c5wdziwl/ramdisk/ramdisk.cpio.gz.uboot
245 09:39:19.526595 - {KERNEL_ADDR}: 0x01080000
246 09:39:19.526984 - {KERNEL}: 922162/tftp-deploy-c5wdziwl/kernel/uImage
247 09:39:19.527374 - {LAVA_MAC}: None
248 09:39:19.527795 - {PRESEED_CONFIG}: None
249 09:39:19.528210 - {PRESEED_LOCAL}: None
250 09:39:19.528599 - {RAMDISK_ADDR}: 0x08000000
251 09:39:19.528985 - {RAMDISK}: 922162/tftp-deploy-c5wdziwl/ramdisk/ramdisk.cpio.gz.uboot
252 09:39:19.529373 - {ROOT_PART}: None
253 09:39:19.529757 - {ROOT}: None
254 09:39:19.530140 - {SERVER_IP}: 192.168.6.2
255 09:39:19.530529 - {TEE_ADDR}: 0x83000000
256 09:39:19.530914 - {TEE}: None
257 09:39:19.531299 Parsed boot commands:
258 09:39:19.531673 - setenv autoload no
259 09:39:19.532110 - setenv initrd_high 0xffffffff
260 09:39:19.532501 - setenv fdt_high 0xffffffff
261 09:39:19.532885 - dhcp
262 09:39:19.533269 - setenv serverip 192.168.6.2
263 09:39:19.533652 - tftpboot 0x01080000 922162/tftp-deploy-c5wdziwl/kernel/uImage
264 09:39:19.534035 - tftpboot 0x08000000 922162/tftp-deploy-c5wdziwl/ramdisk/ramdisk.cpio.gz.uboot
265 09:39:19.534419 - tftpboot 0x01070000 922162/tftp-deploy-c5wdziwl/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 09:39:19.534802 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:39:19.535189 - bootm 0x01080000 0x08000000 0x01070000
268 09:39:19.535677 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:39:19.537184 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:39:19.537618 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 09:39:19.552287 Setting prompt string to ['lava-test: # ']
273 09:39:19.553736 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:39:19.554309 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:39:19.554835 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:39:19.555348 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:39:19.556515 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 09:39:19.593179 >> OK - accepted request
279 09:39:19.595121 Returned 0 in 0 seconds
280 09:39:19.696177 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:39:19.697689 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:39:19.698231 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:39:19.698721 Setting prompt string to ['Hit any key to stop autoboot']
285 09:39:19.699156 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:39:19.700745 Trying 192.168.56.21...
287 09:39:19.701216 Connected to conserv1.
288 09:39:19.701626 Escape character is '^]'.
289 09:39:19.702032
290 09:39:19.702449 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 09:39:19.702870
292 09:39:27.004110 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 09:39:27.004741 bl2_stage_init 0x01
294 09:39:27.005187 bl2_stage_init 0x81
295 09:39:27.009469 hw id: 0x0000 - pwm id 0x01
296 09:39:27.009958 bl2_stage_init 0xc1
297 09:39:27.014965 bl2_stage_init 0x02
298 09:39:27.015436
299 09:39:27.015866 L0:00000000
300 09:39:27.016316 L1:00000703
301 09:39:27.016714 L2:00008067
302 09:39:27.017108 L3:15000000
303 09:39:27.020570 S1:00000000
304 09:39:27.021008 B2:20282000
305 09:39:27.021408 B1:a0f83180
306 09:39:27.021800
307 09:39:27.022194 TE: 69617
308 09:39:27.022588
309 09:39:27.026244 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 09:39:27.026678
311 09:39:27.031751 Board ID = 1
312 09:39:27.032209 Set cpu clk to 24M
313 09:39:27.032607 Set clk81 to 24M
314 09:39:27.037503 Use GP1_pll as DSU clk.
315 09:39:27.037930 DSU clk: 1200 Mhz
316 09:39:27.038325 CPU clk: 1200 MHz
317 09:39:27.043035 Set clk81 to 166.6M
318 09:39:27.048612 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 09:39:27.049038 board id: 1
320 09:39:27.055807 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:39:27.066541 fw parse done
322 09:39:27.072471 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:39:27.115559 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:39:27.126761 PIEI prepare done
325 09:39:27.127190 fastboot data load
326 09:39:27.127590 fastboot data verify
327 09:39:27.132297 verify result: 266
328 09:39:27.137903 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 09:39:27.138326 LPDDR4 probe
330 09:39:27.138719 ddr clk to 1584MHz
331 09:39:27.145899 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:39:27.183681
333 09:39:27.184148 dmc_version 0001
334 09:39:27.190756 Check phy result
335 09:39:27.196621 INFO : End of CA training
336 09:39:27.197039 INFO : End of initialization
337 09:39:27.202245 INFO : Training has run successfully!
338 09:39:27.202662 Check phy result
339 09:39:27.207808 INFO : End of initialization
340 09:39:27.208251 INFO : End of read enable training
341 09:39:27.213471 INFO : End of fine write leveling
342 09:39:27.219015 INFO : End of Write leveling coarse delay
343 09:39:27.219428 INFO : Training has run successfully!
344 09:39:27.219823 Check phy result
345 09:39:27.224629 INFO : End of initialization
346 09:39:27.225049 INFO : End of read dq deskew training
347 09:39:27.230233 INFO : End of MPR read delay center optimization
348 09:39:27.235794 INFO : End of write delay center optimization
349 09:39:27.241453 INFO : End of read delay center optimization
350 09:39:27.241872 INFO : End of max read latency training
351 09:39:27.247001 INFO : Training has run successfully!
352 09:39:27.247419 1D training succeed
353 09:39:27.256216 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:39:27.304645 Check phy result
355 09:39:27.305114 INFO : End of initialization
356 09:39:27.331865 INFO : End of 2D read delay Voltage center optimization
357 09:39:27.356054 INFO : End of 2D read delay Voltage center optimization
358 09:39:27.412752 INFO : End of 2D write delay Voltage center optimization
359 09:39:27.466781 INFO : End of 2D write delay Voltage center optimization
360 09:39:27.472386 INFO : Training has run successfully!
361 09:39:27.472809
362 09:39:27.473212 channel==0
363 09:39:27.477929 RxClkDly_Margin_A0==78 ps 8
364 09:39:27.478346 TxDqDly_Margin_A0==98 ps 10
365 09:39:27.483475 RxClkDly_Margin_A1==88 ps 9
366 09:39:27.483900 TxDqDly_Margin_A1==98 ps 10
367 09:39:27.484356 TrainedVREFDQ_A0==76
368 09:39:27.489151 TrainedVREFDQ_A1==74
369 09:39:27.489571 VrefDac_Margin_A0==22
370 09:39:27.489964 DeviceVref_Margin_A0==38
371 09:39:27.494738 VrefDac_Margin_A1==22
372 09:39:27.495154 DeviceVref_Margin_A1==40
373 09:39:27.495551
374 09:39:27.495942
375 09:39:27.500361 channel==1
376 09:39:27.500776 RxClkDly_Margin_A0==78 ps 8
377 09:39:27.501173 TxDqDly_Margin_A0==98 ps 10
378 09:39:27.505911 RxClkDly_Margin_A1==78 ps 8
379 09:39:27.506326 TxDqDly_Margin_A1==78 ps 8
380 09:39:27.511468 TrainedVREFDQ_A0==78
381 09:39:27.511888 TrainedVREFDQ_A1==75
382 09:39:27.512317 VrefDac_Margin_A0==22
383 09:39:27.517133 DeviceVref_Margin_A0==36
384 09:39:27.517545 VrefDac_Margin_A1==22
385 09:39:27.522704 DeviceVref_Margin_A1==38
386 09:39:27.523117
387 09:39:27.523515 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:39:27.523904
389 09:39:27.556299 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
390 09:39:27.556788 2D training succeed
391 09:39:27.561873 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:39:27.567503 auto size-- 65535DDR cs0 size: 2048MB
393 09:39:27.567924 DDR cs1 size: 2048MB
394 09:39:27.573086 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:39:27.573503 cs0 DataBus test pass
396 09:39:27.578667 cs1 DataBus test pass
397 09:39:27.579084 cs0 AddrBus test pass
398 09:39:27.579478 cs1 AddrBus test pass
399 09:39:27.579863
400 09:39:27.584312 100bdlr_step_size ps== 471
401 09:39:27.584743 result report
402 09:39:27.589909 boot times 0Enable ddr reg access
403 09:39:27.595136 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:39:27.609004 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 09:39:28.268131 bl2z: ptr: 05129330, size: 00001e40
406 09:39:28.275623 0.0;M3 CHK:0;cm4_sp_mode 0
407 09:39:28.276098 MVN_1=0x00000000
408 09:39:28.276505 MVN_2=0x00000000
409 09:39:28.287082 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 09:39:28.287522 OPS=0x04
411 09:39:28.287924 ring efuse init
412 09:39:28.292734 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 09:39:28.293164 [0.017354 Inits done]
414 09:39:28.293560 secure task start!
415 09:39:28.300255 high task start!
416 09:39:28.300688 low task start!
417 09:39:28.301083 run into bl31
418 09:39:28.308887 NOTICE: BL31: v1.3(release):4fc40b1
419 09:39:28.316663 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 09:39:28.317107 NOTICE: BL31: G12A normal boot!
421 09:39:28.332376 NOTICE: BL31: BL33 decompress pass
422 09:39:28.337995 ERROR: Error initializing runtime service opteed_fast
423 09:39:29.554191 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 09:39:29.554729 bl2_stage_init 0x01
425 09:39:29.555137 bl2_stage_init 0x81
426 09:39:29.559750 hw id: 0x0000 - pwm id 0x01
427 09:39:29.560259 bl2_stage_init 0xc1
428 09:39:29.564637 bl2_stage_init 0x02
429 09:39:29.565060
430 09:39:29.565463 L0:00000000
431 09:39:29.565853 L1:00000703
432 09:39:29.566245 L2:00008067
433 09:39:29.570207 L3:15000000
434 09:39:29.570624 S1:00000000
435 09:39:29.571021 B2:20282000
436 09:39:29.571411 B1:a0f83180
437 09:39:29.571798
438 09:39:29.572230 TE: 68768
439 09:39:29.572624
440 09:39:29.581407 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 09:39:29.581838
442 09:39:29.582237 Board ID = 1
443 09:39:29.582643 Set cpu clk to 24M
444 09:39:29.583035 Set clk81 to 24M
445 09:39:29.587060 Use GP1_pll as DSU clk.
446 09:39:29.587479 DSU clk: 1200 Mhz
447 09:39:29.587875 CPU clk: 1200 MHz
448 09:39:29.592619 Set clk81 to 166.6M
449 09:39:29.598227 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 09:39:29.598646 board id: 1
451 09:39:29.606104 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 09:39:29.616812 fw parse done
453 09:39:29.622859 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 09:39:29.665347 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 09:39:29.676334 PIEI prepare done
456 09:39:29.676750 fastboot data load
457 09:39:29.677149 fastboot data verify
458 09:39:29.681898 verify result: 266
459 09:39:29.687492 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 09:39:29.687906 LPDDR4 probe
461 09:39:29.688373 ddr clk to 1584MHz
462 09:39:31.050444 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 09:39:31.051035 bl2_stage_init 0x01
464 09:39:31.051450 bl2_stage_init 0x81
465 09:39:31.055954 hw id: 0x0000 - pwm id 0x01
466 09:39:31.056435 bl2_stage_init 0xc1
467 09:39:31.061619 bl2_stage_init 0x02
468 09:39:31.062095
469 09:39:31.062482 L0:00000000
470 09:39:31.062858 L1:00000703
471 09:39:31.063237 L2:00008067
472 09:39:31.063613 L3:15000000
473 09:39:31.067186 S1:00000000
474 09:39:31.067597 B2:20282000
475 09:39:31.067975 B1:a0f83180
476 09:39:31.068388
477 09:39:31.068767 TE: 66519
478 09:39:31.069141
479 09:39:31.072868 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 09:39:31.073281
481 09:39:31.078405 Board ID = 1
482 09:39:31.078808 Set cpu clk to 24M
483 09:39:31.079188 Set clk81 to 24M
484 09:39:31.084007 Use GP1_pll as DSU clk.
485 09:39:31.084419 DSU clk: 1200 Mhz
486 09:39:31.084799 CPU clk: 1200 MHz
487 09:39:31.089559 Set clk81 to 166.6M
488 09:39:31.095183 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 09:39:31.095586 board id: 1
490 09:39:31.102377 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 09:39:31.113072 fw parse done
492 09:39:31.119081 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 09:39:31.161655 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 09:39:31.172621 PIEI prepare done
495 09:39:31.173023 fastboot data load
496 09:39:31.173403 fastboot data verify
497 09:39:31.178217 verify result: 266
498 09:39:31.183819 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 09:39:31.184282 LPDDR4 probe
500 09:39:31.184665 ddr clk to 1584MHz
501 09:39:31.191756 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 09:39:31.229028
503 09:39:31.229454 dmc_version 0001
504 09:39:31.235690 Check phy result
505 09:39:31.241615 INFO : End of CA training
506 09:39:31.242030 INFO : End of initialization
507 09:39:31.247231 INFO : Training has run successfully!
508 09:39:31.247653 Check phy result
509 09:39:31.252832 INFO : End of initialization
510 09:39:31.253257 INFO : End of read enable training
511 09:39:31.258434 INFO : End of fine write leveling
512 09:39:31.264093 INFO : End of Write leveling coarse delay
513 09:39:31.264510 INFO : Training has run successfully!
514 09:39:31.264908 Check phy result
515 09:39:31.269602 INFO : End of initialization
516 09:39:31.270022 INFO : End of read dq deskew training
517 09:39:31.275224 INFO : End of MPR read delay center optimization
518 09:39:31.280825 INFO : End of write delay center optimization
519 09:39:31.286442 INFO : End of read delay center optimization
520 09:39:31.286858 INFO : End of max read latency training
521 09:39:31.292094 INFO : Training has run successfully!
522 09:39:31.292514 1D training succeed
523 09:39:31.301221 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 09:39:31.348756 Check phy result
525 09:39:31.349185 INFO : End of initialization
526 09:39:31.371187 INFO : End of 2D read delay Voltage center optimization
527 09:39:31.390293 INFO : End of 2D read delay Voltage center optimization
528 09:39:31.442180 INFO : End of 2D write delay Voltage center optimization
529 09:39:31.491348 INFO : End of 2D write delay Voltage center optimization
530 09:39:31.496996 INFO : Training has run successfully!
531 09:39:31.497434
532 09:39:31.497837 channel==0
533 09:39:31.502543 RxClkDly_Margin_A0==78 ps 8
534 09:39:31.502959 TxDqDly_Margin_A0==98 ps 10
535 09:39:31.508196 RxClkDly_Margin_A1==88 ps 9
536 09:39:31.508611 TxDqDly_Margin_A1==88 ps 9
537 09:39:31.509009 TrainedVREFDQ_A0==74
538 09:39:31.513730 TrainedVREFDQ_A1==74
539 09:39:31.514144 VrefDac_Margin_A0==23
540 09:39:31.514538 DeviceVref_Margin_A0==40
541 09:39:31.519340 VrefDac_Margin_A1==23
542 09:39:31.519755 DeviceVref_Margin_A1==40
543 09:39:31.520184
544 09:39:31.520580
545 09:39:31.520970 channel==1
546 09:39:31.524976 RxClkDly_Margin_A0==88 ps 9
547 09:39:31.525391 TxDqDly_Margin_A0==98 ps 10
548 09:39:31.530512 RxClkDly_Margin_A1==78 ps 8
549 09:39:31.530927 TxDqDly_Margin_A1==88 ps 9
550 09:39:31.536163 TrainedVREFDQ_A0==78
551 09:39:31.536579 TrainedVREFDQ_A1==75
552 09:39:31.536975 VrefDac_Margin_A0==22
553 09:39:31.541736 DeviceVref_Margin_A0==36
554 09:39:31.542181 VrefDac_Margin_A1==22
555 09:39:31.547382 DeviceVref_Margin_A1==39
556 09:39:31.547815
557 09:39:31.548249 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 09:39:31.548644
559 09:39:31.581028 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
560 09:39:31.581489 2D training succeed
561 09:39:31.586515 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 09:39:31.592210 auto size-- 65535DDR cs0 size: 2048MB
563 09:39:31.592635 DDR cs1 size: 2048MB
564 09:39:31.597738 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 09:39:31.598158 cs0 DataBus test pass
566 09:39:31.603342 cs1 DataBus test pass
567 09:39:31.603761 cs0 AddrBus test pass
568 09:39:31.604197 cs1 AddrBus test pass
569 09:39:31.604593
570 09:39:31.608990 100bdlr_step_size ps== 478
571 09:39:31.609422 result report
572 09:39:31.614537 boot times 0Enable ddr reg access
573 09:39:31.619715 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 09:39:31.633565 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 09:39:32.288680 bl2z: ptr: 05129330, size: 00001e40
576 09:39:32.296065 0.0;M3 CHK:0;cm4_sp_mode 0
577 09:39:32.296518 MVN_1=0x00000000
578 09:39:32.296918 MVN_2=0x00000000
579 09:39:32.307590 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 09:39:32.308060 OPS=0x04
581 09:39:32.308466 ring efuse init
582 09:39:32.310702 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 09:39:32.316841 [0.017319 Inits done]
584 09:39:32.317258 secure task start!
585 09:39:32.317651 high task start!
586 09:39:32.318038 low task start!
587 09:39:32.320857 run into bl31
588 09:39:32.329555 NOTICE: BL31: v1.3(release):4fc40b1
589 09:39:32.337317 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 09:39:32.337740 NOTICE: BL31: G12A normal boot!
591 09:39:32.352938 NOTICE: BL31: BL33 decompress pass
592 09:39:32.358386 ERROR: Error initializing runtime service opteed_fast
593 09:39:33.603840 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 09:39:33.604421 bl2_stage_init 0x01
595 09:39:33.604831 bl2_stage_init 0x81
596 09:39:33.609549 hw id: 0x0000 - pwm id 0x01
597 09:39:33.609974 bl2_stage_init 0xc1
598 09:39:33.615091 bl2_stage_init 0x02
599 09:39:33.615511
600 09:39:33.615912 L0:00000000
601 09:39:33.616353 L1:00000703
602 09:39:33.616751 L2:00008067
603 09:39:33.617139 L3:15000000
604 09:39:33.620570 S1:00000000
605 09:39:33.620995 B2:20282000
606 09:39:33.621393 B1:a0f83180
607 09:39:33.621783
608 09:39:33.622174 TE: 69660
609 09:39:33.622564
610 09:39:33.626192 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 09:39:33.626620
612 09:39:33.631816 Board ID = 1
613 09:39:33.632262 Set cpu clk to 24M
614 09:39:33.632658 Set clk81 to 24M
615 09:39:33.637585 Use GP1_pll as DSU clk.
616 09:39:33.638008 DSU clk: 1200 Mhz
617 09:39:33.638406 CPU clk: 1200 MHz
618 09:39:33.643082 Set clk81 to 166.6M
619 09:39:33.648701 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 09:39:33.649126 board id: 1
621 09:39:33.655754 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 09:39:33.666733 fw parse done
623 09:39:33.672715 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 09:39:33.715627 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 09:39:33.726813 PIEI prepare done
626 09:39:33.727241 fastboot data load
627 09:39:33.727643 fastboot data verify
628 09:39:33.732427 verify result: 266
629 09:39:33.737983 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 09:39:33.738405 LPDDR4 probe
631 09:39:33.738803 ddr clk to 1584MHz
632 09:39:33.745951 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 09:39:33.783682
634 09:39:33.784142 dmc_version 0001
635 09:39:33.790751 Check phy result
636 09:39:33.796733 INFO : End of CA training
637 09:39:33.797153 INFO : End of initialization
638 09:39:33.802431 INFO : Training has run successfully!
639 09:39:33.802852 Check phy result
640 09:39:33.807945 INFO : End of initialization
641 09:39:33.808386 INFO : End of read enable training
642 09:39:33.811303 INFO : End of fine write leveling
643 09:39:33.816852 INFO : End of Write leveling coarse delay
644 09:39:33.822445 INFO : Training has run successfully!
645 09:39:33.822861 Check phy result
646 09:39:33.823253 INFO : End of initialization
647 09:39:33.828067 INFO : End of read dq deskew training
648 09:39:33.833652 INFO : End of MPR read delay center optimization
649 09:39:33.834074 INFO : End of write delay center optimization
650 09:39:33.839303 INFO : End of read delay center optimization
651 09:39:33.844827 INFO : End of max read latency training
652 09:39:33.845244 INFO : Training has run successfully!
653 09:39:33.850485 1D training succeed
654 09:39:33.856385 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 09:39:33.904583 Check phy result
656 09:39:33.905028 INFO : End of initialization
657 09:39:33.931968 INFO : End of 2D read delay Voltage center optimization
658 09:39:33.956207 INFO : End of 2D read delay Voltage center optimization
659 09:39:34.012860 INFO : End of 2D write delay Voltage center optimization
660 09:39:34.066857 INFO : End of 2D write delay Voltage center optimization
661 09:39:34.072470 INFO : Training has run successfully!
662 09:39:34.072894
663 09:39:34.073292 channel==0
664 09:39:34.078044 RxClkDly_Margin_A0==78 ps 8
665 09:39:34.078462 TxDqDly_Margin_A0==98 ps 10
666 09:39:34.081350 RxClkDly_Margin_A1==88 ps 9
667 09:39:34.081767 TxDqDly_Margin_A1==98 ps 10
668 09:39:34.086915 TrainedVREFDQ_A0==77
669 09:39:34.087332 TrainedVREFDQ_A1==75
670 09:39:34.092507 VrefDac_Margin_A0==23
671 09:39:34.092929 DeviceVref_Margin_A0==37
672 09:39:34.093330 VrefDac_Margin_A1==23
673 09:39:34.098104 DeviceVref_Margin_A1==39
674 09:39:34.098524
675 09:39:34.098922
676 09:39:34.099315 channel==1
677 09:39:34.099702 RxClkDly_Margin_A0==88 ps 9
678 09:39:34.103710 TxDqDly_Margin_A0==98 ps 10
679 09:39:34.104161 RxClkDly_Margin_A1==78 ps 8
680 09:39:34.109536 TxDqDly_Margin_A1==88 ps 9
681 09:39:34.109972 TrainedVREFDQ_A0==78
682 09:39:34.110370 TrainedVREFDQ_A1==75
683 09:39:34.114889 VrefDac_Margin_A0==23
684 09:39:34.115308 DeviceVref_Margin_A0==36
685 09:39:34.120524 VrefDac_Margin_A1==22
686 09:39:34.120939 DeviceVref_Margin_A1==38
687 09:39:34.121332
688 09:39:34.126110 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 09:39:34.126529
690 09:39:34.154082 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
691 09:39:34.159655 2D training succeed
692 09:39:34.165349 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 09:39:34.165775 auto size-- 65535DDR cs0 size: 2048MB
694 09:39:34.170881 DDR cs1 size: 2048MB
695 09:39:34.171300 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 09:39:34.176484 cs0 DataBus test pass
697 09:39:34.176904 cs1 DataBus test pass
698 09:39:34.177298 cs0 AddrBus test pass
699 09:39:34.182119 cs1 AddrBus test pass
700 09:39:34.182545
701 09:39:34.182951 100bdlr_step_size ps== 471
702 09:39:34.183358 result report
703 09:39:34.187695 boot times 0Enable ddr reg access
704 09:39:34.195315 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 09:39:34.209179 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 09:39:34.868578 bl2z: ptr: 05129330, size: 00001e40
707 09:39:34.875533 0.0;M3 CHK:0;cm4_sp_mode 0
708 09:39:34.875976 MVN_1=0x00000000
709 09:39:34.876422 MVN_2=0x00000000
710 09:39:34.887004 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 09:39:34.887431 OPS=0x04
712 09:39:34.887833 ring efuse init
713 09:39:34.892599 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 09:39:34.893031 [0.017354 Inits done]
715 09:39:34.893428 secure task start!
716 09:39:34.899784 high task start!
717 09:39:34.900228 low task start!
718 09:39:34.900625 run into bl31
719 09:39:34.908384 NOTICE: BL31: v1.3(release):4fc40b1
720 09:39:34.916176 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 09:39:34.916598 NOTICE: BL31: G12A normal boot!
722 09:39:34.931690 NOTICE: BL31: BL33 decompress pass
723 09:39:34.937481 ERROR: Error initializing runtime service opteed_fast
724 09:39:35.733032
725 09:39:35.733493
726 09:39:35.738407 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 09:39:35.738934
728 09:39:35.742103 Model: Libre Computer AML-S905D3-CC Solitude
729 09:39:35.888942 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 09:39:35.904291 DRAM: 2 GiB (effective 3.8 GiB)
731 09:39:36.005243 Core: 406 devices, 33 uclasses, devicetree: separate
732 09:39:36.011055 WDT: Not starting watchdog@f0d0
733 09:39:36.036151 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 09:39:36.048366 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 09:39:36.053344 ** Bad device specification mmc 0 **
736 09:39:36.063537 Card did not respond to voltage select! : -110
737 09:39:36.071063 ** Bad device specification mmc 0 **
738 09:39:36.071832 Couldn't find partition mmc 0
739 09:39:36.079401 Card did not respond to voltage select! : -110
740 09:39:36.084948 ** Bad device specification mmc 0 **
741 09:39:36.085705 Couldn't find partition mmc 0
742 09:39:36.089976 Error: could not access storage.
743 09:39:36.388194 Net: eth0: ethernet@ff3f0000
744 09:39:36.389087 starting USB...
745 09:39:36.631244 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 09:39:36.631842 Starting the controller
747 09:39:36.638120 USB XHCI 1.10
748 09:39:38.192364 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 09:39:38.200636 scanning usb for storage devices... 0 Storage Device(s) found
751 09:39:38.252258 Hit any key to stop autoboot: 1
752 09:39:38.253227 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 09:39:38.253892 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 09:39:38.254423 Setting prompt string to ['=>']
755 09:39:38.254956 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 09:39:38.266605 0
757 09:39:38.267640 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 09:39:38.369054 => setenv autoload no
760 09:39:38.369851 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 09:39:38.375127 setenv autoload no
763 09:39:38.476775 => setenv initrd_high 0xffffffff
764 09:39:38.477571 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 09:39:38.481870 setenv initrd_high 0xffffffff
767 09:39:38.583451 => setenv fdt_high 0xffffffff
768 09:39:38.584340 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 09:39:38.588676 setenv fdt_high 0xffffffff
771 09:39:38.690260 => dhcp
772 09:39:38.690990 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 09:39:38.695047 dhcp
774 09:39:39.701090 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 09:39:39.701753 Speed: 1000, full duplex
776 09:39:39.702216 BOOTP broadcast 1
777 09:39:39.949857 BOOTP broadcast 2
778 09:39:39.961241 DHCP client bound to address 192.168.6.21 (260 ms)
780 09:39:40.062807 => setenv serverip 192.168.6.2
781 09:39:40.063590 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
782 09:39:40.068222 setenv serverip 192.168.6.2
784 09:39:40.169802 => tftpboot 0x01080000 922162/tftp-deploy-c5wdziwl/kernel/uImage
785 09:39:40.170587 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
786 09:39:40.177402 tftpboot 0x01080000 922162/tftp-deploy-c5wdziwl/kernel/uImage
787 09:39:40.177914 Speed: 1000, full duplex
788 09:39:40.178368 Using ethernet@ff3f0000 device
789 09:39:40.182895 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
790 09:39:40.188368 Filename '922162/tftp-deploy-c5wdziwl/kernel/uImage'.
791 09:39:40.192406 Load address: 0x1080000
792 09:39:43.241735 Loading: *################################################## 44.1 MiB
793 09:39:43.242159 14.5 MiB/s
794 09:39:43.242378 done
795 09:39:43.246152 Bytes transferred = 46260800 (2c1e240 hex)
797 09:39:43.347369 => tftpboot 0x08000000 922162/tftp-deploy-c5wdziwl/ramdisk/ramdisk.cpio.gz.uboot
798 09:39:43.348097 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
799 09:39:43.354741 tftpboot 0x08000000 922162/tftp-deploy-c5wdziwl/ramdisk/ramdisk.cpio.gz.uboot
800 09:39:43.355106 Speed: 1000, full duplex
801 09:39:43.355317 Using ethernet@ff3f0000 device
802 09:39:43.360179 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
803 09:39:43.368983 Filename '922162/tftp-deploy-c5wdziwl/ramdisk/ramdisk.cpio.gz.uboot'.
804 09:39:43.369338 Load address: 0x8000000
805 09:39:45.102587 Loading: *################################################# UDP wrong checksum 00000005 00004416
806 09:39:50.103774 T UDP wrong checksum 00000005 00004416
807 09:40:00.105915 T T UDP wrong checksum 00000005 00004416
808 09:40:20.108309 T T T UDP wrong checksum 00000005 00004416
809 09:40:34.484289 T T T UDP wrong checksum 000000ff 000003ee
810 09:40:34.523260 UDP wrong checksum 000000ff 000088e0
811 09:40:40.113930 T
812 09:40:40.114592 Retry count exceeded; starting again
814 09:40:40.116109 end: 2.4.3 bootloader-commands (duration 00:01:02) [common]
817 09:40:40.118043 end: 2.4 uboot-commands (duration 00:01:21) [common]
819 09:40:40.119502 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
821 09:40:40.120633 end: 2 uboot-action (duration 00:01:21) [common]
823 09:40:40.122274 Cleaning after the job
824 09:40:40.122847 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/ramdisk
825 09:40:40.124335 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/kernel
826 09:40:40.154740 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/dtb
827 09:40:40.156140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/922162/tftp-deploy-c5wdziwl/modules
828 09:40:40.181548 start: 4.1 power-off (timeout 00:00:30) [common]
829 09:40:40.182180 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
830 09:40:40.215309 >> OK - accepted request
831 09:40:40.217519 Returned 0 in 0 seconds
832 09:40:40.318416 end: 4.1 power-off (duration 00:00:00) [common]
834 09:40:40.320107 start: 4.2 read-feedback (timeout 00:10:00) [common]
835 09:40:40.321303 Listened to connection for namespace 'common' for up to 1s
836 09:40:41.322116 Finalising connection for namespace 'common'
837 09:40:41.322917 Disconnecting from shell: Finalise
838 09:40:41.323507 =>
839 09:40:41.424728 end: 4.2 read-feedback (duration 00:00:01) [common]
840 09:40:41.425570 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/922162
841 09:40:41.882335 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/922162
842 09:40:41.883103 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.