Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:12:01.012674 lava-dispatcher, installed at version: 2024.01
2 09:12:01.013513 start: 0 validate
3 09:12:01.014034 Start time: 2024-11-01 09:12:01.014002+00:00 (UTC)
4 09:12:01.014602 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:12:01.015170 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:12:01.054425 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:12:01.054982 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 09:12:01.085736 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:12:01.086793 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:12:09.161953 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:12:09.162490 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 09:12:10.207711 validate duration: 9.19
14 09:12:10.210401 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:12:10.210801 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:12:10.211143 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:12:10.211873 Not decompressing ramdisk as can be used compressed.
18 09:12:10.212407 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:12:10.212697 saving as /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/ramdisk/rootfs.cpio.gz
20 09:12:10.212979 total size: 8181887 (7 MB)
21 09:12:10.280910 progress 0 % (0 MB)
22 09:12:10.293418 progress 5 % (0 MB)
23 09:12:10.304913 progress 10 % (0 MB)
24 09:12:10.317218 progress 15 % (1 MB)
25 09:12:10.326218 progress 20 % (1 MB)
26 09:12:10.331902 progress 25 % (1 MB)
27 09:12:10.337204 progress 30 % (2 MB)
28 09:12:10.343532 progress 35 % (2 MB)
29 09:12:10.349505 progress 40 % (3 MB)
30 09:12:10.355510 progress 45 % (3 MB)
31 09:12:10.361235 progress 50 % (3 MB)
32 09:12:10.366940 progress 55 % (4 MB)
33 09:12:10.372258 progress 60 % (4 MB)
34 09:12:10.377970 progress 65 % (5 MB)
35 09:12:10.383263 progress 70 % (5 MB)
36 09:12:10.389174 progress 75 % (5 MB)
37 09:12:10.394645 progress 80 % (6 MB)
38 09:12:10.400619 progress 85 % (6 MB)
39 09:12:10.406071 progress 90 % (7 MB)
40 09:12:10.411642 progress 95 % (7 MB)
41 09:12:10.416830 progress 100 % (7 MB)
42 09:12:10.417524 7 MB downloaded in 0.20 s (38.15 MB/s)
43 09:12:10.418152 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:12:10.419197 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:12:10.419565 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:12:10.419902 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:12:10.420486 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 09:12:10.420804 saving as /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/kernel/Image
50 09:12:10.421047 total size: 66843136 (63 MB)
51 09:12:10.421298 No compression specified
52 09:12:10.490108 progress 0 % (0 MB)
53 09:12:10.531453 progress 5 % (3 MB)
54 09:12:10.571863 progress 10 % (6 MB)
55 09:12:10.612227 progress 15 % (9 MB)
56 09:12:10.652672 progress 20 % (12 MB)
57 09:12:10.693340 progress 25 % (15 MB)
58 09:12:10.734937 progress 30 % (19 MB)
59 09:12:10.775962 progress 35 % (22 MB)
60 09:12:10.817225 progress 40 % (25 MB)
61 09:12:10.859292 progress 45 % (28 MB)
62 09:12:10.900586 progress 50 % (31 MB)
63 09:12:10.944950 progress 55 % (35 MB)
64 09:12:10.986140 progress 60 % (38 MB)
65 09:12:11.027563 progress 65 % (41 MB)
66 09:12:11.069296 progress 70 % (44 MB)
67 09:12:11.111711 progress 75 % (47 MB)
68 09:12:11.154588 progress 80 % (51 MB)
69 09:12:11.197148 progress 85 % (54 MB)
70 09:12:11.238458 progress 90 % (57 MB)
71 09:12:11.278935 progress 95 % (60 MB)
72 09:12:11.319016 progress 100 % (63 MB)
73 09:12:11.319808 63 MB downloaded in 0.90 s (70.93 MB/s)
74 09:12:11.320324 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:12:11.321136 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:12:11.321411 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:12:11.321674 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:12:11.322157 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 09:12:11.322436 saving as /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/dtb/meson-g12b-a311d-libretech-cc.dtb
81 09:12:11.322644 total size: 54703 (0 MB)
82 09:12:11.322852 No compression specified
83 09:12:11.356049 progress 59 % (0 MB)
84 09:12:11.356920 progress 100 % (0 MB)
85 09:12:11.357518 0 MB downloaded in 0.03 s (1.50 MB/s)
86 09:12:11.358031 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:12:11.358916 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:12:11.359217 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:12:11.359514 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:12:11.360049 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 09:12:11.360335 saving as /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/modules/modules.tar
93 09:12:11.360559 total size: 16180864 (15 MB)
94 09:12:11.360782 Using unxz to decompress xz
95 09:12:11.403824 progress 0 % (0 MB)
96 09:12:11.529467 progress 5 % (0 MB)
97 09:12:11.665657 progress 10 % (1 MB)
98 09:12:11.798340 progress 15 % (2 MB)
99 09:12:11.949576 progress 20 % (3 MB)
100 09:12:12.095657 progress 25 % (3 MB)
101 09:12:12.209969 progress 30 % (4 MB)
102 09:12:12.316437 progress 35 % (5 MB)
103 09:12:12.431404 progress 40 % (6 MB)
104 09:12:12.540202 progress 45 % (6 MB)
105 09:12:12.652909 progress 50 % (7 MB)
106 09:12:12.765034 progress 55 % (8 MB)
107 09:12:12.884217 progress 60 % (9 MB)
108 09:12:12.994130 progress 65 % (10 MB)
109 09:12:13.107947 progress 70 % (10 MB)
110 09:12:13.228506 progress 75 % (11 MB)
111 09:12:13.357295 progress 80 % (12 MB)
112 09:12:13.488962 progress 85 % (13 MB)
113 09:12:13.623968 progress 90 % (13 MB)
114 09:12:13.729886 progress 95 % (14 MB)
115 09:12:13.846078 progress 100 % (15 MB)
116 09:12:13.860012 15 MB downloaded in 2.50 s (6.17 MB/s)
117 09:12:13.861131 end: 1.4.1 http-download (duration 00:00:03) [common]
119 09:12:13.862913 end: 1.4 download-retry (duration 00:00:03) [common]
120 09:12:13.863502 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 09:12:13.864113 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 09:12:13.864672 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:12:13.865235 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 09:12:13.872303 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs
125 09:12:13.877993 makedir: /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin
126 09:12:13.878627 makedir: /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/tests
127 09:12:13.879130 makedir: /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/results
128 09:12:13.879536 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-add-keys
129 09:12:13.880452 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-add-sources
130 09:12:13.881513 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-background-process-start
131 09:12:13.882591 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-background-process-stop
132 09:12:13.883575 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-common-functions
133 09:12:13.884580 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-echo-ipv4
134 09:12:13.885567 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-install-packages
135 09:12:13.886480 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-installed-packages
136 09:12:13.887232 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-os-build
137 09:12:13.887956 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-probe-channel
138 09:12:13.888680 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-probe-ip
139 09:12:13.889249 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-target-ip
140 09:12:13.890350 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-target-mac
141 09:12:13.891011 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-target-storage
142 09:12:13.891693 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-test-case
143 09:12:13.892343 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-test-event
144 09:12:13.893031 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-test-feedback
145 09:12:13.893703 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-test-raise
146 09:12:13.894488 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-test-reference
147 09:12:13.895850 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-test-runner
148 09:12:13.896751 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-test-set
149 09:12:13.897441 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-test-shell
150 09:12:13.898164 Updating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-install-packages (oe)
151 09:12:13.900312 Updating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/bin/lava-installed-packages (oe)
152 09:12:13.901389 Creating /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/environment
153 09:12:13.902020 LAVA metadata
154 09:12:13.902354 - LAVA_JOB_ID=921897
155 09:12:13.903001 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:12:13.903431 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 09:12:13.905978 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:12:13.906372 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 09:12:13.906612 skipped lava-vland-overlay
160 09:12:13.906878 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:12:13.907166 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 09:12:13.907409 skipped lava-multinode-overlay
163 09:12:13.907676 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:12:13.907952 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 09:12:13.908274 Loading test definitions
166 09:12:13.908600 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 09:12:13.908854 Using /lava-921897 at stage 0
168 09:12:13.910417 uuid=921897_1.5.2.4.1 testdef=None
169 09:12:13.910773 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:12:13.911072 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 09:12:13.913110 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:12:13.914013 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 09:12:13.917453 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:12:13.918391 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 09:12:13.927457 runner path: /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/0/tests/0_dmesg test_uuid 921897_1.5.2.4.1
178 09:12:13.928471 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:12:13.929608 Creating lava-test-runner.conf files
181 09:12:13.929899 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/921897/lava-overlay-jvrn0xjs/lava-921897/0 for stage 0
182 09:12:13.932328 - 0_dmesg
183 09:12:13.932855 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:12:13.933191 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 09:12:13.961970 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:12:13.962437 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 09:12:13.962934 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:12:13.963298 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:12:13.963622 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 09:12:14.912968 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:12:14.913414 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 09:12:14.913662 extracting modules file /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/921897/extract-overlay-ramdisk-grfsrw5o/ramdisk
193 09:12:16.691032 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 09:12:16.691534 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 09:12:16.691813 [common] Applying overlay /var/lib/lava/dispatcher/tmp/921897/compress-overlay-ud8te0mv/overlay-1.5.2.5.tar.gz to ramdisk
196 09:12:16.692057 [common] Applying overlay /var/lib/lava/dispatcher/tmp/921897/compress-overlay-ud8te0mv/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/921897/extract-overlay-ramdisk-grfsrw5o/ramdisk
197 09:12:16.723017 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:12:16.723500 start: 1.5.6 prepare-kernel (timeout 00:09:53) [common]
199 09:12:16.723785 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:53) [common]
200 09:12:16.724052 Converting downloaded kernel to a uImage
201 09:12:16.724378 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/kernel/Image /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/kernel/uImage
202 09:12:17.449456 output: Image Name:
203 09:12:17.449848 output: Created: Fri Nov 1 09:12:16 2024
204 09:12:17.450063 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:12:17.450270 output: Data Size: 66843136 Bytes = 65276.50 KiB = 63.75 MiB
206 09:12:17.450472 output: Load Address: 01080000
207 09:12:17.450669 output: Entry Point: 01080000
208 09:12:17.450867 output:
209 09:12:17.451200 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 09:12:17.451467 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 09:12:17.451736 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 09:12:17.452018 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:12:17.452291 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 09:12:17.452545 Building ramdisk /var/lib/lava/dispatcher/tmp/921897/extract-overlay-ramdisk-grfsrw5o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/921897/extract-overlay-ramdisk-grfsrw5o/ramdisk
215 09:12:20.965848 >> 257076 blocks
216 09:12:32.086789 Adding RAMdisk u-boot header.
217 09:12:32.087495 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/921897/extract-overlay-ramdisk-grfsrw5o/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/921897/extract-overlay-ramdisk-grfsrw5o/ramdisk.cpio.gz.uboot
218 09:12:32.487238 output: Image Name:
219 09:12:32.487656 output: Created: Fri Nov 1 09:12:32 2024
220 09:12:32.487863 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:12:32.488190 output: Data Size: 33795718 Bytes = 33003.63 KiB = 32.23 MiB
222 09:12:32.488637 output: Load Address: 00000000
223 09:12:32.489072 output: Entry Point: 00000000
224 09:12:32.489504 output:
225 09:12:32.490638 rename /var/lib/lava/dispatcher/tmp/921897/extract-overlay-ramdisk-grfsrw5o/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/ramdisk/ramdisk.cpio.gz.uboot
226 09:12:32.491409 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 09:12:32.492036 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 09:12:32.492629 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 09:12:32.493130 No LXC device requested
230 09:12:32.493678 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:12:32.494233 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 09:12:32.494770 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:12:32.495219 Checking files for TFTP limit of 4294967296 bytes.
234 09:12:32.498175 end: 1 tftp-deploy (duration 00:00:22) [common]
235 09:12:32.498812 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:12:32.499389 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:12:32.499935 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:12:32.500518 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:12:32.501097 Using kernel file from prepare-kernel: 921897/tftp-deploy-hagfe41e/kernel/uImage
240 09:12:32.501784 substitutions:
241 09:12:32.502238 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:12:32.502681 - {DTB_ADDR}: 0x01070000
243 09:12:32.503120 - {DTB}: 921897/tftp-deploy-hagfe41e/dtb/meson-g12b-a311d-libretech-cc.dtb
244 09:12:32.503559 - {INITRD}: 921897/tftp-deploy-hagfe41e/ramdisk/ramdisk.cpio.gz.uboot
245 09:12:32.504032 - {KERNEL_ADDR}: 0x01080000
246 09:12:32.504475 - {KERNEL}: 921897/tftp-deploy-hagfe41e/kernel/uImage
247 09:12:32.504919 - {LAVA_MAC}: None
248 09:12:32.505393 - {PRESEED_CONFIG}: None
249 09:12:32.505831 - {PRESEED_LOCAL}: None
250 09:12:32.506264 - {RAMDISK_ADDR}: 0x08000000
251 09:12:32.506691 - {RAMDISK}: 921897/tftp-deploy-hagfe41e/ramdisk/ramdisk.cpio.gz.uboot
252 09:12:32.507128 - {ROOT_PART}: None
253 09:12:32.507562 - {ROOT}: None
254 09:12:32.508015 - {SERVER_IP}: 192.168.6.2
255 09:12:32.508457 - {TEE_ADDR}: 0x83000000
256 09:12:32.508892 - {TEE}: None
257 09:12:32.509327 Parsed boot commands:
258 09:12:32.509748 - setenv autoload no
259 09:12:32.510181 - setenv initrd_high 0xffffffff
260 09:12:32.510612 - setenv fdt_high 0xffffffff
261 09:12:32.511040 - dhcp
262 09:12:32.511469 - setenv serverip 192.168.6.2
263 09:12:32.511898 - tftpboot 0x01080000 921897/tftp-deploy-hagfe41e/kernel/uImage
264 09:12:32.512357 - tftpboot 0x08000000 921897/tftp-deploy-hagfe41e/ramdisk/ramdisk.cpio.gz.uboot
265 09:12:32.512789 - tftpboot 0x01070000 921897/tftp-deploy-hagfe41e/dtb/meson-g12b-a311d-libretech-cc.dtb
266 09:12:32.513216 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:12:32.513652 - bootm 0x01080000 0x08000000 0x01070000
268 09:12:32.514191 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:12:32.515816 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:12:32.516326 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 09:12:32.530638 Setting prompt string to ['lava-test: # ']
273 09:12:32.532283 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:12:32.532973 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:12:32.533582 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:12:32.534148 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:12:32.535420 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 09:12:32.572319 >> OK - accepted request
279 09:12:32.574220 Returned 0 in 0 seconds
280 09:12:32.675703 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:12:32.677557 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:12:32.678172 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:12:32.678714 Setting prompt string to ['Hit any key to stop autoboot']
285 09:12:32.679209 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:12:32.680960 Trying 192.168.56.21...
287 09:12:32.681492 Connected to conserv1.
288 09:12:32.681951 Escape character is '^]'.
289 09:12:32.682406
290 09:12:32.682887 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 09:12:32.683364
292 09:12:44.426206 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 09:12:44.426631 bl2_stage_init 0x01
294 09:12:44.426884 bl2_stage_init 0x81
295 09:12:44.431793 hw id: 0x0000 - pwm id 0x01
296 09:12:44.432122 bl2_stage_init 0xc1
297 09:12:44.432368 bl2_stage_init 0x02
298 09:12:44.432596
299 09:12:44.437381 L0:00000000
300 09:12:44.437642 L1:20000703
301 09:12:44.437877 L2:00008067
302 09:12:44.438091 L3:14000000
303 09:12:44.442991 B2:00402000
304 09:12:44.443257 B1:e0f83180
305 09:12:44.443476
306 09:12:44.443691 TE: 58124
307 09:12:44.443906
308 09:12:44.448584 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 09:12:44.448844
310 09:12:44.449064 Board ID = 1
311 09:12:44.454153 Set A53 clk to 24M
312 09:12:44.454424 Set A73 clk to 24M
313 09:12:44.454645 Set clk81 to 24M
314 09:12:44.459768 A53 clk: 1200 MHz
315 09:12:44.460054 A73 clk: 1200 MHz
316 09:12:44.460281 CLK81: 166.6M
317 09:12:44.460496 smccc: 00012a92
318 09:12:44.465331 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 09:12:44.470930 board id: 1
320 09:12:44.476810 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:12:44.487526 fw parse done
322 09:12:44.493535 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:12:44.536164 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:12:44.547041 PIEI prepare done
325 09:12:44.547535 fastboot data load
326 09:12:44.547975 fastboot data verify
327 09:12:44.552620 verify result: 266
328 09:12:44.558234 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 09:12:44.558765 LPDDR4 probe
330 09:12:44.559211 ddr clk to 1584MHz
331 09:12:44.566193 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:12:44.602744
333 09:12:44.603257 dmc_version 0001
334 09:12:44.610136 Check phy result
335 09:12:44.616043 INFO : End of CA training
336 09:12:44.616540 INFO : End of initialization
337 09:12:44.621628 INFO : Training has run successfully!
338 09:12:44.622108 Check phy result
339 09:12:44.627192 INFO : End of initialization
340 09:12:44.627663 INFO : End of read enable training
341 09:12:44.632807 INFO : End of fine write leveling
342 09:12:44.638386 INFO : End of Write leveling coarse delay
343 09:12:44.638874 INFO : Training has run successfully!
344 09:12:44.639312 Check phy result
345 09:12:44.644046 INFO : End of initialization
346 09:12:44.644533 INFO : End of read dq deskew training
347 09:12:44.649679 INFO : End of MPR read delay center optimization
348 09:12:44.655196 INFO : End of write delay center optimization
349 09:12:44.660825 INFO : End of read delay center optimization
350 09:12:44.661356 INFO : End of max read latency training
351 09:12:44.666395 INFO : Training has run successfully!
352 09:12:44.666881 1D training succeed
353 09:12:44.675602 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:12:44.723191 Check phy result
355 09:12:44.723713 INFO : End of initialization
356 09:12:44.745880 INFO : End of 2D read delay Voltage center optimization
357 09:12:44.766036 INFO : End of 2D read delay Voltage center optimization
358 09:12:44.818068 INFO : End of 2D write delay Voltage center optimization
359 09:12:44.867540 INFO : End of 2D write delay Voltage center optimization
360 09:12:44.873049 INFO : Training has run successfully!
361 09:12:44.873544
362 09:12:44.873991 channel==0
363 09:12:44.878720 RxClkDly_Margin_A0==88 ps 9
364 09:12:44.879250 TxDqDly_Margin_A0==98 ps 10
365 09:12:44.884336 RxClkDly_Margin_A1==88 ps 9
366 09:12:44.884809 TxDqDly_Margin_A1==98 ps 10
367 09:12:44.885215 TrainedVREFDQ_A0==74
368 09:12:44.889916 TrainedVREFDQ_A1==74
369 09:12:44.890404 VrefDac_Margin_A0==25
370 09:12:44.890829 DeviceVref_Margin_A0==40
371 09:12:44.895528 VrefDac_Margin_A1==25
372 09:12:44.896040 DeviceVref_Margin_A1==40
373 09:12:44.896449
374 09:12:44.896845
375 09:12:44.901117 channel==1
376 09:12:44.901610 RxClkDly_Margin_A0==98 ps 10
377 09:12:44.902033 TxDqDly_Margin_A0==98 ps 10
378 09:12:44.906767 RxClkDly_Margin_A1==98 ps 10
379 09:12:44.907294 TxDqDly_Margin_A1==88 ps 9
380 09:12:44.912363 TrainedVREFDQ_A0==77
381 09:12:44.912889 TrainedVREFDQ_A1==77
382 09:12:44.913326 VrefDac_Margin_A0==23
383 09:12:44.917915 DeviceVref_Margin_A0==37
384 09:12:44.918405 VrefDac_Margin_A1==23
385 09:12:44.923932 DeviceVref_Margin_A1==37
386 09:12:44.924464
387 09:12:44.924879 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:12:44.929102
389 09:12:44.957115 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 09:12:44.957733 2D training succeed
391 09:12:44.962782 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:12:44.968318 auto size-- 65535DDR cs0 size: 2048MB
393 09:12:44.968842 DDR cs1 size: 2048MB
394 09:12:44.973902 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:12:44.974420 cs0 DataBus test pass
396 09:12:44.979542 cs1 DataBus test pass
397 09:12:44.980130 cs0 AddrBus test pass
398 09:12:44.980554 cs1 AddrBus test pass
399 09:12:44.980947
400 09:12:44.985125 100bdlr_step_size ps== 420
401 09:12:44.985669 result report
402 09:12:44.990767 boot times 0Enable ddr reg access
403 09:12:44.996197 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:12:45.009565 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 09:12:45.582343 0.0;M3 CHK:0;cm4_sp_mode 0
406 09:12:45.582749 MVN_1=0x00000000
407 09:12:45.587888 MVN_2=0x00000000
408 09:12:45.593699 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 09:12:45.594022 OPS=0x10
410 09:12:45.594264 ring efuse init
411 09:12:45.594492 chipver efuse init
412 09:12:45.601963 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 09:12:45.602501 [0.018961 Inits done]
414 09:12:45.609512 secure task start!
415 09:12:45.610022 high task start!
416 09:12:45.610419 low task start!
417 09:12:45.610810 run into bl31
418 09:12:45.616192 NOTICE: BL31: v1.3(release):4fc40b1
419 09:12:45.623998 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 09:12:45.624504 NOTICE: BL31: G12A normal boot!
421 09:12:45.649351 NOTICE: BL31: BL33 decompress pass
422 09:12:45.654039 ERROR: Error initializing runtime service opteed_fast
423 09:12:46.887866
424 09:12:46.888507
425 09:12:46.896287 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 09:12:46.896768
427 09:12:46.897168 Model: Libre Computer AML-A311D-CC Alta
428 09:12:47.104939 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 09:12:47.128305 DRAM: 2 GiB (effective 3.8 GiB)
430 09:12:47.271320 Core: 408 devices, 31 uclasses, devicetree: separate
431 09:12:47.277101 WDT: Not starting watchdog@f0d0
432 09:12:47.309348 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 09:12:47.321813 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 09:12:47.326829 ** Bad device specification mmc 0 **
435 09:12:47.337239 Card did not respond to voltage select! : -110
436 09:12:47.344827 ** Bad device specification mmc 0 **
437 09:12:47.345305 Couldn't find partition mmc 0
438 09:12:47.353139 Card did not respond to voltage select! : -110
439 09:12:47.358577 ** Bad device specification mmc 0 **
440 09:12:47.359040 Couldn't find partition mmc 0
441 09:12:47.362840 Error: could not access storage.
442 09:12:48.627458 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 09:12:48.627867 bl2_stage_init 0x01
444 09:12:48.628130 bl2_stage_init 0x81
445 09:12:48.632736 hw id: 0x0000 - pwm id 0x01
446 09:12:48.633088 bl2_stage_init 0xc1
447 09:12:48.633302 bl2_stage_init 0x02
448 09:12:48.633510
449 09:12:48.638498 L0:00000000
450 09:12:48.639134 L1:20000703
451 09:12:48.639657 L2:00008067
452 09:12:48.640331 L3:14000000
453 09:12:48.645366 B2:00402000
454 09:12:48.645743 B1:e0f83180
455 09:12:48.645974
456 09:12:48.646227 TE: 58159
457 09:12:48.646465
458 09:12:48.649412 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 09:12:48.649928
460 09:12:48.650337 Board ID = 1
461 09:12:48.654757 Set A53 clk to 24M
462 09:12:48.655247 Set A73 clk to 24M
463 09:12:48.655513 Set clk81 to 24M
464 09:12:48.660400 A53 clk: 1200 MHz
465 09:12:48.660885 A73 clk: 1200 MHz
466 09:12:48.661155 CLK81: 166.6M
467 09:12:48.661369 smccc: 00012ab4
468 09:12:48.666108 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 09:12:48.671542 board id: 1
470 09:12:48.676463 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 09:12:48.688204 fw parse done
472 09:12:48.693018 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 09:12:48.735911 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 09:12:48.747437 PIEI prepare done
475 09:12:48.747790 fastboot data load
476 09:12:48.748048 fastboot data verify
477 09:12:48.753517 verify result: 266
478 09:12:48.758781 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 09:12:48.759315 LPDDR4 probe
480 09:12:48.759781 ddr clk to 1584MHz
481 09:12:48.767006 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 09:12:48.804242
483 09:12:48.804576 dmc_version 0001
484 09:12:48.810687 Check phy result
485 09:12:48.816523 INFO : End of CA training
486 09:12:48.817078 INFO : End of initialization
487 09:12:48.822174 INFO : Training has run successfully!
488 09:12:48.822778 Check phy result
489 09:12:48.827711 INFO : End of initialization
490 09:12:48.828277 INFO : End of read enable training
491 09:12:48.833506 INFO : End of fine write leveling
492 09:12:48.839191 INFO : End of Write leveling coarse delay
493 09:12:48.839843 INFO : Training has run successfully!
494 09:12:48.840314 Check phy result
495 09:12:48.844441 INFO : End of initialization
496 09:12:48.844786 INFO : End of read dq deskew training
497 09:12:48.850017 INFO : End of MPR read delay center optimization
498 09:12:48.855589 INFO : End of write delay center optimization
499 09:12:48.861464 INFO : End of read delay center optimization
500 09:12:48.862367 INFO : End of max read latency training
501 09:12:48.867003 INFO : Training has run successfully!
502 09:12:48.867590 1D training succeed
503 09:12:48.876121 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 09:12:48.923889 Check phy result
505 09:12:48.924703 INFO : End of initialization
506 09:12:48.948269 INFO : End of 2D read delay Voltage center optimization
507 09:12:48.966434 INFO : End of 2D read delay Voltage center optimization
508 09:12:49.018275 INFO : End of 2D write delay Voltage center optimization
509 09:12:49.070226 INFO : End of 2D write delay Voltage center optimization
510 09:12:49.073475 INFO : Training has run successfully!
511 09:12:49.074194
512 09:12:49.074721 channel==0
513 09:12:49.078704 RxClkDly_Margin_A0==88 ps 9
514 09:12:49.079299 TxDqDly_Margin_A0==98 ps 10
515 09:12:49.084274 RxClkDly_Margin_A1==88 ps 9
516 09:12:49.084877 TxDqDly_Margin_A1==98 ps 10
517 09:12:49.085351 TrainedVREFDQ_A0==74
518 09:12:49.089902 TrainedVREFDQ_A1==74
519 09:12:49.090539 VrefDac_Margin_A0==25
520 09:12:49.090989 DeviceVref_Margin_A0==40
521 09:12:49.095534 VrefDac_Margin_A1==24
522 09:12:49.096218 DeviceVref_Margin_A1==40
523 09:12:49.096674
524 09:12:49.097100
525 09:12:49.101037 channel==1
526 09:12:49.101664 RxClkDly_Margin_A0==98 ps 10
527 09:12:49.102110 TxDqDly_Margin_A0==98 ps 10
528 09:12:49.106568 RxClkDly_Margin_A1==88 ps 9
529 09:12:49.107119 TxDqDly_Margin_A1==98 ps 10
530 09:12:49.112335 TrainedVREFDQ_A0==77
531 09:12:49.112997 TrainedVREFDQ_A1==77
532 09:12:49.113312 VrefDac_Margin_A0==23
533 09:12:49.117870 DeviceVref_Margin_A0==37
534 09:12:49.118487 VrefDac_Margin_A1==24
535 09:12:49.123458 DeviceVref_Margin_A1==37
536 09:12:49.123821
537 09:12:49.124092 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 09:12:49.130073
539 09:12:49.157058 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
540 09:12:49.157613 2D training succeed
541 09:12:49.163552 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 09:12:49.168170 auto size-- 65535DDR cs0 size: 2048MB
543 09:12:49.168681 DDR cs1 size: 2048MB
544 09:12:49.174260 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 09:12:49.174861 cs0 DataBus test pass
546 09:12:49.179424 cs1 DataBus test pass
547 09:12:49.179971 cs0 AddrBus test pass
548 09:12:49.180446 cs1 AddrBus test pass
549 09:12:49.180864
550 09:12:49.185018 100bdlr_step_size ps== 420
551 09:12:49.185533 result report
552 09:12:49.190546 boot times 0Enable ddr reg access
553 09:12:49.196112 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 09:12:49.210033 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 09:12:49.781493 0.0;M3 CHK:0;cm4_sp_mode 0
556 09:12:49.782151 MVN_1=0x00000000
557 09:12:49.786876 MVN_2=0x00000000
558 09:12:49.792597 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 09:12:49.792915 OPS=0x10
560 09:12:49.793125 ring efuse init
561 09:12:49.793329 chipver efuse init
562 09:12:49.800837 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 09:12:49.801172 [0.018961 Inits done]
564 09:12:49.808399 secure task start!
565 09:12:49.808690 high task start!
566 09:12:49.808898 low task start!
567 09:12:49.809101 run into bl31
568 09:12:49.815031 NOTICE: BL31: v1.3(release):4fc40b1
569 09:12:49.822823 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 09:12:49.823120 NOTICE: BL31: G12A normal boot!
571 09:12:49.848311 NOTICE: BL31: BL33 decompress pass
572 09:12:49.853918 ERROR: Error initializing runtime service opteed_fast
573 09:12:51.086764
574 09:12:51.087191
575 09:12:51.095122 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 09:12:51.095528
577 09:12:51.095862 Model: Libre Computer AML-A311D-CC Alta
578 09:12:51.303594 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 09:12:51.326937 DRAM: 2 GiB (effective 3.8 GiB)
580 09:12:51.469964 Core: 408 devices, 31 uclasses, devicetree: separate
581 09:12:51.475804 WDT: Not starting watchdog@f0d0
582 09:12:51.508088 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 09:12:51.520531 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 09:12:51.525435 ** Bad device specification mmc 0 **
585 09:12:51.535832 Card did not respond to voltage select! : -110
586 09:12:51.543475 ** Bad device specification mmc 0 **
587 09:12:51.543770 Couldn't find partition mmc 0
588 09:12:51.551792 Card did not respond to voltage select! : -110
589 09:12:51.557310 ** Bad device specification mmc 0 **
590 09:12:51.557623 Couldn't find partition mmc 0
591 09:12:51.562346 Error: could not access storage.
592 09:12:51.906012 Net: eth0: ethernet@ff3f0000
593 09:12:51.906436 starting USB...
594 09:12:52.157813 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 09:12:52.158242 Starting the controller
596 09:12:52.164671 USB XHCI 1.10
597 09:12:53.876734 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 09:12:53.877147 bl2_stage_init 0x01
599 09:12:53.877359 bl2_stage_init 0x81
600 09:12:53.882224 hw id: 0x0000 - pwm id 0x01
601 09:12:53.882512 bl2_stage_init 0xc1
602 09:12:53.882731 bl2_stage_init 0x02
603 09:12:53.882946
604 09:12:53.887972 L0:00000000
605 09:12:53.888300 L1:20000703
606 09:12:53.888517 L2:00008067
607 09:12:53.888729 L3:14000000
608 09:12:53.893420 B2:00402000
609 09:12:53.893689 B1:e0f83180
610 09:12:53.893904
611 09:12:53.894115 TE: 58159
612 09:12:53.894326
613 09:12:53.899087 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 09:12:53.899375
615 09:12:53.899584 Board ID = 1
616 09:12:53.904615 Set A53 clk to 24M
617 09:12:53.904895 Set A73 clk to 24M
618 09:12:53.905109 Set clk81 to 24M
619 09:12:53.910268 A53 clk: 1200 MHz
620 09:12:53.910547 A73 clk: 1200 MHz
621 09:12:53.910767 CLK81: 166.6M
622 09:12:53.910975 smccc: 00012ab5
623 09:12:53.915963 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 09:12:53.921494 board id: 1
625 09:12:53.927418 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 09:12:53.937889 fw parse done
627 09:12:53.943912 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 09:12:53.986520 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 09:12:53.997409 PIEI prepare done
630 09:12:53.997905 fastboot data load
631 09:12:53.998358 fastboot data verify
632 09:12:54.003093 verify result: 266
633 09:12:54.008669 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 09:12:54.009162 LPDDR4 probe
635 09:12:54.009604 ddr clk to 1584MHz
636 09:12:54.016675 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 09:12:54.053921
638 09:12:54.054467 dmc_version 0001
639 09:12:54.060587 Check phy result
640 09:12:54.066457 INFO : End of CA training
641 09:12:54.066938 INFO : End of initialization
642 09:12:54.072089 INFO : Training has run successfully!
643 09:12:54.072571 Check phy result
644 09:12:54.077655 INFO : End of initialization
645 09:12:54.078131 INFO : End of read enable training
646 09:12:54.080966 INFO : End of fine write leveling
647 09:12:54.086507 INFO : End of Write leveling coarse delay
648 09:12:54.092087 INFO : Training has run successfully!
649 09:12:54.092560 Check phy result
650 09:12:54.093002 INFO : End of initialization
651 09:12:54.097691 INFO : End of read dq deskew training
652 09:12:54.103283 INFO : End of MPR read delay center optimization
653 09:12:54.103761 INFO : End of write delay center optimization
654 09:12:54.108958 INFO : End of read delay center optimization
655 09:12:54.114506 INFO : End of max read latency training
656 09:12:54.114982 INFO : Training has run successfully!
657 09:12:54.120100 1D training succeed
658 09:12:54.126094 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 09:12:54.173629 Check phy result
660 09:12:54.174140 INFO : End of initialization
661 09:12:54.195179 INFO : End of 2D read delay Voltage center optimization
662 09:12:54.216244 INFO : End of 2D read delay Voltage center optimization
663 09:12:54.268180 INFO : End of 2D write delay Voltage center optimization
664 09:12:54.317527 INFO : End of 2D write delay Voltage center optimization
665 09:12:54.323002 INFO : Training has run successfully!
666 09:12:54.323482
667 09:12:54.323938 channel==0
668 09:12:54.328536 RxClkDly_Margin_A0==88 ps 9
669 09:12:54.329015 TxDqDly_Margin_A0==98 ps 10
670 09:12:54.334153 RxClkDly_Margin_A1==88 ps 9
671 09:12:54.334629 TxDqDly_Margin_A1==98 ps 10
672 09:12:54.335085 TrainedVREFDQ_A0==74
673 09:12:54.339734 TrainedVREFDQ_A1==74
674 09:12:54.340262 VrefDac_Margin_A0==25
675 09:12:54.340716 DeviceVref_Margin_A0==40
676 09:12:54.345338 VrefDac_Margin_A1==25
677 09:12:54.345812 DeviceVref_Margin_A1==40
678 09:12:54.346256
679 09:12:54.346697
680 09:12:54.350977 channel==1
681 09:12:54.351451 RxClkDly_Margin_A0==98 ps 10
682 09:12:54.351895 TxDqDly_Margin_A0==98 ps 10
683 09:12:54.356522 RxClkDly_Margin_A1==98 ps 10
684 09:12:54.356998 TxDqDly_Margin_A1==88 ps 9
685 09:12:54.362174 TrainedVREFDQ_A0==77
686 09:12:54.362658 TrainedVREFDQ_A1==77
687 09:12:54.363108 VrefDac_Margin_A0==24
688 09:12:54.367741 DeviceVref_Margin_A0==37
689 09:12:54.368251 VrefDac_Margin_A1==23
690 09:12:54.373354 DeviceVref_Margin_A1==37
691 09:12:54.373838
692 09:12:54.374285 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 09:12:54.379014
694 09:12:54.407123 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 09:12:54.407666 2D training succeed
696 09:12:54.412620 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 09:12:54.418271 auto size-- 65535DDR cs0 size: 2048MB
698 09:12:54.418753 DDR cs1 size: 2048MB
699 09:12:54.423818 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 09:12:54.424334 cs0 DataBus test pass
701 09:12:54.429455 cs1 DataBus test pass
702 09:12:54.429937 cs0 AddrBus test pass
703 09:12:54.430383 cs1 AddrBus test pass
704 09:12:54.430824
705 09:12:54.435084 100bdlr_step_size ps== 420
706 09:12:54.435581 result report
707 09:12:54.440528 boot times 0Enable ddr reg access
708 09:12:54.445965 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 09:12:54.459491 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 09:12:55.031506 0.0;M3 CHK:0;cm4_sp_mode 0
711 09:12:55.032222 MVN_1=0x00000000
712 09:12:55.036956 MVN_2=0x00000000
713 09:12:55.042711 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 09:12:55.043288 OPS=0x10
715 09:12:55.043742 ring efuse init
716 09:12:55.044223 chipver efuse init
717 09:12:55.048321 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 09:12:55.053918 [0.018960 Inits done]
719 09:12:55.054404 secure task start!
720 09:12:55.054840 high task start!
721 09:12:55.058489 low task start!
722 09:12:55.058973 run into bl31
723 09:12:55.065166 NOTICE: BL31: v1.3(release):4fc40b1
724 09:12:55.072947 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 09:12:55.073446 NOTICE: BL31: G12A normal boot!
726 09:12:55.098295 NOTICE: BL31: BL33 decompress pass
727 09:12:55.103948 ERROR: Error initializing runtime service opteed_fast
728 09:12:56.336871
729 09:12:56.337543
730 09:12:56.345340 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 09:12:56.345875
732 09:12:56.346346 Model: Libre Computer AML-A311D-CC Alta
733 09:12:56.553695 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 09:12:56.577137 DRAM: 2 GiB (effective 3.8 GiB)
735 09:12:56.720259 Core: 408 devices, 31 uclasses, devicetree: separate
736 09:12:56.726049 WDT: Not starting watchdog@f0d0
737 09:12:56.758308 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 09:12:56.770720 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 09:12:56.775756 ** Bad device specification mmc 0 **
740 09:12:56.786104 Card did not respond to voltage select! : -110
741 09:12:56.793731 ** Bad device specification mmc 0 **
742 09:12:56.794221 Couldn't find partition mmc 0
743 09:12:56.802064 Card did not respond to voltage select! : -110
744 09:12:56.807589 ** Bad device specification mmc 0 **
745 09:12:56.808116 Couldn't find partition mmc 0
746 09:12:56.812667 Error: could not access storage.
747 09:12:57.156112 Net: eth0: ethernet@ff3f0000
748 09:12:57.156678 starting USB...
749 09:12:57.407896 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 09:12:57.408486 Starting the controller
751 09:12:57.414897 USB XHCI 1.10
752 09:12:59.576910 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 09:12:59.577325 bl2_stage_init 0x01
754 09:12:59.577546 bl2_stage_init 0x81
755 09:12:59.582571 hw id: 0x0000 - pwm id 0x01
756 09:12:59.582966 bl2_stage_init 0xc1
757 09:12:59.583285 bl2_stage_init 0x02
758 09:12:59.583599
759 09:12:59.588151 L0:00000000
760 09:12:59.588537 L1:20000703
761 09:12:59.588778 L2:00008067
762 09:12:59.588986 L3:14000000
763 09:12:59.591024 B2:00402000
764 09:12:59.591399 B1:e0f83180
765 09:12:59.591718
766 09:12:59.592083 TE: 58124
767 09:12:59.592407
768 09:12:59.602138 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 09:12:59.602435
770 09:12:59.602646 Board ID = 1
771 09:12:59.602849 Set A53 clk to 24M
772 09:12:59.603051 Set A73 clk to 24M
773 09:12:59.607845 Set clk81 to 24M
774 09:12:59.608262 A53 clk: 1200 MHz
775 09:12:59.608587 A73 clk: 1200 MHz
776 09:12:59.613344 CLK81: 166.6M
777 09:12:59.613732 smccc: 00012a91
778 09:12:59.618979 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 09:12:59.619360 board id: 1
780 09:12:59.624573 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 09:12:59.638162 fw parse done
782 09:12:59.644157 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 09:12:59.686756 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 09:12:59.697688 PIEI prepare done
785 09:12:59.697981 fastboot data load
786 09:12:59.698192 fastboot data verify
787 09:12:59.703243 verify result: 266
788 09:12:59.708828 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 09:12:59.709208 LPDDR4 probe
790 09:12:59.709525 ddr clk to 1584MHz
791 09:12:59.716825 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 09:12:59.754075
793 09:12:59.754390 dmc_version 0001
794 09:12:59.760824 Check phy result
795 09:12:59.766689 INFO : End of CA training
796 09:12:59.767065 INFO : End of initialization
797 09:12:59.772216 INFO : Training has run successfully!
798 09:12:59.772493 Check phy result
799 09:12:59.777817 INFO : End of initialization
800 09:12:59.778091 INFO : End of read enable training
801 09:12:59.783428 INFO : End of fine write leveling
802 09:12:59.789034 INFO : End of Write leveling coarse delay
803 09:12:59.789318 INFO : Training has run successfully!
804 09:12:59.789529 Check phy result
805 09:12:59.794700 INFO : End of initialization
806 09:12:59.795080 INFO : End of read dq deskew training
807 09:12:59.800221 INFO : End of MPR read delay center optimization
808 09:12:59.805818 INFO : End of write delay center optimization
809 09:12:59.811437 INFO : End of read delay center optimization
810 09:12:59.811814 INFO : End of max read latency training
811 09:12:59.817019 INFO : Training has run successfully!
812 09:12:59.817293 1D training succeed
813 09:12:59.826195 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 09:12:59.873850 Check phy result
815 09:12:59.874175 INFO : End of initialization
816 09:13:00.189501 INFO : End of 2D read delay Voltage center optimization
817 09:13:00.192113 INFO : End of 2D read delay Voltage center optimization
818 09:13:00.192640 INFO : End of 2D write delay Voltage center optimization
819 09:13:00.193045 INFO : End of 2D write delay Voltage center optimization
820 09:13:00.193439 INFO : Training has run successfully!
821 09:13:00.193832
822 09:13:00.194222 channel==0
823 09:13:00.194606 RxClkDly_Margin_A0==78 ps 8
824 09:13:00.194988 TxDqDly_Margin_A0==98 ps 10
825 09:13:00.195376 RxClkDly_Margin_A1==88 ps 9
826 09:13:00.195759 TxDqDly_Margin_A1==98 ps 10
827 09:13:00.196197 TrainedVREFDQ_A0==74
828 09:13:00.196587 TrainedVREFDQ_A1==74
829 09:13:00.196969 VrefDac_Margin_A0==25
830 09:13:00.197348 DeviceVref_Margin_A0==40
831 09:13:00.197725 VrefDac_Margin_A1==25
832 09:13:00.198103 DeviceVref_Margin_A1==40
833 09:13:00.198478
834 09:13:00.198859
835 09:13:00.199239 channel==1
836 09:13:00.199614 RxClkDly_Margin_A0==88 ps 9
837 09:13:00.200008 TxDqDly_Margin_A0==98 ps 10
838 09:13:00.200396 RxClkDly_Margin_A1==98 ps 10
839 09:13:00.200770 TxDqDly_Margin_A1==88 ps 9
840 09:13:00.201154 TrainedVREFDQ_A0==77
841 09:13:00.201531 TrainedVREFDQ_A1==77
842 09:13:00.201909 VrefDac_Margin_A0==23
843 09:13:00.202279 DeviceVref_Margin_A0==37
844 09:13:00.202652 VrefDac_Margin_A1==23
845 09:13:00.203022 DeviceVref_Margin_A1==37
846 09:13:00.203390
847 09:13:00.203765 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 09:13:00.204162
849 09:13:00.204544 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
850 09:13:00.204950 2D training succeed
851 09:13:00.205334 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 09:13:00.205708 auto size-- 65535DDR cs0 size: 2048MB
853 09:13:00.206082 DDR cs1 size: 2048MB
854 09:13:00.206452 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 09:13:00.206823 cs0 DataBus test pass
856 09:13:00.207194 cs1 DataBus test pass
857 09:13:00.207566 cs0 AddrBus test pass
858 09:13:00.207948 cs1 AddrBus test pass
859 09:13:00.208353
860 09:13:00.208729 100bdlr_step_size ps== 420
861 09:13:00.209109 result report
862 09:13:00.209478 boot times 0Enable ddr reg access
863 09:13:00.209851 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 09:13:00.210619 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 09:13:00.732974 0.0;M3 CHK:0;cm4_sp_mode 0
866 09:13:00.733600 MVN_1=0x00000000
867 09:13:00.738380 MVN_2=0x00000000
868 09:13:00.744243 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 09:13:00.744733 OPS=0x10
870 09:13:00.745159 ring efuse init
871 09:13:00.745569 chipver efuse init
872 09:13:00.752419 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 09:13:00.752894 [0.018961 Inits done]
874 09:13:00.753303 secure task start!
875 09:13:00.759928 high task start!
876 09:13:00.760431 low task start!
877 09:13:00.760845 run into bl31
878 09:13:00.766579 NOTICE: BL31: v1.3(release):4fc40b1
879 09:13:00.774388 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 09:13:00.774852 NOTICE: BL31: G12A normal boot!
881 09:13:00.799805 NOTICE: BL31: BL33 decompress pass
882 09:13:00.805505 ERROR: Error initializing runtime service opteed_fast
883 09:13:02.038394
884 09:13:02.038970
885 09:13:02.046807 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 09:13:02.047293
887 09:13:02.047710 Model: Libre Computer AML-A311D-CC Alta
888 09:13:02.255210 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 09:13:02.278605 DRAM: 2 GiB (effective 3.8 GiB)
890 09:13:02.421591 Core: 408 devices, 31 uclasses, devicetree: separate
891 09:13:02.427485 WDT: Not starting watchdog@f0d0
892 09:13:02.459710 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 09:13:02.472189 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 09:13:02.477164 ** Bad device specification mmc 0 **
895 09:13:02.487491 Card did not respond to voltage select! : -110
896 09:13:02.495144 ** Bad device specification mmc 0 **
897 09:13:02.495613 Couldn't find partition mmc 0
898 09:13:02.503491 Card did not respond to voltage select! : -110
899 09:13:02.509038 ** Bad device specification mmc 0 **
900 09:13:02.509505 Couldn't find partition mmc 0
901 09:13:02.514114 Error: could not access storage.
902 09:13:02.857557 Net: eth0: ethernet@ff3f0000
903 09:13:02.858098 starting USB...
904 09:13:03.109400 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 09:13:03.109897 Starting the controller
906 09:13:03.116350 USB XHCI 1.10
907 09:13:04.976912 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
908 09:13:04.977529 bl2_stage_init 0x81
909 09:13:04.982528 hw id: 0x0000 - pwm id 0x01
910 09:13:04.982993 bl2_stage_init 0xc1
911 09:13:04.983410 bl2_stage_init 0x02
912 09:13:04.983814
913 09:13:04.987951 L0:00000000
914 09:13:04.988432 L1:20000703
915 09:13:04.988842 L2:00008067
916 09:13:04.989241 L3:14000000
917 09:13:04.989637 B2:00402000
918 09:13:04.990909 B1:e0f83180
919 09:13:04.991352
920 09:13:04.991759 TE: 58150
921 09:13:04.992209
922 09:13:05.001940 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 09:13:05.002400
924 09:13:05.002817 Board ID = 1
925 09:13:05.003219 Set A53 clk to 24M
926 09:13:05.003619 Set A73 clk to 24M
927 09:13:05.007541 Set clk81 to 24M
928 09:13:05.008005 A53 clk: 1200 MHz
929 09:13:05.008423 A73 clk: 1200 MHz
930 09:13:05.013209 CLK81: 166.6M
931 09:13:05.013653 smccc: 00012aac
932 09:13:05.018788 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 09:13:05.019234 board id: 1
934 09:13:05.027603 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 09:13:05.037950 fw parse done
936 09:13:05.043934 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 09:13:05.086572 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 09:13:05.097472 PIEI prepare done
939 09:13:05.097917 fastboot data load
940 09:13:05.098331 fastboot data verify
941 09:13:05.103105 verify result: 266
942 09:13:05.108702 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 09:13:05.109142 LPDDR4 probe
944 09:13:05.109546 ddr clk to 1584MHz
945 09:13:05.116698 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 09:13:05.153969
947 09:13:05.154418 dmc_version 0001
948 09:13:05.160780 Check phy result
949 09:13:05.166551 INFO : End of CA training
950 09:13:05.166992 INFO : End of initialization
951 09:13:05.172175 INFO : Training has run successfully!
952 09:13:05.172620 Check phy result
953 09:13:05.177707 INFO : End of initialization
954 09:13:05.178165 INFO : End of read enable training
955 09:13:05.181035 INFO : End of fine write leveling
956 09:13:05.186515 INFO : End of Write leveling coarse delay
957 09:13:05.192166 INFO : Training has run successfully!
958 09:13:05.192607 Check phy result
959 09:13:05.193040 INFO : End of initialization
960 09:13:05.197782 INFO : End of read dq deskew training
961 09:13:05.201251 INFO : End of MPR read delay center optimization
962 09:13:05.206828 INFO : End of write delay center optimization
963 09:13:05.212375 INFO : End of read delay center optimization
964 09:13:05.212826 INFO : End of max read latency training
965 09:13:05.217971 INFO : Training has run successfully!
966 09:13:05.218400 1D training succeed
967 09:13:05.226091 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 09:13:05.273700 Check phy result
969 09:13:05.274130 INFO : End of initialization
970 09:13:05.296161 INFO : End of 2D read delay Voltage center optimization
971 09:13:05.316266 INFO : End of 2D read delay Voltage center optimization
972 09:13:05.368211 INFO : End of 2D write delay Voltage center optimization
973 09:13:05.417468 INFO : End of 2D write delay Voltage center optimization
974 09:13:05.422961 INFO : Training has run successfully!
975 09:13:05.423420
976 09:13:05.423837 channel==0
977 09:13:05.428598 RxClkDly_Margin_A0==78 ps 8
978 09:13:05.429047 TxDqDly_Margin_A0==98 ps 10
979 09:13:05.431899 RxClkDly_Margin_A1==78 ps 8
980 09:13:05.432372 TxDqDly_Margin_A1==98 ps 10
981 09:13:05.437456 TrainedVREFDQ_A0==74
982 09:13:05.437907 TrainedVREFDQ_A1==74
983 09:13:05.443086 VrefDac_Margin_A0==26
984 09:13:05.443586 DeviceVref_Margin_A0==40
985 09:13:05.444030 VrefDac_Margin_A1==24
986 09:13:05.448627 DeviceVref_Margin_A1==40
987 09:13:05.449069
988 09:13:05.449480
989 09:13:05.449885 channel==1
990 09:13:05.450282 RxClkDly_Margin_A0==98 ps 10
991 09:13:05.452150 TxDqDly_Margin_A0==98 ps 10
992 09:13:05.457669 RxClkDly_Margin_A1==98 ps 10
993 09:13:05.458112 TxDqDly_Margin_A1==98 ps 10
994 09:13:05.463269 TrainedVREFDQ_A0==77
995 09:13:05.463718 TrainedVREFDQ_A1==77
996 09:13:05.464167 VrefDac_Margin_A0==22
997 09:13:05.468802 DeviceVref_Margin_A0==37
998 09:13:05.469241 VrefDac_Margin_A1==24
999 09:13:05.469643 DeviceVref_Margin_A1==37
1000 09:13:05.470047
1001 09:13:05.474388 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 09:13:05.474838
1003 09:13:05.508024 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1004 09:13:05.508505 2D training succeed
1005 09:13:05.513609 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 09:13:05.519195 auto size-- 65535DDR cs0 size: 2048MB
1007 09:13:05.519632 DDR cs1 size: 2048MB
1008 09:13:05.524858 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 09:13:05.525312 cs0 DataBus test pass
1010 09:13:05.525723 cs1 DataBus test pass
1011 09:13:05.530390 cs0 AddrBus test pass
1012 09:13:05.530829 cs1 AddrBus test pass
1013 09:13:05.531235
1014 09:13:05.536029 100bdlr_step_size ps== 420
1015 09:13:05.536495 result report
1016 09:13:05.536903 boot times 0Enable ddr reg access
1017 09:13:05.546073 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 09:13:05.559628 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 09:13:06.131557 0.0;M3 CHK:0;cm4_sp_mode 0
1020 09:13:06.132183 MVN_1=0x00000000
1021 09:13:06.137016 MVN_2=0x00000000
1022 09:13:06.142767 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 09:13:06.143224 OPS=0x10
1024 09:13:06.143638 ring efuse init
1025 09:13:06.144078 chipver efuse init
1026 09:13:06.148373 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 09:13:06.153970 [0.018961 Inits done]
1028 09:13:06.154419 secure task start!
1029 09:13:06.154827 high task start!
1030 09:13:06.158636 low task start!
1031 09:13:06.159082 run into bl31
1032 09:13:06.165222 NOTICE: BL31: v1.3(release):4fc40b1
1033 09:13:06.173107 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 09:13:06.173571 NOTICE: BL31: G12A normal boot!
1035 09:13:06.198356 NOTICE: BL31: BL33 decompress pass
1036 09:13:06.204047 ERROR: Error initializing runtime service opteed_fast
1037 09:13:07.436925
1038 09:13:07.437544
1039 09:13:07.445274 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 09:13:07.445747
1041 09:13:07.446165 Model: Libre Computer AML-A311D-CC Alta
1042 09:13:07.653645 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 09:13:07.677022 DRAM: 2 GiB (effective 3.8 GiB)
1044 09:13:07.820065 Core: 408 devices, 31 uclasses, devicetree: separate
1045 09:13:07.825925 WDT: Not starting watchdog@f0d0
1046 09:13:07.858207 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 09:13:07.870643 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 09:13:07.875615 ** Bad device specification mmc 0 **
1049 09:13:07.885941 Card did not respond to voltage select! : -110
1050 09:13:07.893606 ** Bad device specification mmc 0 **
1051 09:13:07.894081 Couldn't find partition mmc 0
1052 09:13:07.901935 Card did not respond to voltage select! : -110
1053 09:13:07.907445 ** Bad device specification mmc 0 **
1054 09:13:07.907900 Couldn't find partition mmc 0
1055 09:13:07.912500 Error: could not access storage.
1056 09:13:08.255084 Net: eth0: ethernet@ff3f0000
1057 09:13:08.255626 starting USB...
1058 09:13:08.506767 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 09:13:08.507319 Starting the controller
1060 09:13:08.513721 USB XHCI 1.10
1061 09:13:10.067907 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 09:13:10.076166 scanning usb for storage devices... 0 Storage Device(s) found
1064 09:13:10.127804 Hit any key to stop autoboot: 1
1065 09:13:10.128681 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 09:13:10.129294 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1067 09:13:10.129774 Setting prompt string to ['=>']
1068 09:13:10.130256 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1069 09:13:10.143644 0
1070 09:13:10.144577 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 09:13:10.145076 Sending with 10 millisecond of delay
1073 09:13:11.279657 => setenv autoload no
1074 09:13:11.290468 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1075 09:13:11.295416 setenv autoload no
1076 09:13:11.296142 Sending with 10 millisecond of delay
1078 09:13:13.092717 => setenv initrd_high 0xffffffff
1079 09:13:13.103496 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1080 09:13:13.104409 setenv initrd_high 0xffffffff
1081 09:13:13.105141 Sending with 10 millisecond of delay
1083 09:13:14.721078 => setenv fdt_high 0xffffffff
1084 09:13:14.731693 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 09:13:14.732264 setenv fdt_high 0xffffffff
1086 09:13:14.732765 Sending with 10 millisecond of delay
1088 09:13:15.024316 => dhcp
1089 09:13:15.035130 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1090 09:13:15.035824 dhcp
1091 09:13:15.036157 Speed: 1000, full duplex
1092 09:13:15.036402 BOOTP broadcast 1
1093 09:13:15.043210 DHCP client bound to address 192.168.6.27 (8 ms)
1094 09:13:15.044187 Sending with 10 millisecond of delay
1096 09:13:16.720517 => setenv serverip 192.168.6.2
1097 09:13:16.731316 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 09:13:16.732244 setenv serverip 192.168.6.2
1099 09:13:16.732939 Sending with 10 millisecond of delay
1101 09:13:20.455311 => tftpboot 0x01080000 921897/tftp-deploy-hagfe41e/kernel/uImage
1102 09:13:20.466074 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1103 09:13:20.466871 tftpboot 0x01080000 921897/tftp-deploy-hagfe41e/kernel/uImage
1104 09:13:20.467313 Speed: 1000, full duplex
1105 09:13:20.467725 Using ethernet@ff3f0000 device
1106 09:13:20.468848 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 09:13:20.474314 Filename '921897/tftp-deploy-hagfe41e/kernel/uImage'.
1108 09:13:20.478276 Load address: 0x1080000
1109 09:13:24.582062 Loading: *#################################################
1110 09:13:24.582464 TFTP error: trying to overwrite reserved memory...
1112 09:13:24.585952 end: 2.4.3 bootloader-commands (duration 00:00:14) [common]
1115 09:13:24.586933 end: 2.4 uboot-commands (duration 00:00:52) [common]
1117 09:13:24.587647 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1119 09:13:24.588260 end: 2 uboot-action (duration 00:00:52) [common]
1121 09:13:24.589075 Cleaning after the job
1122 09:13:24.589398 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/ramdisk
1123 09:13:24.600059 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/kernel
1124 09:13:24.617647 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/dtb
1125 09:13:24.618435 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921897/tftp-deploy-hagfe41e/modules
1126 09:13:24.646644 start: 4.1 power-off (timeout 00:00:30) [common]
1127 09:13:24.647308 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1128 09:13:24.679345 >> OK - accepted request
1129 09:13:24.681370 Returned 0 in 0 seconds
1130 09:13:24.782095 end: 4.1 power-off (duration 00:00:00) [common]
1132 09:13:24.783075 start: 4.2 read-feedback (timeout 00:10:00) [common]
1133 09:13:24.783741 Listened to connection for namespace 'common' for up to 1s
1134 09:13:25.784140 Finalising connection for namespace 'common'
1135 09:13:25.784627 Disconnecting from shell: Finalise
1136 09:13:25.784902 =>
1137 09:13:25.885560 end: 4.2 read-feedback (duration 00:00:01) [common]
1138 09:13:25.886043 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/921897
1139 09:13:26.182617 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/921897
1140 09:13:26.183225 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.