Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:12:01.155974 lava-dispatcher, installed at version: 2024.01
2 09:12:01.156835 start: 0 validate
3 09:12:01.157303 Start time: 2024-11-01 09:12:01.157273+00:00 (UTC)
4 09:12:01.157847 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:12:01.158410 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:12:01.195236 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:12:01.195953 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 09:12:01.229292 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:12:01.230003 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 09:12:09.303051 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:12:09.303542 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fmaster%2Fnext-20241101%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 09:12:10.346116 validate duration: 9.19
14 09:12:10.347054 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:12:10.347580 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:12:10.347954 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:12:10.348707 Not decompressing ramdisk as can be used compressed.
18 09:12:10.349192 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:12:10.349483 saving as /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/ramdisk/rootfs.cpio.gz
20 09:12:10.349781 total size: 8181887 (7 MB)
21 09:12:10.387212 progress 0 % (0 MB)
22 09:12:10.393199 progress 5 % (0 MB)
23 09:12:10.398867 progress 10 % (0 MB)
24 09:12:10.404936 progress 15 % (1 MB)
25 09:12:10.410351 progress 20 % (1 MB)
26 09:12:10.416240 progress 25 % (1 MB)
27 09:12:10.421986 progress 30 % (2 MB)
28 09:12:10.427681 progress 35 % (2 MB)
29 09:12:10.432880 progress 40 % (3 MB)
30 09:12:10.438430 progress 45 % (3 MB)
31 09:12:10.443573 progress 50 % (3 MB)
32 09:12:10.449125 progress 55 % (4 MB)
33 09:12:10.454284 progress 60 % (4 MB)
34 09:12:10.459803 progress 65 % (5 MB)
35 09:12:10.465060 progress 70 % (5 MB)
36 09:12:10.470590 progress 75 % (5 MB)
37 09:12:10.475751 progress 80 % (6 MB)
38 09:12:10.481357 progress 85 % (6 MB)
39 09:12:10.486523 progress 90 % (7 MB)
40 09:12:10.492060 progress 95 % (7 MB)
41 09:12:10.496843 progress 100 % (7 MB)
42 09:12:10.497513 7 MB downloaded in 0.15 s (52.83 MB/s)
43 09:12:10.498055 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:12:10.498930 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:12:10.499218 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:12:10.499487 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:12:10.500115 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 09:12:10.500389 saving as /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/kernel/Image
50 09:12:10.500597 total size: 66843136 (63 MB)
51 09:12:10.500807 No compression specified
52 09:12:10.536311 progress 0 % (0 MB)
53 09:12:10.577612 progress 5 % (3 MB)
54 09:12:10.618828 progress 10 % (6 MB)
55 09:12:10.660331 progress 15 % (9 MB)
56 09:12:10.701099 progress 20 % (12 MB)
57 09:12:10.742701 progress 25 % (15 MB)
58 09:12:10.786019 progress 30 % (19 MB)
59 09:12:10.828655 progress 35 % (22 MB)
60 09:12:10.871960 progress 40 % (25 MB)
61 09:12:10.913418 progress 45 % (28 MB)
62 09:12:10.956359 progress 50 % (31 MB)
63 09:12:10.997968 progress 55 % (35 MB)
64 09:12:11.039305 progress 60 % (38 MB)
65 09:12:11.081182 progress 65 % (41 MB)
66 09:12:11.123022 progress 70 % (44 MB)
67 09:12:11.164974 progress 75 % (47 MB)
68 09:12:11.206697 progress 80 % (51 MB)
69 09:12:11.248706 progress 85 % (54 MB)
70 09:12:11.290119 progress 90 % (57 MB)
71 09:12:11.331059 progress 95 % (60 MB)
72 09:12:11.374987 progress 100 % (63 MB)
73 09:12:11.375806 63 MB downloaded in 0.88 s (72.84 MB/s)
74 09:12:11.376355 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:12:11.377173 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:12:11.377479 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:12:11.377755 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:12:11.378220 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 09:12:11.378490 saving as /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 09:12:11.378699 total size: 53209 (0 MB)
82 09:12:11.378911 No compression specified
83 09:12:11.449557 progress 61 % (0 MB)
84 09:12:11.450419 progress 100 % (0 MB)
85 09:12:11.450977 0 MB downloaded in 0.07 s (0.70 MB/s)
86 09:12:11.451496 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:12:11.452435 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:12:11.452742 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:12:11.453046 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:12:11.453561 downloading http://storage.kernelci.org/next/master/next-20241101/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 09:12:11.453830 saving as /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/modules/modules.tar
93 09:12:11.454050 total size: 16180864 (15 MB)
94 09:12:11.454282 Using unxz to decompress xz
95 09:12:11.502078 progress 0 % (0 MB)
96 09:12:11.603357 progress 5 % (0 MB)
97 09:12:11.716234 progress 10 % (1 MB)
98 09:12:11.838530 progress 15 % (2 MB)
99 09:12:11.965678 progress 20 % (3 MB)
100 09:12:12.113915 progress 25 % (3 MB)
101 09:12:12.262431 progress 30 % (4 MB)
102 09:12:12.368910 progress 35 % (5 MB)
103 09:12:12.486519 progress 40 % (6 MB)
104 09:12:12.594216 progress 45 % (6 MB)
105 09:12:12.708137 progress 50 % (7 MB)
106 09:12:12.820452 progress 55 % (8 MB)
107 09:12:12.939739 progress 60 % (9 MB)
108 09:12:13.049695 progress 65 % (10 MB)
109 09:12:13.163708 progress 70 % (10 MB)
110 09:12:13.285882 progress 75 % (11 MB)
111 09:12:13.403113 progress 80 % (12 MB)
112 09:12:13.513288 progress 85 % (13 MB)
113 09:12:13.626377 progress 90 % (13 MB)
114 09:12:13.733493 progress 95 % (14 MB)
115 09:12:13.849730 progress 100 % (15 MB)
116 09:12:13.863874 15 MB downloaded in 2.41 s (6.40 MB/s)
117 09:12:13.864721 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:12:13.866086 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:12:13.866402 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 09:12:13.866698 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 09:12:13.867061 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:12:13.867690 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 09:12:13.875056 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i
125 09:12:13.878207 makedir: /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin
126 09:12:13.878760 makedir: /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/tests
127 09:12:13.879237 makedir: /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/results
128 09:12:13.879618 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-add-keys
129 09:12:13.880617 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-add-sources
130 09:12:13.881445 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-background-process-start
131 09:12:13.882592 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-background-process-stop
132 09:12:13.883576 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-common-functions
133 09:12:13.884570 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-echo-ipv4
134 09:12:13.885627 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-install-packages
135 09:12:13.886392 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-installed-packages
136 09:12:13.887267 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-os-build
137 09:12:13.887976 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-probe-channel
138 09:12:13.888586 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-probe-ip
139 09:12:13.889135 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-target-ip
140 09:12:13.889656 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-target-mac
141 09:12:13.890195 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-target-storage
142 09:12:13.890888 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-test-case
143 09:12:13.891651 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-test-event
144 09:12:13.892268 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-test-feedback
145 09:12:13.893007 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-test-raise
146 09:12:13.893789 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-test-reference
147 09:12:13.895114 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-test-runner
148 09:12:13.895924 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-test-set
149 09:12:13.896749 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-test-shell
150 09:12:13.897510 Updating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-install-packages (oe)
151 09:12:13.898537 Updating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/bin/lava-installed-packages (oe)
152 09:12:13.899357 Creating /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/environment
153 09:12:13.899824 LAVA metadata
154 09:12:13.900208 - LAVA_JOB_ID=921891
155 09:12:13.900447 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:12:13.900846 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 09:12:13.902499 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:12:13.902904 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 09:12:13.903168 skipped lava-vland-overlay
160 09:12:13.903470 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:12:13.903767 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 09:12:13.904091 skipped lava-multinode-overlay
163 09:12:13.904371 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:12:13.904645 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 09:12:13.904909 Loading test definitions
166 09:12:13.905203 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 09:12:13.905432 Using /lava-921891 at stage 0
168 09:12:13.907771 uuid=921891_1.5.2.4.1 testdef=None
169 09:12:13.908131 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:12:13.908418 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 09:12:13.910680 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:12:13.911520 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 09:12:13.914376 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:12:13.915353 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 09:12:13.918779 runner path: /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/0/tests/0_dmesg test_uuid 921891_1.5.2.4.1
178 09:12:13.922958 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:12:13.924576 Creating lava-test-runner.conf files
181 09:12:13.924877 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/921891/lava-overlay-h4p_if9i/lava-921891/0 for stage 0
182 09:12:13.926164 - 0_dmesg
183 09:12:13.926655 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:12:13.927011 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 09:12:13.953687 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:12:13.954142 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 09:12:13.954414 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:12:13.954686 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:12:13.954959 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 09:12:14.911408 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:12:14.911972 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 09:12:14.912330 extracting modules file /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/921891/extract-overlay-ramdisk-7g1yfph4/ramdisk
193 09:12:16.725032 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 09:12:16.725527 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 09:12:16.725809 [common] Applying overlay /var/lib/lava/dispatcher/tmp/921891/compress-overlay-honvbw3l/overlay-1.5.2.5.tar.gz to ramdisk
196 09:12:16.726024 [common] Applying overlay /var/lib/lava/dispatcher/tmp/921891/compress-overlay-honvbw3l/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/921891/extract-overlay-ramdisk-7g1yfph4/ramdisk
197 09:12:16.757135 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:12:16.757610 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 09:12:16.757886 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 09:12:16.758119 Converting downloaded kernel to a uImage
201 09:12:16.758440 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/kernel/Image /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/kernel/uImage
202 09:12:17.536874 output: Image Name:
203 09:12:17.537305 output: Created: Fri Nov 1 09:12:16 2024
204 09:12:17.537515 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:12:17.537719 output: Data Size: 66843136 Bytes = 65276.50 KiB = 63.75 MiB
206 09:12:17.537920 output: Load Address: 01080000
207 09:12:17.538118 output: Entry Point: 01080000
208 09:12:17.538315 output:
209 09:12:17.538647 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 09:12:17.538916 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 09:12:17.539184 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 09:12:17.539441 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:12:17.539698 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 09:12:17.539952 Building ramdisk /var/lib/lava/dispatcher/tmp/921891/extract-overlay-ramdisk-7g1yfph4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/921891/extract-overlay-ramdisk-7g1yfph4/ramdisk
215 09:12:21.076062 >> 257076 blocks
216 09:12:32.129815 Adding RAMdisk u-boot header.
217 09:12:32.130471 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/921891/extract-overlay-ramdisk-7g1yfph4/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/921891/extract-overlay-ramdisk-7g1yfph4/ramdisk.cpio.gz.uboot
218 09:12:32.499592 output: Image Name:
219 09:12:32.500012 output: Created: Fri Nov 1 09:12:32 2024
220 09:12:32.500425 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:12:32.500829 output: Data Size: 33795878 Bytes = 33003.79 KiB = 32.23 MiB
222 09:12:32.501221 output: Load Address: 00000000
223 09:12:32.501612 output: Entry Point: 00000000
224 09:12:32.501999 output:
225 09:12:32.502823 rename /var/lib/lava/dispatcher/tmp/921891/extract-overlay-ramdisk-7g1yfph4/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/ramdisk/ramdisk.cpio.gz.uboot
226 09:12:32.503500 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 09:12:32.504054 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 09:12:32.504576 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 09:12:32.505021 No LXC device requested
230 09:12:32.505512 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:12:32.506007 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 09:12:32.506490 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:12:32.506893 Checking files for TFTP limit of 4294967296 bytes.
234 09:12:32.509528 end: 1 tftp-deploy (duration 00:00:22) [common]
235 09:12:32.510091 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:12:32.510607 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:12:32.511098 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:12:32.511589 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:12:32.512126 Using kernel file from prepare-kernel: 921891/tftp-deploy-zym08mxi/kernel/uImage
240 09:12:32.512747 substitutions:
241 09:12:32.513157 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:12:32.513555 - {DTB_ADDR}: 0x01070000
243 09:12:32.513948 - {DTB}: 921891/tftp-deploy-zym08mxi/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 09:12:32.514341 - {INITRD}: 921891/tftp-deploy-zym08mxi/ramdisk/ramdisk.cpio.gz.uboot
245 09:12:32.514734 - {KERNEL_ADDR}: 0x01080000
246 09:12:32.515119 - {KERNEL}: 921891/tftp-deploy-zym08mxi/kernel/uImage
247 09:12:32.515506 - {LAVA_MAC}: None
248 09:12:32.515926 - {PRESEED_CONFIG}: None
249 09:12:32.516343 - {PRESEED_LOCAL}: None
250 09:12:32.516731 - {RAMDISK_ADDR}: 0x08000000
251 09:12:32.517112 - {RAMDISK}: 921891/tftp-deploy-zym08mxi/ramdisk/ramdisk.cpio.gz.uboot
252 09:12:32.517500 - {ROOT_PART}: None
253 09:12:32.517885 - {ROOT}: None
254 09:12:32.518266 - {SERVER_IP}: 192.168.6.2
255 09:12:32.518653 - {TEE_ADDR}: 0x83000000
256 09:12:32.519033 - {TEE}: None
257 09:12:32.519416 Parsed boot commands:
258 09:12:32.519793 - setenv autoload no
259 09:12:32.520205 - setenv initrd_high 0xffffffff
260 09:12:32.520592 - setenv fdt_high 0xffffffff
261 09:12:32.520972 - dhcp
262 09:12:32.521358 - setenv serverip 192.168.6.2
263 09:12:32.521741 - tftpboot 0x01080000 921891/tftp-deploy-zym08mxi/kernel/uImage
264 09:12:32.522123 - tftpboot 0x08000000 921891/tftp-deploy-zym08mxi/ramdisk/ramdisk.cpio.gz.uboot
265 09:12:32.522505 - tftpboot 0x01070000 921891/tftp-deploy-zym08mxi/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 09:12:32.522887 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:12:32.523277 - bootm 0x01080000 0x08000000 0x01070000
268 09:12:32.523768 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:12:32.525278 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:12:32.525714 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 09:12:32.539826 Setting prompt string to ['lava-test: # ']
273 09:12:32.541354 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:12:32.541951 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:12:32.542480 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:12:32.542995 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:12:32.544203 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 09:12:32.578724 >> OK - accepted request
279 09:12:32.581045 Returned 0 in 0 seconds
280 09:12:32.682117 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:12:32.683667 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:12:32.684272 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:12:32.684768 Setting prompt string to ['Hit any key to stop autoboot']
285 09:12:32.685211 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:12:32.686794 Trying 192.168.56.21...
287 09:12:32.687265 Connected to conserv1.
288 09:12:32.687679 Escape character is '^]'.
289 09:12:32.688131
290 09:12:32.688561 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 09:12:32.688977
292 09:12:41.412260 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 09:12:41.412925 bl2_stage_init 0x01
294 09:12:41.413369 bl2_stage_init 0x81
295 09:12:41.417716 hw id: 0x0000 - pwm id 0x01
296 09:12:41.418209 bl2_stage_init 0xc1
297 09:12:41.423412 bl2_stage_init 0x02
298 09:12:41.423914
299 09:12:41.424410 L0:00000000
300 09:12:41.424848 L1:00000703
301 09:12:41.425265 L2:00008067
302 09:12:41.425696 L3:15000000
303 09:12:41.429469 S1:00000000
304 09:12:41.429965 B2:20282000
305 09:12:41.430362 B1:a0f83180
306 09:12:41.430749
307 09:12:41.431149 TE: 69100
308 09:12:41.431568
309 09:12:41.435104 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 09:12:41.435572
311 09:12:41.440644 Board ID = 1
312 09:12:41.441127 Set cpu clk to 24M
313 09:12:41.441534 Set clk81 to 24M
314 09:12:41.446239 Use GP1_pll as DSU clk.
315 09:12:41.446734 DSU clk: 1200 Mhz
316 09:12:41.447144 CPU clk: 1200 MHz
317 09:12:41.447554 Set clk81 to 166.6M
318 09:12:41.457419 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 09:12:41.457931 board id: 1
320 09:12:41.464134 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:12:41.475037 fw parse done
322 09:12:41.481001 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:12:41.524127 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:12:41.535202 PIEI prepare done
325 09:12:41.535682 fastboot data load
326 09:12:41.536127 fastboot data verify
327 09:12:41.540789 verify result: 266
328 09:12:41.546415 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 09:12:41.546850 LPDDR4 probe
330 09:12:41.547273 ddr clk to 1584MHz
331 09:12:41.553485 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:12:41.592225
333 09:12:41.592816 dmc_version 0001
334 09:12:41.599189 Check phy result
335 09:12:41.605145 INFO : End of CA training
336 09:12:41.605642 INFO : End of initialization
337 09:12:41.610732 INFO : Training has run successfully!
338 09:12:41.611207 Check phy result
339 09:12:41.616472 INFO : End of initialization
340 09:12:41.616948 INFO : End of read enable training
341 09:12:41.621973 INFO : End of fine write leveling
342 09:12:41.627569 INFO : End of Write leveling coarse delay
343 09:12:41.628175 INFO : Training has run successfully!
344 09:12:41.628616 Check phy result
345 09:12:41.633164 INFO : End of initialization
346 09:12:41.633658 INFO : End of read dq deskew training
347 09:12:41.638736 INFO : End of MPR read delay center optimization
348 09:12:41.644417 INFO : End of write delay center optimization
349 09:12:41.649917 INFO : End of read delay center optimization
350 09:12:41.650365 INFO : End of max read latency training
351 09:12:41.655543 INFO : Training has run successfully!
352 09:12:41.656085 1D training succeed
353 09:12:41.664811 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:12:41.713042 Check phy result
355 09:12:41.713615 INFO : End of initialization
356 09:12:41.739640 INFO : End of 2D read delay Voltage center optimization
357 09:12:41.764685 INFO : End of 2D read delay Voltage center optimization
358 09:12:41.821309 INFO : End of 2D write delay Voltage center optimization
359 09:12:41.875364 INFO : End of 2D write delay Voltage center optimization
360 09:12:41.880872 INFO : Training has run successfully!
361 09:12:41.881342
362 09:12:41.881752 channel==0
363 09:12:41.886339 RxClkDly_Margin_A0==78 ps 8
364 09:12:41.886630 TxDqDly_Margin_A0==98 ps 10
365 09:12:41.891866 RxClkDly_Margin_A1==88 ps 9
366 09:12:41.892181 TxDqDly_Margin_A1==98 ps 10
367 09:12:41.892409 TrainedVREFDQ_A0==77
368 09:12:41.897464 TrainedVREFDQ_A1==74
369 09:12:41.897739 VrefDac_Margin_A0==24
370 09:12:41.897956 DeviceVref_Margin_A0==37
371 09:12:41.903103 VrefDac_Margin_A1==23
372 09:12:41.903373 DeviceVref_Margin_A1==40
373 09:12:41.903592
374 09:12:41.903809
375 09:12:41.908791 channel==1
376 09:12:41.909502 RxClkDly_Margin_A0==88 ps 9
377 09:12:41.909802 TxDqDly_Margin_A0==88 ps 9
378 09:12:41.914378 RxClkDly_Margin_A1==88 ps 9
379 09:12:41.915186 TxDqDly_Margin_A1==88 ps 9
380 09:12:41.920118 TrainedVREFDQ_A0==75
381 09:12:41.920877 TrainedVREFDQ_A1==77
382 09:12:41.921607 VrefDac_Margin_A0==23
383 09:12:41.925613 DeviceVref_Margin_A0==39
384 09:12:41.926450 VrefDac_Margin_A1==22
385 09:12:41.931274 DeviceVref_Margin_A1==37
386 09:12:41.932161
387 09:12:41.932917 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:12:41.933709
389 09:12:41.964633 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000019 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
390 09:12:41.965626 2D training succeed
391 09:12:41.970152 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:12:41.975792 auto size-- 65535DDR cs0 size: 2048MB
393 09:12:41.976680 DDR cs1 size: 2048MB
394 09:12:41.981384 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:12:41.982229 cs0 DataBus test pass
396 09:12:41.986976 cs1 DataBus test pass
397 09:12:41.987824 cs0 AddrBus test pass
398 09:12:41.988707 cs1 AddrBus test pass
399 09:12:41.989468
400 09:12:41.992655 100bdlr_step_size ps== 485
401 09:12:41.993491 result report
402 09:12:41.998314 boot times 0Enable ddr reg access
403 09:12:42.003696 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:12:42.016712 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 09:12:42.675850 bl2z: ptr: 05129330, size: 00001e40
406 09:12:42.683607 0.0;M3 CHK:0;cm4_sp_mode 0
407 09:12:42.684468 MVN_1=0x00000000
408 09:12:42.685189 MVN_2=0x00000000
409 09:12:42.695087 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 09:12:42.695870 OPS=0x04
411 09:12:42.696631 ring efuse init
412 09:12:42.700779 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 09:12:42.701568 [0.017354 Inits done]
414 09:12:42.702293 secure task start!
415 09:12:42.707947 high task start!
416 09:12:42.708743 low task start!
417 09:12:42.709359 run into bl31
418 09:12:42.716725 NOTICE: BL31: v1.3(release):4fc40b1
419 09:12:42.724264 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 09:12:42.725014 NOTICE: BL31: G12A normal boot!
421 09:12:42.740084 NOTICE: BL31: BL33 decompress pass
422 09:12:42.745603 ERROR: Error initializing runtime service opteed_fast
423 09:12:43.961757 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 09:12:43.962272 bl2_stage_init 0x01
425 09:12:43.962661 bl2_stage_init 0x81
426 09:12:43.967161 hw id: 0x0000 - pwm id 0x01
427 09:12:43.967537 bl2_stage_init 0xc1
428 09:12:43.972779 bl2_stage_init 0x02
429 09:12:43.973116
430 09:12:43.973745 L0:00000000
431 09:12:43.974438 L1:00000703
432 09:12:43.974843 L2:00008067
433 09:12:43.975122 L3:15000000
434 09:12:43.978378 S1:00000000
435 09:12:43.978736 B2:20282000
436 09:12:43.979240 B1:a0f83180
437 09:12:43.979926
438 09:12:43.980332 TE: 68529
439 09:12:43.980637
440 09:12:43.983960 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 09:12:43.984355
442 09:12:43.989586 Board ID = 1
443 09:12:43.989956 Set cpu clk to 24M
444 09:12:43.990275 Set clk81 to 24M
445 09:12:43.995150 Use GP1_pll as DSU clk.
446 09:12:43.995469 DSU clk: 1200 Mhz
447 09:12:43.995788 CPU clk: 1200 MHz
448 09:12:44.000755 Set clk81 to 166.6M
449 09:12:44.006354 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 09:12:44.006751 board id: 1
451 09:12:44.013703 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 09:12:44.024482 fw parse done
453 09:12:44.030397 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 09:12:44.073692 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 09:12:44.084663 PIEI prepare done
456 09:12:44.085002 fastboot data load
457 09:12:44.085245 fastboot data verify
458 09:12:44.090363 verify result: 266
459 09:12:44.096008 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 09:12:44.096283 LPDDR4 probe
461 09:12:44.096511 ddr clk to 1584MHz
462 09:12:45.463088 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x000 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 09:12:45.463523 bl2_stage_init 0x01
464 09:12:45.463768 bl2_stage_init 0x81
465 09:12:45.468648 hw id: 0x0000 - pwm id 0x01
466 09:12:45.468957 bl2_stage_init 0xc1
467 09:12:45.474186 bl2_stage_init 0x02
468 09:12:45.474489
469 09:12:45.474720 L0:00000000
470 09:12:45.474940 L1:00000703
471 09:12:45.475158 L2:00008067
472 09:12:45.475378 L3:15000000
473 09:12:45.479822 S1:00000000
474 09:12:45.480134 B2:20282000
475 09:12:45.480359 B1:a0f83180
476 09:12:45.480585
477 09:12:45.480804 TE: 68796
478 09:12:45.481018
479 09:12:45.485394 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 09:12:45.485689
481 09:12:45.491029 Board ID = 1
482 09:12:45.491329 Set cpu clk to 24M
483 09:12:45.491561 Set clk81 to 24M
484 09:12:45.496680 Use GP1_pll as DSU clk.
485 09:12:45.496997 DSU clk: 1200 Mhz
486 09:12:45.497226 CPU clk: 1200 MHz
487 09:12:45.502208 Set clk81 to 166.6M
488 09:12:45.507844 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 09:12:45.508157 board id: 1
490 09:12:45.515006 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 09:12:45.525688 fw parse done
492 09:12:45.531637 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 09:12:45.574247 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 09:12:45.585296 PIEI prepare done
495 09:12:45.585625 fastboot data load
496 09:12:45.585860 fastboot data verify
497 09:12:45.590872 verify result: 266
498 09:12:45.596438 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 09:12:45.596745 LPDDR4 probe
500 09:12:45.596983 ddr clk to 1584MHz
501 09:12:45.603581 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 09:12:45.641772
503 09:12:45.642157 dmc_version 0001
504 09:12:45.647561 Check phy result
505 09:12:45.654293 INFO : End of CA training
506 09:12:45.654591 INFO : End of initialization
507 09:12:45.659942 INFO : Training has run successfully!
508 09:12:45.660266 Check phy result
509 09:12:45.665563 INFO : End of initialization
510 09:12:45.665975 INFO : End of read enable training
511 09:12:45.671062 INFO : End of fine write leveling
512 09:12:45.676660 INFO : End of Write leveling coarse delay
513 09:12:45.677052 INFO : Training has run successfully!
514 09:12:45.677357 Check phy result
515 09:12:45.682250 INFO : End of initialization
516 09:12:45.682632 INFO : End of read dq deskew training
517 09:12:45.687892 INFO : End of MPR read delay center optimization
518 09:12:45.693423 INFO : End of write delay center optimization
519 09:12:45.699058 INFO : End of read delay center optimization
520 09:12:45.699429 INFO : End of max read latency training
521 09:12:45.704702 INFO : Training has run successfully!
522 09:12:45.705133 1D training succeed
523 09:12:45.713954 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 09:12:45.761519 Check phy result
525 09:12:45.762032 INFO : End of initialization
526 09:12:45.783813 INFO : End of 2D read delay Voltage center optimization
527 09:12:45.803081 INFO : End of 2D read delay Voltage center optimization
528 09:12:45.854929 INFO : End of 2D write delay Voltage center optimization
529 09:12:45.904148 INFO : End of 2D write delay Voltage center optimization
530 09:12:45.909556 INFO : Training has run successfully!
531 09:12:45.909949
532 09:12:45.910265 channel==0
533 09:12:45.915150 RxClkDly_Margin_A0==78 ps 8
534 09:12:45.915549 TxDqDly_Margin_A0==88 ps 9
535 09:12:45.920803 RxClkDly_Margin_A1==88 ps 9
536 09:12:45.921181 TxDqDly_Margin_A1==88 ps 9
537 09:12:45.921489 TrainedVREFDQ_A0==74
538 09:12:45.926332 TrainedVREFDQ_A1==74
539 09:12:45.926704 VrefDac_Margin_A0==24
540 09:12:45.927007 DeviceVref_Margin_A0==40
541 09:12:45.931948 VrefDac_Margin_A1==23
542 09:12:45.932336 DeviceVref_Margin_A1==40
543 09:12:45.932648
544 09:12:45.932943
545 09:12:45.933235 channel==1
546 09:12:45.937513 RxClkDly_Margin_A0==88 ps 9
547 09:12:45.937886 TxDqDly_Margin_A0==98 ps 10
548 09:12:45.943204 RxClkDly_Margin_A1==78 ps 8
549 09:12:45.943581 TxDqDly_Margin_A1==98 ps 10
550 09:12:45.948842 TrainedVREFDQ_A0==78
551 09:12:45.949219 TrainedVREFDQ_A1==78
552 09:12:45.949520 VrefDac_Margin_A0==22
553 09:12:45.954354 DeviceVref_Margin_A0==36
554 09:12:45.954734 VrefDac_Margin_A1==22
555 09:12:45.960014 DeviceVref_Margin_A1==36
556 09:12:45.960399
557 09:12:45.960704 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 09:12:45.960997
559 09:12:45.993586 soc_vref_reg_value 0x 0000001a 00000019 00000018 00000017 00000019 00000016 00000018 00000016 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
560 09:12:45.994087 2D training succeed
561 09:12:45.999187 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 09:12:46.004770 auto size-- 65535DDR cs0 size: 2048MB
563 09:12:46.005119 DDR cs1 size: 2048MB
564 09:12:46.010329 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 09:12:46.010681 cs0 DataBus test pass
566 09:12:46.015905 cs1 DataBus test pass
567 09:12:46.016280 cs0 AddrBus test pass
568 09:12:46.016563 cs1 AddrBus test pass
569 09:12:46.016838
570 09:12:46.021501 100bdlr_step_size ps== 471
571 09:12:46.021861 result report
572 09:12:46.027113 boot times 0Enable ddr reg access
573 09:12:46.032288 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 09:12:46.046102 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 09:12:46.700833 bl2z: ptr: 05129330, size: 00001e40
576 09:12:46.708902 0.0;M3 CHK:0;cm4_sp_mode 0
577 09:12:46.709415 MVN_1=0x00000000
578 09:12:46.709845 MVN_2=0x00000000
579 09:12:46.720355 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 09:12:46.720850 OPS=0x04
581 09:12:46.721277 ring efuse init
582 09:12:46.726021 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 09:12:46.726504 [0.017319 Inits done]
584 09:12:46.726924 secure task start!
585 09:12:46.733862 high task start!
586 09:12:46.734337 low task start!
587 09:12:46.734750 run into bl31
588 09:12:46.742438 NOTICE: BL31: v1.3(release):4fc40b1
589 09:12:46.750235 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 09:12:46.750716 NOTICE: BL31: G12A normal boot!
591 09:12:46.765742 NOTICE: BL31: BL33 decompress pass
592 09:12:46.771449 ERROR: Error initializing runtime service opteed_fast
593 09:12:48.163495 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 09:12:48.163947 bl2_stage_init 0x01
595 09:12:48.164224 bl2_stage_init 0x81
596 09:12:48.168644 hw id: 0x0000 - pwm id 0x01
597 09:12:48.169217 bl2_stage_init 0xc1
598 09:12:48.175027 bl2_stage_init 0x02
599 09:12:48.175442
600 09:12:48.175654 L0:00000000
601 09:12:48.175893 L1:00000703
602 09:12:48.176167 L2:00008067
603 09:12:48.176378 L3:15000000
604 09:12:48.179819 S1:00000000
605 09:12:48.181303 B2:20282000
606 09:12:48.181790 B1:a0f83180
607 09:12:48.182226
608 09:12:48.182653 TE: 69699
609 09:12:48.183077
610 09:12:48.185527 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 09:12:48.186136
612 09:12:48.191001 Board ID = 1
613 09:12:48.191609 Set cpu clk to 24M
614 09:12:48.192047 Set clk81 to 24M
615 09:12:48.196667 Use GP1_pll as DSU clk.
616 09:12:48.197264 DSU clk: 1200 Mhz
617 09:12:48.197667 CPU clk: 1200 MHz
618 09:12:48.202021 Set clk81 to 166.6M
619 09:12:48.207605 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 09:12:48.208112 board id: 1
621 09:12:48.215213 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 09:12:48.226316 fw parse done
623 09:12:48.231852 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 09:12:48.275629 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 09:12:48.285033 PIEI prepare done
626 09:12:48.285603 fastboot data load
627 09:12:48.286082 fastboot data verify
628 09:12:48.290938 verify result: 266
629 09:12:48.296653 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 09:12:48.297112 LPDDR4 probe
631 09:12:48.297363 ddr clk to 1584MHz
632 09:12:48.304716 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 09:12:48.341548
634 09:12:48.342004 dmc_version 0001
635 09:12:48.348277 Check phy result
636 09:12:48.354348 INFO : End of CA training
637 09:12:48.354785 INFO : End of initialization
638 09:12:48.359736 INFO : Training has run successfully!
639 09:12:48.360169 Check phy result
640 09:12:48.365458 INFO : End of initialization
641 09:12:48.365871 INFO : End of read enable training
642 09:12:48.375412 INFO : End of fine write leveling
643 09:12:48.382045 INFO : End of Write leveling coarse delay
644 09:12:48.382457 INFO : Training has run successfully!
645 09:12:48.382671 Check phy result
646 09:12:48.383652 INFO : End of initialization
647 09:12:48.383917 INFO : End of read dq deskew training
648 09:12:48.388014 INFO : End of MPR read delay center optimization
649 09:12:48.393456 INFO : End of write delay center optimization
650 09:12:48.399661 INFO : End of read delay center optimization
651 09:12:48.400094 INFO : End of max read latency training
652 09:12:48.404648 INFO : Training has run successfully!
653 09:12:48.405440 1D training succeed
654 09:12:48.413775 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 09:12:48.461365 Check phy result
656 09:12:48.462136 INFO : End of initialization
657 09:12:48.483786 INFO : End of 2D read delay Voltage center optimization
658 09:12:48.508043 INFO : End of 2D read delay Voltage center optimization
659 09:12:48.555221 INFO : End of 2D write delay Voltage center optimization
660 09:12:48.604176 INFO : End of 2D write delay Voltage center optimization
661 09:12:48.609764 INFO : Training has run successfully!
662 09:12:48.610379
663 09:12:48.610857 channel==0
664 09:12:48.615249 RxClkDly_Margin_A0==78 ps 8
665 09:12:48.615828 TxDqDly_Margin_A0==88 ps 9
666 09:12:48.620926 RxClkDly_Margin_A1==88 ps 9
667 09:12:48.621557 TxDqDly_Margin_A1==88 ps 9
668 09:12:48.622099 TrainedVREFDQ_A0==74
669 09:12:48.626702 TrainedVREFDQ_A1==74
670 09:12:48.627325 VrefDac_Margin_A0==25
671 09:12:48.627798 DeviceVref_Margin_A0==40
672 09:12:48.632276 VrefDac_Margin_A1==23
673 09:12:48.632925 DeviceVref_Margin_A1==40
674 09:12:48.633415
675 09:12:48.633897
676 09:12:48.634372 channel==1
677 09:12:48.637966 RxClkDly_Margin_A0==78 ps 8
678 09:12:48.638635 TxDqDly_Margin_A0==78 ps 8
679 09:12:48.643263 RxClkDly_Margin_A1==88 ps 9
680 09:12:48.643663 TxDqDly_Margin_A1==88 ps 9
681 09:12:48.649002 TrainedVREFDQ_A0==75
682 09:12:48.649431 TrainedVREFDQ_A1==75
683 09:12:48.649676 VrefDac_Margin_A0==22
684 09:12:48.654675 DeviceVref_Margin_A0==39
685 09:12:48.655053 VrefDac_Margin_A1==22
686 09:12:48.655451 DeviceVref_Margin_A1==39
687 09:12:48.660160
688 09:12:48.660757 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 09:12:48.661163
690 09:12:48.695893 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000019 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000015 00000018 00000015 00000016 00000017 00000019 00000019 00000018 00000019 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
691 09:12:48.696318 2D training succeed
692 09:12:48.699208 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 09:12:48.705568 auto size-- 65535DDR cs0 size: 2048MB
694 09:12:48.706069 DDR cs1 size: 2048MB
695 09:12:48.710412 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 09:12:48.710760 cs0 DataBus test pass
697 09:12:48.715918 cs1 DataBus test pass
698 09:12:48.716291 cs0 AddrBus test pass
699 09:12:48.716523 cs1 AddrBus test pass
700 09:12:48.717054
701 09:12:48.721599 100bdlr_step_size ps== 478
702 09:12:48.721963 result report
703 09:12:48.728348 boot times 0Enable ddr reg access
704 09:12:48.731101 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 09:12:48.744845 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 09:12:49.400881 bl2z: ptr: 05129330, size: 00001e40
707 09:12:49.407411 0.0;M3 CHK:0;cm4_sp_mode 0
708 09:12:49.407950 MVN_1=0x00000000
709 09:12:49.408466 MVN_2=0x00000000
710 09:12:49.418880 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 09:12:49.419402 OPS=0x04
712 09:12:49.419862 ring efuse init
713 09:12:49.424502 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 09:12:49.424764 [0.017319 Inits done]
715 09:12:49.424978 secure task start!
716 09:12:49.432022 high task start!
717 09:12:49.432526 low task start!
718 09:12:49.432981 run into bl31
719 09:12:49.440650 NOTICE: BL31: v1.3(release):4fc40b1
720 09:12:49.448502 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 09:12:49.449021 NOTICE: BL31: G12A normal boot!
722 09:12:49.463917 NOTICE: BL31: BL33 decompress pass
723 09:12:49.469594 ERROR: Error initializing runtime service opteed_fast
724 09:12:50.264838
725 09:12:50.265267
726 09:12:50.270377 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 09:12:50.270802
728 09:12:50.273785 Model: Libre Computer AML-S905D3-CC Solitude
729 09:12:50.420872 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 09:12:50.436270 DRAM: 2 GiB (effective 3.8 GiB)
731 09:12:50.537239 Core: 406 devices, 33 uclasses, devicetree: separate
732 09:12:50.543046 WDT: Not starting watchdog@f0d0
733 09:12:50.568164 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 09:12:50.580376 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 09:12:50.585401 ** Bad device specification mmc 0 **
736 09:12:50.595571 Card did not respond to voltage select! : -110
737 09:12:50.603135 ** Bad device specification mmc 0 **
738 09:12:50.603628 Couldn't find partition mmc 0
739 09:12:50.611440 Card did not respond to voltage select! : -110
740 09:12:50.616945 ** Bad device specification mmc 0 **
741 09:12:50.617431 Couldn't find partition mmc 0
742 09:12:50.622009 Error: could not access storage.
743 09:12:50.918438 Net: eth0: ethernet@ff3f0000
744 09:12:50.919059 starting USB...
745 09:12:51.163069 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 09:12:51.163692 Starting the controller
747 09:12:51.170032 USB XHCI 1.10
748 09:12:52.726660 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 09:12:52.734993 scanning usb for storage devices... 0 Storage Device(s) found
751 09:12:52.786662 Hit any key to stop autoboot: 1
752 09:12:52.787620 end: 2.4.2 bootloader-interrupt (duration 00:00:20) [common]
753 09:12:52.788296 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
754 09:12:52.788819 Setting prompt string to ['=>']
755 09:12:52.789342 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
756 09:12:52.800950 0
757 09:12:52.801888 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 09:12:52.903214 => setenv autoload no
760 09:12:52.904062 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
761 09:12:52.909354 setenv autoload no
763 09:12:53.010942 => setenv initrd_high 0xffffffff
764 09:12:53.011722 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
765 09:12:53.016261 setenv initrd_high 0xffffffff
767 09:12:53.117765 => setenv fdt_high 0xffffffff
768 09:12:53.118446 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
769 09:12:53.122744 setenv fdt_high 0xffffffff
771 09:12:53.224330 => dhcp
772 09:12:53.225111 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
773 09:12:53.229126 dhcp
774 09:12:54.184905 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
775 09:12:54.185554 Speed: 1000, full duplex
776 09:12:54.186019 BOOTP broadcast 1
777 09:12:54.201610 DHCP client bound to address 192.168.6.21 (16 ms)
779 09:12:54.303211 => setenv serverip 192.168.6.2
780 09:12:54.303878 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
781 09:12:54.308174 setenv serverip 192.168.6.2
783 09:12:54.409679 => tftpboot 0x01080000 921891/tftp-deploy-zym08mxi/kernel/uImage
784 09:12:54.410422 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
785 09:12:54.417079 tftpboot 0x01080000 921891/tftp-deploy-zym08mxi/kernel/uImage
786 09:12:54.417604 Speed: 1000, full duplex
787 09:12:54.418083 Using ethernet@ff3f0000 device
788 09:12:54.422535 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
789 09:12:54.428133 Filename '921891/tftp-deploy-zym08mxi/kernel/uImage'.
790 09:12:54.431428 Load address: 0x1080000
791 09:12:58.659145 Loading: *#################################################
792 09:12:58.659767 TFTP error: trying to overwrite reserved memory...
794 09:12:58.661283 end: 2.4.3 bootloader-commands (duration 00:00:06) [common]
797 09:12:58.663071 end: 2.4 uboot-commands (duration 00:00:26) [common]
799 09:12:58.664539 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
801 09:12:58.665592 end: 2 uboot-action (duration 00:00:26) [common]
803 09:12:58.667090 Cleaning after the job
804 09:12:58.667626 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/ramdisk
805 09:12:58.686508 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/kernel
806 09:12:58.716240 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/dtb
807 09:12:58.717043 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/921891/tftp-deploy-zym08mxi/modules
808 09:12:58.744707 start: 4.1 power-off (timeout 00:00:30) [common]
809 09:12:58.745346 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
810 09:12:58.775687 >> OK - accepted request
811 09:12:58.778084 Returned 0 in 0 seconds
812 09:12:58.878759 end: 4.1 power-off (duration 00:00:00) [common]
814 09:12:58.879667 start: 4.2 read-feedback (timeout 00:10:00) [common]
815 09:12:58.880340 Listened to connection for namespace 'common' for up to 1s
816 09:12:59.881254 Finalising connection for namespace 'common'
817 09:12:59.881921 Disconnecting from shell: Finalise
818 09:12:59.882426 =>
819 09:12:59.983366 end: 4.2 read-feedback (duration 00:00:01) [common]
820 09:12:59.984076 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/921891
821 09:13:00.289038 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/921891
822 09:13:00.289637 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.